Software radar front end and control method thereof

Abstract

The invention provides a software radar front end. Front end control carries out uplink control analysis distribution and timing generation; each digital sub-array in the digital sub-array generates a baseband waveform, and performs up-down conversion, signal amplification, radio-frequency signal space radiation and receiving and echo sampling; the frequency combining module provides a local oscillator signal required by up-down frequency conversion and a digital sub-array for the digital sub-array, and provides a reference clock signal required by front-end control; and the beam forming module completes beam forming processing on echo signals generated by the digital sub-arrays. Specific implementation details of the front end of the radar are shielded, rapid iteration of each module is supported, the characteristics of convenient development and easy upgrading of the CPU processor and the characteristics of real-time efficient calculation and high-precision synchronous distribution of the FPGA processor are considered, front and rear end decoupling of the radar is effectively realized, the maintainability of the system is effectively improved, and the cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to a software radar front-end and a control method thereof, which is mainly used for realizing the modular design of the front-end control, improving the development efficiency of the radar system, and reducing the cost of the radar system. BACKGROUND

[0002] With the rapid development of modern military technology, as one of the main combat equipment in modern war, the role of radar in target detection, tracking and command control cannot be ignored. In the radar system, the front-end part plays a crucial role. For different types and functions of radar products, the composition structure, driving mode, processing flow and performance of the front-end part of the radar system are quite different. At the same time, the types of hardware constituting the radar system front-end are various, and the connection mode and interface form are numerous. Combined with the rapid iteration of electronic information technology, it results in the diversity of radar system front-end design. Therefore, it is particularly important to realize the radar system front-end design with high performance, high reliability and low cost.

[0003] The radar front-end control technology aims to develop a universal front-end control scheme for multiple types of radars. The radar complex front-end control system is decomposed into independent and function-specific modules such as front-end control, digital subarray and frequency combiner by using modular design thinking. Each module completes a specific sub-function, and through the combination of these modules, the required functions of the entire radar system front-end control can be completed. In such a radar front-end control method, each module is a unit that can be combined, decomposed and replaced, making the complex system easier to manage, enhancing the maintainability, scalability and reusability of the radar front-end system, and reducing the cost and difficulty of radar development and maintenance.

[0004] The current research on radar front-end control method mainly focuses on integrated chips based on digital circuits, and there is no research on common design for processor parts, which causes problems such as long development cycle, high cost and hardware resource limitations of the radar system. Therefore, it is urgent to develop a modular design of radar front-end control method for CPU processors. SUMMARY

[0005] In order to overcome the shortcomings of the prior art, the present application provides a software radar front-end and a control method thereof, which is mainly used for realizing the modular design of the front-end control, improving the development efficiency of the radar system, and reducing the cost of the radar system.

[0006] The technical scheme adopted by the present application to solve its technical problems is:

[0007] The software radar front end comprises a front end control, a digital subarray array, a frequency combination module and a beam synthesis module, the front end control performs uplink control analysis distribution and timing generation; each digital subarray in the digital subarray array generates a baseband waveform, and performs upconversion and downconversion, signal amplification, spatial radiation and reception of radio frequency signals and echo sampling; the frequency combination module provides a local oscillator signal required by the digital subarray array for upconversion and downconversion, and a digital subarray, and provides a reference clock signal required by the front end control; and the beam synthesis module completes beam forming processing on the echo signal generated by the digital subarray array.

[0008] The front end control comprises a CPU chip and an FPGA chip, the CPU chip receives an instruction, analyzes an uplink control signal and a timing control signal required by the digital subarray and the frequency combination module, and sends the uplink control signal and the timing control signal to the FPGA chip, the FPGA chip receives the timing control signal, generates a timing signal required by the software radar front end according to a requirement, and distributes the timing signal to the digital subarray and the frequency combination module, and synchronously distributes an uplink control instruction required by the digital subarray, the frequency combination module and the beam synthesis module to the digital subarray, the frequency combination module and the beam synthesis module;

[0009] The digital subarray receives the uplink control signal and the timing control signal, generates a baseband waveform according to a requirement, and performs upconversion and downconversion, signal amplification, spatial radiation and reception of radio frequency signals and echo sampling, and sends echo data to the beam synthesis module; the beam synthesis module receives the uplink control signal, generates beam data according to a requirement, and sends the beam data to a back end processing; and the frequency combination module receives the uplink control signal and the timing control signal, generates a local oscillator signal and a clock signal required by the digital subarray according to a requirement, and distributes the local oscillator signal and the clock signal to the digital subarray array through a network.

[0010] When the software radar front end is running, the CPU chip of the front end control sends an interrupt signal to a back end processing, the back end processing receives the interrupt signal, sends front end control instructions of a plurality of CPIs in a current scheduling interval to the CPU chip of the front end control, the CPU chip of the front end control receives the front end control instructions in the current scheduling interval, completes instruction analysis, waits for an interrupt signal of the FPGA chip of the front end control, receives an interrupt signal once, and sends a control instruction of one CPI in a scheduling sequence, the FPGA chip of the front end control receives the control instruction, synchronously distributes the control instruction to the digital subarray and the frequency combination module according to a timing requirement, and sends a next interrupt signal to the CPU chip of the front end control; after the CPU chip of the front end control sends the instructions in the current scheduling interval, the CPU chip of the front end control continues to send an interrupt to the back end processing, and requests the back end processing to send front end control instructions in a next scheduling interval.

[0011] A control method of a software radar front end, and specific steps are as follows:

[0012] Step 1: the CPU chip of the front-end control sends an interrupt signal to the back-end processing;

[0013] Step 2: after receiving the interrupt signal, the back-end processing sends the front-end control instruction of the control instruction of the plurality of CPIs in the current scheduling interval to the CPU chip of the front-end control;

[0014] Step 3: the CPU chip of the front-end control receives the front-end control instruction of the current scheduling interval, completes instruction analysis, and waits for the interrupt signal of the FPGA chip of the front-end control;

[0015] Step 4: the CPU chip of the front-end control receives an interrupt signal from the front-end control FPGA chip once, that is, sends the control instruction of a CPI to the FPGA chip of the front-end control in turn according to the scheduling sequence;

[0016] Step 5: after receiving the control instruction, the FPGA chip of the front-end control synchronously distributes to the digital subarray and frequency synthesis module according to the timing requirement, and sends the next interrupt signal to the CPU chip of the front-end control;

[0017] Step 6: after the CPU chip of the front-end control sends the instructions of the current scheduling interval, the CPU chip of the front-end control continues to send an interrupt signal to the back-end processing, and requests the back-end processing to send the front-end control instruction of the next scheduling interval.

[0018] The application has the beneficial effects that the modular design is applied to the radar front-end, the uplink control mode is performed between the CPU and the FPGA, the specific implementation details of the radar front-end are shielded through the software-defined mode, and the rapid iteration of the modules is supported. The control method of the application considers the features that the CPU processor is convenient to develop and easy to upgrade and the features that the FPGA processor is real-time and efficient in calculation and high in precision in synchronous distribution, effectively realizes the decoupling of the radar front-end and back-end, shields the specific implementation details of the radar front-end by using the front-end control, makes the front-end system more easy to manage when the system works, independently completes the functions of the modules, effectively improves the maintainability of the system, and reduces the cost. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a connection relationship schematic diagram of the application applied to the radar front-end.

[0020] Figure 2 is a flowchart of the control method. DETAILED DESCRIPTION

[0021] The application will be further described below in combination with the drawings and embodiments.

[0022] As Figure 1As shown, the radar front end is composed of front end control, digital subarray array, frequency combination, and beam forming, wherein the front end control completes uplink control analysis distribution and timing generation functions; the digital subarray array completes baseband waveform generation, upconversion and downconversion, signal amplification, radio frequency signal space radiation / reception, and echo sampling functions of each digital subarray; the frequency combination provides the local oscillator signals required by the digital subarray array for upconversion and downconversion, and the reference clock signals required by the digital subarray and the front end control; and the beam forming completes beam forming processing on the echo signals generated by the digital subarray array.

[0023] The front end control includes a CPU and an FPGA chip. The CPU chip completes front end control instruction receiving and analyzes uplink control instructions and timing control instructions required by the digital subarray and the frequency combination, and sends the instructions to the FPGA chip. The FPGA chip receives the timing control instructions, generates timing signals required by the system according to requirements, and distributes the timing signals to the digital subarray and the frequency combination. The FPGA chip also synchronously distributes uplink control instructions required by the digital subarray, the frequency combination, and the beam forming to the digital subarray, the frequency combination, and the beam forming.

[0024] The digital subarray receives the uplink control instructions and the timing signals, and completes baseband waveform generation, upconversion and downconversion, signal amplification, radio frequency signal space radiation / reception, and echo sampling according to requirements, and sends the echo to the beam forming. The beam forming receives the uplink control instructions, generates beam data according to requirements, and sends the beam data to the back end processing. The frequency combination receives the uplink control instructions and the timing signals, generates local oscillator signals and clock signals required by the digital subarray according to requirements, and distributes the signals to the digital subarray array through a network.

[0025] When the system is running, the front end control CPU chip sends an interrupt signal to the back end processing. After receiving the interrupt, the back end processing sends front end control instructions of a current scheduling interval (including control instructions of multiple CPIs) to the front end control CPU chip. The front end control CPU chip receives the front end control instructions of the current scheduling interval, completes instruction analysis, waits for an interrupt signal of the front end control FPGA chip, and, after receiving an interrupt signal, sends a control instruction of one CPI (sent in a scheduling order) to the front end control FPGA chip. The front end control FPGA chip receives the control instruction, synchronously distributes the control instruction to the controlled end (the digital subarray and the frequency combination) according to timing requirements, and sends a next interrupt signal to the front end control CPU chip. After the front end control CPU chip sends all the instructions of the current scheduling interval, the front end control CPU chip continues to send an interrupt to the back end processing, and requests the back end processing to send front end control instructions of a next scheduling interval.

[0026] As shown in FIG. 1, Figure 2 A control method applied to a radar front end, and the specific steps are

[0027] Step 1: The front end control CPU chip sends an interrupt signal to the back end processing.

[0028] Step 2: After receiving the interrupt, the back-end processing sends the front-end control instruction of the current scheduling interval (including the control instruction of multiple CPIs) to the front-end control CPU chip;

[0029] Step 3: The front-end control CPU chip receives the front-end control instruction of the current scheduling interval, completes the control instruction analysis of multiple CPIs, and waits for the interrupt signal of the front-end control FPGA chip;

[0030] Step 4: The front-end control CPU chip receives an interrupt signal (from the front-end control FPGA chip) and sends a control instruction of one CPI (in the order of scheduling) to the front-end control FPGA chip;

[0031] Step 5: The front-end control FPGA chip receives the control instruction, synchronously distributes it to the digital subarray and frequency synthesis module according to the timing requirements, and sends the next interrupt signal to the front-end control CPU chip;

[0032] Step 6: After the front-end control CPU chip sends the instructions of the current scheduling interval, the front-end control CPU chip continues to send an interrupt to the back-end processing to request the back-end processing to send the front-end control instruction of the next scheduling interval.

Claims

1. A software-defined radar front-end, comprising front-end control, a digital subarray, a frequency combining module, and a beam combining module, characterized in that: The software-defined radar front end controls uplink control parsing and distribution, as well as timing generation; each digital subarray in the digital subarray generates baseband waveforms and performs up / down conversion, signal amplification, radio frequency signal spatial radiation and reception, and echo sampling. The frequency combining module provides the local oscillator signal and digital subarray required for up and down conversion of the digital subarray, and provides the reference clock signal required for front-end control; the beamforming module completes beamforming processing on the echo signal generated by the digital subarray.

2. The software-based radar front-end according to claim 1, characterized in that: The aforementioned front-end control includes a CPU chip and an FPGA chip. The CPU chip receives commands and parses them into uplink control signals and timing control signals required by the digital subarray and frequency combining module, and then sends them to the FPGA chip. The FPGA chip receives the timing control signals, generates the timing signals required by the software-defined radar front-end as required, and distributes them to the digital subarray and frequency combining module. It also synchronously distributes the uplink control commands required by the digital subarray, frequency combining module, and beam combining module to the digital subarray, frequency combining module, and beam combining module.

3. The software-based radar front-end according to claim 1, characterized in that: The digital subarray receives uplink control signals and timing control signals, generates baseband waveforms as required, and performs up / down conversion, signal amplification, RF signal spatial radiation and reception, and echo sampling, then sends the echo data to the beamforming module. The beamforming module receives uplink control signals, generates beam data as required, and sends the beam data down to the backend for processing. The frequency combining module receives uplink control signals and timing control signals, generates the local oscillator signal and clock signal required by the digital subarray as required, and distributes the local oscillator signal and clock signal to the digital subarray array through the network.

4. The software-based radar front-end according to claim 1, characterized in that: When the software-defined radar front-end is running, the CPU chip of the front-end control sends an interrupt signal to the back-end processing. After receiving the interrupt signal, the back-end processing sends the front-end control command containing multiple CPI control commands for the current scheduling interval to the CPU chip of the front-end control. The CPU chip of the front-end control receives the front-end control command for the current scheduling interval, completes the command parsing, and waits for the interrupt signal from the FPGA chip of the front-end control. Upon receiving an interrupt signal, it sends one CPI control command in the scheduling order. After receiving the control command, the FPGA chip of the front-end control synchronously distributes it to the digital subarray and frequency combining module according to the timing requirements, and sends the next interrupt signal to the CPU chip of the front-end control. After the CPU chip of the front-end control finishes sending the commands for the current scheduling interval, it continues to send an interrupt to the back-end processing, requesting the back-end processing to send the front-end control command for the next scheduling interval.

5. A control method utilizing the software-based radar front-end as described in claim 1, characterized in that... Includes the following steps: Step 1: The CPU chip controlled by the front end sends an interrupt signal to the back end for processing; Step 2: After receiving the interrupt signal, the backend processing sends the frontend control instructions containing multiple CPI control instructions for this scheduling interval to the CPU chip of the frontend control. Step 3: The CPU chip of the front-end control receives the front-end control instruction for this scheduling interval, completes instruction parsing, and waits for the interrupt signal from the FPGA chip of the front-end control. Step 4: The CPU chip of the front-end control receives an interrupt signal from the FPGA chip of the front-end control, that is, it sends a CPI control instruction to the FPGA chip of the front-end control in the order of scheduling. Step 5: After receiving the control command, the FPGA chip of the front-end control synchronously distributes it to the digital subarray and frequency combining module according to the timing requirements, and sends the next interrupt signal to the CPU chip of the front-end control. Step 6: After the front-end control CPU chip finishes sending the instructions for this scheduling interval, the front-end control CPU chip continues to send an interrupt signal to the back-end processing, requesting the back-end processing to send the front-end control instructions for the next scheduling interval.

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