Access method and device of network register model
By establishing a STAC network access path for the SoC chip and optimizing the JTAG scanning process, the problem of high JTAG scanning overhead in register read/write operations is solved, resulting in a more efficient testing method.
Patent Information
- Application Number
- CN202511187030.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-21
- Publication Date
- 2025-12-19
AI Technical Summary
In existing technologies, when testing SoC chips via the JTAG interface, register read and write operations require opening the scan chain, resulting in significant JTAG scan overhead. Reducing JTAG scan overhead has become an urgent problem to be solved.
By establishing the access path of the target TDR, determining the status of the STAC network, obtaining the access path of the previous TDR, and opening the STAC network nodes to be opened, the number of nodes opened is reduced, thus optimizing the JTAG scanning process.
It reduces the overhead of JTAG scanning, improves testing efficiency, and lowers testing costs.
Smart Images
Figure CN121166471A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer technology, and more specifically to a method and apparatus for accessing a network register model. Background Technology
[0002] As the integration scale of System-on-Chip (SoC) chips increases and their designs become more complex, higher demands are being placed on SoC chip testing. To meet these testing requirements, chip testing is typically conducted through the Joint Test Action Group (JTAG) interface.
[0003] When performing JTAG-based testing, register read / write operations need to be converted into JTAG scan chain operations. This involves scanning JTAG data into the Test Data Register (TDR) using a JTAG register adapter. This scanning process is implemented using the JTAG register adapter's `reg2bus` and `bus2reg` functions. The `reg2bus` function queries the TDR's routing information, then concatenates the TDR address and the data to be written to generate the IR and DR, which are then passed to the JTAG driver to complete the register read / write operation. However, before performing a register read / write operation, the TDR scan chain needs to be opened. Each register read / write operation requires opening the corresponding TDR scan chain, resulting in significant JTAG scanning overhead. Therefore, proposing a register access method that reduces the overhead of JTAG scanning has become a crucial issue that urgently needs to be addressed in this field. Summary of the Invention
[0004] To address the problems in the prior art, embodiments of the present invention provide a method and apparatus for accessing a network register model, which can at least partially solve the problems existing in the prior art.
[0005] In a first aspect, the present invention proposes a method for accessing a network register model, comprising:
[0006] Based on the access address of the target TDR and the target STAC network, the access path of the target TDR is obtained; wherein, the target STAC network is pre-established, including STAC network nodes at all levels and corresponding hierarchical relationships; the access path of the target TDR includes the STAC network nodes at all levels to which the target TDR belongs;
[0007] If it is determined that the target STAC network is in an open state, then the access path of the previous TDR is obtained; the access path of the previous TDR includes the STAC network nodes at all levels to which the previous TDR belongs;
[0008] If, based on the access path of the target TDR and the previously opened access path, it is determined that there is a STAC network node to be opened in the access path of the target TDR, then the STAC network node to be opened in the access path of the target TDR is opened.
[0009] Furthermore, the STAC network nodes to be opened in the access path for opening the target TDR include:
[0010] Select the SIB corresponding to the current STAC network node in the access path of the target TDR; wherein, the current STAC network node is the lowest-level STAC network node that has been opened in the access path of the target TDR.
[0011] Configure the SIB corresponding to the current STAC network node to open a path from the current STAC network node to the next level STAC network node to be opened.
[0012] Furthermore, the network register model access method provided in this embodiment of the invention further includes:
[0013] If it is determined that the access address of the target TDR is the same as the access address of the previous TDR, or the access path of the target TDR is the same as the access path of the previous TDR, then it is determined that the access path of the target TDR is open.
[0014] Furthermore, the network register model access method provided in this embodiment of the invention further includes:
[0015] If it is determined that the target STAC network is in a closed state, then the access path of the target TDR is opened based on the STAC network nodes at all levels to which the target TDR belongs, including the access path of the target TDR.
[0016] Furthermore, the network register model access method provided in this embodiment of the invention further includes:
[0017] Obtain the register bit width value of the target TDR;
[0018] The register bit width value of the target TDR is stored in a dynamic array; wherein the dynamic array is pre-established.
[0019] Based on the register bit width value stored in the dynamic array, create the register object of the target TDR.
[0020] Secondly, the present invention proposes an access device for a network register model, comprising:
[0021] The access path acquisition module is used to obtain the access path of the target TDR based on the access address of the target TDR and the target STAC network; wherein, the target STAC network is pre-established and includes STAC network nodes at all levels and corresponding hierarchical relationships; the access path of the target TDR includes the STAC network nodes at all levels to which the target TDR belongs;
[0022] The judgment module is used to obtain the access path of the previous TDR after determining that the target STAC network is in an open state; the access path of the previous TDR includes the STAC network nodes at all levels to which the previous TDR belongs;
[0023] The STAC network node opening module is used to open the STAC network node to be opened in the access path of the target TDR if it is determined that there is a STAC network node to be opened in the access path of the target TDR based on the access path of the target TDR and the access path opened last time.
[0024] Furthermore, the STAC network node activation module includes:
[0025] The selection unit is used to select the SIB corresponding to the current STAC network node in the access path of the target TDR; wherein, the current STAC network node is the lowest-level STAC network node that has been opened in the access path of the target TDR.
[0026] The configuration unit is used to configure the SIB corresponding to the current STAC network node to open a path from the current STAC network node to the next level STAC network node to be opened.
[0027] Thirdly, the present invention provides a computer device including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the program to implement the network register model access method described in any of the above embodiments.
[0028] Fourthly, the present invention provides a computer-readable storage medium storing a computer program / instructions that, when executed by a processor, implement the network register model access method described in any of the above embodiments.
[0029] Fifthly, the present invention provides a computer program product, including a computer program / instruction that, when executed by a processor, implements the network register model access method described in any of the above embodiments.
[0030] The network register model access method and apparatus provided in this invention can obtain the access path of a target TDR based on the access address of the target TDR and the target STAC network. The target STAC network is pre-established and includes STAC network nodes at various levels and corresponding hierarchical relationships. The access path of the target TDR includes the STAC network nodes at various levels to which the target TDR belongs. If it is determined that the target STAC network is in an open state, the access path of the previous TDR is obtained. The access path of the previous TDR includes the STAC network nodes at various levels to which the previous TDR belongs. If, based on the access path of the target TDR and the previously opened access path, it is determined that there are STAC network nodes to be opened in the access path of the target TDR, then the STAC network nodes to be opened in the access path of the target TDR are opened. This reduces the number of opened STAC network nodes, thereby reducing the overhead of JATG scanning. Attached Figure Description
[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:
[0032] Figure 1 This is a flowchart illustrating the access method of the network register model provided in the first embodiment of the present invention.
[0033] Figure 2 This is a schematic diagram of the STAC network provided in the second embodiment of the present invention.
[0034] Figure 3 This is a flowchart illustrating the access method of the network register model provided in the third embodiment of the present invention.
[0035] Figure 4 This is a flowchart illustrating the access method of the network register model provided in the fourth embodiment of the present invention.
[0036] Figure 5 This is a schematic diagram of the access device for the network register model provided in the fifth embodiment of the present invention.
[0037] Figure 6 This is a schematic diagram of the access device for the network register model provided in the sixth embodiment of the present invention.
[0038] Figure 7 This is a schematic diagram of the access device for the network register model provided in the seventh embodiment of the present invention.
[0039] Figure 8 This is a schematic diagram of the access device for the network register model provided in the eighth embodiment of the present invention.
[0040] Figure 9 This is a schematic diagram of the physical structure of a computer device provided in the ninth embodiment of the present invention. Detailed Implementation
[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments and descriptions of the present invention are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other. The acquisition, storage, use, and processing of data in the technical solutions of this application all comply with the relevant provisions of laws and regulations. The user information in the embodiments of this application is obtained through legal and compliant means, and the acquisition, storage, use, and processing of user information have been agreed upon by the customer.
[0042] To facilitate understanding of the technical solution provided in this application, the relevant content of the technical solution in this application will be explained below.
[0043] Universal Verification Methodology (UVM) is a verification platform development framework based on the SystemVerilog class library. Verification engineers can use its reusable components to build functional verification environments with standardized hierarchical structures and interfaces.
[0044] IEEE 1687: IEEE 1687 is a general standard for DFT multilayer network architecture. Its core contents include the Instrument Connectivity Language (ICL) and the Procedural Description Language (PDL).
[0045] Joint Test Action Group (JTAG): This is the common name for IEEE standard 1149.1, which is used to verify the functionality of designed and tested printed circuit boards.
[0046] Design for Testability (DFT) is an integrated circuit design technique that incorporates special structures into the circuit during the design phase so that the design can be tested after completion.
[0047] Test Data Register (TDR): Composed of multiple data registers, each implemented using a shift register, allowing data to be written to the selected register via serial input. It is a key component in boundary scan testing, primarily used to store and transmit test data during the testing process, helping to verify the functionality of connections, pin functions, and internal logic on integrated circuits (ICs) or circuit boards.
[0048] Segment Insertion Bit (SIB): A basic unit of the IEEE 1687 standard specification, the SIB circuit characteristics enable plug-and-play functionality and flexible configuration of IJTAG networks. Essentially, the SIB is a single-bit, special TDR used to control the test path.
[0049] The Scalable Test Access Controller (STAC) is a TAP controller specified in the IEEE 1687 standard. STAC is used to interpret instructions and schedule specific TDR operations.
[0050] STAC Router (STR): In a STAC network, it functions as a router.
[0051] Master Test Access Port Controller (MTAP): This is a TAP controller specified in the IEEE 1149.1 standard. It is used to manage and control the operation of the Test Access Port (TAP). Since a System-on-a-Chip (SoC) contains multiple functional modules and IP cores, it needs to use the MTAP to uniformly manage the test access of each module and realize comprehensive testing of the entire chip.
[0052] In Design for Test (DFT), the entire chip can be viewed as a collection of numerous registers and combinational logic between them. A scan chain is formed by replacing some or all of the chip's registers with scannable registers and connecting them in a chain. During chip testing, external test equipment can send access requests to the MTAP (Test Module Access Point), carrying the access address of the TDR (Test Module Data Rate) to be accessed. The JTAG register adapter processes the access request and returns the corresponding result.
[0053] Network Register Model: In DFT, the Device Under Test (DUT) can be abstracted into a network register model. DUTs include, but are not limited to, chips, circuit boards, etc.
[0054] Figure 1 This is a flowchart illustrating the network register model access method provided in the first embodiment of the present invention, as shown below. Figure 1 As shown, the network register model access method provided in this embodiment of the invention includes:
[0055] S101. Obtain the access path of the target TDR based on the access address of the target TDR and the target STAC network; wherein, the target STAC network is pre-established and includes STAC network nodes at all levels, access addresses of TDRs corresponding to AC nodes at all levels, and hierarchical relationships of STAC network nodes at all levels; the access path of the target TDR includes the STAC network nodes at all levels to which the target TDR belongs.
[0056] Specifically, based on the access address of the target TDR, the access address of the target TDR is queried in the target STAC network. That is, the access addresses of the TDRs corresponding to each level of STAC network node are checked to see if there is an access address that is the same as the access address of the target TDR. If it exists, the access path of the target TDR is determined according to the level of SATAC to which the queried TDR access address belongs. The execution entity of the network register model access method provided in this embodiment of the invention can be MTAP.
[0057] The target TDR is the TDR that needs to be accessed. The target STAC network is a pre-established network of multi-level STAC network nodes, with each STAC network node corresponding to at least one TDR, and each TDR has a unique access address.
[0058] For example, the target STAC network is designed based on the hierarchical structure of the device under test (DUT) registers, and can be a tree structure, such as... Figure 2 As shown, STR0, STR00, STR01, STC000, STC000, STC001, STC002, and STC003 are STAC network nodes.
[0059] For example, based on the access address of the target TDR in Figure 2In the STAC network shown, query the access address of the target TDR. If the access address of the TDR corresponding to STC001 is the same as the access address of the target TDR, then STR0, STR00, and STC001 are the STAC network nodes of each level to which the target TDR belongs, and the access path of the target TDR includes STR0, STR00, and STC001.
[0060] S102. If it is determined that the target STAC network is in an open state, then obtain the access path of the previous TDR; the access path of the previous TDR includes the STAC network nodes at all levels to which the previous TDR belongs;
[0061] Specifically, after a target STAC network's TDR is accessed, the target STAC network will be in an open state, and this open state can be recorded. If it is determined that the target STAC network is in an open state, then the access path of the previous TDR is obtained. The previous TDR refers to the most recently accessed TDR of the STAC network. The access path of the previous TDR includes the STAC network nodes at all levels to which the previous TDR belongs.
[0062] S103. If, based on the access path of the target TDR and the previously opened access path, it is determined that there is a STAC network node to be opened in the access path of the target TDR, then the STAC network node to be opened in the access path of the target TDR is opened.
[0063] Specifically, the access path of the target TDR is compared with the previously opened access path. STAC network nodes in the target TDR's access path that are different from those in the previously opened access path are identified as STAC network nodes in the target TDR's access path that need to be opened. To access the target TDR, these STAC network nodes in the target TDR's access path need to be opened. STAC network nodes in the target TDR's access path that are the same as those in the previously opened access path do not need to be opened again.
[0064] For the target TDR, the number of STAC network nodes that need to be opened is reduced because the previously opened access path can be utilized, thereby reducing the overhead of JATG scanning.
[0065] For example, such as Figure 2The target STAC network shown is a tree structure. STR0 is the first-level STAC network node, i.e., the root node; STR00 and STR01 are second-level STAC network nodes; and STC000, STC001, STC002, and STC003 are third-level STAC network nodes. STR0, STR00, and STR01 can be STRs, which have routing controllers. STRs are based on the IEEE 1687 protocol and are scalable, allowing the number of CR controllers to be flexibly changed according to needs. STC000, STC001, STC002, and STC003 can be STACs, which have corresponding TDRs and are connected to their respective TDRs.
[0066] The target TDR is TDR STC002, and the previous TDR is TDR STC000. The access path of the target TDR is STR0 -> STR01 -> STC002, and the access path of the previous TDR is STR0 -> STR00 -> STC000. Comparing the access paths of the target TDR and the previous TDR, a common STAC network node, STR0, is found. The STAC network nodes STR01 and STC002 in the target TDR's access path are different from those in the previous TDR's access path. STR01 and STC002 are designated as STAC network nodes to be opened. Since STR0 is already opened to access the target TDR, it does not need to be opened again; opening STR01 and STC002 is sufficient, reducing the overhead of JATG scanning.
[0067] The network register model access method provided in this embodiment of the invention can obtain the access path of a target TDR based on the access address of the target TDR and the target STAC network. The target STAC network is pre-established and includes STAC network nodes at various levels and corresponding hierarchical relationships. The access path of the target TDR includes the STAC network nodes at various levels to which the target TDR belongs. If it is determined that the target STAC network is in an open state, the access path of the previous TDR is obtained. The access path of the previous TDR includes the STAC network nodes at various levels to which the previous TDR belongs. If, based on the access path of the target TDR and the previously opened access path, it is determined that there are STAC network nodes to be opened in the access path of the target TDR, then the STAC network nodes to be opened in the access path of the target TDR are opened. This reduces the number of opened STAC network nodes, thereby reducing the overhead of JATG scanning.
[0068] Figure 3 This is a flowchart illustrating the network register model access method provided in the third embodiment of the present invention, as shown below. Figure 3 As shown, based on the above embodiments, the STAC network nodes to be opened in the access path to open the target TDR further include:
[0069] S301. Select the SIB corresponding to the current STAC network node in the access path of the target TDR; wherein, the current STAC network node is the lowest-level STAC network node that has been opened in the access path of the target TDR.
[0070] Specifically, the lowest-level STAC network node that is already open is obtained from the access path of the target TDR and designated as the current STAC network node. The SIB corresponding to the current STAC network node can be selected by configuring the SIB.
[0071] S302. Configure the SIB corresponding to the current STAC network node to open the path from the current STAC network node to the next level STAC network node to be opened.
[0072] Specifically, the SIB corresponding to the current STAC network node is configured so that the current STAC network node can connect to the path of the next level STAC network node to be opened, that is, the object for establishing the path is written into the SIB corresponding to the selected current STAC network node.
[0073] For example, such as Figure 2 In the target STAC network shown, the address of the control register of the SIB corresponding to STR0 is 8'h13. 8'h13 represents an 8-bit hexadecimal value of 0x13, corresponding to the binary value 00010011. The SIB corresponding to STR0 can be selected by writing {1'b1, 8'h13} to its control register, facilitating subsequent configuration of its control register. 1'b1 represents a 1-bit binary number with a value of 1, and 1 indicates that the following number 8'h13 is the address.
[0074] If STR0 is already open, but STR01 is not, to establish a path between STR0 and STR01, after selecting the SIB corresponding to STR0, write {1'b0, 2'b10} to the control register of the SIB corresponding to STR0 to open the path from STR0 to STR01. 1'b0 represents a 1-bit binary number with a value of 0, indicating a connection mode where a link is established with STR01 corresponding to 2'b10. 2'b10 represents a 2-bit binary number with a value of 10, indicating that a connection is established with STR01. If a connection is established with STR00, it can be represented as 2'b01.
[0075] If there are STAC network nodes to be opened in the access path of the target TDR, they will be opened level by level. Each time a STAC network node to be opened is opened, that STAC network node will become the lowest level STAC network node already opened in the access path of the target TDR, and can be used as the current STAC network node. The process of steps S301 and S302 is repeated until there are no more STAC network nodes to be opened in the access path of the target TDR.
[0076] Based on the above embodiments, the network register model access method provided by the embodiments of the present invention further includes:
[0077] If it is determined that the access address of the target TDR is the same as the access address of the previous TDR, then it is determined that the access path of the target TDR has been opened.
[0078] Specifically, each TDR has a unique corresponding access address. The access address of the target TDR is compared with the access address of the previous TDR. If the access address of the target TDR is the same as the access address of the previous TDR, it can be determined that the access path of the target TDR has been opened since the access address of the previous TDR has not been closed after being opened.
[0079] Based on the above embodiments, the network register model access method provided by the embodiments of the present invention further includes:
[0080] If it is determined that the access path of the target TDR is the same as the access path of the previous TDR, then it is determined that the access path of the target TDR is open.
[0081] Specifically, the access path of the target TDR is compared with the access path of the previous TDR. If the access path of the target TDR is the same as the access path of the previous TDR, it can be determined that the access path of the target TDR is open since the access address of the previous TDR has not been closed after being opened.
[0082] The access path of the target TDR is the same as that of the previous TDR. The target TDR can be accessed directly through the access path of the previous TDR without having to open the access path of the target TDR again, thus reducing the overhead of JATG scanning.
[0083] Based on the above embodiments, the network register model access method provided by the embodiments of the present invention further includes:
[0084] If it is determined that the target STAC network is in a closed state, then the access path of the target TDR is opened based on the STAC network nodes at all levels to which the target TDR belongs, including the access path of the target TDR.
[0085] Specifically, if it is determined that the target STAC network is in a closed state, then it is necessary to see the STAC network nodes at all levels to which the target TDR belongs in the access path to open the target TDR, so as to open the access path of the target TDR.
[0086] For example, you can query the open status record of the target STAC network. If no open record of the target STAC network is found, then you can determine that the target STAC network is in a closed state.
[0087] Figure 4 This is a flowchart illustrating the network register model access method provided in the fourth embodiment of the present invention, as shown below. Figure 4 As shown, based on the above embodiments, the network register model access method provided by the embodiments of the present invention further includes:
[0088] S401. Obtain the register bit width value of the target TDR;
[0089] Specifically, each TDR has a register bit width value, and the register bit width value of the target TDR can be obtained.
[0090] Because JTAG scan chains can be very long, TDRs can be registers of arbitrary length and width. UVM limits the maximum width of register data using UVM_REG_DATA_WIDTH. To accommodate all TDRs, UVM_REG_DATA_WIDTH is typically set relatively large, leading to excessive memory consumption during register model instantiation and resulting in memory waste. Therefore, this application proposes dynamically configuring the width of each TDR based on its actual width during register instantiation, instead of setting it to a uniform fixed value, to save memory usage.
[0091] S402. Store the register bit width value of the target TDR into a dynamic array; wherein the dynamic array is pre-established;
[0092] Specifically, the register bit width value of the target TDR is stored in a dynamic array, which is pre-established.
[0093] S403. Create a register object for the target TDR based on the register bit width value stored in the dynamic array.
[0094] Specifically, when the target TDR is instantiated, a register object of the target TDR is created. When the register object of the target TDR is created, the register bit width value of the target TDR is read from the dynamic array. Memory is allocated to the register object of the target TDR based on the register bit width value of the target TDR. This allows memory to be allocated according to the actual register bit width value of the target TDR, which reduces memory usage compared to the method of allocating memory by UVM according to a fixed value in the prior art.
[0095] The network register model access method provided in this embodiment of the invention can reduce the number of DFT network scans, accelerate the scanning speed of multi-layer DFT networks, and at the same time realize support for arbitrary bit-width register models, solving the difficulty of TDR modeling with different bit widths.
[0096] Figure 5 This is a schematic diagram of the structure of the access device for the network register model provided in the fifth embodiment of the present invention, as shown below. Figure 5 As shown, the network register model access device provided in this embodiment of the invention includes an access path acquisition module 501, a judgment module 502, and a STAC network node activation module 503, wherein:
[0097] The access path acquisition module 501 is used to obtain the access path of the target TDR based on the access address of the target TDR and the target STAC network; wherein, the target STAC network is pre-established, including STAC network nodes at all levels and corresponding hierarchical relationships; the access path of the target TDR includes the STAC network nodes at all levels to which the target TDR belongs; the judgment module 502 is used to obtain the access path of the previous TDR after determining that the target STAC network is in an open state; the access path of the previous TDR includes the STAC network nodes at all levels to which the previous TDR belongs; the STAC network node opening module 503 is used to open the STAC network node to be opened in the access path of the target TDR if it is determined, based on the access path of the target TDR and the previously opened access path, that there is a STAC network node to be opened in the access path of the target TDR.
[0098] Specifically, the access path acquisition module 501 queries the target STAC network for the access address of the target TDR based on the target TDR's access address. That is, it checks among the access addresses of TDRs corresponding to each level of STAC network nodes to see if there is an access address that is the same as the target TDR's access address. If it exists, then the access path of the target TDR is determined based on the level of SATAC to which the queried TDR's access address belongs.
[0099] After a target STAC network's TDR is accessed, the target STAC network will be in an open state, and this open state can be recorded. If the determination module 502 determines that the target STAC network is in an open state, it obtains the access path of the previous TDR. The previous TDR refers to the most recently accessed TDR of the STAC network. The access path of the previous TDR includes the STAC network nodes at all levels to which the previous TDR belongs.
[0100] The STAC network node opening module 503 compares the access path of the target TDR with the previously opened access path, and identifies STAC network nodes in the target TDR's access path that are different from those in the previously opened access path as STAC network nodes that exist in the target TDR's access path and need to be opened. To access the target TDR, it is necessary to open the STAC network nodes that need to be opened in the target TDR's access path. For STAC network nodes in the target TDR's access path that are the same as those in the previously opened access path, there is no need to open them again.
[0101] The network register model access device provided in this embodiment of the invention can obtain the access path of a target TDR based on the access address of the target TDR and the target STAC network. The target STAC network is pre-established and includes STAC network nodes at various levels and corresponding hierarchical relationships. The access path of the target TDR includes the STAC network nodes at various levels to which the target TDR belongs. If it is determined that the target STAC network is in an open state, the access path of the previous TDR is obtained. The access path of the previous TDR includes the STAC network nodes at various levels to which the previous TDR belongs. If, based on the access path of the target TDR and the previously opened access path, it is determined that there are STAC network nodes to be opened in the access path of the target TDR, then the STAC network nodes to be opened in the access path of the target TDR are opened. This reduces the number of opened STAC network nodes, thereby reducing the overhead of JATG scanning.
[0102] Figure 6 This is a schematic diagram of the structure of the network register model access device provided in the sixth embodiment of the present invention, as shown below. Figure 6 As shown, based on the above embodiments, the STAC network node activation module 503 further includes a selection unit 5031 and a configuration unit 5032, wherein:
[0103] The selection unit 5031 is used to select the SIB corresponding to the current STAC network node in the access path of the target TDR; wherein, the current STAC network node is the lowest-level STAC network node that has been opened in the access path of the target TDR; the configuration unit 5032 is used to configure the SIB corresponding to the current STAC network node to open the path from the current STAC network node to the next level STAC network node to be opened.
[0104] Figure 7 This is a schematic diagram of the structure of the access device for the network register model provided in the seventh embodiment of the present invention, as shown below. Figure 7 As shown, based on the above embodiments, the network register model access device provided in this embodiment further includes a determination module 504, wherein:
[0105] The determining module 504 is used to determine that the access path of the target TDR is open after determining that the access address of the target TDR is the same as the access address of the previous TDR, or the access path of the target TDR is the same as the access path of the previous TDR.
[0106] Based on the above embodiments, the STAC network node activation module 503 is further configured to:
[0107] After determining that the target STAC network is in a closed state, the access path of the target TDR is opened based on the STAC network nodes at all levels to which the target TDR belongs, including the access path of the target TDR.
[0108] Figure 8 This is a schematic diagram of the structure of the access device for the network register model provided in the eighth embodiment of the present invention, as shown below. Figure 8 As shown, based on the above embodiments, the network register model provided in this embodiment further includes an acquisition module 505, a storage module 506, and a creation module 507, wherein:
[0109] The acquisition module 505 is used to acquire the register bit width value of the target TDR; the storage module 506 is used to store the register bit width value of the target TDR into a dynamic array; wherein, the dynamic array is pre-established; the creation module 507 is used to create a register object of the target TDR according to the register bit width value stored in the dynamic array.
[0110] The embodiments of the device provided in this invention can be used to execute the processing flow of the above-described method embodiments. Its functions will not be repeated here, but can be referred to the detailed description of the above-described method embodiments.
[0111] Figure 9This is a schematic diagram of the physical structure of the computer device provided in the ninth embodiment of the present invention, as shown below. Figure 9 As shown, the computer device may include: a processor 901, a communication interface 902, a memory 903, and a communication bus 904, wherein the processor 901, the communication interface 902, and the memory 903 communicate with each other through the communication bus 904. The processor 901 can call logical instructions in the memory 903 to execute the methods provided in the above-described method embodiments, such as: obtaining the access path of the target TDR based on the access address of the target TDR and the target STAC network; wherein the target STAC network is pre-established and includes STAC network nodes at all levels and corresponding hierarchical relationships; the access path of the target TDR includes the STAC network nodes at all levels to which the target TDR belongs; if it is determined that the target STAC network is in an open state, then the access path of the previous TDR is obtained; the access path of the previous TDR includes the STAC network nodes at all levels to which the previous TDR belongs; if it is determined, based on the access path of the target TDR and the previously opened access path, that there is a STAC network node to be opened in the access path of the target TDR, then the STAC network node to be opened in the access path of the target TDR is opened.
[0112] Furthermore, the logical instructions in the aforementioned memory 903 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0113] This embodiment discloses a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions, and when the program instructions are executed by a computer, the computer can execute the methods provided in the above-described method embodiments, such as: obtaining the access path of the target TDR based on the access address of the target TDR and the target STAC network; wherein the target STAC network is pre-established, including STAC network nodes at all levels and corresponding hierarchical relationships; the access path of the target TDR includes the STAC network nodes at all levels to which the target TDR belongs; if it is determined that the target STAC network is in an open state, then the access path of the previous TDR is obtained; the access path of the previous TDR includes the STAC network nodes at all levels to which the previous TDR belongs; if it is determined, based on the access path of the target TDR and the previously opened access path, that there is a STAC network node to be opened in the access path of the target TDR, then the STAC network node to be opened in the access path of the target TDR is opened.
[0114] This embodiment provides a computer-readable storage medium storing a computer program that causes a computer to execute the methods provided in the above-described method embodiments. For example, the methods include: obtaining the access path of a target TDR based on its access address and a target STAC network; wherein the target STAC network is pre-established and includes STAC network nodes at various levels and corresponding hierarchical relationships; the access path of the target TDR includes the STAC network nodes at various levels to which the target TDR belongs; if it is determined that the target STAC network is in an open state, then obtaining the access path of the previous TDR; the access path of the previous TDR includes the STAC network nodes at various levels to which the previous TDR belongs; if, based on the access path of the target TDR and the previously opened access path, it is determined that there is a STAC network node to be opened in the access path of the target TDR, then opening the STAC network node to be opened in the access path of the target TDR.
[0115] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0116] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0117] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0118] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0119] In the description of this specification, the references to terms such as "an embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0120] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for accessing a network register model, characterized in that, include: Based on the access address of the target TDR and the target STAC network, the access path of the target TDR is obtained; wherein, the target STAC network is pre-established, including STAC network nodes at all levels and corresponding hierarchical relationships; the access path of the target TDR includes the STAC network nodes at all levels to which the target TDR belongs; If it is determined that the target STAC network is in an open state, then the access path of the previous TDR is obtained; the access path of the previous TDR includes the STAC network nodes at all levels to which the previous TDR belongs; If, based on the access path of the target TDR and the previously opened access path, it is determined that there is a STAC network node to be opened in the access path of the target TDR, then the STAC network node to be opened in the access path of the target TDR is opened.
2. The method according to claim 1, characterized in that, The STAC network nodes to be opened in the access path for opening the target TDR include: Select the SIB corresponding to the current STAC network node in the access path of the target TDR; wherein, the current STAC network node is the lowest-level STAC network node that has been opened in the access path of the target TDR. Configure the SIB corresponding to the current STAC network node to open a path from the current STAC network node to the next level STAC network node to be opened.
3. The method according to claim 1, characterized in that, Also includes: If it is determined that the access address of the target TDR is the same as the access address of the previous TDR, or the access path of the target TDR is the same as the access path of the previous TDR, then it is determined that the access path of the target TDR is open.
4. The method according to claim 1, characterized in that, Also includes: If it is determined that the target STAC network is in a closed state, then the access path of the target TDR is opened based on the STAC network nodes at all levels to which the target TDR belongs, including the access path of the target TDR.
5. The method according to any one of claims 1 to 4, characterized in that, Also includes: Obtain the register bit width value of the target TDR; The register bit width value of the target TDR is stored in a dynamic array; wherein the dynamic array is pre-established. Based on the register bit width value stored in the dynamic array, create the register object of the target TDR.
6. An access device for a network register model, characterized in that, include: The access path acquisition module is used to obtain the access path of the target TDR based on the access address of the target TDR and the target STAC network; wherein, the target STAC network is pre-established and includes STAC network nodes at all levels and corresponding hierarchical relationships; the access path of the target TDR includes the STAC network nodes at all levels to which the target TDR belongs; The judgment module is used to obtain the access path of the previous TDR after determining that the target STAC network is in an open state; the access path of the previous TDR includes the STAC network nodes at all levels to which the previous TDR belongs; The STAC network node opening module is used to open the STAC network node to be opened in the access path of the target TDR if it is determined that there is a STAC network node to be opened in the access path of the target TDR based on the access path of the target TDR and the access path opened last time.
7. The apparatus according to claim 6, characterized in that, The STAC network node activation module includes: The selection unit is used to select the SIB corresponding to the current STAC network node in the access path of the target TDR; wherein, the current STAC network node is the lowest-level STAC network node that has been opened in the access path of the target TDR. The configuration unit is used to configure the SIB corresponding to the current STAC network node to open a path from the current STAC network node to the next level STAC network node to be opened.
8. A computer device, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the method according to any one of claims 1 to 5.
9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program / instructions that, when executed by a processor, implement the method described in any one of claims 1 to 5.
10. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, they implement the method described in any one of claims 1 to 5.