Driving circuit, driving method and display device of display panel

Abstract

The application discloses a display panel driving circuit, a driving method and a display device. A display area of the display panel is divided into a first display area and a second display area. A plurality of rows of sub-pixels are arranged in the display panel. Each row of sub-pixels is provided with at least two scanning lines. One scanning line is connected with a sub-pixel in the first display area, and the other scanning line is connected with a sub-pixel in the second display area. A first gate driving unit inputs a first scanning signal to a corresponding first row of scanning lines. A second gate driving unit inputs a second scanning signal to a corresponding second row of scanning lines. A third gate driving unit inputs a fourth scanning signal to a corresponding third row of scanning lines. A fourth gate driving unit inputs a third scanning signal to a corresponding fourth row of scanning lines. The application changes the traditional line-by-line scanning. In every four rows, the scanning sequence of the last two rows is exchanged, and HSR (Hardware Super Resolution) driving under a DRD (Double Rate Driving) architecture is realized.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a driving circuit, driving method and display device for a display panel. Background Technology

[0002] Liquid Crystal Displays (LCDs) have many advantages, such as thinness, energy saving, and no radiation, and are widely used. In the LCD display industry, in order to reduce costs, a dual rate driver (DRD) driving method can be used. When using the DRD driving method, two sets of scanning signals are used to drive the pixels in the same row. In the first row of pixels, two adjacent signals are used to drive the pixels. Products using the DRD driving method can reduce the number of data lines and the number of COF (Chip On Film), thus achieving the goal of reducing costs. Therefore, the DRD design is currently being used more and more.

[0003] In current DRD technology, the same data line is often connected to sub-pixel units of different colors. That is, sub-pixels in the same column may be connected to different data lines. Therefore, the driving voltage on the data line must change line by line during the display of one frame of image. When HSR (Hardware Super Resolution) mode is required, it is necessary to mix the data of certain rows with those of their adjacent rows. Currently, DRD display panels cannot share the voltage on the data lines, which makes it impossible to implement functions such as HSR. Summary of the Invention

[0004] The purpose of this application is to provide a driving circuit, driving method, and display device for a display panel, enabling functions such as HSR display.

[0005] This application discloses a driving circuit for a display panel. Along the extension direction of the scan lines, the display area of ​​the display panel is divided into a first display area and a second display area. Each first display area has N columns of sub-pixels, and each second display area has N columns of sub-pixels. Along the extension direction of the data lines, the display panel has multiple rows of sub-pixels. Each row of sub-pixels corresponds to at least two rows of scan lines. One row of scan lines connects to the N columns of pixels in the first display area, and the other row of scan lines connects to the N columns of sub-pixels in the second display area.

[0006] The driving circuit includes multiple gate driving units, with each group of four gate driving units forming a gate driving unit group. The four gate driving units are a first gate driving unit, a second gate driving unit, a third gate driving unit, and a fourth gate driving unit. The first gate driving unit inputs a first scan signal to the corresponding first row of scan lines, the second gate driving unit inputs a second scan signal to the corresponding second row of scan lines, the third gate driving unit inputs a fourth scan signal to the corresponding third row of scan lines, and the fourth gate driving unit inputs a third scan signal to the corresponding fourth row of scan lines.

[0007] Wherein, N is a natural number greater than or equal to 3, the data lines corresponding to the first column of sub-pixels in the first display area are connected to the data lines corresponding to the first column of sub-pixels in the second display area, the data lines corresponding to the second column of sub-pixels in the first display area are connected to the data lines corresponding to the second column of sub-pixels in the second display area, ..., the data lines corresponding to the Nth column of sub-pixels in the first display area are connected to the data lines corresponding to the Nth column of sub-pixels in the second display area.

[0008] Optionally, the driving circuit includes at least four clock signal lines, with different clock signal lines connected to the corresponding gate driving units and outputting clock signals to the corresponding gate driving units. The gate driving units generate scan signals based on the frame start signal and the clock signals and output them to the scan lines.

[0009] In the first gate driving unit group, the first gate driving unit, the second gate driving unit, the third gate driving unit, and the fourth gate driving unit respectively output a first scan signal to the first scan line, output a second scan signal to the second scan line, output a third scan signal to the fourth scan line, and output a fourth scan signal to the third scan line. The first scan signal, the second scan signal, the third scan signal, and the fourth scan signal are transmitted independently and do not interfere with each other. The input terminals of the four gate driving units in the second gate driving unit group are connected to the output terminals of the four gate driving units in the corresponding first gate driving unit group as the start signal of the current stage.

[0010] Optionally, each scan signal includes a first level signal time period and a second level signal time period. The first level signal time period outputs a high level signal to the scan line, and the second level signal time period outputs a low level signal to the scan line. The start time of the first level signal time period of the scan signal corresponding to the current scan line is earlier than the end time of the first level signal time period of the scan signal corresponding to the previous scan line, and is also earlier than the start time of the first level signal time period of the scan signal corresponding to the next scan line.

[0011] Optionally, the duration between the start time of the first level signal time period of the scan signal corresponding to the current row scan line and the start time of the first level signal time period of the scan signal corresponding to the previous row scan line is greater than or equal to 1 / 2 of the duration of the first level signal time period.

[0012] Optionally, the driving circuit includes a data driving module and a flip-chip film. The data driving module outputs a data driving signal to the fan-out trace through the data channel on the flip-chip film, and outputs it to the data line through the fan-out trace. In this case, the two data lines corresponding to the first column of sub-pixels in the first display area and the first column of sub-pixels of the same color and polarity in the second display area are connected to the same data channel through the same fan-out trace.

[0013] Optionally, both the first display area and the second display area are provided with multiple sub-pixel columns. The number of sub-pixel columns in each display area is a multiple of 6. Along the extension direction of the data line, each row of sub-pixels includes multiple sub-pixels, which are red sub-pixels, green sub-pixels, and blue sub-pixels respectively. In each row of sub-pixels, the red sub-pixels, green sub-pixels, and blue sub-pixels are arranged in sequence. The polarity of the red sub-pixels, green sub-pixels, and blue sub-pixels in every 6 columns is arranged in either +-+-+- or -+-+-+.

[0014] In this configuration, the two scan lines corresponding to each row of sub-pixels are respectively set above and below each row of sub-pixels.

[0015] Optionally, the driving circuit further includes a first switching circuit, which is disposed on the side of the data line away from the data driving module. The first switching circuit includes multiple first switches, each of which is connected to two data lines corresponding to sub-pixels of the same color in the first and second display areas. Each scan signal includes a first level signal time period and a second level signal time period. The first level signal time period outputs a high-level signal to the scan line, and the second level signal time period outputs a low-level signal to the scan line. The first switch is controlled to be turned on during the time period between the start of the first level signal time period of the scan signal corresponding to the current row scan line and the start of the first level signal time period of the scan signal corresponding to the next row scan line.

[0016] This application also discloses a driving method for a display panel, using any of the driving circuits described above to drive the display panel, the driving method comprising the steps of:

[0017] The first, second, third, and fourth gate driving units in each gate driving unit group generate a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal based on the frame start signal / Gn-4 level scan signal and the clock signal; and

[0018] Output a first scan signal to the first scan line and control the first row of sub-pixels in the first display area to charge; output a second scan signal to the second scan line and control the first row of sub-pixels in the second display area to charge; output a third scan signal to the fourth scan line and control the second row of sub-pixels in the second display area to charge; output a fourth scan signal to the third scan line and control the second row of sub-pixels in the first display area to charge.

[0019] Optionally, the driving circuit further includes a first switching circuit, which is disposed on the side of the data line away from the data driving module. The first switching circuit includes multiple first switches, each of which connects two data lines corresponding to sub-pixels of the same color in the first and second display areas. Each scan signal includes a first level signal time period and a second level signal time period. The first level signal time period outputs a high-level signal to the scan line, and the second level signal time period outputs a low-level signal to the scan line. The steps of outputting a first scan signal to the first row of scan lines and controlling the first row of sub-pixels in the first display area to charge, outputting a second scan signal to the second row of scan lines and controlling the first row of sub-pixels in the second display area to charge, outputting a third scan signal to the fourth row of scan lines and controlling the second row of sub-pixels in the second display area to charge, and outputting a fourth scan signal to the third row of scan lines and controlling the second row of sub-pixels in the first display area to charge include:

[0020] A first scan signal is output to the first scan line and controls the first row of sub-pixels in the first display area to charge. At the beginning of the first level signal time period of the first scan signal, the first switch is turned on and the corresponding data line is connected. After half the duration of the first level signal time period of the first scan signal, a second scan signal is output to the second scan line and controls the first row of sub-pixels in the second display area to charge. After half the duration of the first level signal time period of the second scan signal, a third scan signal is output to the fourth scan line and controls the second row of sub-pixels in the second display area to charge. After half the duration of the first level signal time period of the third scan signal, a fourth scan signal is output to the third scan line and controls the second row of sub-pixels in the first display area to charge. After charging is completed, the first switch is turned off within a preset time.

[0021] This application also discloses a display device, the display device including a display panel and a driving circuit as described in any of the above claims, the driving circuit driving the display panel using a driving method as described in any of the above claims.

[0022] Compared to commonly used DRD display panels, this application provides a novel DRD display panel that partitions the display panel, connecting the data lines of different areas together to share data signals. Simultaneously, in every four gate driving units, the first gate driving unit is connected to the first scan line, the second gate driving unit to the second scan line, the third gate driving unit to the fourth scan line, and the fourth gate driving unit to the third scan line. This changes the commonly used progressive scanning; in every four lines per cycle, the scanning order of the last two scan lines is swapped. After the first and second scan lines are scanned sequentially, the fourth scan line is scanned, and then the third scan line is scanned. This achieves HSR (Hardware Super Resolution) driving under the DRD (Double Rate Driving) architecture. When displaying mixed data from adjacent lines, voltage sharing on the data lines can be achieved. Attached Figure Description

[0023] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without any creative effort. In the drawings:

[0024] Figure 1 This is a schematic diagram of the driving circuit and display panel of the first embodiment of this application;

[0025] Figure 2 This is a schematic diagram of the gate driving unit structure of the driving circuit in the first embodiment of this application;

[0026] Figure 3a This is a schematic diagram of the driving circuit and display panel structure according to the second embodiment of this application;

[0027] Figure 3b This corresponds to the second embodiment of this application. Figure 3a Schematic color illustration of the driving circuit and display panel structure;

[0028] Figure 4 This is a schematic diagram of the gate driving unit structure of the driving circuit of the second embodiment of this application;

[0029] Figure 5 This is a schematic diagram of the scanning signal waveform according to the second embodiment of this application;

[0030] Figure 6 This is a schematic diagram of the driving circuit and display panel according to the third embodiment of this application;

[0031] Figure 7 This is a schematic diagram of the driving circuit and display panel according to the fourth embodiment of this application;

[0032] Figure 8 This is a schematic flowchart of the driving method for the display panel according to the fifth embodiment of this application;

[0033] Figure 9 This is a schematic flowchart of the driving method for the display panel according to the sixth embodiment of this application;

[0034] Figure 10 This is a schematic diagram of the structure of the display device according to the seventh embodiment of this application.

[0035] Among them, 100 is the driving circuit; 110 is the gate driving unit group; 111 is the first gate driving unit; 112 is the second gate driving unit; 113 is the third gate driving unit; 114 is the fourth gate driving unit; 120 is the data driving module; 130 is the flip-chip film; 140 is the first switching circuit; 141 is the first switch; 200 is the display panel; 210 is the display area; 211 is the first display area; 212 is the second display area; 220 is the sub-pixel; 230 is the scan line; 240 is the data line; 250 is the fan-out area; 251 is the fan-out trace; 300 is the display device; G1 is the first scan signal; G2 is the second scan signal; G3 is the third scan signal; G4 is the fourth scan signal; D1 is the first data line; D2 is the second data line; ...; Dm is the m-th data line. Detailed Implementation

[0036] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0037] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments.

[0038] like Figure 1 As shown, as a first embodiment of this application, a driving circuit 100 for a display panel 200 is disclosed, referencing... Figure 1 and Figure 2As shown, along the extension direction of the scan line 230, the display area 210 of the display panel 200 is divided into a first display area 211 and a second display area 212. Each first display area 211 has N columns of sub-pixels 220, and each second display area 212 has N columns of sub-pixels 220. Along the extension direction of the data line 240, the display panel 200 has multiple rows of sub-pixels 220. Each row of sub-pixels 220 corresponds to at least two rows of scan lines 230. One row of scan lines 230 connects to the N columns of pixels in the first display area 211, and the other row of scan lines 230 connects to the N columns of sub-pixels 220 in the second display area 212. The driving circuit 100 includes multiple gate driving units, with four gate driving units forming one gate driving unit. Group 110 comprises four gate driving units: a first gate driving unit 111, a second gate driving unit 112, a third gate driving unit 113, and a fourth gate driving unit 114. The first gate driving unit 111 inputs a first scan signal G1 to the corresponding first row scan line 230, the second gate driving unit 112 inputs a second scan signal G2 to the corresponding second row scan line 230, the third gate driving unit 113 inputs a fourth scan signal G4 to the corresponding third row scan line 230, and the fourth gate driving unit 114 inputs a third scan signal G3 to the corresponding fourth row scan line 230. The first, second, third, and fourth scan signals are transmitted independently and do not interfere with each other.

[0039] Where N is a natural number greater than or equal to 3, the data lines 240 corresponding to the first column of sub-pixels 220 in the first display area 211 and the first column of sub-pixels 220 in the second display area 212 are connected, the data lines 240 corresponding to the second column of sub-pixels 220 in the first display area 211 and the second column of sub-pixels 220 in the second display area 212 are connected, ..., the data lines 240 corresponding to the Nth column of sub-pixels 220 in the first display area 211 and the Nth column of sub-pixels 220 in the second display area 212 are connected. For example, with N equal to 3, the data lines 240 corresponding to the first column of sub-pixels 220 in the first display area 211 and the first column of sub-pixels 220 in the second display area 212 are connected. The data lines 240 corresponding to the second column of sub-pixels 220 in the first display area 211 and the second column of sub-pixels 220 in the second display area 212 are also connected. The data lines 240 corresponding to the third column of sub-pixels 220 in the first display area 211 and the third column of sub-pixels 220 in the second display area 212 are also connected.

[0040] In this embodiment, the display area 210 is divided into two different areas: the first display area 211 and the second display area 212. The scan lines 230 connecting the pixels of the two display areas 210 are different, and the corresponding data lines 240 within the two display areas 210 are interconnected, which is essentially data voltage sharing. To achieve HSR (Hardware Super Resolution) driven display under the DRD (Double Rate Driving) architecture, the sub-pixels 220 in a row of sub-pixels 220 are connected to different scan lines 230 respectively. During scanning, after scanning the first and second rows of scan lines 230 in sequence, the fourth row of scan lines 230 is scanned, and then the third row of scan lines 230 is scanned. Instead of scanning line by line, the scanning order of the last two rows of scan lines 230 is exchanged in every four rows as a cycle. In this way, when the data of adjacent rows is mixed and displayed, voltage sharing on the data lines 240 can still be achieved, realizing HSR (Hardware Super Resolution) driven display under the DRD (Double Rate Driving) architecture. Resolution (hardware super-resolution) drives the display.

[0041] The second embodiment of this application is a further refinement of the first embodiment described above, as referred to in the following text. Figure 3a , Figure 3b , Figure 4 and Figure 5 As shown, the driving circuit 100 includes at least four clock signal lines, typically multiples of four. This embodiment mainly uses eight clock signal lines as an example for illustration, namely, the first clock signal line CK1, the second clock signal line CK2, the third clock signal line CK3, the fourth clock signal line CK4, the fifth clock signal line CK5, the sixth clock signal line CK6, the seventh clock signal line CK7, and the eighth clock signal line CK8. Each clock signal line is connected to a corresponding gate driving unit and outputs a clock signal to the corresponding gate driving unit. For example, the first clock signal line is connected to the first gate driving unit 111, which generates a scan signal based on the frame start signal and the clock signal and outputs it to the scan line 230. The four gate driving units in the first gate driving unit group 110 generate scan signals based on the frame start signal and the clock signal and output them to the scan line 230. The four gate driving units in the second gate driving unit group 110 generate scan signals based on the scan signals and clock signals output by the four gate driving units in the first gate driving unit group 110 and output them to the corresponding scan line 230.

[0042] Generally, the driving circuit 100 includes multiple gate driving unit groups 110, with four units per group. In the first gate driving unit group 110, the first gate driving unit 111, the second gate driving unit 112, the third gate driving unit 113, and the fourth gate driving unit 114 respectively output a first scan signal G1 to the first row scan line 230, a second scan signal G2 to the second row scan line 230, a third scan signal G3 to the fourth row scan line 230, and a fourth scan signal G4 to the third row scan line 230. The first scan signal, the second scan signal, the third scan signal, and the fourth scan signal are transmitted independently and do not interfere with each other. The fifth, sixth, seventh, and eighth gate driving units in the second gate driving unit group 110 respectively output a fifth scan signal to the fifth row scan line 230, a sixth scan signal to the sixth row scan line 230, a seventh scan signal to the eighth row scan line 230, and an eighth scan signal to the seventh row scan line 230; the first gate driving unit 111, the second gate driving unit 112, the third gate driving unit 113, the fourth gate driving unit 114, the fifth gate driving unit, the sixth gate driving unit, the seventh gate driving unit, and the eighth gate driving unit correspond to the GDL in the figure. Circuits 1, 2, 3, 4, 5, 6, 7, and 8, and the input terminals of the four gate driving units in the second gate driving unit group 110 are connected to the output terminals of the four gate driving units in the corresponding first gate driving unit group 110. The first scan signal, second scan signal, third scan signal, and fourth scan signal output by the four gate driving units in the first gate driving unit group 110 are used as the start signal of the current stage.

[0043] Each scan signal includes a first level signal time period and a second level signal time period. The first level signal time period outputs a high-level signal to scan line 230, and the second level signal time period outputs a low-level signal to scan line 230. To avoid insufficient charging, each row of pixels is pre-charged. The start time of the first level signal time period of the scan signal corresponding to the current row of scan line 230 is earlier than the end time of the first level signal time period of the scan signal corresponding to the previous row of scan line 230, and also earlier than the start time of the first level signal time period of the scan signal corresponding to the next row of scan line 230. The duration between the start time of the first level signal time period of the scan signal corresponding to the current row of scan line 230 and the start time of the first level signal time period of the scan signal corresponding to the previous row of scan line 230 is greater than or equal to half the duration of the first level signal time period.

[0044] Furthermore, both the first display area 211 and the second display area 212 are provided with multiple sub-pixel columns 220. The number of columns of sub-pixels 220 in each display area 210 is a multiple of 6. Along the extension direction of the data line 240, each row of sub-pixels 220 includes multiple sub-pixels 220, which are red sub-pixels 220, green sub-pixels 220, and blue sub-pixels 220 respectively. In each row of sub-pixels 220, the red sub-pixels 220, green sub-pixels 220, and blue sub-pixels 220 are arranged sequentially. The polarities of the red sub-pixels 220, green sub-pixels 220, and blue sub-pixels 220 in every 6 columns are arranged in a +-+-+-+- or -+-+-+ arrangement. The two scan lines 230 corresponding to each row of sub-pixels 220 are respectively set above and below each row of sub-pixels 220. The first column of sub-pixels 220 in the first display area 211 and the first column of sub-pixels 220 in the second display area 212 have the same color and the same polarity.

[0045] In this embodiment, as Figure 3a and Figure 3b Taking the middle arrow as an example, during line-by-line scanning, the red sub-pixel 220R is displayed in the order D1 / G1->D7 / G2->D7 / G3->D1 / G4->D1 / G5->D7 / G6->D7 / G7->D1 / G8. This is not line-by-line scanning, but rather scanning in a cycle of four pixels, with the last two rows swapping their scanning order, scanning end-to-end. Pixel arrangement is driven by scanning in cycles of four pixels because the GDL order must be periodic of four, including the number of CKs (cutoff, pull-up, pull-down) which must be a multiple of four (6 / 12 / 16 / 20...), and the pull-up signal of each GDL level must be -4 / -8 / -12..., and the pull-down signal of each GDL level must be... Down needs to be +4 / +8 / +12... to achieve this. Only with this kind of GDL combination can the four sets of GDL signals GDL1 / GDL5 / GDL9..., GDL2 / GDL6 / GDL10..., GDL3 / GDL7 / GDL11..., GDL4 / GDL8 / GDL12... be transmitted independently without interfering with each other, so that they can be used in conjunction with the pixel arrangement for driving.

[0046] like Figure 5 The Gate signals G1 / G2 / G4 / G3 / G5 / G6 / G8 / G7 output by GDL are paired with data to realize HSR drive under DRD architecture. Taking R pixel as an example, G2 / G4 / G6 / G8 respectively realize the partial charging of R pixel to the next row of R pixels, thereby realizing HSR function. In order for HSR to charge more data of the next row of R pixels, it is preferable to make the shift time between H / 2 and H.

[0047] As a third embodiment of this application, it further limits and improves upon any of the above embodiments, see reference. Figure 6 As shown, the driving circuit 100 includes a data driving module 120 and a flip-chip film 130. The data driving module 120 outputs a data driving signal to the fan-out trace 251 through the data channel on the flip-chip film 130, and outputs it to the data line 240 through the fan-out trace 251. The two data lines 240 corresponding to the first column of sub-pixels 220 in the first display area 211 and the first column of sub-pixels 220 of the same color and polarity in the second display area 212 are connected to the same data channel through the same fan-out trace 251.

[0048] In this embodiment, two data lines 240 at different locations are connected together and connected by a fan-out trace 251 of the fan-out area 250. Compared with the original fan-out area 250, the number of fan-out traces 251 is reduced by half. In order to ensure the uniformity of display, the pixel columns that were originally close to the flip-chip film 130 are made farther away due to the connection line. This adjusts the display brightness of each first display area 211 and second display area 212, thereby adjusting the brightness of the entire display area 210 of the display panel 200. This avoids excessive brightness difference at the junction of the flip-chip film 130 and also improves the problem of the difference between the brightness of the middle and the brightness of the two sides of the pixel corresponding to the fan-out trace 251.

[0049] like Figure 7 As shown, this fourth embodiment of the present application is a further improvement on any of the above embodiments. (Refer to...) Figure 7 As shown, the driving circuit 100 further includes a first switching circuit 140. The first switching circuit 140 is disposed on the side of the data line 240 away from the data driving module 120. The first switching circuit 140 includes a plurality of first switches 141. Each first switch 141 is connected to two data lines 240 corresponding to sub-pixels 220 of the same color in the first display area 211 and the second display area 212. Each scan signal includes a first level signal time period and a second level signal time period. The first level signal time period outputs a high level signal to the scan line 230, and the second level signal time period outputs a low level signal to the scan line 230. The first switch 141 is turned on during the time period between the start time of the first level signal time period of the scan signal corresponding to the current row scan line 230 and the start time of the first level signal time period of the scan signal corresponding to the next row scan line 230.

[0050] In this embodiment, two data lines 240 are connected to form a loop, so that the data voltage charged is the same when each scan line 230 is turned on. This avoids uneven charging caused by different data lines 240 being charged with different voltages when the scan line 230 is turned on, which would result in uneven brightness display.

[0051] As a fifth embodiment of this application, a method for driving a display panel is disclosed, which uses the driving circuit described in any of the above descriptions to drive the display panel. (Refer to...) Figure 1 , Figure 2 and Figure 8 As shown, the driving method includes the following steps:

[0052] S1: The first gate driving unit, second gate driving unit, third gate driving unit, and fourth gate driving unit in each gate driving unit group generate a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal based on the frame start signal / Gn-4 level scan signal and the clock signal; and

[0053] S2: Output a first scan signal to the first scan line and control the first row of sub-pixels in the first display area to charge; output a second scan signal to the second scan line and control the first row of sub-pixels in the second display area to charge; output a third scan signal to the fourth scan line and control the second row of sub-pixels in the second display area to charge; output a fourth scan signal to the third scan line and control the second row of sub-pixels in the first display area to charge.

[0054] The display panel is divided into zones, and the internal data lines of different zones are connected together to share data signals. Within each group of four gate drive units, the first gate drive unit connects to the first scan line, the second gate drive unit connects to the second scan line, the third gate drive unit connects to the fourth scan line, and the fourth gate drive unit connects to the third scan line. Each gate drive unit group generates a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal based on the frame start signal / Gn-4 level scan signal and the clock signal. In each cycle of four lines, the scanning order of the last two scan lines is swapped. After scanning the first and second scan lines in sequence, the fourth scan line is scanned, and then the third scan line is scanned. This achieves HSR (Hardware Super Resolution) driving under the DRD (Double Rate Driving) architecture, enabling voltage sharing on the data lines when data from adjacent rows is mixed and displayed.

[0055] Further reference Figure 9As shown, the sixth embodiment of this application is a further refinement of the fifth embodiment described above. (Refer to...) Figures 4 to 9 As shown, the driving circuit further includes a first switching circuit, which is disposed on the side of the data line away from the data driving module. The first switching circuit includes multiple first switches, each of which connects two data lines corresponding to sub-pixels of the same color in the first and second display areas. Each scan signal includes a first level signal time period and a second level signal time period. The first level signal time period outputs a high-level signal to the scan line, and the second level signal time period outputs a low-level signal to the scan line. The steps of outputting a first scan signal to the first scan line and controlling the first row of sub-pixels in the first display area to charge, outputting a second scan signal to the second scan line and controlling the first row of sub-pixels in the second display area to charge, outputting a third scan signal to the fourth scan line and controlling the second row of sub-pixels in the second display area to charge, and outputting a fourth scan signal to the third scan line and controlling the second row of sub-pixels in the first display area to charge include:

[0056] S21: Output a first scan signal to the first scan line and control the first row of sub-pixels in the first display area to charge. At the beginning of the first level signal time period of the first scan signal, turn on the first switch and connect the corresponding data line. After half the duration of the first level signal time period of the first scan signal, output a second scan signal to the second scan line and control the first row of sub-pixels in the second display area to charge. After half the duration of the first level signal time period of the second scan signal, output a third scan signal to the fourth scan line and control the second row of sub-pixels in the second display area to charge. After half the duration of the first level signal time period of the third scan signal, output a fourth scan signal to the third scan line and control the second row of sub-pixels in the first display area to charge. After charging is completed, turn off the first switch within a preset time.

[0057] In this example, a first switching circuit is added so that the two connected data lines form a loop. The voltage on the loop is the same, ensuring that the charging voltage is the same when the pixels in the corresponding two display areas are charged. Moreover, after half the time when the current scan line is input with a high-level signal, the next scan line is input with a high-level signal in advance to achieve pre-charging, thereby improving the charging rate of the next row of pixels.

[0058] refer to Figure 10 As shown, as the seventh embodiment of this application, a display device 300 is disclosed. The display device 300 includes a display panel 200 and a driving circuit 100 as described above. The driving circuit 100 drives the display panel 200 using the driving method described above.

[0059] It should be noted that the limitations on each step involved in this solution are not considered as limiting the order of steps, provided that they do not affect the implementation of the specific solution. The steps listed first can be executed first, later, or even simultaneously. As long as this solution can be implemented, it should be considered to fall within the scope of protection of this application.

[0060] It should be noted that the inventive concept of this application can form many embodiments, but due to the limited space of the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effect will be enhanced.

[0061] The technical solution of this application can be widely used in driving circuits of various display panels, such as driving circuits of TN (Twisted Nematic) display panels, driving circuits of IPS (In-Plane Switching) display panels, driving circuits of VA (Vertical Alignment) display panels, and driving circuits of MVA (Multi-Domain Vertical Alignment) display panels. Of course, it can also be used for driving circuits of other types of display panels, such as driving circuits of OLED (Organic Light-Emitting Diode) display panels, and the above solution is applicable to all of them.

[0062] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A drive circuit of a display panel, characterized by, The display panel is divided into a first display area and a second display area along the extension direction of the scan lines, each of the first display areas is provided with N columns of sub-pixels, and the second display area is provided with N columns of sub-pixels; along the extension direction of the data lines, the display panel is provided with a plurality of rows of sub-pixels, each row of sub-pixels is provided with at least two rows of scan lines, one row of scan lines is connected to N columns of pixels in the first display area, and the other row of scan lines is connected to N columns of sub-pixels in the second display area; The driving circuit includes a plurality of gate driving units, every four gate driving units form a gate driving unit group, and the four gate driving units are a first gate driving unit, a second gate driving unit, a third gate driving unit and a fourth gate driving unit; the first gate driving unit inputs a first scan signal to the corresponding first row of scan lines, the second gate driving unit inputs a second scan signal to the corresponding second row of scan lines, the third gate driving unit inputs a fourth scan signal to the corresponding third row of scan lines, and the fourth gate driving unit inputs a third scan signal to the corresponding fourth row of scan lines; wherein N is a natural number greater than or equal to 3, the data line corresponding to the first column of sub-pixels in the first display area is connected to the data line corresponding to the first column of sub-pixels in the second display area, the data line corresponding to the second column of sub-pixels in the first display area is connected to the data line corresponding to the second column of sub-pixels in the second display area, and so on, and the data line corresponding to the Nth column of sub-pixels in the first display area is connected to the data line corresponding to the Nth column of sub-pixels in the second display area.

2. The drive circuit of claim 1, wherein, The driving circuit includes at least four clock signal lines, different clock signal lines are connected to corresponding gate driving units, and clock signals are output to the corresponding gate driving units, and the gate driving units generate scan signals based on a frame start signal and a clock signal and output the scan signals to the scan lines; wherein the first gate driving unit, the second gate driving unit, the third gate driving unit and the fourth gate driving unit in the first gate driving unit group output a first scan signal to the first row of scan lines, output a second scan signal to the second row of scan lines, output a third scan signal to the fourth row of scan lines, and output a fourth scan signal to the third row of scan lines, the first scan signal, the second scan signal, the third scan signal and the fourth scan signal are independently level-transmitted and do not interfere with each other; the input ends of the four gate driving units in the second gate driving unit group are connected to the output ends of the four gate driving units in the first gate driving unit group, and serve as the starting signals of the current level.

3. The drive circuit of claim 2, wherein, Each scan signal includes a first level signal time period and a second level signal time period, the first level signal time period outputs a high-level signal to the scan line, and the second level signal time period outputs a low-level signal to the scan line, the start time of the first level signal time period of the scan signal corresponding to the current row of scan lines is earlier than the end time of the first level signal time period of the scan signal corresponding to the previous row of scan lines, and is also earlier than the start time of the first level signal time period of the scan signal corresponding to the next row of scan lines.

4. The drive circuit of claim 3, wherein The time length between the start time of the first level signal time period of the scan signal corresponding to the current row scanning line and the start time of the first level signal time period of the scan signal corresponding to the last row scanning line is greater than or equal to 1 / 2 of the time length of the first level signal time period.

5. The drive circuit of claim 1, wherein, The driving circuit comprises a data driving module and a chip on film, the data driving module outputs a data driving signal to a fan-out wire through a data channel on the chip on film, and the data driving signal is output to a data line through the fan-out wire, wherein two data lines corresponding to first column sub-pixels of the same color and the same polarity in the first display area and the second display area are connected to the same data channel through the same fan-out wire.

6. The drive circuit of claim 1, wherein, The first display area and the second display area are each provided with a plurality of sub-pixel columns, the number of sub-pixel columns in each display area is a multiple of 6, each row of sub-pixels comprises a plurality of sub-pixels along the extension direction of the data line, the plurality of sub-pixels are red sub-pixels, green sub-pixels and blue sub-pixels, and the red sub-pixels, the green sub-pixels and the blue sub-pixels in each row of sub-pixels are arranged in sequence, and the polarities of the red sub-pixels, the green sub-pixels and the blue sub-pixels in every 6 columns are arranged in sequence as +-+-+ or -+-+-+. Each row of sub-pixels corresponds to two scanning lines arranged above and below the row of sub-pixels.

7. The drive circuit according to any one of claims 1 to 6, wherein The driving circuit further comprises a first switch circuit, the first switch circuit is arranged on the side of the data line away from the data driving module, the first switch circuit comprises a plurality of first switches, each first switch is connected to two data lines corresponding to sub-pixels of the same color in the first display area and the second display area, each scan signal comprises a first level signal time period and a second level signal time period, the first level signal time period outputs a high level signal to the scanning line, the second level signal time period outputs a low level signal to the scanning line, and the first switch is controlled to be turned on in the time period between the start time of the first level signal time period of the scan signal corresponding to the current row scanning line and the start time of the first level signal time period of the scan signal corresponding to the next row scanning line.

8. A driving method of a display panel, wherein the display panel is driven using the driving circuit according to any one of claims 1 to 7, characterized by The driving method comprises the steps of: The first gate driving unit, the second gate driving unit, the third gate driving unit and the fourth gate driving unit in each gate driving unit group generate a first scan signal, a second scan signal, a third scan signal and a fourth scan signal based on a frame start signal / Gn-4 level scan signal and a clock signal; and The first scan signal is output to the first row scanning line and the first row of sub-pixels in the first display area is controlled to be charged, the second scan signal is output to the second row scanning line and the first row of sub-pixels in the second display area is controlled to be charged, the third scan signal is output to the fourth row scanning line and the second row of sub-pixels in the second display area is controlled to be charged, and the fourth scan signal is output to the third row scanning line and the second row of sub-pixels in the first display area is controlled to be charged.

9. The driving method of a display panel according to claim 8, wherein The driving circuit further comprises a first switch circuit arranged on the side of the data lines away from the data driving module, the first switch circuit comprising a plurality of first switches, each of the first switches being connected to two data lines corresponding to a same color of a pair of sub-pixels in the first display area and the second display area, each of the scan signals comprising a first level signal time period and a second level signal time period, the first level signal time period outputting a high level signal to the scan lines, and the second level signal time period outputting a low level signal to the scan lines, the steps of outputting the first scan signal to the first row of scan lines and controlling the first row of sub-pixels in the first display area to charge, outputting the second scan signal to the second row of scan lines and controlling the first row of sub-pixels in the second display area to charge, outputting the third scan signal to the fourth row of scan lines and controlling the second row of sub-pixels in the second display area to charge, and outputting the fourth scan signal to the third row of scan lines and controlling the second row of sub-pixels in the first display area to charge comprising: The first scan signal is output to the first row of scan lines and the first row of sub-pixels in the first display area is controlled to charge, the first switch is turned on at the beginning of the first level signal time period of the first scan signal, and the corresponding data lines are connected, the second scan signal is output to the second row of scan lines and the first row of sub-pixels in the second display area is controlled to charge after 1 / 2 of the first level signal time period of the first scan signal, the third scan signal is output to the fourth row of scan lines and the second row of sub-pixels in the second display area is controlled to charge after 1 / 2 of the first level signal time period of the second scan signal, the fourth scan signal is output to the third row of scan lines and the second row of sub-pixels in the first display area is controlled to charge after 1 / 2 of the first level signal time period of the third scan signal, and the first switch is turned off in a preset time after the charging is completed.

10. A display device, characterized by comprising: The display panel is driven by the driving circuit according to any one of claims 1-7, and the driving circuit is driven by the driving method according to any one of claims 8-9.

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