A successive approximation analog-to-digital converter

Abstract

The application discloses a successive approximation analog-to-digital converter and relates to an analog circuit, which comprises a capacitor array composed of an N-end capacitor array and a P-end capacitor array, which is used for sampling a signal and outputting a first upper plate voltage V N and a second upper plate voltage V P ; a comparator, which is used for comparing the first upper plate voltage V N and the second upper plate voltage V P ; a logic circuit, which is used for controlling switch switching in the N-end capacitor array and the P-end capacitor array according to a comparison result, so that the voltage under a corresponding capacitor is switched from a common-mode voltage VCM to a first reference voltage VREFP or a second reference voltage VREFN; the logic circuit is further provided with control logic for controlling an RRN circuit; and the RRN circuit is embedded at a power supply of the SAR ADC, so that the RRN circuit is simultaneously connected to a delivery line of the first reference voltage VREFP and the second reference voltage VREFN. The application improves the charge compensation effect of a ripple neutralization circuit on an ADC, reduces the power supply ripple of an on-chip circuit, and greatly improves the signal-to-noise ratio and the spurious-free dynamic range of the SAR ADC.

Description

Technical Field

[0001] This invention relates to analog circuits, and more specifically, to a successive approximation analog-to-digital converter. Background Technology

[0002] In successive approximation analog-to-digital converter (SAR ADC) design, non-ideal on-chip power supplies cause reference voltage fluctuations during capacitor switching during ADC quantization. Since the accuracy of the reference voltage directly affects the converter's signal-to-noise ratio and harmonic distortion ratio, this issue has become a key factor limiting ADC performance. Currently, two main engineering strategies address this: one is to reduce parasitic inductance parameters through optimized package design, and the other is to use on-chip power supply decoupling capacitors several times larger than the ADC capacitor to suppress voltage fluctuations.

[0003] There are two main existing ripple reduction techniques. One is Reference Ripple Cancellation (RRC), which involves designing a power supply ripple extraction circuit to process the power supply ripple and the signal from the upper plate of the ADC through a four-input comparator. The power supply ripple is then converted into a common-mode signal, and the common-mode rejection capability of the differential comparator is used to reduce the impact of the power supply ripple on the comparator's comparison process. The other is Reference Ripple Neutralization (RRN), which uses a capacitor of a certain size to store charge and releases it when the ADC switches to compensate for the charge drawn by the ADC. This reduces the current draw during on-chip capacitor switching and thus reduces ripple. However, all of the above solutions have limitations. For example, the ripple cancellation circuit does not reduce the power supply ripple. For pipelined SAR ADCs, the ripple will be passed to the next stage ADC, introducing noise of equal magnitude to the ripple for the secondary ADC. Furthermore, the four-input comparator consumes nearly twice the power and introduces new noise through the ripple extraction circuit. As for the ripple neutralization circuit, since the charge extracted by the ADC is code-dependent, for an N-bit ADC, there exists (2... N -1) For the charge extraction results, the existing methods only perform high-level compensation (usually the first three bits) and ignore the ripple generated when switching the lower bits. At the same time, due to the use of the power supply chip buffer circuit, it can often only compensate for the positive reference voltage. Summary of the Invention

[0004] The technical problem to be solved by this invention is to address the shortcomings of existing technologies by providing a successive approximation analog-to-digital converter (ADC). After each comparison, the required charge amount is calculated using on-chip logic circuitry, and then rounded down using a lookup table to simplify the charge extraction result. Finally, the sum of all results is converted into thermometer code, which ensures that after compensation for each symbol, there is basically no need to extract current from outside the chip. This improves the charge compensation effect of the ripple neutralization circuit on the ADC, reduces the power supply ripple of the on-chip circuitry, and greatly improves the signal-to-noise ratio of the SAR ADC.

[0005] The successive approximation analog-to-digital converter of the present invention includes:

[0006] A capacitor array consisting of an N-terminal capacitor array and a P-terminal capacitor array is used to sample the signal and output the voltage V of the first upper plate. N The voltage V of the second upper plate P ;

[0007] A comparator is used to compare the voltage V of the first upper plate. N The voltage V of the second upper plate P Compare;

[0008] The logic circuit is used to control the switching of the switches in the N-terminal capacitor array and the P-terminal capacitor array according to the comparison result of the comparator, so that the voltage under the corresponding capacitor switches from the common-mode voltage VCM to the first reference voltage VREFP or the second reference voltage VREFN; the logic circuit is also provided with control logic for controlling the RRN circuit.

[0009] The RRN circuit is embedded at the power supply of the SAR ADC so that it is simultaneously connected to the transmission lines of the first reference voltage VREFP and the second reference voltage VREFN.

[0010] Preferably, the RRN circuit is designed with X groups, and the value of the X groups of the RRN circuit is calculated based on the ratio between the total capacitance value of the capacitor array and the capacitance value of each capacitor in it.

[0011] Preferably, the X group value of the RRN circuit is calculated by the following formula:

[0012]

[0013] In the formula, C all C is the total capacitance value. i Let C1 be the capacitance value of the i-th capacitor, N be the total number of capacitors in the capacitor array, and C1 be the capacitance value of the capacitor with the largest weight in the capacitor array. u The capacitance is per unit.

[0014] Preferably, the RRN circuit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a first capacitor, and a second capacitor; the gate of the first switch is connected to a first control signal. The source of the first switching transistor is connected to the transmission line of the first reference voltage VREFP, the drain of the first switching transistor is simultaneously connected to the source of the second switching transistor and one end of the first capacitor, and the gate of the second switching transistor is connected to the second control signal. The drain of the second switch is connected to the first charging voltage signal VREFP_TMP. The other end of the first capacitor is simultaneously connected to the source of the eighth switch, the drain of the third switch, and the drain of the seventh switch. The gate of the eighth switch is connected to the third control signal φ. s The drain of the eighth switch is connected to the second charging voltage signal VREFN_TMP, and the gate of the third switch is connected to the first control signal. The gate of the seventh switch is connected to the fourth control signal φ switch The source of the third switch is connected to the source of the seventh switch and simultaneously connected to one end of the second capacitor and the source of the fourth switch. The gate of the fourth switch is connected to the second control signal. The drain of the fourth switch is connected to the first charging voltage signal VREFP_TMP, the other end of the second capacitor is connected to the drain of the fifth switch and the source of the sixth switch, and the gate of the fifth switch is connected to the fourth control signal φ. switch The source of the fifth switch is connected to the transmission line of the second reference voltage VREFN, and the gate of the sixth switch is connected to the third control signal φ. s The drain of the sixth switch is connected to the second charging voltage signal VREFN_TMP; the first control signal With the fourth control signal φ switch The high and low levels of the second control signal are opposite. With the third control signal φ s The high and low levels are opposite.

[0015] Preferably, the first capacitor and the second capacitor have the same capacitance, and both are ADC unit capacitors.

[0016] Preferably, the first and fifth switching transistors are of the same size, and both are the same size as the switches in the capacitor array.

[0017] Preferably, the third and seventh switching transistors are of the same size, and are 3-5 times the size of the first or fifth switching transistor.

[0018] Preferably, the control logic is as follows:

[0019] Calculate the charge required for the capacitor array to switch during the current cycle;

[0020] Calculate the required number of RNN capacitors;

[0021] Calculate the total capacitance of all RRN capacitors;

[0022] Output control signal.

[0023] Preferably, the method for calculating the charge required for switching the capacitor array in the current cycle is as follows:

[0024] Q require =D Ci (D Call -D CVrefpP +D CVrefpN (VREFP-VCM),

[0025] Among them, Q require D represents the charge required for the switching of the capacitor array during the current cycle. CVrefpP D is the control signal for the P-terminal capacitor array stored in the logic circuit. CVrefpN D is the control signal for the N-terminal capacitor array stored in the logic circuit. Ci This represents the number of capacitors that are about to be switched.

[0026] Preferably, the method for calculating the required number of RNN capacitors is as follows:

[0027] The charge required for switching the capacitor array during the current comparison cycle is calculated as (VREFP-VCM)*C. u After partitioning, the result n is obtained by step-rounding. i And write it into the logic circuit as a table;

[0028] D CVrefpP With D CVrefpN Multiply by the unit capacitance C u Calculate C VrefpP With C VrefpN The number of RNN capacitors required for this switching process is obtained by subtracting the RNN capacitors from the RNN capacitors and then looking up the table based on the structure.

[0029] Beneficial effects

[0030] The advantages of this invention are as follows: After each comparison, the required charge amount is calculated using on-chip logic circuitry, and then rounded down by a lookup table, thereby simplifying the charge extraction result; then, the sum of all results is converted into thermometer code, which ensures that after each symbol is compensated, there is basically no need to extract current from outside the chip, improving the charge compensation effect of the ripple neutralization circuit on the ADC, reducing the power supply ripple of the on-chip circuit, and greatly improving the signal-to-noise ratio of the ADC. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the overall architecture of the SAR ADC based on thermometer codes of the present invention;

[0032] Figure 2 This is a schematic diagram of the key clock timing of the SAR ADC based on thermometer code of the present invention;

[0033] Figure 3 This is a schematic diagram illustrating the charge required by the CDAC of the present invention during switching between different symbols;

[0034] Figure 4 This is a schematic diagram illustrating the charge required for switching different symbols in the CDAC of the present invention and its step-down method.

[0035] Figure 5 This is a schematic diagram comparing the ripple and extraction current of the ADC when it is on / off according to the present invention.

[0036] Figure 6 This is a schematic diagram comparing the neutral voltage ripple with and without the ADC enabled in this invention.

[0037] Figure 7 This is a schematic diagram comparing the ripple neutralization spectrum of the ADC with / without being turned on in this invention. Detailed Implementation

[0038] The present invention will be further described below with reference to embodiments, but this does not constitute any limitation on the present invention. Any limited modifications made by any person within the scope of the claims of the present invention are still within the scope of the claims of the present invention.

[0039] The present invention provides a successive approximation analog-to-digital converter, the overall structure of which is as follows: Figure 1 As shown. A traditional SAR ADC consists of logic circuits, a comparator, and a capacitor array (CDAC). The CDAC is a differential structure, composed of an N-terminal capacitor array and a P-terminal capacitor array. When the CDAC samples the signal, the voltage V on its upper plate... N With V PThe input comparator compares the values ​​and obtains the result, which is then input into the logic circuit. The logic circuit controls the switch in the CDAC based on the result, causing the voltage under the corresponding capacitor to switch from the common-mode voltage VCM to the reference voltage VREFP or VREFN, thereby achieving V... N With V P The binary approximation.

[0040] This invention is based on the conventional SAR ADC, incorporating new control logic to control the RRN circuit. Simultaneously, the RRN circuit is embedded at the power supply, allowing it to be simultaneously connected to the transmission lines of the first reference voltage VREFP and the second reference voltage VREFN. The original SAR ADC's reference voltage transmission line remains unchanged. Therefore, the RRN circuit of this invention and the original circuit's reference voltage transmission line can simultaneously compensate for the reference voltages VREFP and VREFN. Furthermore, a second power supply is used to charge the capacitor, ensuring that the current drawn during charging does not cause ripple in the reference voltage.

[0041] In this embodiment, the RRN circuit specifically includes a first switch PM0, a second switch PM1, a third switch PM2, a fourth switch PM3, a fifth switch NM0, a sixth switch NM1, a seventh switch NM2, an eighth switch NM3, and a first capacitor C. P Second capacitor C N The gate of the first switching transistor PM0 is connected to the first control signal. The source of the first switching transistor PM0 is connected to the transmission line of the first reference voltage VREFP, and the drain of the first switching transistor PM0 is simultaneously connected to the source of the second switching transistor PM1 and the first capacitor C. P One end is connected, and the gate of the second switching transistor PM1 is connected to the second control signal. The drain of the second switch PM1 is connected to the first charging voltage signal VREFP_TMP, and the first capacitor C P The other end is simultaneously connected to the source of the eighth switch NM3, the drain of the third switch PM2, and the drain of the seventh switch NM2. The gate of the eighth switch NM3 is connected to the third control signal φ. s The drain of the eighth switch NM3 is connected to the second charging voltage signal VREFN_TMP, and the gate of the third switch PM2 is connected to the first control signal. The gate of the seventh switch NM2 is connected to the fourth control signal φ switch The source of the third switch PM2 is connected to the source of the seventh switch NM2 and simultaneously connected to the second capacitor C. N One end of the transistor is connected to the source of the fourth switch PM3, and the gate of the fourth switch PM3 is connected to the second control signal. The drain of the fourth switching transistor PM3 is connected to the first charging voltage signal VREFP_TMP, and the second capacitor C N The other end is simultaneously connected to the drain of the fifth switch NM0 and the source of the sixth switch NM1, and the gate of the fifth switch NM0 is connected to the fourth control signal φ. switch The source of the fifth switch NM0 is connected to the transmission line of the second reference voltage VREFN, and the gate of the sixth switch NM1 is connected to the third control signal φ. s The drain of the sixth switch NM1 is connected to the second charging voltage signal VREFN_TMP.

[0042] In this RRN circuit, the first control signal With the fourth control signal φ switch The high and low levels of the second control signal are opposite. With the third control signal φ s The high and low voltage levels are reversed. The first capacitor C... P Second capacitor C N The capacitances are the same, and both are the unit capacitance C of the ADC. u The first switch PM0 and the fifth switch NM0 have the same size, and both are the same size as the switches in the capacitor array. The third switch PM2 and the seventh switch NM2 have the same size, and both are 3-5 times the size of the first switch PM0 or the fifth switch NM0.

[0043] In this embodiment, the RRN circuit is designed with X groups, and the value of the X groups of the RRN circuit is calculated based on the ratio between the total capacitance value of the capacitor array and the capacitance value of each capacitor in it. The specific calculation formula is as follows:

[0044]

[0045] In the formula, C all C is the total capacitance value. i Let be the capacitance value of the i-th capacitor, N be the total number of capacitors in the capacitor array, and C1 be the capacitance value of the capacitor with the largest weight in the capacitor array.

[0046] The charge required for CDAC switching during a comparison cycle is calculated using the following formula:

[0047] Q require =D Ci (D Call -D CVrefpP +D CVrefpN (VREFP-VCM),

[0048] In the formula, D CVrefpP With D CVrefpNThese are the control signals for the P-terminal capacitor array and the N-terminal capacitor array stored in the logic circuit, respectively. Ci This represents the number of capacitors that will be switched. To avoid using a divider in digital logic circuits, Q... require Magnified D Call The multiple does not affect subsequent calculations.

[0049] Taking a 6-bit CDAC as an example, such as Figure 3 As shown, a 6-bit CDAC requires 6 switching operations, resulting in 2, 4, 8, 16, 32, and 64 possible symbol combinations, respectively, in top-to-bottom order. The symbol value represents all comparison results stored in the logic circuit within the current sampling period. Different symbols require different amounts of charge, in top-to-bottom order... Figure 3 In the diagram, the horizontal axis represents the symbol value after switching the capacitors of the 1st, 2nd, 3rd, 4th, 5th, and 6th bits of the CDAC, and the vertical axis represents the required charge corresponding to the symbol value. After calculating the charge based on the symbol value, D is used... CVrefpP -D CVrefpN As the new horizontal axis, D CVrefpP For the control signal of the capacitor array at the P terminal of the CDAC, D CVrefpN This represents the control signal for the N-terminal capacitor array of the CDAC, with the vertical axis representing the charge amount corresponding to the symbol value. The total charge may not be an integer; it is calculated as (VREFP - VCM) * C. u After partitioning, the result n is obtained by step-rounding. i ,like Figure 4 As shown.

[0050] Regarding the calculation of the required number of RNN capacitors, as follows: Figure 3 As shown, assuming the number of capacitors is A, a range [A-0.5, A+0.5] can contain the charge corresponding to different symbol values, meaning that the error after neutralization is less than 0.25C. u Under the premise of *(VREFP-VREFN), the same number of capacitors can neutralize different amounts of charge. Therefore, as Figure 4 As shown, in the host computer, the charge corresponding to all symbols is calculated and then processed into a step-like manner. The result is written into the digital logic circuit. The logic circuit directly finds the number of RRN capacitors required for this conversion based on the charge calculated in the previous step.

[0051] Specifically, the host computer pre-calculates the integer n corresponding to each symbol value. i The result is then written into the logic circuit of the SAR ADC as a table. After the comparison is completed, the output of the comparator is input to the logic circuit, which then calculates D based on this result and the comparison result from the previous comparison period in the current sampling period. CVrefpP With D CVrefpN Multiply it by the unit capacitance Cu Calculate C VrefpP With C VrefpN , where C VrefpP C refers to the capacitance value of all capacitors connected to VREFP in the capacitor array with higher potential during this comparison period. VrefpN This refers to the capacitance values ​​of all capacitors in the capacitor array with lower potentials connected to and about to be connected to VREFP during this comparison period. The difference between these values ​​is then used to look up the result in a table to obtain n. i n i This represents the number of RNN capacitors required during this switching process. The calculation is simplified by using a lookup table, avoiding the use of numerous multipliers and dividers.

[0052] Finally, regarding the calculation of the sum of all RRN capacitances, all RRN capacitance results obtained within this sampling period are added together. Since the RRN capacitance is a unit capacitance, the sum of the capacitances is equivalent to adding all n values ​​from the comparison process completed within this sampling period. i Adding them together gives N i The result is converted into thermometer code, i.e., φ. s and φ switch Control N i One RRN circuit is operational.

[0053] The following will describe the workflow of the RRN circuit and the control logic section of the logic circuit in the SAR ADC of this invention.

[0054] like Figure 2 The figure shows the start-stop timing of the SAR ADC. When φ s High level, φ switch When the signal is low, the SAR ADC is at the sampling time. In the RRN circuit, switches PM1, PM3, NM1, and NM3 are turned on, while switches PM0, PM2, NM0, and NM2 are turned off. The charging voltage signals VREFP_TMP and VREFN_TMP, which are of equal magnitude to the reference voltage, affect capacitor C. P With C N Charging, a single capacitor stores C u The charge of *(VREFP-VREFN).

[0055] φ s Return to low level, φ comp When the signal is high, the comparator operates, and the SAR ADC begins quantization. At this time, switches PM0, PM1, PM2, PM3, NM0, NM1, NM2, and NM3 are all off, and the capacitors are floating. Due to the conservation of charge on the positive and negative plates of the capacitors, the charge on both plates is latched. At this point, capacitor C... P With C N The charge remains C u*(VREFP-VREFN).

[0056] When φ s Low level, φ switch When the voltage is high, the switching transistors PM1, PM3, NM1, and NM3 in the RRN circuit are off, while the switching transistors PM0, PM2, NM0, and NM2 are on, and the capacitor C... P With C N With the capacitor connected in series, its capacitance is effectively halved, thus releasing 0.5C from the transmission lines supplying reference voltages VREFP and VREFN. u *(VREFP-VREFN). At this time, the SAR ADC draws a maximum charge of 0.25C from the power supply. u *(VREFP-VREFN). According to the formula... It can be seen that, due to the significant reduction in extracted charge, the current change is also greatly reduced, thus the ripple can be greatly improved. Its ripple elimination effect on a 12-bit 10MSPS SAR ADC is as follows: Figure 5 As shown, with ripple neutralization disabled, the peak circuit current reaches approximately 3mA, while with it enabled, the peak current is only about 0.2mA. Meanwhile, as... Figure 6 This is reflected in the voltage ripple, which decreased from 17mV to 1.8mV. With a half-full swing input, the ADC signal-to-noise ratio (SNR) improved from 50.77dB to 64dB, and the spurious-free dynamic range (SFDR) improved from 69.5dB to 82.7dB. Figure 7 As shown.

[0057] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several modifications and improvements without departing from the structure of the present invention, and these will not affect the effectiveness of the implementation of the present invention or the practicality of the patent.

Claims

1. A successive approximation analog-to-digital converter, characterized in that, include: A capacitor array consisting of an N-terminal capacitor array and a P-terminal capacitor array is used to sample the signal and output the voltage V of the first upper plate. N The voltage V of the second upper plate P ; A comparator is used to compare the voltage V of the first upper plate. N The voltage V of the second upper plate P Compare; The logic circuit is used to control the switching of the switches in the N-terminal capacitor array and the P-terminal capacitor array according to the comparison result of the comparator, so that the voltage under the corresponding capacitor switches from the common-mode voltage VCM to the first reference voltage VREFP or the second reference voltage VREFN; the logic circuit is also provided with control logic for controlling the RRN circuit. The RRN circuit is embedded in the power supply of the SAR ADC so that it can be simultaneously connected to the transmission lines of the first reference voltage VREFP and the second reference voltage VREFN. The control logic is as follows: Calculate the charge required for the capacitor array to switch during the current comparison cycle; Calculate the required number of RNN capacitors; Calculate the sum of all RRN capacitances within the current sampling period; Output control signal; The method for calculating the charge required for switching the capacitor array during the current cycle is as follows: ， Among them, Q require D represents the charge required for the switching of the capacitor array during the current cycle. CVrefpP D is the control signal for the P-terminal capacitor array stored in the logic circuit. CVrefpN D is the control signal for the N-terminal capacitor array stored in the logic circuit. Ci C represents the number of capacitors that will be switched. u The capacitance is per unit.

2. The successive approximation analog-to-digital converter according to claim 1, characterized in that, The RRN circuit is designed with X groups, and the value of the X groups of the RRN circuit is calculated based on the ratio between the total capacitance value of the capacitor array and the capacitance value of each capacitor in it.

3. A successive approximation analog-to-digital converter according to claim 2, characterized in that, The X group value of the RRN circuit is calculated by the following formula: ， In the formula, C all C is the total capacitance value. i Let be the capacitance value of the i-th capacitor, N be the total number of capacitors in the capacitor array, and C1 be the capacitance value of the capacitor with the largest weight in the capacitor array.

4. A successive approximation analog-to-digital converter according to any one of claims 1-3, characterized in that, The RRN circuit includes a first switch (PM0), a second switch (PM1), a third switch (PM2), a fourth switch (PM3), a fifth switch (NM0), a sixth switch (NM1), a seventh switch (NM2), an eighth switch (NM3), and a first capacitor (C). P ), second capacitor (C) N The gate of the first switching transistor (PM0) is connected to the first control signal. The source of the first switching transistor (PM0) is connected to the transmission line of the first reference voltage VREFP, and the drain of the first switching transistor (PM0) is simultaneously connected to the source of the second switching transistor (PM1) and the first capacitor (C). P One end of the second switch (PM1) is connected, and the gate of the second switch (PM1) is connected to the second control signal. The drain of the second switch (PM1) is connected to the first charging voltage signal VREFP_TMP, and the first capacitor (C P The other end of the transistor is simultaneously connected to the source of the eighth switch (NM3), the drain of the third switch (PM2), and the drain of the seventh switch (NM2). The gate of the eighth switch (NM3) is connected to the third control signal. The drain of the eighth switch (NM3) is connected to the second charging voltage signal VREFN_TMP, and the gate of the third switch (PM2) is connected to the first control signal. The gate of the seventh switch (NM2) is connected to the fourth control signal. The source of the third switch (PM2) and the source of the seventh switch (NM2) are connected and simultaneously connected to the second capacitor (C). N One end of the transistor is connected to the source of the fourth switch (PM3), and the gate of the fourth switch (PM3) is connected to the second control signal. The drain of the fourth switch (PM3) is connected to the first charging voltage signal VREFP_TMP, and the second capacitor (C N The other end of the transistor is connected to the drain of the fifth switch (NM0) and the source of the sixth switch (NM1), and the gate of the fifth switch (NM0) is connected to the fourth control signal. The source of the fifth switch (NM0) is connected to the transmission line of the second reference voltage VREFN, and the gate of the sixth switch (NM1) is connected to the third control signal. The drain of the sixth switch (NM1) is connected to the second charging voltage signal VREFN_TMP; the first control signal With the fourth control signal The high and low levels of the second control signal are opposite. With the third control signal The high and low levels are opposite.

5. A successive approximation analog-to-digital converter according to claim 4, characterized in that, The first capacitor (C) P ) and second capacitor (C N The capacitances of the two capacitors are the same, and both are ADC unit capacitances.

6. A successive approximation analog-to-digital converter according to claim 4, characterized in that, The first switch (PM0) and the fifth switch (NM0) are the same size, and both are the same size as the switches in the capacitor array.

7. A successive approximation analog-to-digital converter according to claim 6, characterized in that, The third switch (PM2) and the seventh switch (NM2) are the same size, and are 3-5 times the size of the first switch (PM0) or the fifth switch (NM0).

8. A successive approximation analog-to-digital converter according to claim 1, characterized in that, The method for calculating the required number of RNN capacitors is as follows: The charge required for switching the capacitor array during the current comparison cycle is calculated according to (VREFP-VCM). C u After partitioning, the result n is obtained by step-rounding. i And write it into the logic circuit as a table; D CVrefpP With D CVrefpN Multiply by the unit capacitance C u Calculate C VrefpP With C VrefpN The number of RNN capacitors required for this switching process is obtained by subtracting the RNN capacitors from the RNN capacitors and then looking up the table based on the structure.

Images