Pulse synchronization method, electronic device, storage medium, and program product

Abstract

The application discloses a pulse synchronization method, an electronic device, a storage medium and a program product. The method comprises the following steps: acquiring a period quantity sequence generated by local clock counting; performing quality evaluation on a signal according to the period quantity sequence to determine a current signal state; determining a target count value according to the current signal state, and latching the target count value to a corresponding cache space after a latching condition is met; acquiring a current target count value from the cache space, and outputting a pulse synchronization signal based on the current target count value, wherein the pulse synchronization signal is used for pulse synchronization, thereby solving the problem of inaccurate pulse signal synchronization, obtaining a stable target count value, and effectively avoiding problems such as unstable time synchronization and poor precision caused by environmental factors; and counting the output pulse synchronization signal through the current target count value, controlling the output of the pulse synchronization signal, realizing pulse synchronization, and improving synchronization precision and stability.

Description

Technical Field

[0001] This application relates to the field of data synchronization technology, and in particular to pulse synchronization methods, electronic devices, storage media, and program products. Background Technology

[0002] Precise time synchronization is the cornerstone of collaborative operation in modern digital systems. Pulses per second (PPS) signals, as a widely used time synchronization standard, directly determine the performance of the entire synchronization network. Currently, Global Navigation Satellite Systems (GNSS), such as GPS, GLONASS, Galileo, and China's BeiDou system, are the primary sources of high-precision PPS signals. However, the stability of PPS signals output by GNSS receivers is not perfect in practical applications. The reception quality of satellite signals is susceptible to various complex environmental factors, including urban canyon effects, multipath propagation, ionospheric / tropospheric delay variations, electromagnetic interference (intentional or unintentional), receiver antenna performance, and even short-term instability of the receiver's internal clock. These factors can all cause significant phase jitter, frequency drift, and even pulse loss or periodic anomalies in GNSS PPS signals under adverse conditions.

[0003] Traditional PPS signal processing methods, such as simple digital filtering (e.g., FIR or IIR filters), analog phase-locked loops (APLLs), or basic digital phase-locked loops (DPLLs), can smooth the input signal to some extent. However, their holdover performance is often limited when faced with a sharp deterioration in the quality of the input PPS signal or a short-term interruption. This makes it difficult to meet increasingly stringent application requirements and achieve precise synchronization of pulse signals. Summary of the Invention

[0004] This application provides a pulse synchronization method, electronic device, storage medium, and program product to solve the problem of inaccurate pulse synchronization.

[0005] According to one aspect of this application, a pulse synchronization method is provided, comprising:

[0006] Obtain a sequence of period counts generated by counting with a local clock, the sequence of period counts including at least one period count, the period count being generated by detecting a second pulse signal sent by a time synchronization system;

[0007] The signal quality is evaluated based on the cycle number sequence to determine the current signal state;

[0008] The target count value is determined based on the current signal state, and the target count value is latched into the corresponding buffer space after the latching condition is met;

[0009] The current target count value is obtained from the buffer space, and a pulse synchronization signal is output based on the current target count value. The pulse synchronization signal is used for pulse synchronization.

[0010] According to another aspect of this application, a pulse synchronization device is provided, comprising:

[0011] The periodic sequence acquisition module is used to acquire a periodic quantity sequence generated by counting with a local clock. The periodic quantity sequence includes at least one periodic quantity, which is generated by detecting the second pulse signal sent by the time synchronization system.

[0012] The signal state determination module is used to perform quality assessment on the signal based on the period quantity sequence and determine the current signal state;

[0013] The target count value determination module is used to determine the target count value based on the current signal state, and latch the target count value into the corresponding buffer space after the latching condition is met;

[0014] A synchronization signal output module is used to obtain the current target count value from the buffer space and output a pulse synchronization signal based on the current target count value. The pulse synchronization signal is used for pulse synchronization.

[0015] According to another aspect of this application, an electronic device is provided, the electronic device comprising:

[0016] At least one processor, and a memory communicatively connected to said at least one processor;

[0017] The memory stores a computer program that is executed by the at least one processor, which enables the at least one processor to perform the pulse synchronization method described in any embodiment of this application.

[0018] According to another aspect of this application, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the pulse synchronization method described in any embodiment of this application.

[0019] According to another aspect of this application, a computer program product is provided, the computer program product including a computer program that, when executed by a processor, implements the pulse synchronization method described in any embodiment of this application.

[0020] The technical solution of this application embodiment obtains a cycle count sequence generated by counting with a local clock. The cycle count sequence includes at least one cycle count, generated by detecting the second pulse signal sent by the time synchronization system. The signal quality is evaluated based on the cycle count sequence to determine the current signal state. A target count value is determined based on the current signal state, and the target count value is latched into a corresponding buffer space after a latching condition is met. The current target count value is obtained from the buffer space, and a pulse synchronization signal is output based on the current target count value. This pulse synchronization signal is used for pulse synchronization, solving the problem of inaccurate pulse signal synchronization. The cycle count is generated by counting the second pulse signal sent by the time synchronization system using a local clock, thus obtaining the cycle count sequence. The pulse synchronization signal is evaluated using the pulse sequence to determine its current state. A target count value is determined based on this state, resulting in a stable count that effectively avoids instability and poor accuracy caused by environmental factors. Even with a sharp deterioration in the input PPS signal quality or a short-term interruption, a stable target count value is provided. This target count value is then latched into a corresponding buffer. Upon meeting the latching condition, the current target count value is retrieved from the buffer and latched. Latching the current target count value ensures the accuracy of the pulse synchronization signal. The output pulse synchronization signal is counted using the current target count value to control its output, achieving pulse synchronization and improving synchronization accuracy and stability.

[0021] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a flowchart of a pulse synchronization method according to Embodiment 1 of this application;

[0024] Figure 2 This is a flowchart of a pulse synchronization method according to Embodiment 2 of this application;

[0025] Figure 3This is a flowchart of a pulse synchronization method according to Embodiment 3 of this application;

[0026] Figure 4 This is a schematic diagram of the architecture of a pulse synchronization system according to Embodiment 3 of this application;

[0027] Figure 5 This is a schematic diagram of a DTFC-ACE according to Embodiment 3 of this application;

[0028] Figure 6 This is a schematic diagram illustrating the implementation of pulse synchronization according to Embodiment 3 of this application;

[0029] Figure 7 This is a schematic diagram illustrating the change of N_target and the output PPS effect when the input PPS signal has different qualities, according to Embodiment 3 of this application.

[0030] Figure 8 This is a schematic diagram of a pulse synchronization device according to Embodiment 4 of this application;

[0031] Figure 9 This is a schematic diagram of the structure of an electronic device that implements the pulse synchronization method of the embodiments of this application. Detailed Implementation

[0032] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0033] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0034] Example 1

[0035] Figure 1This is a flowchart of a pulse synchronization method provided in Embodiment 1 of this application. This embodiment is applicable to situations requiring high-precision time synchronization. The method can be executed by a pulse synchronization device, which can be implemented in hardware and / or software and can be configured in an electronic device. Figure 1 As shown, the method includes:

[0036] S101. Obtain the cycle count sequence generated by counting with the local clock. The cycle count sequence includes at least one cycle count, which is generated by detecting the second pulse signal sent by the time synchronization system.

[0037] In this embodiment, the cycle number sequence can be understood as a sequence formed by the number of cycles detected by different detection cycles; the cycle number can be understood as the number of rising edges of the second pulse detected in one detection cycle, which is generated by detecting the second pulse signal sent by the time synchronization system; one detection cycle in this embodiment refers to a period of time between two rising edge events.

[0038] The second pulse signal sent by the time synchronization system is detected and counted using a local clock. The count value within a detection period is determined and stored as the period count. At least one buffered period count is obtained to form a period count sequence.

[0039] S102. Evaluate the quality of the signal based on the periodicity sequence to determine the current signal state.

[0040] In this embodiment, the current signal state can be understood as the signal quality of the currently received second pulse signal, such as stable, jittery, or lost. The period number sequence is analyzed, including at least one period number. The magnitude and fluctuation of the period number can be analyzed to assess signal quality. Based on the analysis results, the current signal state is determined. For example, an excessively large number of periods may indicate a signal loss state, while significant fluctuations in the number of periods may indicate severe jitter, and so on.

[0041] S103. Determine the target count value based on the current signal state and cache the target count value to the corresponding cache space.

[0042] In this embodiment, the target count value can be understood as a count value used to guide the generation of the pulse synchronization signal. The target count value is a stable count value obtained after processing.

[0043] Different methods are used to calculate the target count value under different signal states to obtain a stable target count value. The current signal state is analyzed, and an appropriate calculation method is selected based on this state. The target count value is then calculated according to the selected method. For example, when the current signal state is stable, the target count value is determined by a pre-stored number of cycles; when the current signal state is in a state of severe jitter, the target count value is predicted using a neural network model, or a count value and a compensation value are calculated, with the compensation value used to compensate for the count value, and so on. After determining the target count value, it is cached in the corresponding cache space.

[0044] S104. After the latching condition is met, the current target count value is obtained from the buffer space and latched. The pulse synchronization signal is output based on the current target count value and is used for pulse synchronization.

[0045] In this embodiment, the latching condition can be preset, for example, the latching condition is to generate a target count value, or to successfully output a PPS pulse, etc. The current target count value can be understood as the target value of the current count, which serves as the current overflow target of the main counter when outputting the pulse synchronization signal.

[0046] The buffer space stores target count values ​​calculated at different times. A latching condition is pre-set. Upon detecting that the latching condition is met, a target count value is retrieved from the buffer space as the current target count value. For example, the latest target count value is retrieved as the current count value; if an unretrieved target count value is found in the buffer space, the earliest cached target count value is selected as the current count value, and so on. The current target count value is latched to ensure that it does not change during the counting period of the output pulse synchronization signal, thus preventing inaccuracies in the output pulse synchronization signal. The clock's valid edges are detected, and the count value is incremented by a set value after each valid edge is detected. When the count value reaches the current target count value, a pulse synchronization signal is output, which can then be used for pulse synchronization.

[0047] After outputting a pulse synchronization signal, the current target count value can be deleted. Upon detecting that the buffer condition is met again, a new current target count value can be acquired and latched. Alternatively, after outputting a pulse synchronization signal, the current target count value can be left undeleted. Upon detecting that the buffer condition is met again, a new current target count value can be acquired, replacing the original current target count value, and the new current target count value can be latched. For example, the latching condition could be the successful output of a pulse synchronization signal (i.e., a successful output of a pps pulse) or the generation of the first target count value.

[0048] In this embodiment, the target count value N_target can be latched as the current overflow target of the main counter. The latching timing should ensure that updating N_target does not cause problems in the middle of the counting cycle; for example, it can be updated after each output PPS is generated or at a specific moment. N_target is calculated and output in real time, representing the target value that the main counter (pps_counter) should count to in order to generate an accurate 1-second PPS pulse under the current conditions. pps_counter increments every 125MHz clock cycle. If the value of N_target suddenly changes while pps_counter is counting (i.e., before a PPS cycle has ended), the length of the currently generated PPS cycle will be inaccurate (potentially too long or too short). Therefore, it is necessary to choose an appropriate time to load or latch the new output N_target value for pps_counter as the comparison target for the next cycle. The ability to update N_target after each output PPS can be understood as follows: when pps_counter reaches its current N_target value and successfully outputs a PPS pulse (pps_out goes high), pps_counter is immediately reset to begin the next counting cycle. Simultaneously or immediately after this reset, the latest N_target value output by the ADF-PTFSM can be latched in as the overflow target for the next PPS cycle. This ensures that the target count value for each PPS cycle is determined before the cycle begins. Updating N_target at a specific time can be understood as follows: a synchronization signal or a specific state of the state machine can be designed to allow HAPPG to latch a new N_target value. This update operation should be decoupled from the pps_counter's counting process to avoid changing the target value midway through counting. That is, the value of N_target should be fixed at the beginning of a PPS cycle and only after the cycle ends and a PPS pulse is generated should a new N_target value be loaded for the next cycle.

[0049] For example, the method provided in this application embodiment can be applied to a single programmable logic device (FPGA) to achieve pulse synchronization through the hardware and software integrated in the FPGA.

[0050] This application provides a pulse synchronization method that solves the problem of inaccurate pulse signal synchronization. It uses a local clock to count the second pulse signal sent by the time synchronization system to generate a period count sequence, which includes at least one period count. The signal quality is evaluated using the period count sequence to determine the current signal state. A target count value is determined based on the current signal state. This method yields a stable target count value, effectively avoiding problems such as instability and poor accuracy in time synchronization caused by environmental factors. Even if the input PPS signal quality deteriorates sharply or experiences a short-term interruption, a stable target count value can still be provided. The target count value is then latched into a corresponding buffer space. After the latching condition is met, the current target count value is retrieved from the buffer space and latched. Latching the current target count value ensures the accuracy of the pulse synchronization signal. The output pulse synchronization signal is counted using the current target count value to control the output of the pulse synchronization signal, thereby achieving pulse synchronization and improving synchronization accuracy and stability.

[0051] Example 2

[0052] Figure 2 This is a flowchart of a pulse synchronization method provided in Embodiment 2 of this application. This embodiment is a refinement based on the above embodiments. Figure 2 As shown, the method includes:

[0053] S201. Obtain a set number of cycles from the cache space of the number of cycles to form a sequence of cycle numbers.

[0054] In this embodiment, the set quantity can be preset according to requirements, such as 10, 5, etc. The number of cycles is cached to the corresponding cache space after each count; the set number of cycles is obtained from the cache space of the number of cycles in chronological order, and a sequence of cycle numbers is formed in chronological order; for example, the latest 10 cycle numbers are obtained to form a sequence of cycle numbers.

[0055] Optionally, the process of generating the number of cycles includes: detecting the second pulse signal sent by the time synchronization system; if a rising edge event is detected and the rising edge event is not the first rising edge event, storing the current count value of the counter as the number of cycles in the buffer space of the number of cycles and clearing the current count value to zero; and controlling the counter to count the clock at a set frequency based on the local clock.

[0056] A pre-set counter counts the clock at a set frequency. A trigger detects the second pulse signal sent by the time synchronization system. If a rising edge event is detected, it is determined whether the rising edge event is the first rising edge event. If it is not the first rising edge event, the current count value of the counter is stored as the period count in the period count buffer, and the current count value of the counter is cleared. The counter restarts counting the clock at the set frequency output by the local clock until the next rising edge event is detected, at which point it is cleared again and restarted. The time between two rising edge events is one pps period. For the first detected rising edge event, since there is only one rising edge event and a complete pps period has not been formed, no period count is generated at this time, and the current count value is directly cleared. The counter is then controlled by the local clock to count the clock at the set frequency. That is, if a rising edge event is detected and it is the first rising edge event, the current count value is cleared. The counter is then controlled by the local clock to count the clock at the set frequency.

[0057] For example, this counter can be referred to as the first counter. The first counter can be a 32-bit counter (current_clk_count) driven by a 125MHz clock. The maximum counting time that a 32-bit counter can count at 125MHz is approximately (2^32) / (125×10^6)≈34.36 seconds. Since the nominal period of the PPS signal is 1 second, a 32-bit counter is sufficient to cover a 1-second period measurement without overflowing, even if the PPS period is slightly larger than 1 second due to jitter or frequency offset (e.g., reaching 1.1 seconds, corresponding to 1.1×125×10^6=137,500,000 counts, which is much smaller than 2^32).

[0058] For example, the second pulse signal sent by the time synchronization system is detected using dual D flip-flops. For instance, the input PPS signal (PPS_IN) provided by the time synchronization system first passes through the FPGA's I / O buffer; to accurately capture its rising edge and eliminate metastability, this embodiment uses a dual D flip-flop synchronous sampling mechanism to detect rising edge events. The PPS_IN signal is sampled by two consecutive D flip-flops driven by a 125MHz clock. A valid PPS rising edge event is considered detected only when the outputs of both flip-flops change from 0 to 1 within the same clock cycle (for a rising edge).

[0059] A specific implementation could be: `reg pps_s1, pps_s2; always@(posedge clk_125MHz){pps_s1<=pps_in; pps_s2<=pps_s1;}`. The rising edge event would then be `(pps_s2==1'b1&&pps_s1==1'b0)` (or `(pps_s2==1'b0&&pps_s1==1'b1)`, depending on which sample is closer to the actual edge, usually `!pps_s2&pps_s1`). This event signal (pps_in_event) is output to DTFC-ACE as a single 125MHz clock cycle pulse.

[0060] First, define two registers (corresponding to D flip-flops in the FPGA): pps_s1 and pps_s2. Both registers are triggered by the rising edge of the FPGA's internal 125MHz system clock (clk_125MHz). The externally input PPS signal (pps_in) is first sampled by the first D flip-flop pps_s1 at the rising edge of each 125MHz clock cycle. That is, pps_s1 <= pps_in. The output of the first flip-flop pps_s1 is then sampled again by the second D flip-flop pps_s2 at the rising edge of the next 125MHz clock cycle. That is, pps_s2 <= pps_s1. This cascaded sampling structure of two D flip-flops can eliminate or significantly reduce metastability caused by asynchronous signal inputs. The first stage sampling may produce metastability, but after a complete clock cycle, when the second stage flip-flop samples the output of the first stage, the metastability has a very high probability of decaying and stabilizing to logic 0 or 1. In this way, pps_s2 obtains a sampled value of pps_in from the previous cycle that is relatively stable and synchronized with the system clock.

[0061] Rising edge detection logic: A rising edge of a signal means that the signal was low (logic 0) in the previous moment and has become high (logic 1) in the current moment. Based on the signals synchronized at the two levels above: pps_s1 represents the sampled value of pps_in in the current 125MHz clock cycle; ps_s2 represents the sampled value of pps_in in the previous 125MHz clock cycle (the value after one level of synchronization). Therefore, the condition for detecting the rising edge of the pps_in signal is: the sampled value was low in the previous clock cycle (pps_s2 == 1'b0), and the sampled value was high in the current clock cycle (pps_s1 == 1'b1).

[0062] For example, the frequency is set to 125MHz. Upon detecting a rising edge event, if it is the first valid rising edge event (e.g., determined by a status flag), the current count value of the counter, `current_clk_count`, is simply reset to 0, and counting begins. If it is not the first, the current value of `current_clk_count` is latched into the cycle count `N_measured` register as the measurement result of the previous PPS cycle. Then, `current_clk_count` is immediately reset to 0, and counting for the next cycle begins. Between two `pps_in_event`s, i.e., within one PPS cycle, `current_clk_count` is incremented by 1 on each rising edge of the 125MHz clock, thus measuring the cycle count.

[0063] The core purpose of N_measured is to accurately measure the number of cycles of the FPGA's internal high-frequency local clock (125MHz) between two consecutive valid pps_in_event signals. This value directly reflects the instantaneous cycle length of the input PPS signal.

[0064] Its workflow can be summarized in the following steps:

[0065] 1. Initialization / First Valid Rising Edge Event (Rising edge event can also be called PPS event): This is the first valid pps_in_event signal received after system startup or after the enable_calibration signal becomes valid. Its main function is to initiate the cycle measurement process. At this time, the internal cycle counter current_clk_count is cleared and begins counting based on a 125MHz clock. This first event itself does not immediately generate an N_measured output because a complete PPS cycle has not yet been formed.

[0066] 2. Subsequent PPS events and the generation of N_measured: Starting from the second valid pps_in_event signal, each time this event arrives, the current value of the current_clk_count counter is latched into the N_measured register. This latched value represents the number of 125MHz clock cycles that have elapsed between the previous pps_in_event and the current pps_in_event. Then, the current_clk_count counter is immediately cleared and restarts counting for the next PPS cycle.

[0067] 3. Periodic counting: Between two consecutive pps_in_event signals, the current_clk_count counter increments by 1 on the rising edge of each 125MHz clock.

[0068] For example, let's illustrate the process of forming the number of cycles by counting cycles: assuming enable_calibration is high.

[0069] Time T0: The first valid pps_in_event arrives. current_clk_count is cleared and begins counting. At this time, N_measured has no valid updates. (Between T0 and T1, current_clk_count increments with a 125MHz clock...);

[0070] Time T1: The second valid pps_in_event arrives. Assuming the current_clk_count value is C1 at this time, N_measured is updated to C1 (representing the period length between T0 and T1). The current_clk_count is immediately cleared and counting restarts. (Between T1 and T2, the current_clk_count increments with a 125MHz clock...).

[0071] Time T2: The third valid pps_in_event arrives. Assuming the current_clk_count value is C2 at this time, N_measured is updated to C2 (representing the period length between T1 and T2). The current_clk_count is immediately cleared and counting restarts.

[0072] By analogy, the number of cycles within different PPS cycles can be obtained.

[0073] Optionally, after detecting a rising edge event, it is determined whether the calibration enable signal indicates that calibration is enabled. If the calibration enable signal indicates that calibration is enabled, it is determined whether the rising edge event is not the first rising edge event. If the rising edge event is not the first rising edge event, the current count value of the counter is stored as the number of cycles in the cache space of the number of cycles and the current count value is cleared. If the rising edge event is the first rising edge event, the current count value is cleared. The counter is controlled to count the clock of the set frequency based on the local clock.

[0074] The activation calibration signal indicates whether the pulse signal is calibrated using the method provided in this application embodiment, thereby achieving high-precision pulse synchronization. If the activation calibration signal does not indicate that calibration is enabled, the counting of the number of cycles can be stopped.

[0075] Optionally, the second pulse signal sent by the time synchronization system is detected, including: detecting the rising edge of the second pulse signal sent by the time synchronization system; if a rising edge is detected, starting a second counter to count; if the second pulse signal returns to a low level and the count value of the second counter is not less than a set value, then it is determined that a rising edge event has been detected.

[0076] To prevent narrow pulse interference on the input PPS signal from being mistakenly identified as valid PPS, this embodiment of the application incorporates digital de-glitch logic. For example, based on minimum pulse width judgment: upon detecting a rising edge of PPS_IN, a counter (i.e., a second counter) is started; if PPS_IN returns to a low level before this counter reaches a preset minimum valid pulse width (e.g., corresponding to 50 microseconds, i.e., 50µs × 125MHz = 6250 125MHz clock cycles), then this rising edge is considered a glitch, and no rising edge event pps_in_event is generated. Only when PPS_IN remains high for more than the preset width is it confirmed as the start of a valid PPS, and a rising edge event is generated, i.e., a rising edge event is determined to have been detected. Similarly, the duration of the low level can also be judged.

[0077] S202. Evaluate the quality of the signal based on the periodicity sequence to determine the current signal state.

[0078] Optionally, the signal quality is evaluated based on the period number sequence to determine the current signal state, including A1-A2:

[0079] A1. Analyze the number of periods in the period number sequence, and evaluate the signal quality based on at least one of the following: the average value of the period number sequence, the standard deviation of the first difference of the period number sequence, and the relationship between the number of periods and the period number threshold.

[0080] In this embodiment, the period number threshold can be preset. Signal quality can be one or more of the following: stable, no quality degradation, slight degradation, severe degradation, slight jitter, severe jitter, pulse loss, etc. The signal quality is assessed by analyzing the period number sequence, for example, by calculating the average, standard deviation, maximum value, the difference between the maximum and minimum values, calculating the standard deviation of the first-order difference, etc. The signal quality is determined by calculating the average period number, the standard deviation of the first-order difference, and the relationship between the period number and the period number threshold. For example, the signal quality is assessed by calculating the difference between the average period number and the latest period number, by calculating the standard deviation of the first-order difference of the period number sequence, by comparing the relationship between the period number in the period number sequence and the period number threshold, and so on.

[0081] A2. Determine the current signal state based on the signal quality. The current signal state can be stable, slightly jittery, severely jittery, or lost signal.

[0082] The current signal state is determined by analyzing signal quality and considering its impact on the signal status. Alternatively, it can be determined by comprehensively considering signal quality over a period of time, or by pre-setting current signal states corresponding to different signal qualities, and then determining the current signal state based on the correlation after the signal quality is determined. For example, after determining the signal quality, the duration of that quality is determined, and the current signal state is determined by comprehensively considering the signal quality over that period, thus avoiding abrupt changes or jumps in the signal state. The current signal state can be a stable state, a state with slight jitter, a state with severe jitter, or a state of signal loss.

[0083] For example, the following methods can be used to determine the current signal state based on signal quality:

[0084] Method 1: If the signal quality is stable and does not degrade for a first preset time, the current signal state is determined to be stable.

[0085] If the signal quality simultaneously meets the conditions of no quality degradation and stability, determine the duration of this state. If it has lasted for a first preset time, i.e. the duration is not less than the first preset time, determine that the current signal state is stable.

[0086] Method 2: If the signal quality is slightly degraded or slightly jittery and continues for a second preset time, determine that the current signal state is slightly jittery.

[0087] If the signal quality is slightly degraded or slightly jittery, determine the duration of this state. If it has lasted for a second preset time, i.e. the duration is not less than the second preset time, determine that the current signal state is a slightly jittery state.

[0088] Method 3: If the signal quality is severely degraded or jittered and continues for a third preset time, the current signal state is determined to be a state of severe jitter.

[0089] If the signal quality is severely degraded or severely jittered, determine the duration of this state. If it has lasted for a third preset time, i.e. the duration is not less than the third preset time, determine that the current signal state is a severely jittered state.

[0090] Method 4: If the signal quality is pulse loss, determine the current signal state as signal loss state.

[0091] If the signal quality is pulse loss, then the current signal state can be directly determined to be a signal loss state.

[0092] Method 5: If the signal quality is stable and continues for a fourth preset time, and the previous signal state was a state of slight jitter, severe jitter, or signal loss, then the current signal state is determined to be a stable state.

[0093] In this embodiment, the previous signal state can be understood as the signal state determined during the last signal quality assessment. If the signal quality is stable, the duration is determined. If it lasts for a fourth preset time, the previous signal state is obtained. If the previous signal state is a state of slight jitter, severe jitter, or signal loss, the current signal state is determined to be a stable state. That is, after the signal quality remains stable for a period of time, the signal changes from an unstable state to a stable state. The unstable state can be a state of slight jitter, severe jitter, or signal loss.

[0094] It should be noted that the first preset time, the second preset time, the third preset time and the fourth preset time in the embodiments of this application can be set according to actual needs, and can be the same or different, or partially the same and partially different.

[0095] Optionally, the signal quality is determined by analyzing the number of periods in the period number sequence and evaluating the signal quality based on at least one of the following: the average value of the period number sequence, the standard deviation of the first difference of the period number sequence, and the relationship between the number of periods and a period number threshold, including at least one of the following B1-B3:

[0096] B1. Calculate the average value based on the number of cycles in the cycle number sequence, and determine the absolute value of the difference between the current number of cycles and the average value. If the absolute value is between the first preset threshold and the second preset threshold and lasts for a fifth preset time, the signal quality is determined to be slightly degraded. If the absolute value is greater than or equal to the second preset threshold and lasts for a fifth preset time, the signal quality is determined to be severely degraded. If the absolute value is not greater than the first preset threshold, the signal quality is determined to be undegraded.

[0097] In this embodiment, the first preset threshold and the second preset threshold can be preset, with the second preset threshold being greater than the first preset threshold. The current number of cycles can be understood as the latest statistically obtained number of cycles at the current moment.

[0098] Select the number of cycles to be used for calculation from the cycle number sequence. For example, select all cycles in the cycle number sequence and calculate the average, or select a portion of the cycles in the cycle number sequence and calculate the average, for example, select the latest N cycles and calculate the average. Determine the current cycle number. The current cycle number can be the latest cycle number in the cycle number sequence, or it can be a cycle number that was just generated but was not generated when the cycle number sequence was obtained. Calculate the difference between the current cycle number and the average, and take the absolute value of this difference. If the absolute value is not greater than a first preset threshold, the signal quality is determined to be no degradation. If the absolute value is between the first and second preset thresholds and lasts for a fifth preset time, the signal quality is determined to be slightly degraded. If the absolute value is greater than or equal to the second preset threshold and lasts for a fifth preset time, the signal quality is determined to be severely degraded.

[0099] B2. Calculate the first-order difference based on the number of periods in the period sequence, and calculate the standard deviation based on the first-order difference. If the standard deviation is greater than the third preset threshold and less than the fourth preset threshold, the signal quality is determined to be slightly jittery; if the standard deviation is greater than or equal to the fourth preset threshold, the signal quality is determined to be severely jittery; if the standard deviation is not greater than the third preset threshold, the signal quality is determined to be stable.

[0100] In this embodiment, the third and fourth preset thresholds can be preset, with the third preset threshold being less than the fourth preset threshold. All or part of the number of periods are selected from the period number sequence. The first-order difference between two adjacent periods is calculated sequentially based on the selected period number, and the standard deviation is calculated based on each calculated first-order difference. If the standard deviation is not greater than the third preset threshold, the signal quality is determined to be stable; if the standard deviation is greater than the third preset threshold but less than the fourth preset threshold, the signal quality is determined to have slight jitter; if the standard deviation is greater than or equal to the fourth preset threshold, the signal quality is determined to have severe jitter.

[0101] B3. When it is determined, based on the number of periods in the period number sequence, that there exists a period number greater than the set period number threshold, the signal quality is determined to be pulse loss.

[0102] For example, the period number threshold is K × 1.5, where K is determined based on the target count value determined from historical records. For instance, K could be the average, median, or other values ​​of the target count value determined historically. The period number in the period number sequence is compared with the period number threshold. If there is a period number greater than the set period number threshold, the signal quality is determined to be pulse loss.

[0103] For example, signal quality is judged by the deviation of the moving average: A moving average of N_measured is maintained (e.g., the average of the most recent 8 or 16 samples, N_avg). If the absolute value of the difference between the current N_measured and N_avg, |N_measured - N_avg|, consistently exceeds a preset threshold X1 (e.g., a deviation of several hundred nanoseconds or microseconds, i.e., X1 = 0.000001 × 125,000,000 = 125 counts), the signal quality is considered to have degraded. This is determined by whether the deviation of the current N_measured value from its average value N_avg exceeds a first preset threshold. If the deviation remains excessively large, the frequency stability of the input PPS signal is considered to have decreased, i.e., the quality has degraded. Further determination is made based on whether the deviation exceeds a second preset threshold X2 to determine whether the quality degradation is severe or minor.

[0104] For example, signal quality is assessed using the short-term standard deviation of the first-order difference (jitter assessment): Calculate the first-order difference Diff(k) of the N_measured sequence: Diff(k) = N_measured(k) - N_measured(k-1). Then calculate the standard deviation of the most recent P Diff(k) values. If this standard deviation exceeds a third preset threshold Y1 (e.g., corresponding to peak-to-peak jitter of several hundred nanoseconds), the periodicity of the input PPS signal is considered to have deteriorated, i.e., jitter has increased; further, it is determined whether it exceeds a fourth preset threshold Y2 to determine whether it is minor or severe jitter.

[0105] When the deviation of the calculated average or the standard deviation of the jitter remains consistently below a certain optimal threshold, the signal state tends to transition to or remain in the STABLE (stable) state. When the deviation or standard deviation exceeds a first-level threshold (e.g., a first or third preset threshold) but remains below a second-level, worse threshold (e.g., a second or fourth preset threshold), the signal state may transition to the MINOR_JITTER (slight jitter) state. When the deviation or standard deviation exceeds a second-level, worse threshold, or when a PPS pulse loss is detected, the signal state may transition to the SEVERE_JITTER (severe jitter) or SIGNAL_LOST (signal loss) states. The output of these states (pps_quality_out) guides subsequent calculations of the target count value using different filtering or timing strategies.

[0106] In the embodiments of this application, the signal state can switch from one state to another, or it can remain unchanged. For example, the initial state is NOT_CALIBRATING or INITIALIZING; when enable_calibration is effective, if the deviation and jitter of Q consecutive N_measured samples are all less than the threshold, it enters the stable STABLE state; in the STABLE state, if the deviation exceeds the threshold X1 but is less than X2, or the jitter exceeds the threshold Y1 but is less than Y2, and this continues for a period of time, it enters the MINOR_JITTER state. If the deviation exceeds the threshold X2 or the jitter exceeds the threshold Y2 and this continues for a period of time, it enters the SEVERE_JITTER state; if pulse loss is detected, it enters the SIGNAL_LOST state. When recovering from an unstable state, more stringent conditions (e.g., more consecutive stable samples) are required to return to the STABLE state to avoid frequent state switching.

[0107] In this embodiment, the state transition does not occur immediately "as long as the threshold is exceeded once". To prevent excessively frequent and unstable state transitions (i.e., "jittering" states themselves), state machines typically incorporate continuous judgment or counting mechanisms. For example, transitioning from the STABLE state to the MINOR_JITTER state may require the deviation index to remain between X1 and X2 for several consecutive (e.g., M, where M is usually less than Q) PPS cycles, or the jitter index to remain between Y1 and Y2, or the number of times the threshold is exceeded to reach a certain proportion within a certain time window. A single overshoot may only be recorded or used for short-term alarms, and may not immediately trigger the transition to the core states (STABLE, MINOR_JITTER, SEVERE_JITTER) of the state machine, unless the overshoot is so severe that it directly reaches the criteria for a worse state. Therefore, the state transition logic is more robust than "switching as long as the threshold is exceeded once," and comprehensively considers the signal performance over a period of time.

[0108] The current signal state is typically updated once per PPS cycle (or each time a new N_measured value becomes available for analysis). It reflects the current stable state of the signal. The determination of the signal state is related to the output of signal quality, but the switching of the signal state requires the satisfaction of a persistence condition.

[0109] For example, even if the jitter value of the current PPS period slightly exceeds the threshold of the STABLE state, if it has been STABLE previously and the state transition requires "M consecutive overshoots" before entering MINOR_JITTER, then pps_quality_out may still output STABLE until these M overshoots are completed. Once the switching condition (e.g., M consecutive overshoots) is met, the state will transition to a new state (e.g., MINOR_JITTER), and from this point on, the current signal state pps_quality_out will output MINOR_JITTER until the condition for transitioning to another state is met again.

[0110] Recovery from an unstable state to a stable state requires multiple consecutive samples. This is to increase the system's stability after recovering from a fault or severe interference, and to avoid incorrectly classifying it as STABLE when the signal has just improved but is not fully stable, and then quickly falling back to an unstable state. Output method: Since multiple consecutive samples need to stabilize over a period of time, pps_quality_out may still output the previous unstable state (e.g., MINOR_JITTER or SEVERE_JITTER). Only when multiple consecutive samples (e.g., Q samples) satisfy the STABLE state criteria will the signal state truly transition to STABLE, at which point pps_quality_out will output the STABLE state.

[0111] It is understood that the current signal state determined by the quality assessment in this application embodiment is the currently established state, and the state transition itself is based on a comprehensive assessment of the signal quality over a period of time, rather than an instantaneous response to each input (unless it is a serious event that can be directly judged, such as PPS loss).

[0112] S203. Determine the target count value based on the current signal state and cache the target count value to the corresponding cache space.

[0113] S204. After the latching condition is met, retrieve the current target count value from the cache space and latch the current target count value.

[0114] S205. Determine the initial count value, and determine the maximum count value based on the initial count value and the current target count value.

[0115] In this embodiment, the initial count value can be understood as the initial value of the counter; the highest count value can be understood as the highest value recorded by the counter. A numerical value is initialized as the initial count value, for example, 0. The sum of the initial count value and the current target count value, SUM, is calculated. The highest count value is determined based on SUM, for example, SUM can be used as the highest count value, or SUM-1 can be used as the highest count value, etc. The highest count value can be determined according to different counting methods.

[0116] S206. After detecting a rising edge event, control the main counter to start counting from the initial counting value. The initial counting value of the main counter is accumulated after detecting the rising edge of the clock at the set frequency.

[0117] After detecting a rising edge event, the main counter is controlled to start counting from the initial counting value. The count value of the main counter is increased by a set value x each time a rising edge of a clock at a set frequency is detected; that is, after detecting a rising edge of a clock at a set frequency, the count value of the main counter is incremented by x, and the count value of the main counter is incremented from the initial counting value. For example, the value of x is 1.

[0118] S207. After the main counter reaches its maximum count value, output a high-level signal with a set pulse width and restore the main counter's count value to its initial count value.

[0119] After the main counter reaches its maximum count value, a pulse signal is generated, and a high-level signal with a set pulse width is output as a pulse synchronization signal. The count value of the main counter is then restored to its initial count value, and the counting cycle begins again.

[0120] For example, taking an initial count value of 0 as an example, the output process of the pulse synchronization signal is explained as follows: When a PPS cycle begins (for example, after the previous PPS pulse is generated, the count value pps_counter of the main counter is reset to 0), the value of pps_counter increments on each rising edge of the next 125MHz clock: 0->1->2->3->... This incrementing process continues until the value of pps_counter reaches the currently latched N_target-1 (or N_target, depending on the specific comparison logic and the expected pulse generation time; both have similar effects, only the comparison value and judgment condition are slightly different). When the maximum count value is reached, the generation of the next PPS pulse is triggered, and pps_counter is reset to 0 again, starting the counting and incrementing of the next cycle. Therefore, pps_counter increments by 1 once every 125MHz (i.e., every 8 nanoseconds), continuously recording the number of 125MHz clock cycles that have elapsed since the last PPS pulse was generated.

[0121] ps_counter starts counting from 0. When the value of pps_counter reaches N_target-1 (or N_target, depending on the counting method):

[0122] 1. Set the pps_out signal to high level.

[0123] 2. Start a pulse width counter (e.g., 16-bit, pulse_width_counter).

[0124] 3. The main counter pps_counter is immediately reset to 0, and the next round of counting for 1-second cycles begins.

[0125] The pulse_width_counter counts at 125MHz. When the preset pulse width value is reached (e.g., for a 100ms pulse width, the count value is 0.1s × 125MHz = 12,500,000; for a 100us pulse width, the count value is 0.0001s × 125MHz = 12,500. This can be configured by ECCSIU), the pps_out signal goes low, and the pulse ends.

[0126] Optionally, the method further includes: upon receiving a timekeeping mode switching instruction, determining that the current signal state is either a severe jitter state or a signal loss state.

[0127] In this embodiment, the timekeeping mode switching command can be understood as an instruction to switch to timekeeping mode. Timekeeping mode refers to a mode where the current signal state is poor, requiring the prediction of a stable target count value to ensure accurate synchronization. In this embodiment, when the current signal state is in a state of severe jitter or pulse loss, it can automatically enter timekeeping mode. Upon receiving the timekeeping mode switching command, it determines that the current signal state is in a state of severe jitter or signal loss, and forcibly enters timekeeping mode. When this execution device receives the timekeeping mode switching command, the signal state it determines may be stable, slightly jittery, severely jittery, etc. Regardless of the determined signal state, it forcibly switches to a state of severe jitter or signal loss after receiving the timekeeping mode switching command; when the signal state is in a state of severe jitter or signal loss, it can be considered to have entered timekeeping mode.

[0128] The timekeeping mode switching instruction can be carried in a specific command, for example, in an SPI command.

[0129] Optionally, the timekeeping mode switching command is generated and sent by the main control system after detecting that the timekeeping conditions are met.

[0130] In this embodiment, the master control system can be understood as an external control system, which may be a processor or controller, such as a CPU of a PTP master clock or other host computer controller, i.e., an SPI master. The timekeeping conditions can be preset. After detecting that the timekeeping conditions are met, the master control system generates a timekeeping mode switching instruction and sends it to the execution device.

[0131] Optionally, the punctuality condition includes at least one of the following:

[0132] The status information of the time synchronization system meets the switching conditions;

[0133] It is predicted that the time synchronization system will experience a jump or interruption within a certain period of time;

[0134] A switching instruction has been received.

[0135] In this embodiment, the status information of the time synchronization system can include satellite signal quality, the number of locked satellites, whether antenna switching is in progress, and whether the receiver is performing internal self-calibration. Switching conditions are preset; when the status information of the time synchronization system meets these conditions, the timekeeping condition is considered met. The main control system can directly communicate with the satellite receiver module to obtain the status information of the time synchronization system and determine whether the switching conditions are met. For example, if the status information of the time synchronization system is one or more of the following: weak satellite signal, insufficient number of locked satellites, antenna switching in progress, or receiver internal self-calibration, the switching condition can be considered met. In the above situations, even if the satellite receiver is still outputting a PPS signal (the quality may have begun to degrade but has not yet reached the critical threshold within the FPGA), the main control system can, based on its earlier and more comprehensive judgment, pre-force the PPS timekeeping module into timekeeping mode to avoid using a PPS input that may soon become unreliable.

[0136] The main control system can predict whether the time synchronization system will experience a jump or interruption within a certain period of time based on external information. For example, the external information could be information from an external reference source or other information. If it is predicted that the time synchronization system will experience a jump or interruption within a certain period of time, for example, by switching to a backup reference source, then the timekeeping condition can be considered met. By generating a timekeeping mode switching command, the execution device is forced to enter timekeeping mode, and then exits after the external reference stabilizes, thus achieving a smooth transition.

[0137] Switching commands can be automatically generated or manually triggered by maintenance personnel. When performing system maintenance or requiring specific testing, switching commands can be generated automatically or manually to control the device to enter standby mode for specific system tests or maintenance operations.

[0138] Optionally, the method further includes: upon receiving a timekeeping mode exit command, determining whether the current signal state is a small jitter or a stable state.

[0139] In this embodiment, the timekeeping mode exit command can be understood as a control command to exit the timekeeping mode. Upon receiving the timekeeping mode exit command, it is determined that the current signal state is either slightly jittery or stable, and the timekeeping mode is forcibly exited.

[0140] Optionally, the timekeeping mode exit command is generated and sent by the main control system after it detects that the time synchronization system has recovered to a stable state.

[0141] The master control system confirms that the time synchronization system has returned to a highly stable and reliable state. However, this execution device may not have fully exited timekeeping mode and is closely tracking the new reference due to its slow pull-in mechanism or more conservative recovery criteria. At this point, the master control system can force it to exit timekeeping mode to accelerate synchronization with the new reference.

[0142] This application provides a pulse synchronization method that solves the problem of inaccurate pulse signal synchronization. It counts a counter by detecting rising edge events to determine the number of cycles within a PPS period, thus measuring the length of the PPS period. The signal quality is accurately evaluated by calculating the average and standard deviation of the number of cycles in the cycle count sequence, determining the current signal state. A target count value is determined based on the current signal state. This method yields a stable target count value, effectively avoiding problems such as unstable time synchronization and poor accuracy caused by environmental factors. Even if the input PPS signal quality deteriorates sharply or is interrupted briefly, a stable target count value can still be provided. The target count value is latched into a corresponding buffer space. After the latching condition is met, the current target count value is retrieved from the buffer space and latched. By latching the current target count value, the inaccuracy of the output pulse synchronization signal is avoided due to changes in the current target count value during the output pulse synchronization process, achieving high pulse synchronization and improving synchronization accuracy and stability. The pulse synchronization method provided in this application can automatically adapt to dynamic changes in the quality of the input PPS signal without manual intervention or complex parameter reconfiguration, exhibiting excellent performance under various complex electromagnetic environments and signal reception conditions. The system boasts high integration and strong configurability, making it easy to achieve high integration and miniaturization, while also providing great flexibility for future algorithm upgrades and online parameter optimization.

[0143] Example 3

[0144] Figure 3 This is a flowchart of a pulse synchronization method provided in Embodiment 3 of this application. This embodiment is a refinement based on the above embodiments. Figure 3 As shown, the method includes:

[0145] S301. Obtain the cycle count sequence generated by counting with the local clock. The cycle count sequence includes at least one cycle count, which is generated by detecting the second pulse signal sent by the time synchronization system.

[0146] S302. Evaluate the quality of the signal based on the period quantity sequence to determine the current signal state.

[0147] S303. When the current signal state is stable or slightly jittery, determine the target count value based on the number of cycles in the cycle count sequence.

[0148] When the current signal state is stable or has slight jitter, the PPS signal quality can be considered good. The target count value can be determined by directly analyzing the number of cycles in the cycle count sequence. For example, the average number of cycles in the cycle count sequence can be used as the target count value.

[0149] S304. When the current signal state is a severe jitter state or a signal loss state, determine the previous stable target count value, and determine the target count value based on the previous stable target count value.

[0150] In this embodiment, the previous stable target count value can be understood as the target count value under the previous stable condition. When the current signal state is in a state of severe jitter or signal loss, the PPS signal quality can be considered poor, and the reliability of the measured number of cycles is low. Therefore, the number of cycles in the cycle number sequence is not directly used to determine the target count value. Determining the previous stable target count value can be done by directly using the previous stable target count value as the target count value, or by compensating the previous stable target count value and using the compensated value as the target count value. In this embodiment, after each target count value is calculated, the target count value can be marked according to the current signal state. For example, the target count value determined in a stable state is marked as a stable state.

[0151] S305. Cache the target count value to the corresponding cache space.

[0152] S306. After the latching condition is met, the current target count value is obtained from the buffer space and latched. The pulse synchronization signal is output based on the current target count value and is used for pulse synchronization.

[0153] Optionally, the target count value is determined based on the number of periods in the period count sequence, including steps C1-C3:

[0154] C1. Determine the first count value based on the number of cycles in the cycle number sequence.

[0155] In this embodiment, the first count value can be understood as a count value obtained by calculating the number of periods. The number of periods in the period number sequence is analyzed, for example, by calculating the average value, weighted average value, etc., to obtain the first count value.

[0156] C2. If the previous signal state was a stable state or a state with slight jitter, the first count value is determined as the target count value.

[0157] Determine the previous signal state. If the previous signal state is a stable state or a state with slight jitter, it can be assumed that the PPS signal quality has always been good. In this case, the first count value is directly determined as the target count value.

[0158] C3. If the previous signal state was a severe jitter state or a signal loss state, determine the phase error between the phase of the currently output pulse synchronization signal and the phase of the input second pulse signal, determine the correction amount based on the phase error, and use the sum of the correction amount and the first count value as the target count value.

[0159] If the previous signal state was one of severe jitter or signal loss, it can be considered that the signal has recovered from an unstable state to a relatively stable state. At this point, it is necessary to control the target count value to smoothly converge to a value corresponding to the average period of the newly recovered input PPS, avoiding visually noticeable jumps in the output PPS. The method employed is as follows: determine the phase error between the phase of the currently output pulse synchronization signal and the phase of the input second pulse signal; calculate the correction amount based on the phase error. For example, the phase error can be used as input to a prediction model to predict the correction amount; alternatively, the correction amount can be calculated using a digital proportional-integral (PI) controller, with the phase error used as input to the PI controller, outputting a small correction amount. The sum of the correction amount and the first count value is used as the target count value, i.e., the correction amount is superimposed on the first count value to obtain the target count value. The parameters of the PI controller (proportional gain Kp, integral gain Ki) determine the speed and stability of the phase correction. The design goal is to quickly eliminate steady-state phase errors while avoiding overshoot.

[0160] During pulse synchronization, as the current signal state recovers from a state of severe jitter or signal loss to a stable state, the target count value is smoothly adjusted by gradually correcting the phase error between the output pulse synchronization signal and the input second pulse signal.

[0161] Optionally, a first count value is determined based on the number of periods in the period count sequence, including at least one of D1 and D2:

[0162] D1. Determine the weight information based on the current signal state, select the first number of cycles from the cycle number sequence, and weight the selected cycle number according to the weight information to obtain the first count value.

[0163] In this embodiment, the weight information may include multiple weights. For example, the weight information may include a first number of weights, each weight corresponding to a number of cycles, and weights are applied to a number of cycles. Different weight information is pre-set and stored for different signal states. After determining the current signal state, the correspondence between the pre-stored weight information and the signal state is queried to determine the weight information corresponding to the current signal state. The size of the first number can be pre-set, and the first number is less than or equal to the length of the cycle number sequence. The first number of cycles can be selected from the cycle number sequence in a certain order, or randomly selected, etc. For example, the latest first number of cycles can be selected in chronological order. The weight corresponding to each selected cycle number is determined based on the weight information, and the cycle numbers are weighted and summed according to the weights to obtain a first count value.

[0164] For example, this application provides a method for calculating a first count value:

[0165] N_target(k) = (w_k × N_measured(k) + w_{k-1} × N_measured(k-1) + ... + w_1 × N_measured(k-M+1)) / (sum of weights); the weights w_i are dynamically adjusted according to the current signal state, i = 1…k. For example, in the STABLE state, the recent N_measured weights are higher, and the historical N_measured weights are lower, in order to quickly track small changes; in the MINOR_JITTER state, all weights tend to be averaged, or more emphasis is placed on the historical average, in order to smooth out jitter.

[0166] D2. Determine the first filtering parameter based on the current signal state, filter out the latest cycle number from the cycle number sequence, and determine the previous target count value. Perform weighted filtering on the latest cycle number and the previous target count value based on the first filtering parameter to determine the first count value.

[0167] In this embodiment, the first filter parameter can be understood as a filter parameter or filter coefficient; the previous target count value can be understood as the target count value calculated previously. Different first filter parameters are pre-set and stored for different signal states. After determining the current signal state, the correspondence between the pre-stored weight information and the first filter parameters is queried to determine the first filter parameter corresponding to the current signal state. The latest cycle count is filtered out from the cycle count sequence in chronological order. In this embodiment, the target count value can be stored after each calculation to form a historical record. When calculating the first count value, the historical record is queried to determine the previous target count value. The weights of the latest cycle count and the previous target count value are determined according to the first filter parameter. The latest cycle count and the previous target count value are weighted and summed according to the weights to determine the first count value.

[0168] For example, this application provides another method for calculating the first count value:

[0169] N_target(k) = α × N_measured(k) + (1-α) × N_target(k-1); the filter coefficient α (alpha) is dynamically controlled by pps_quality_out and IRSTCU (during resynchronization); in STABLE mode, α is larger (e.g., 0.1 to 0.5), allowing N_target to track changes in N_measured more quickly, thus compensating for local crystal oscillator temperature drift. In MINOR_JITTER mode, α is reduced (e.g., 0.01 to 0.1), enhancing the filtering effect and smoothing jitter; in SEVERE_JITTER or SIGNAL_LOST (timekeeping mode), α is set to a minimum value (close to 0) or completely 0. At this time, N_target(k) ≈ N_target(k-1), that is, maintaining the target value of the previous cycle.

[0170] Optionally, the target count value is determined based on the number of periods in the period count sequence, including at least one of E1 and E2:

[0171] E1. If the previous signal state was a severe jitter state or a signal loss state, determine the weight information and the second quantity based on the time recovery time, select the second quantity of cycles from the cycle quantity sequence, and weight the selected cycle quantity according to the weight information to obtain the target count value.

[0172] When the current signal state is stable or has slight jitter, if the previous signal state was severely jittered or lost, it can be considered that the severely jittered or lost signal state has recovered to a stable or slightly jittered state. This triggers a slow pull-in mechanism, gradually increasing the confidence in the newly recovered stable input PPS signal (i.e., tracking speed) while reducing the reliance on historical data or prediction models in the previous timekeeping mode. This application provides two slow pull-in methods, E1 and E2.

[0173] The time to enter timekeeping mode is determined and recorded as the timekeeping recovery time. The correspondence between different timekeeping recovery times, weight information, and the second quantity is pre-defined and stored. After determining the timekeeping recovery time, the correspondence is queried to determine its corresponding weight information and second quantity. The second quantity of cycles is selected from the cycle quantity sequence. This can be done by filtering in a certain order or by random selection, etc. For example, the latest second quantity of cycles can be selected in chronological order. Based on the weight information corresponding to the timekeeping recovery time, the weight corresponding to each selected cycle quantity is determined. The cycle quantities are then weighted and summed according to their weights to obtain the target count value.

[0174] For example, upon recovery from timed mode, historical N_target (or values ​​based on the prediction model) is given a higher "virtual" weight, while newly entering N_measured is given a lower weight. Over time (multiple PPS cycles), the weight of new N_measured in calculating N_target is gradually increased, while the weight of historical or predicted values ​​is decreased, until a full transition to normal WMA calculation based on the new input signal is achieved. Alternatively, the WMA window size M (M being a second quantity) can be adjusted, gradually decreasing from a larger M (smoother, slower response) to a smaller M (faster response).

[0175] E2. If the previous signal state was a severe jitter state or a signal loss state, determine the second filtering parameter based on the time recovery time, filter out the latest cycle number from the cycle number sequence, determine the previous target count value, and perform weighted filtering on the latest cycle number and the previous target count value based on the second filtering parameter to determine the target count value.

[0176] In this embodiment, the second filtering parameter can be understood as a filtering parameter or filtering coefficient. The correspondence between different time recovery times and the second filtering parameter is predetermined and stored. After determining the time recovery time, the correspondence is queried to determine the corresponding second filtering parameter. The latest cycle count is filtered from the cycle count sequence in chronological order; simultaneously, the previous target count value is determined by querying historical records; the weights of the latest cycle count and the previous target count value are determined based on the second filtering parameter; and a weighted sum of the latest cycle count and the previous target count value is performed based on the weights to determine the target count value. For example, the second filtering parameter is used as the weight of the latest cycle count, and 1 minus the second filtering parameter is used as the weight of the previous target count value.

[0177] For example, slow pull-in can be achieved by gradually increasing the second filter coefficient (starting from a very small value close to 0, such as 0.001, and gradually and smoothly increasing it over several PPS periods until it returns to the value under normal tracking conditions, such as 0.1). The step size and rate of increase of the second filter coefficient are configurable to control the resynchronization time. A smaller second filter coefficient means a lower weight for the current N_measured, resulting in a slower response; gradually increasing the second filter coefficient will speed up the tracking of new input signals.

[0178] Optionally, the target count value is determined based on the previous stable target count value, including at least one of F1 and F2:

[0179] F1. Use the previous stable target count value as the target count value.

[0180] F2. Predict the cumulative drift, add the cumulative drift to the previous stable target count value to obtain the target count value.

[0181] In this embodiment, the cumulative drift is the count value corresponding to the cumulative frequency drift of the local crystal oscillator relative to its frequency at the time N_target_last_stable, estimated from the start of entering the timekeeping mode to the current time t_current.

[0182] By analyzing factors such as frequency and temperature, the cumulative drift is predicted; the cumulative drift is added to the previous stable target count value, and the cumulative drift is used to compensate for the previous stable target count value to obtain the target count value.

[0183] For example, this application provides a formula for calculating a target count value:

[0184] N_target_holdover(t_current) = N_target_last_stable + Accumulated_Drift_Prediction; where N_target_holdover(t_current) is the target count value obtained after compensation, N_target_last_stable is the previous stable target count value, that is, the last N_target value considered stable before entering the timekeeping mode. It is the N_target value calculated and latched when the input PPS signal is last determined to be in a STABLE (stable) state before entering the timekeeping mode, and it serves as the benchmark for frequency prediction during the timekeeping period; Accumulated_Drift_Prediction is the accumulated drift, which is added to N_target_last_stable to compensate for the natural drift of the local crystal oscillator during the timekeeping period.

[0185] Optionally, predict cumulative drift, including at least one of G1 and G2:

[0186] G1. Determine the frequency drift rate and the timekeeping time. Multiply the frequency drift rate by the timekeeping time to obtain the cumulative drift.

[0187] In this embodiment, the frequency drift rate can be understood as the change in the count value corresponding to the frequency drift per second, used to describe the rate of change of the local crystal oscillator's frequency deviation relative to an ideal 1 second. The timekeeping time can be understood as the time to enter timekeeping mode.

[0188] By comparing the change in N_target in the short period before entering timekeeping mode, the change in count value corresponding to the frequency drift of the local crystal oscillator per second relative to the ideal 1 second can be estimated, thus obtaining the frequency drift rate. For example, if N_target changes from A to A+50 in the last 10 seconds before entering timekeeping mode (meaning the crystal oscillator has slowed down relative to the ideal 1 second, counting 5 more times per second), then the frequency drift rate drift_rate_count_per_second is approximately equal to (A+50-A) / 10 = 5 counts / second. Determine the time point of entering timekeeping mode and the current time, calculate the timekeeping time; multiply the frequency drift rate by the timekeeping time to obtain the cumulative drift, that is, by multiplying the estimated drift per second by the length of the timekeeping period (Δt seconds), the predicted drift of the cumulative count value during this period is obtained.

[0189] G2. Obtain the current temperature, and determine the temperature compensation count based on the current temperature and the pre-generated temperature characteristic table. Use the temperature compensation count as the cumulative drift.

[0190] In this embodiment, the current temperature can be understood as the temperature of the local crystal oscillator at the current moment, which can be acquired by a temperature sensor. The temperature characteristic table can be understood as information related to the corresponding storage temperature and the effect of temperature on the count value; the temperature compensation count can be understood as the compensation value for the count value at the current temperature.

[0191] During pulse synchronization, the temperature of the local crystal oscillator is recorded in real time, and the current temperature is recorded as the current temperature. Stable target count values ​​at different temperatures during normal operation are pre-recorded. Compensation values ​​are calculated based on these stable target count values ​​to form a temperature characteristic table, or the stable target count values ​​are stored in a table to form a temperature characteristic table. The temperature compensation count is obtained by querying the temperature characteristic table based on the current temperature, or the count value is determined based on the current temperature, and then the temperature compensation count is determined based on the count value. This temperature compensation count is used as the cumulative drift. This method can more accurately compensate for temperature drift and extend the timekeeping time.

[0192] Optionally, based on the current temperature and a pre-generated temperature characteristic table, a temperature compensation count is determined, including at least one of H1 and H2:

[0193] H1. When the temperature characteristic table contains the corresponding stored temperature and compensation value, the temperature characteristic table is queried according to the current temperature, and the compensation value corresponding to the current temperature is used as the temperature compensation count.

[0194] When the temperature characteristic table contains the corresponding stored temperature and compensation value, the compensation value corresponding to the current temperature can be directly determined by querying the temperature characteristic table based on the current temperature, and this compensation value is used as the temperature compensation count.

[0195] H2. When the temperature characteristic table corresponds to the stored temperature and count value, determine the previous steady-state temperature, query the temperature characteristic table according to the current temperature to determine the second count value, query the temperature characteristic table according to the previous steady-state temperature to determine the third count value, and use the difference between the second count value and the third count value as the temperature compensation count.

[0196] In this embodiment, the temperature of the previous stable state can be understood as the temperature corresponding to the previous stable state; the second count value and the third count value are the target count values ​​under ideal conditions.

[0197] When the temperature and count value are stored in the temperature characteristic table, the time of the previous steady state is determined, and the corresponding temperature is obtained based on the time and recorded as the previous steady state temperature. The temperature characteristic table is then consulted based on the current temperature, and the count value corresponding to the current temperature is used as the second count value. The temperature characteristic table is then consulted based on the previous steady state temperature, and the count value corresponding to the previous steady state temperature is used as the third count value. The difference between the second and third count values ​​is calculated, and this difference is used as the temperature compensation count. This method accurately compensates for the local crystal oscillator frequency drift caused by changes in ambient temperature, thereby achieving longer and more accurate timekeeping performance.

[0198] For example, the N_target compensation value or absolute ideal value corresponding to different discrete temperature points (every 1°C) can be calculated in advance through experimental calibration or based on the fT data provided in the crystal oscillator datasheet. The absolute ideal value is the target count value under ideal conditions. These correspondences between "temperature point - N_target compensation value / absolute value" are stored in a look-up table (LUT) inside the FPGA. During the timekeeping period, after reading the current temperature, the FPGA retrieves the corresponding F(current_temp) and F(temp_at_last_stable) values ​​by looking up this table.

[0199] Temperature compensation count temp_compensation_counts = F(current_temp) - F(temp_at_last_stable).

[0200] For example, determining the target count value based on the current signal state can be achieved in the following way:

[0201] 1. If the current signal state is stable or slightly jittery and the previous signal state was stable or slightly jittery, determine the first count value based on the number of cycles in the cycle count sequence, and set the first count value as the target count value.

[0202] 2. If the current signal state is stable or slightly jittery and the previous signal state was severely jittery or lost, determine the first count value based on the number of cycles in the cycle number sequence, determine the phase error between the phase of the currently output pulse synchronization signal and the phase of the input second pulse signal, determine the correction amount based on the phase error, and use the sum of the correction amount and the first count value as the target count value.

[0203] 3. If the current signal state is stable or slightly jittery and the previous signal state was severely jittery or lost, determine the weight information and the second quantity based on the time recovery time. Select the second quantity of cycles from the cycle quantity sequence. Weight the selected cycle quantity according to the weight information to obtain the target count value.

[0204] 4. If the current signal state is stable or has slight jitter, and the previous signal state was severe jitter or signal loss, determine the second filtering parameter based on the time recovery time. Filter the latest cycle count from the cycle count sequence and determine the previous target count value. Apply a weighted filter to the latest cycle count and the previous target count value based on the second filtering parameter to determine the target count value.

[0205] 5. If the current signal status is severe jitter or signal loss, determine the previous stable target count value, and then determine the target count value based on the previous stable target count value.

[0206] This application provides a pulse synchronization method that solves the problem of inaccurate pulse signal synchronization. It uses a local clock to count the second pulse signal sent by the time synchronization system to generate a period count sequence, which includes at least one period count. The signal quality is evaluated using the period count sequence to determine the current signal state. A target count value is determined based on the current signal state. This method yields a stable target count value, effectively avoiding problems such as instability and poor accuracy in time synchronization caused by environmental factors. Even if the input PPS signal quality deteriorates sharply or experiences a short-term interruption, a stable target count value can still be provided. The target count value is then latched into a corresponding buffer space. After the latching condition is met, the current target count value is retrieved from the buffer space and latched. Latching the current target count value ensures the accuracy of the pulse synchronization signal. The output pulse synchronization signal is counted using the current target count value to control the output of the pulse synchronization signal, thereby achieving pulse synchronization and improving synchronization accuracy and stability.

[0207] This application provides a pulse synchronization method that solves the problem of inaccurate pulse signal synchronization. The short-term jitter (such as TDEV and Allen variance) of the output PPS signal is significantly improved, typically by 1-2 orders of magnitude compared to the original input GNSS PPS signal. This provides a rock-solid time reference for high-precision applications and exhibits excellent short-term stability. When the input PPS signal deteriorates or is lost, the system can automatically switch to a timekeeping mode based on historical data and a predictive model. This maintains the frequency accuracy and phase continuity of the output PPS for a relatively long period (the specific duration depends on the short-term stability of the local crystal oscillator and the rate of change of ambient temperature), far exceeding the open-loop hold capability of traditional DPLLs. After the input PPS is recovered, the system employs a controlled slow pull-in mechanism to ensure a smooth transition in the frequency and phase of the output PPS, avoiding lock-out or performance oscillations in downstream precision timing systems such as PTP. Thanks to its real-time dynamic frequency measurement and calibration mechanism, the system effectively compensates for the initial frequency deviation and slow temperature drift of conventional crystal oscillators (XOs) during operation. This eliminates the need for expensive and bulky high-stability oscillators (such as OCXOs or high-performance TCXOs), significantly reducing system cost, power consumption, and physical size, thus facilitating modular and embedded applications. The system boasts high integration and configurability, significantly improving the performance and reliability of downstream application systems. It provides an unprecedented high-quality PPS source for applications such as PTP master clocks, communication synchronization, and precision measurement, directly enhancing the overall synchronization accuracy, stability, and survivability in harsh environments.

[0208] For example, Figure 4A schematic diagram of the architecture of a pulse synchronization system is provided. The pulse synchronization system includes: a High-Resolution Local Clock Unit (HLCU), an Input Pulse Precision Capture and Pre-processing Unit (IPCPPU), a Dynamic Time-Frequency Characterization and Adaptive Calibration Engine (DTFC-ACE), a High-Precision Adjustable Period Pulse Generator (HAPPG), an Intelligent Re-synchronization and Smooth Transition Control Unit (IRSTCU), and an External Collaborative Control and Status Interface Unit (ECCSIU).

[0209] The HLCU employs a conventional crystal oscillator (e.g., an XO with a nominal frequency of 125 MHz) with excellent short-term stability as the system's internal time reference. This invention does not rely on the absolute long-term frequency accuracy of this crystal oscillator, but rather cleverly utilizes its high short-term frequency consistency within a specific operating temperature range as a "digital vernier" for precision measurements.

[0210] The IPCPPU is responsible for receiving the externally input PPS signal (PPS_IN). Through high-speed digital sampling and edge detection logic, it accurately marks the arrival time of the valid edge (such as the rising edge) of the input PPS signal in units of the HLCU clock cycle.

[0211] DTFC-ACE is responsible for in-depth analysis of the input PPS signal and dynamic "training" of the local clock to determine the target count value N_target, maximizing the accuracy of the output PPS. DTFC-ACE includes: an Instantaneous Period Quantization Module (IPQM), a Signal Quality Assessment and State Decision Module (SQADM), and an Adaptive Digital Filtering and Predictive Target Frequency Synthesis Module (ADF-PTFSM).

[0212] The HAPPG contains an internal master counter driven by the HLCU's high-frequency clock. The master counter uses the real-time output N_target from the DTFC-ACE as its overflow value. Whenever the master counter reaches N_target local clock cycles, the HAPPG precisely generates a one-cycle output PPS signal (PPS_OUT) and immediately resets the master counter to begin the next counting cycle. The pulse width of the output PPS can be configured independently.

[0213] IRSTCU is activated when the SQADM detects that the input PPS signal has recovered from an unstable state to a stable state. It controls the ADF-PTFSM to gradually calibrate the current N_target (which may have drifted during the timekeeping period) to a level consistent with the newly recovered stable input PPS at a controlled, asymptotic rate (e.g., the "slow start" or "narrow bandwidth capture" characteristics of an analog PLL). This "soft" synchronization mechanism aims to avoid phase steps or frequency abrupt changes in the output PPS, ensuring a disturbance-free transition to downstream systems.

[0214] ECCSIU provides communication interfaces (such as SPI, I2C, or GPIO) with external master control systems (e.g., the CPU of a PTP master clock). This allows the master control system to send control commands to the system based on its more comprehensive assessment of the satellite receiver's status (e.g., satellite lock count, DOP value, timing mode, etc.). These commands can be used to force entry into timekeeping mode, allow initial calibration, and query internal status. The system can also use this interface to report its internal operating status, current N_target, and evaluated input PPS quality to the host computer.

[0215] For example, Figure 5A schematic diagram of the structure of DTFC-ACE is provided. DTFC-ACE includes: IPQM, SQADM and ADF-PTFSM.

[0216] Among them, IPQM accurately calculates the number of clock cycles (N_measured) generated by HLCU within each input PPS cycle based on the continuous PPS arrival time captured by IPCPPU. This value directly reflects the proportional relationship between the instantaneous frequency of the input PPS and the frequency of HLCU.

[0217] SQADM analyzes the statistical characteristics of the N_measured sequence in real time (such as short-term variance, rate of change, deviation from historical mean, whether it is continuously lost, etc.) and intelligently evaluates the quality level of the current input PPS signal (such as: stable, slight jitter, severe jitter, lost).

[0218] ADF-PTFSM determines the current signal state based on signal quality and calculates the target count value accordingly. For example, when the input PPS is determined to be "stable" or "slightly jittery" by SQADM, this module uses a digital filtering algorithm with dynamically adjusted parameters (e.g., an adaptive bandwidth low-pass filter, a machine learning-based trend prediction filter, or a robust estimation algorithm that can distinguish between random noise and true frequency drift) to process the N_measured sequence, generating a highly smooth target count value (N_target) that accurately tracks the long-term average frequency of the input PPS. This N_target is essentially the count value that the local clock should have within an ideal "1 second," dynamically compensating for the inherent frequency offset and slow temperature drift of the local crystal oscillator. When the input PPS is determined to be "severely jittery" or "missing" (i.e., entering a time-keeping state) by SQADM, this module significantly reduces or completely stops using the current N_measured value to update N_target. Instead, it will maintain or fine-tune N_target during the timekeeping period based on the optimal estimate of N_target learned from historical steady states, combined with a short-term frequency drift prediction model (which can be based on the historical temperature drift characteristics of the local crystal oscillator or a simplified physical model) to maximize the accuracy of the output PPS.

[0219] The ECCSIU unit includes a communication interface. This interface is primarily for direct communication between the PPS timekeeping module (FPGA) and an external master control system (such as the CPU of the PTP master clock or other upper-level controller, i.e., the SPI master). Its design aims to allow the master control system to send control commands (such as setting parameters, forcing mode switching, and initiating calibration) to the PPS timekeeping module and read status information (such as operating mode, current N_target, and input PPS quality) from it. Essentially, the ECCSIU is an interface for the PPS timekeeping module to perform dedicated configuration and status monitoring with a specific, higher-level control unit. The communication interface can use an SPI slave interface. The FPGA acts as an SPI slave, receiving commands and data from the PTP master clock CPU (SPI master) and returning status and data to the master.

[0220] For example, the definition of an SPI command word is illustrated below:

[0221] CMD_SET_CONFIG_ALPHA_STABLE(data): Sets the filter coefficient α in the steady state.

[0222] CMD_SET_CONFIG_HOLDOVER_THRESHOLD_X1(data): Sets the deviation threshold for entering the timekeeping phase.

[0223] CMD_FORCE_HOLDOVER(enable): The main controller forces the FPGA to enter / exit timekeeping mode.

[0224] CMD_ENABLE_CALIBRATION(enable): The master controller notifies the FPGA that the satellite signal is stable and calibration can begin.

[0225] CMD_READ_STATUS: Reads the FPGA's internal status word.

[0226] CMD_READ_N_TARGET: Reads the current target count value.

[0227] CMD_READ_PPS_QUALITY: Reads the input PPS quality level of the SQADM assessment.

[0228] FPGA Internal Register Mapping: Design a set of internal FPGA registers to store the above configuration parameters and status information. The SPI interface accesses these registers based on the address field of the command word. For example:

[0229] 0x01: Configuration register - filter parameter α;

[0230] 0x02: Configuration Register - Time-keeping Threshold;

[0231] 0x10: Status Register - Current operating mode (track / timekeeping), lock indicator;

[0232] 0x11: Data register - current high 16 bits of N_target;

[0233] 0x12: Data register - current lower 16 bits of N_target;

[0234] Through these interfaces, the main control system can optimize and control the behavior and monitor the status of this PPS timekeeping module based on higher-level application logic and a comprehensive understanding of the external environment.

[0235] In this application embodiment, there are two ways for the FPGA to enter the timekeeping mode:

[0236] 1. The system automatically enters (based on internal judgment):

[0237] As described in the SQADM module section above, when the PPS timekeeping module detects a severe deterioration in the quality of the input PPS signal (e.g., jitter or frequency deviation consistently exceeding a severe threshold) or a complete loss of pulses, the system will automatically switch to timekeeping mode. This is the system's own protection mechanism and a mechanism to maintain output stability.

[0238] 2. Forced entry / exit of the main control system (via ECCSIU interface):

[0239] The timekeeping mode switching command indicates entry into timekeeping mode, which switches the current signal status to a state of severe jitter or signal loss; the timekeeping mode exit command indicates exit from timekeeping mode, which switches the current signal status to a state of slight jitter or stable.

[0240] For example, the timekeeping mode switching instruction and the timekeeping mode exit instruction can be the CMD_FORCE_HOLDOVER(enable) instruction in the SPI command word example.

[0241] An external master control system (such as the CPU of a PTP master clock) can send the above commands through the ECCSIU interface to force this PPS timekeeping module to enter or exit timekeeping mode, even if the judgment result of the internal SQADM of this module may be different at this time.

[0242] For example, Figure 6A schematic diagram of pulse synchronization implementation is provided. To begin pulse synchronization, a high-resolution local clock is provided to receive and accurately capture the arrival time of the input PPS signal. The instantaneous period of the input PPS is quantized using the local clock to obtain N_measured. The quality level of the input PPS signal is intelligently evaluated to determine if the signal quality is good. For example, severe jitter, significant quality degradation, or pulse loss indicate poor signal quality; other conditions indicate good signal quality. If so, N_measured is adaptively filtered to generate N_target. If not, based on historical data and / or a prediction model, the stability of N_target is maintained or adjusted. It is then determined whether the input PPS has stabilized. If stable, smooth synchronization is performed, and N_target is gradually adjusted. If not stable, the process returns to maintaining or adjusting the stability of N_target based on historical data and / or a prediction model. PPS is accurately generated and output based on the real-time generated N_target and the local clock. The process is then determined whether to continue. If yes, the process returns to receiving and accurately capturing the arrival time of the input PPS signal; otherwise, the process ends.

[0243] For example, Figure 7 This diagram illustrates the variation of N_target and the output PPS effect when the input PPS signal has different qualities. The input PPS signal quality includes stable, jittery, and stable recovery. Figure 7 The diagram illustrates the changes in N_target and the output PPS effect during the stabilization, jitter, and recovery processes of the input PPS signal. It can be seen that the method provided in this embodiment can smoothly input a stable PPS signal even when the input PPS signal quality is poor, improving pulse synchronization accuracy. The yellow area in the diagram represents the transition phase from "timekeeping mode" to "tracking mode," which is the "smooth resynchronization" phase. Figure 7As shown, the input PPS signal is lost between times 4 and 6. At this point, the system relies on its own "timekeeping / prediction" algorithm to generate N_target. Although this prediction is accurate, the local crystal oscillator will inevitably produce a small phase error between itself and the external, recovered PPS signal source. At time 6, when PPS_IN reappears, if the system immediately forces its output PPS_OUT to align with the new PPS_IN, it will cause a phase jump in the output pulse. This sudden jump is fatal to downstream high-precision timing devices (such as PTP devices), potentially causing them to lose lock. During the yellow area phase, the system detects the new PPS_IN, but it doesn't fully trust it or immediately follow it. Instead, it calculates a specially adjusted N_target sequence. These N_target values ​​are slightly longer or shorter than the nominal values, with the aim of gradually and smoothly compensating for the small phase errors accumulated during the timekeeping period over the next few cycles (shown as two cycles in the diagram, from 6 to 8). Therefore, the N_target value in the yellow area is neither a simple tracking value nor a holdover value, but a correction value used for smooth transition. N_target includes several states: nominal value (tracking), holdover (hold / predict), and adjusted recovery. The state changes of N_target can be analyzed based on the actual situation of PPS_IN: Time 0-4: PPS_IN is stable, the system is in tracking mode, and N_target is the nominal value. Time 4: The system detects that the PPS_IN pulse that should have arrived at time 4 has been lost. Time 4-6: Due to the input loss, the system immediately switches to holdover mode. At this time, it continues to generate a very stable N_target based on the most stable historical N_target value and the prediction algorithm. It is precisely because N_target remains highly stable during the holdover period that the final PPS_OUT can continue to be output accurately and without deviation.

[0244] Example 4

[0245] Figure 8 This is a schematic diagram of a pulse synchronization device provided in Embodiment 4 of this application. Figure 8 As shown, the device includes: a periodic sequence acquisition module 41, a signal state determination module 42, a target count value determination module 43, and a synchronization signal output module 44.

[0246] The period sequence acquisition module 41 is used to acquire a period quantity sequence generated by counting with a local clock. The period quantity sequence includes at least one period quantity, which is generated by detecting the second pulse signal sent by the time synchronization system.

[0247] The signal state determination module 42 is used to perform quality assessment on the signal based on the period quantity sequence and determine the current signal state.

[0248] The target count value determination module 43 is used to determine the target count value according to the current signal state, and latch the target count value to the corresponding buffer space after the latching condition is met;

[0249] The synchronization signal output module 44 is used to obtain the current target count value from the buffer space and output a pulse synchronization signal based on the current target count value. The pulse synchronization signal is used for pulse synchronization.

[0250] This application provides a pulse synchronization device that solves the problem of inaccurate pulse signal synchronization. It uses a local clock to count the second pulse signal sent by the time synchronization system to generate a period count sequence, which includes at least one period count. The signal quality is evaluated using the period count sequence to determine the current signal state. A target count value is determined based on the current signal state. This method yields a stable target count value, effectively avoiding problems such as unstable time synchronization and poor accuracy caused by environmental factors. Even if the input PPS signal quality deteriorates sharply or is interrupted briefly, a stable target count value can still be provided. The target count value is then latched into a corresponding buffer space. After the latching condition is met, the current target count value is retrieved from the buffer space and latched. Latching the current target count value ensures the accuracy of the pulse synchronization signal. The output pulse synchronization signal is counted using the current target count value to control the output of the pulse synchronization signal, achieving pulse synchronization and improving synchronization accuracy and stability.

[0251] Optionally, the periodic sequence acquisition module 41 is specifically used to: acquire a set number of periods from the cache space of the number of periods to form a periodic sequence;

[0252] Optionally, the device may also include:

[0253] The cycle count generation module is used to detect the second pulse signal sent by the time synchronization system. If a rising edge event is detected and the rising edge event is not the first rising edge event, the current count value of the counter is stored as the cycle count in the cycle count cache space and the current count value is cleared. The counter is controlled to count the clock at a set frequency based on the local clock.

[0254] Optionally, the signal state determination module 42 includes:

[0255] A quality assessment unit is used to analyze the number of periods in the period number sequence and assess the signal quality based on at least one of the average value of the period number sequence, the standard deviation of the first difference of the period number sequence, and the relationship between the number of periods and the period number threshold, thereby determining the signal quality.

[0256] A signal state determination unit is used to determine the current signal state based on the signal quality, wherein the current signal state is a stable state, a state with slight jitter, a state with severe jitter, or a state of signal loss.

[0257] Optionally, the target count value determination module 43 includes:

[0258] The first target count value determination unit is used to determine the target count value based on the number of cycles in the cycle number sequence when the current signal state is a stable state or a slightly jittery state.

[0259] The second target count value determination unit is used to determine the previous stable target count value when the current signal state is a severe jitter state or a signal loss state, and to determine the target count value based on the previous stable target count value.

[0260] Optionally, the first target count value determination unit is specifically used for: determining a first count value based on the number of periods in the period number sequence; if the previous signal state is a stable state or a slightly jittering state, determining the first count value as the target count value; if the previous signal state is a severely jittering state or a signal loss state, determining the phase error between the phase of the currently output pulse synchronization signal and the phase of the input second pulse signal, determining a correction amount based on the phase error, and using the sum of the correction amount and the first count value as the target count value.

[0261] Optionally, determining the first count value based on the number of periods in the period number sequence includes at least one of the following:

[0262] Based on the current signal state, weight information is determined, a first number of cycles is selected from the cycle number sequence, and the selected cycle number is weighted according to the weight information to obtain a first count value.

[0263] The first filtering parameter is determined based on the current signal state. The latest cycle number is filtered out from the cycle number sequence, and the previous target count value is determined. The latest cycle number and the previous target count value are weighted and filtered according to the first filtering parameter to determine the first count value.

[0264] Optionally, the target count value determination module 43 includes at least one of the following:

[0265] The third target count value determination unit is used to determine the weight information and the second quantity based on the time recovery time if the previous signal state is a severe jitter state or a signal loss state, filter out the second quantity of cycles from the cycle quantity sequence, and weight the filtered cycle quantity according to the weight information to obtain the target count value.

[0266] The fourth target count value determination unit is used to determine the second filtering parameter based on the time recovery time if the previous signal state is a severe jitter state or a signal loss state, filter out the latest cycle number from the cycle number sequence, determine the previous target count value, and perform weighted filtering on the latest cycle number and the previous target count value according to the second filtering parameter to determine the target count value.

[0267] Optionally, the second target count value determination unit includes at least one of the following:

[0268] The count value determination subunit is used to take the previous stable target count value as the target count value;

[0269] The drift prediction subunit is used to predict the cumulative drift by adding the cumulative drift to the previous stable target count value to obtain the target count value.

[0270] Optionally, the predicted cumulative drift includes at least one of the following:

[0271] Determine the frequency drift rate and the timeout period, and multiply the frequency drift rate by the timeout period to obtain the cumulative drift;

[0272] Obtain the current temperature, and determine the temperature compensation count based on the current temperature and a pre-generated temperature characteristic table. Use the temperature compensation count as the cumulative drift.

[0273] Optionally, determining the temperature compensation count based on the current temperature and a pre-generated temperature characteristic table includes at least one of the following:

[0274] When the temperature characteristic table stores the corresponding temperature and compensation value, the temperature characteristic table is queried according to the current temperature, and the compensation value corresponding to the current temperature is used as the temperature compensation count.

[0275] When the temperature and count value are stored in the temperature characteristic table, the previous steady-state temperature is determined. The temperature characteristic table is queried according to the current temperature to determine the second count value. The temperature characteristic table is queried according to the previous steady-state temperature to determine the third count value. The difference between the second count value and the third count value is used as the temperature compensation count.

[0276] Optionally, the synchronization signal output module 44 includes:

[0277] The initial count value determination unit is used to determine the initial count value and determine the maximum count value based on the initial count value and the current target count value.

[0278] The counting and accumulating unit is used to control the main counter to start counting from the initial counting value after detecting a rising edge event. The count value of the main counter is accumulated after detecting the rising edge of a clock at a set frequency.

[0279] The signal output unit is used to output a high-level signal with a set pulse width after the count value of the main counter reaches the highest count value, and to restore the count value of the main counter to the initial count value.

[0280] Optionally, the device may also include:

[0281] The switching instruction receiving module is used to determine whether the current signal state is a severe jitter state or a signal loss state after receiving a timekeeping mode switching instruction.

[0282] Optionally, the timekeeping mode switching command is generated and sent by the main control system after detecting that the timekeeping conditions are met;

[0283] The timekeeping condition includes at least one of the following:

[0284] The status information of the time synchronization system meets the switching conditions;

[0285] It is predicted that the time synchronization system will experience a jump or interruption within a certain period of time;

[0286] A switching instruction has been received.

[0287] Optionally, the device may also include:

[0288] The exit instruction receiving module is used to determine whether the current signal state is a slight jitter or a stable state after receiving a timekeeping mode exit instruction.

[0289] Optionally, the timekeeping mode exit command is generated and sent by the main control system after detecting that the time synchronization system has recovered to a stable state.

[0290] The pulse synchronization device provided in this application can execute the pulse synchronization method provided in any embodiment of this application, and has the corresponding functional modules and beneficial effects of the execution method.

[0291] Example 5

[0292] Figure 9A schematic diagram of an electronic device 50 that can be used to implement embodiments of this application is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the application described and / or claimed herein.

[0293] like Figure 9 As shown, the electronic device 50 includes at least one processor 51 and a memory, such as a read-only memory (ROM) 52 and a random access memory (RAM) 53, communicatively connected to the at least one processor 51. The memory stores computer programs executable by the at least one processor. The processor 51 can perform various appropriate actions and processes based on the computer program stored in the ROM 52 or loaded into the RAM 53 from storage unit 58. The RAM 53 can also store various programs and data required for the operation of the electronic device 50. The processor 51, ROM 52, and RAM 53 are interconnected via a bus 54. An input / output (I / O) interface 55 is also connected to the bus 54.

[0294] Multiple components in electronic device 50 are connected to I / O interface 55, including: input unit 56, such as keyboard, mouse, etc.; output unit 57, such as various types of monitors, speakers, etc.; storage unit 58, such as disk, optical disk, etc.; and communication unit 59, such as network card, modem, wireless transceiver, etc. Communication unit 59 allows electronic device 50 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0295] Processor 51 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 51 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 51 performs the various methods and processes described above, such as pulse synchronization methods.

[0296] In some embodiments, the pulse synchronization method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 58. In some embodiments, part or all of the computer program may be loaded and / or mounted on electronic device 50 via ROM 52 and / or communication unit 59. When the computer program is loaded into RAM 53 and executed by processor 51, one or more steps of the pulse synchronization method described above may be performed. Alternatively, in other embodiments, processor 51 may be configured to perform the pulse synchronization method by any other suitable means (e.g., by means of firmware).

[0297] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0298] Computer programs used to implement the methods of this application may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0299] This application provides a computer program product, which includes a computer program that, when executed by a processor, implements the pulse synchronization method described in any embodiment of this application.

[0300] In the context of this application, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium can be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0301] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0302] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0303] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0304] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.

[0305] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A pulse synchronization method, characterized in that, include: A sequence of period counts generated by counting with a local clock is obtained. The sequence of period counts includes at least one period count, which is a sequence formed by the period counts detected by different detection periods. The period counts are generated by detecting the second pulse signal sent by the time synchronization system. Specifically, the count value is obtained by counting the time interval between two adjacent rising edges of the second pulse signal using a local clock. The signal quality is evaluated based on the cycle number sequence to determine the current signal state; The target count value is determined based on the current signal state, and the target count value is cached in the corresponding cache space; After the latching condition is met, the current target count value is obtained from the buffer space and latched. Based on the current target count value, a pulse synchronization signal is output, which is used for pulse synchronization. The step of evaluating the signal quality based on the period number sequence and determining the current signal state includes: The signal quality is determined by analyzing the number of periods in the period number sequence and evaluating the signal quality based on at least one of the average value of the period number sequence, the standard deviation of the first difference of the period number sequence, and the relationship between the number of periods and the period number threshold. The current signal state is determined based on the signal quality, and the current signal state is a stable state, a state with slight jitter, a state with severe jitter, or a state of signal loss. The step of determining the target count value based on the current signal state includes: When the current signal state is a stable state or a state with slight jitter, the target count value is determined according to the number of cycles in the cycle number sequence; When the current signal state is a severe jitter state or a signal loss state, determine the previous stable target count value, and determine the target count value based on the previous stable target count value; The step of outputting a pulse synchronization signal based on the current target count value includes: Determine the initial count value, and determine the maximum count value based on the initial count value and the current target count value; After detecting a rising edge event, the main counter is controlled to start counting from the initial counting value, and the count value of the main counter is accumulated after detecting the rising edge of the clock at the set frequency; After the main counter reaches its maximum count value, a high-level signal with a set pulse width is output, and the count value of the main counter is restored to its initial count value.

2. The method according to claim 1, characterized in that, The step of obtaining the sequence of period counts generated by local clock counting includes: A set number of cycles is obtained from the cache space containing the specified number of cycles to form a cycle number sequence; Accordingly, the process of generating the number of cycles includes: The second pulse signal sent by the time synchronization system is detected. If a rising edge event is detected and the rising edge event is not the first rising edge event, the current count value of the counter is stored as the number of cycles in the buffer space of the number of cycles and the current count value is cleared to zero. The counter is controlled by the local clock to count clocks at a set frequency.

3. The method according to claim 1, characterized in that, Determining the target count value based on the number of periods in the period number sequence includes: The first count value is determined based on the number of periods in the period number sequence; If the previous signal state was a stable state or a state with slight jitter, the first count value is determined as the target count value; If the previous signal state was a severe jitter state or a signal loss state, determine the phase error between the phase of the currently output pulse synchronization signal and the phase of the input second pulse signal, determine the correction amount based on the phase error, and use the sum of the correction amount and the first count value as the target count value.

4. The method according to claim 3, characterized in that, Determining the first count value based on the number of periods in the period number sequence includes at least one of the following: Based on the current signal state, weight information is determined, a first number of cycles is selected from the cycle number sequence, and the selected cycle number is weighted according to the weight information to obtain a first count value. The first filtering parameter is determined based on the current signal state. The latest cycle number is filtered out from the cycle number sequence, and the previous target count value is determined. The latest cycle number and the previous target count value are weighted and filtered according to the first filtering parameter to determine the first count value.

5. The method according to claim 1, characterized in that, Determining the target count value based on the number of periods in the period number sequence includes at least one of the following: If the previous signal state was a severe jitter state or a signal loss state, the weight information and the second quantity are determined according to the time recovery time. The second quantity of cycles is selected from the cycle quantity sequence. The selected cycle quantity is weighted according to the weight information to obtain the target count value. If the previous signal state was a severe jitter state or a signal loss state, the second filtering parameter is determined based on the time recovery time, the latest cycle number is filtered out from the cycle number sequence, and the previous target count value is determined. The latest cycle number and the previous target count value are weighted and filtered according to the second filtering parameter to determine the target count value.

6. The method according to claim 1, characterized in that, The step of determining the target count value based on the previous stable target count value includes at least one of the following: The previous stable target count value is used as the target count value; The cumulative drift is predicted, and the cumulative drift is added to the previous stable target count value to obtain the target count value.

7. The method according to claim 6, characterized in that, The predicted cumulative drift includes at least one of the following: Determine the frequency drift rate and the timeout period, and multiply the frequency drift rate by the timeout period to obtain the cumulative drift; Obtain the current temperature, and determine the temperature compensation count based on the current temperature and a pre-generated temperature characteristic table. Use the temperature compensation count as the cumulative drift. Accordingly, determining the temperature compensation count based on the current temperature and a pre-generated temperature characteristic table includes at least one of the following: When the temperature characteristic table stores the corresponding temperature and compensation value, the temperature characteristic table is queried according to the current temperature, and the compensation value corresponding to the current temperature is used as the temperature compensation count. When the temperature and count value are stored in the temperature characteristic table, the previous steady-state temperature is determined. The temperature characteristic table is queried according to the current temperature to determine the second count value. The temperature characteristic table is queried according to the previous steady-state temperature to determine the third count value. The difference between the second count value and the third count value is used as the temperature compensation count.

8. An electronic device, characterized in that, The electronic device includes: At least one processor, and a memory communicatively connected to said at least one processor; The memory stores a computer program that is executed by the at least one processor, which enables the at least one processor to perform the pulse synchronization method according to any one of claims 1-7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the pulse synchronization method of any one of claims 1-7.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the pulse synchronization method according to any one of claims 1-7.

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