Semiconductor device and preparation method thereof, storage system and electronic equipment

Abstract

The invention provides a semiconductor device and a preparation method thereof, a storage system and electronic equipment, relates to the technical field of semiconductor chips, and aims to solve the problem of high cost caused by the fact that a first bit line and a second bit line are respectively connected with a circuit. The semiconductor device comprises a first stacking structure, a second stacking structure, a first bit line, a second bit line and a first gate isolation structure, wherein the first stacking structure and the second stacking structure are stacked in a first direction. The first bit line is located on the side, away from the second stacking structure, of the first stacking structure, and the second bit line is located on the side, away from the first stacking structure, of the second stacking structure. The first gate isolation structure penetrates through the first stacking structure and the second stacking structure in the first direction, and the two ends, in the first direction, of the first gate isolation structure are connected with the first bit line and the second bit line respectively. In the semiconductor device, the first bit line and the second bit line are connected through the first gate isolation structure, so that the first bit line and the second bit line share one circuit, metal wires are reduced, and the preparation cost of the semiconductor device is reduced.

Description

[0001] This application claims priority to U.S. Patent Application No. US63 / 661018, filed June 17, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor device and its fabrication method, a storage system, and an electronic device. Background Technology

[0003] As the feature size of memory cells approaches the lower limit of the process, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit.

[0004] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memory with a three-dimensional structure (3D NAND), which increases storage density by arranging storage cells three-dimensionally on a substrate.

[0005] However, as the number of layers in 3D NAND is stacked, the length of the channel structure increases, and the current intensity in the channel structure decreases as the channel structure length increases. Summary of the Invention

[0006] Embodiments of this disclosure provide a semiconductor device, a method for fabricating the same, a storage system, and an electronic device.

[0007] The embodiments of this disclosure adopt the following technical solutions:

[0008] On one hand, some embodiments of this disclosure provide a semiconductor device, including: a first stacked structure and a second stacked structure stacked along a first direction, a first bit line, a second bit line, and a first gate isolation structure. The first bit line is located on the side of the first stacked structure away from the second stacked structure, and extends along a second direction, which intersects the first direction; the second bit line is located on the side of the second stacked structure away from the first stacked structure, and extends along the second direction; the first gate isolation structure extends along a third direction and penetrates the first stacked structure and the second stacked structure along the first direction, and the third direction intersects the plane containing the first direction and the second direction; the two ends of the first gate isolation structure along the first direction are respectively connected to the first bit line and the second bit line.

[0009] In some embodiments, the first gate isolation structure includes an isolation portion and a connection portion. On a plane parallel to the second direction and the third direction, the connection portion is disposed around the isolation portion, and the connection portion is connected to the first bit line and the second bit line at both ends along the first direction, respectively.

[0010] In some embodiments, the dimension of the end of the connecting portion near the second bit line in the second direction is greater than the dimension of the end of the connecting portion near the first bit line in the second direction.

[0011] In some embodiments, the first stacking structure includes a first sub-stack structure and a second sub-stack structure stacked along the first direction, the second stacking structure includes a third sub-stack structure and a fourth sub-stack structure stacked along the first direction, the second sub-stack structure being closer to the third sub-stack structure than the first sub-stack structure, and the third sub-stack structure being closer to the second sub-stack structure than the fourth sub-stack structure; the connecting portion includes: a first sub-part, a second sub-part, and a third sub-part stacked along the first direction and connected sequentially, the first sub-part penetrating the first sub-stack structure, the second sub-part penetrating the second sub-stack structure and the third sub-stack structure, and the third sub-part penetrating the fourth sub-stack structure; the first sub-part is connected to the first bit line, and the third sub-part is connected to the second bit line.

[0012] In some embodiments, the dimension of the end of the first sub-part near the second sub-part in the second direction is greater than the dimension of the end of the second sub-part near the first sub-part in the second direction; the dimension of the end of the second sub-part near the third sub-part in the second direction is greater than the dimension of the end of the third sub-part near the second sub-part in the second direction.

[0013] In some embodiments, the dimension of the end of the first sub-part near the second sub-part in the second direction is greater than the dimension of the end of the first sub-part away from the second sub-part in the second direction; and / or, the dimension of the end of the second sub-part away from the first sub-part in the second direction is greater than the dimension of the end of the second sub-part near the first sub-part in the second direction; and / or, the dimension of the end of the third sub-part away from the second sub-part in the second direction is greater than the dimension of the end of the third sub-part near the second sub-part in the second direction.

[0014] In some embodiments, the semiconductor device further includes: a first connection structure, wherein in the first direction, the two ends of the first connection structure are respectively connected to the first bit line and the first gate isolation structure; and a second connection structure, wherein in the first direction, the two ends of the second connection structure are respectively connected to the second bit line and the first gate isolation structure.

[0015] In some embodiments, the number of the first connection structures is multiple, and the multiple first connection structures are arranged at circumferential intervals along the first gate isolation structure.

[0016] In some embodiments, the dimension of the end of the first connection structure near the first bit line in the second direction is greater than the dimension of the end of the first connection structure near the first gate isolation structure in the second direction.

[0017] In some embodiments, the number of first gate isolation structures is multiple; the multiple first gate isolation structures are arranged in multiple columns along the second direction and in multiple rows along the third direction; the number of first bit lines is multiple, and the multiple first bit lines are arranged sequentially at intervals along the third direction; one first bit line is connected to one end of one first gate isolation structure; the number of second bit lines is multiple, and the multiple second bit lines are arranged sequentially at intervals along the third direction; one second bit line is connected to the other end of one first gate isolation structure.

[0018] In some embodiments, adjacent rows of the first gate isolation structures are offset upwards on the third side.

[0019] In some embodiments, the semiconductor device further includes a plurality of dielectric structures that extend through the first stacked structure and the second stacked structure along the first direction; and in the third direction, at least one of the dielectric structures is disposed between two adjacent first gate isolation structures.

[0020] In some embodiments, the semiconductor device further includes: a plurality of channel structures extending through the first stacked structure and the second stacked structure; the plurality of channel structures arranged in multiple rows along the third direction, and the plurality of channel structures arranged in multiple columns along the second direction, with adjacent rows of channel structures staggered in the third direction; along the second direction, a plurality of rows of channel structures are disposed between adjacent rows of the first gate isolation structures; in the plurality of channel structures, a first bit line is connected to at least one channel structure, and a second bit line is connected to at least one channel structure.

[0021] In some embodiments, a plurality of first bit lines constitute a plurality of first bit line groups, the first bit line group including at least two adjacent first bit lines; in the first direction, each of the first bit lines in the first bit line group overlaps with each of the first gate isolation structures located in the same column.

[0022] In some embodiments, one of the first bit lines in the first bit line group is connected to one of the first gate isolation structures in a column of the plurality of first gate isolation structures that overlap with the first bit line group.

[0023] In some embodiments, the plurality of the first gate isolation structures have the same dimension in the third direction.

[0024] In some embodiments, the semiconductor device further includes: a source layer located between the first stacked structure and the second stacked structure; a first gate isolation structure penetrating the source layer; a connection portion being insulated from the source layer; and a channel structure penetrating the source layer and connected to the source layer.

[0025] In some embodiments, the channel structure includes a channel layer and a functional layer, the functional layer being disposed around a portion of the channel layer; the channel layer penetrates the first stack structure, the source layer, and the second stack structure along the first direction and is in contact with the source layer; the functional layer includes a first portion and a second portion located on opposite sides of the source layer, the first portion penetrating the first stack structure and contacting the source layer, and the second portion penetrating the second stack structure and contacting the source layer.

[0026] In some embodiments, the first stacked structure includes a first gate layer and a first dielectric layer alternately stacked along the first direction, and the second stacked structure includes a second gate layer and a second dielectric layer alternately stacked along the first direction; the first gate isolation structure further includes an isolation layer located between the connection portion and the first gate layer, between the connection portion and the source layer, and between the connection portion and the second gate layer, and the isolation layer is disposed around the connection portion.

[0027] In some embodiments, the first stacked structure includes a first gate layer and a first dielectric layer alternately stacked along the first direction, and the second stacked structure includes a second gate layer and a second dielectric layer alternately stacked along the first direction; the semiconductor device further includes a plurality of third connection structures, the plurality of third connection structures being located on one side of the first stacked structure and the second stacked structure, one third connection structure being connected to at least one first gate layer, and one third connection structure being connected to at least one second gate layer.

[0028] In some embodiments, the semiconductor structure further includes: a third stacked structure and a fourth stacked structure stacked along the first direction, the third stacked structure and the fourth stacked structure being located on one side of the first stacked structure and the second stacked structure along the third direction; the third stacked structure includes a plurality of third dielectric layers and a plurality of fourth dielectric layers alternately stacked along the first direction; the fourth stacked structure includes a plurality of fifth dielectric layers and a plurality of sixth dielectric layers alternately stacked along the first direction; the third connection structure includes: a connection post, at least one first connection layer and at least one second connection layer; the connection post penetrates the third stacked structure and the fourth stacked structure; the first connection layer is parallel to the third direction and the second direction, the first connection layer connects the connection post and a first gate layer, and the first connection layer is connected to one of the third dielectric layers; the second connection layer is parallel to the third direction and the second direction, the second connection layer connects the connection post and a second gate layer, and the second connection layer is connected to one of the fifth dielectric layers.

[0029] In some embodiments, the first stacked structure and the second stacked structure constitute a first region, and the third stacked structure and the fourth stacked structure constitute a second region, the second region being located on one side of the first region along the third direction; the semiconductor structure further includes: a second gate isolation structure that penetrates the third stacked structure and the fourth stacked structure along the first direction and penetrates the second region along the third direction.

[0030] In some embodiments, the first stacked structure and the second stacked structure together constitute a repeating structure, and the number of repeating structures is multiple, with the multiple repeating structures stacked along the first direction.

[0031] In some embodiments, the system further includes: a peripheral circuit layer located on the side of the first bit line away from the first stacked structure, and the peripheral circuit layer is connected to the first bit line.

[0032] On the other hand, some embodiments of this disclosure also provide a method for fabricating a semiconductor device, including: forming a first stacked structure and a second stacked structure stacked along a first direction; forming a first gate isolation structure, the first gate isolation structure penetrating the first stacked structure and the second stacked structure along the first direction; forming a first bit line, the first bit line being located on the side of the first stacked structure away from the second stacked structure, the first bit line extending along a second direction, the first gate isolation structure extending along a third direction, the second direction intersecting the first direction, the third direction intersecting at a plane containing the first direction and the second direction, one end of the first gate isolation structure along the first direction being connected to the first bit line; forming a second bit line, the second bit line being located on the side of the second stacked structure away from the first stacked structure, the second bit line extending along the second direction, the other end of the first gate isolation structure along the first direction being connected to the second bit line.

[0033] In some embodiments, forming a first stacked structure and a second stacked structure stacked along a first direction includes: forming a first stacked structure, a first region of the first stacked structure including a plurality of first sacrificial layers and a plurality of first dielectric layers alternately stacked along the first direction, the first region of the first stacked structure being adjacent to a second region of the first stacked structure; forming a second sacrificial layer, the second sacrificial layer being stacked with the first stacked structure along the first direction; forming a second stacked structure, the second stacked structure being located on the side of the second sacrificial layer away from the first stacked structure, the first region of the second stacked structure including a plurality of third sacrificial layers and a plurality of second dielectric layers alternately stacked along the first direction, the first region of the second stacked structure being adjacent to a second region of the second stacked structure; replacing the first sacrificial layer with a first gate layer, and replacing the third sacrificial layer with a second gate layer.

[0034] In some embodiments, after forming the first stacked structure and before forming the second sacrificial layer, the method further includes: removing a portion of the first stacked structure to form a first channel hole, the first channel hole being located in a first region of the first stacked structure; after forming the second stacked structure and before forming the channel structure, the method further includes: removing a portion of the second stacked structure and a portion of the second sacrificial layer to form a second channel hole, the second channel hole being located in a first region of the second stacked structure, the second channel hole and the first channel hole together constituting a channel hole; and sequentially forming a functional layer and a channel layer within the channel hole, the functional layer and the channel layer together constituting a channel structure.

[0035] In some embodiments, forming the first stacked structure includes: forming a first sub-stacked structure; removing a portion of the first sub-stacked structure to form a third channel hole, the third channel hole being located in a first region of the first sub-stacked structure; forming a second sub-stacked structure, the second sub-stacked structure being stacked with the first sub-stacked structure along a first direction; forming the second stacked structure includes: forming a third sub-stacked structure; removing a portion of the second sub-stacked structure, a portion of the second sacrificial layer, and a portion of the third sub-stacked structure to form a fourth channel hole, the fourth channel hole communicating with the third channel hole; forming a fourth sub-stacked structure, the fourth sub-stacked structure being stacked with the third sub-stacked structure along the first direction; removing a portion of the fourth sub-stacked structure to form a fifth channel hole, the fifth channel hole communicating with the fourth channel hole, the third channel hole, the fourth channel hole, and the fifth channel hole collectively constituting a channel hole; and sequentially forming a functional layer and a channel layer within the channel hole, the functional layer and the channel layer collectively constituting a channel structure.

[0036] In some embodiments, after the functional layer and the channel layer are sequentially formed in the channel via, and before the first sacrificial layer is replaced with the first gate layer, the method further includes: removing a portion of the second sacrificial layer to form a first fill space, the first fill space exposing a portion of the functional layer; removing a portion of the functional layer through the first fill space; and forming a source layer in the first fill space.

[0037] In some embodiments, removing a portion of the stacked structure to form a channel via further includes: forming a gate slit located in a first region of the first stacked structure and a first region of the second stacked structure, and the gate slit being located on one side of the channel via along the second direction.

[0038] In some embodiments, removing a portion of the second sacrificial layer to form a first fill space includes removing a portion of the second sacrificial layer through the gate slit.

[0039] In some embodiments, forming the first gate isolation structure includes: sequentially forming an isolation layer, a connection portion, and an isolation portion within the gate slit, wherein the isolation layer is located between the connection portion and the source layer, between the first stacked structure and the connection portion, and between the second stacked structure and the connection portion, and the isolation layer is disposed around the connection portion, and the connection portion is disposed around the isolation portion on a plane parallel to the second direction and the third direction.

[0040] In some embodiments, after forming the first gate isolation structure and before forming the first bit line, the method further includes: forming a first connection structure, one end of the first connection structure along the first direction being connected to the first gate isolation structure; forming the first bit line includes: connecting the first bit line to the other end of the first connection structure along the first direction; after forming the first bit line and before forming the second bit line, the method further includes: forming a second connection structure, one end of the second connection structure along the first direction being connected to the first gate isolation structure; forming the second bit line includes: connecting the second bit line to the other end of the second connection structure along the first direction.

[0041] In some embodiments, removing a portion of the stacked structure to form a channel via further includes: forming a connection via, the connection via penetrating a second region of the first stacked structure and a second region of the second stacked structure, the second region of the first stacked structure including a plurality of third dielectric layers and a plurality of fourth dielectric layers alternately stacked along the first direction, the second region of the second stacked structure including a plurality of fifth dielectric layers and a plurality of sixth dielectric layers alternately stacked along the first direction; after forming the first gate isolation structure and before forming the first bit line, further including: removing a portion of the third dielectric layers and the fifth dielectric layers to form a second fill space and a third fill space, the second fill space exposing at least one first gate layer, the third fill space exposing at least one second gate layer, the second fill space communicating with the connection via, and the third fill space communicating with the connection via; filling the connection via with conductive material to form a third connection structure.

[0042] In another aspect, some embodiments of this disclosure also provide a storage system, including: a semiconductor device and a controller as described above, the controller being coupled to the semiconductor device to control the semiconductor device to store data.

[0043] In another aspect, some embodiments of this disclosure also provide an electronic device, including a motherboard and a storage system as described above disposed on the motherboard. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual process of the method, etc. involved in the embodiments of this disclosure.

[0045] Figure 1This is a schematic diagram of the three-dimensional structure of a three-dimensional memory according to some embodiments;

[0046] Figure 2 A cross-sectional view of a three-dimensional memory according to some embodiments;

[0047] Figure 3 for Figure 1 A cross-sectional view of a string of storage cells in a three-dimensional memory along section line A-A';

[0048] Figure 4 for Figure 3 Equivalent circuit diagram of the memory cell string;

[0049] Figure 5 This is a schematic diagram of the structure of a semiconductor device according to some embodiments;

[0050] Figure 6 This is a schematic diagram of the first gate isolation structure in the YZ plane according to some embodiments;

[0051] Figure 7 This is a schematic diagram of the structure of a semiconductor device according to some other embodiments;

[0052] Figure 8 This is a schematic diagram of the structure of a semiconductor device in the YZ plane according to some embodiments;

[0053] Figure 9 This is a schematic diagram of the structure of a semiconductor device in the YZ plane according to some other embodiments;

[0054] Figure 10 for Figure 8 Cross-sectional view of AA in the middle;

[0055] Figure 11 This is a schematic diagram of the dielectric structure in the YZ plane according to some embodiments;

[0056] Figure 12 This is a schematic diagram of the structure of a semiconductor device according to some other embodiments;

[0057] Figure 13 for Figure 12 A composite image of the two cross sections, BB and CC.

[0058] Figure 14 This is a structural schematic diagram of multiple repeating structures according to some embodiments;

[0059] Figure 15 A flowchart illustrating a method for fabricating a semiconductor device according to some embodiments;

[0060] Figures 16-21 This is a schematic diagram of the structure of a semiconductor device during the fabrication process according to some embodiments;

[0061] Figure 22 This is a block diagram of a storage system according to some embodiments;

[0062] Figure 23 A block diagram of a storage system according to some other embodiments;

[0063] Figure 24 This is a block diagram of an electronic device according to some embodiments.

[0064] Reference numerals: 10, 3D memory; 100, peripheral device; 110, substrate; 120, transistor; 130, peripheral interconnect layer; 200, semiconductor structure; 290, array interconnect layer; 400, memory cell string; 500, bonding cross-section; SL, source layer; 410, channel structure; 4101, first terminal; 4102, second terminal; 411, channel layer; 412, functional layer; 4121, tunneling layer; 4122, memory layer; 4123, barrier layer; 4124, first portion; 4125, second portion; 300, semiconductor layer; 600, semiconductor device; 610, first stacked structure; 611, first gate layer; 612, first dielectric. Layers; 6101, First sub-stack structure; 6102, Second sub-stack structure; 620, Second stacked structure; 621, Second gate layer; 622, Second dielectric layer; 6201, Third sub-stack structure; 6202, Fourth sub-stack structure; 630, First gate isolation structure; 631, Connecting portion; 632, Isolating portion; 633, First sub-part; 634, Second sub-part; 635, Third sub-part; 636, Isolating layer; 637, First gate isolation structure group; 638, Second gate isolation structure group; 640, Dielectric structure; 641, Arc edge; 650, Third connecting structure; 651, Connecting pillar; 652, First connecting layer; 653, Second connecting layer; 654. First isolation layer; 655. Second isolation layer; 656. Third isolation layer; 657. Fourth isolation layer; 658. Fifth isolation layer; 6302. Second gate isolation structure; 670. Third stacked structure; 671. Third dielectric layer; 672. Fourth dielectric layer; 680. Fourth stacked structure; 681. Fifth dielectric layer; 682. Sixth dielectric layer; 101. First region; 102. Second region; 103. Memory block; 690. Repeating structure; 660. Peripheral circuit layer; BL-1. First bit line; BL-2. Second bit line; 700. First bit line group; 701. First connection structure; 702. Second connection structure; 710. First stacked structure; 7 101. First sub-stack structure; 7102. Second sub-stack structure; 711. First sacrificial layer; 720. Second sub-stack structure; 7201. Third sub-stack structure; 7202. Fourth sub-stack structure; 721. Third sacrificial layer; 730. Second sacrificial layer; 731. First fill space; 740. Structural pile; 750. Channel hole; 751. First channel hole; 752. Second channel hole; 753. Third channel hole; 754. Fourth channel hole; 755. Fifth channel hole; 760. Gate slit; 761. First gate slit; 762. Second gate slit; 763. Third gate slit; 764. Fourth gate slit; 765. Fifth gate slit. Detailed Implementation

[0065] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0066] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0067] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0068] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0069] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0070] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0071] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0072] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0073] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0074] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0075] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0076] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0077] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0078] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0079] The term "three-dimensional memory" refers to a semiconductor device formed by arrays of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / perpendicularly" means nominally perpendicular to the main surface of the substrate or source layer (i.e., the lateral surface).

[0080] Figure 1 This is a schematic diagram of the three-dimensional structure of a three-dimensional memory according to some embodiments. Figure 2 This is a cross-sectional view of a three-dimensional memory according to some embodiments. Figure 3 for Figure 1 The image shows a cross-sectional view of a string of storage cells in a three-dimensional memory along section line A-A'. Figure 4 for Figure 3 Equivalent circuit diagram of the storage cell string.

[0081] Please refer to Figure 1 and Figure 2 This disclosure provides a three-dimensional memory 10 located in a three-dimensional coordinate system XYZ. The three-dimensional memory 10 extends in the YZ plane, with the second direction Y being, for example, the extension direction of the bit line BL, and the third direction Z being, for example, the extension direction of the word line WL. The first direction X is perpendicular to the YZ plane.

[0082] It should be noted that the first direction X intersects with the second direction Y, and the third direction Z intersects with the XY plane. This disclosure only uses the example of the first direction X, the second direction Y, and the third direction Z being mutually perpendicular to each other to explain the structure provided in some embodiments of this disclosure.

[0083] See Figure 1 and Figure 2 Some embodiments of this disclosure provide a three-dimensional memory 10. The three-dimensional memory 10 may include a semiconductor structure 200. The three-dimensional memory 10 may also include a source layer SL coupled to the semiconductor structure 200, and peripheral devices 100 coupled to the semiconductor structure 200. The peripheral devices 100 may be disposed on the side of the semiconductor structure 200 away from the source layer SL.

[0084] The source layer SL may include a semiconductor material, such as single-crystal silicon, single-crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or completely doped. For example, the source layer SL may include doped regions doped with p-type dopant. The source layer SL may also include undoped regions.

[0085] Semiconductor structure 200 may include arrayed strings of memory cell transistors (referred to herein as “memory cell strings”, such as NAND memory cell strings). Source layer SL may be coupled to the source ends of multiple memory cell strings 400.

[0086] Specifically, see Figure 3 and Figure 4 The storage cell string 400 may include multiple transistors T, one transistor T (e.g. Figure 4 Transistors T2 to T5 can be configured as a memory cell, and these transistors T are connected together to form a memory cell string 400. A transistor T (e.g., each transistor T) can be formed by a channel structure 410 and a gate line G surrounding the channel structure 410. The gate line G is configured to control the conduction state of the transistor.

[0087] It should be noted that, Figures 1-4 The number of transistors T is merely illustrative. The storage cell string 400 of the three-dimensional memory 10 provided in this embodiment may also include other numbers of transistors, such as 4, 16, 32, or 64.

[0088] Further, along the first direction X, the lowermost gate line among the multiple gate lines G (e.g., the gate line closest to the source layer SL among the multiple gate lines G) is constructed as a source select gate SGS. The source select gate SGS is configured to control the conduction state of transistor T6, thereby controlling the conduction state of the source channel in the memory cell string 400. Along the first direction X, the uppermost gate line among the multiple gate lines G (e.g., the gate line furthest from the source layer SL among the multiple gate lines G) is constructed as a drain select gate SGD. The drain select gate SGD is configured to control the conduction state of transistor T1, thereby controlling the conduction state of the drain channel in the memory cell string 400. The middle gate line among the multiple gate lines G can be constructed as multiple word lines WL, such as word lines WL0, WL1, WL2, and WL3. By writing different voltages onto the word lines WL, data writing, reading, and erasing of each memory cell (e.g., transistor T) in the memory cell string 400 can be completed.

[0089] See also Figure 1 and Figure 2 In some embodiments, the semiconductor structure 200 may further include an array interconnect layer 290. The array interconnect layer 290 may be coupled to the memory cell string 400. The array interconnect layer 290 may include the drain (i.e., bit line BL) of the memory cell string 400, which may be coupled to the semiconductor channel of at least one transistor T in the memory cell string 400.

[0090] The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may also include a plurality of contacts insulated from each other by these first interlayer insulating layers 292. The contacts may include, for example, bit line contacts BL-CNT, drain select gate contacts SGD-CNT, and gate line contacts G-CNT. Specifically, the bit line contact BL-CNT is coupled to the bit line BL; the drain select gate contact SGD-CNT is coupled to the drain select gate SGD; and the gate line contact G-CNT is coupled to the gate line G.

[0091] The array interconnect layer 290 may further include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include multiple interconnect lines, such as bit lines BL, and word line interconnect lines WL-CL coupled to word lines WL. The materials of the first interconnect conductor layers 291 and the contacts may be conductive materials, such as tungsten, cobalt, copper, aluminum, and combinations of one or more metal silicides, or other conductive materials. The material of the first interlayer insulating layer 292 is an insulating material, such as silicon oxide, silicon nitride, and combinations of one or more high-dielectric-constant insulating materials, or other insulating materials.

[0092] Peripheral device 100 may include peripheral circuitry. The peripheral circuitry is configured to control and sense the array device. The peripheral circuitry may be any suitable digital, analog, or mixed-signal control and sensing circuitry used to support the operation (or function) of the array device, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry may also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (PLDs)) or memory circuitry (e.g., static random-access memory (SRAM)).

[0093] Specifically, in some embodiments, the peripheral device 100 may include a substrate 110, a transistor 120 disposed on the substrate 110, and a peripheral interconnect layer 130 disposed on the substrate 110. The peripheral circuitry may include the transistor 120.

[0094] The substrate 110 can be made of single-crystal silicon or other suitable materials, such as silicon-germanium, germanium or silicon-on-insulator thin film.

[0095] The peripheral interconnect layer 130 is coupled to the transistor 120 to transmit electrical signals between the transistor 120 and the peripheral interconnect layer 130. The peripheral interconnect layer 130 may include one or more second interlayer insulating layers 131, and may also include one or more second interconnect conductor layers 132. Different second interconnect conductor layers 132 may be coupled to each other via contacts. The materials of the second interconnect conductor layers 132 and the contacts may be conductive materials, such as tungsten, cobalt, copper, aluminum, and combinations of one or more metal silicides, or other suitable materials. The material of the second interlayer insulating layer 131 is an insulating material, such as silicon oxide, silicon nitride, and combinations of one or more high dielectric constant insulating materials, or other suitable materials.

[0096] The peripheral interconnect layer 130 can be coupled to the array interconnect layer 290, enabling coupling between the semiconductor structure 200 and the peripheral device 100. Specifically, since the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, the peripheral circuits in the peripheral device 100 can be coupled to the memory cell string in the semiconductor structure 200 to achieve the transmission of electrical signals between the peripheral circuits and the memory cell string. In some possible implementations, an bonding interface 500 can be provided between the peripheral interconnect layer 130 and the array interconnect layer 290, through which the peripheral interconnect layer 130 and the array interconnect layer 290 can be bonded and coupled to each other.

[0097] Figure 5 This is a schematic diagram of the structure of a semiconductor device according to some embodiments. For example... Figure 5 As shown, some embodiments of this disclosure provide a semiconductor device 600, which can be a three-dimensional memory, or a part of a three-dimensional memory. The semiconductor device 600 includes: a first stacked structure 610 and a second stacked structure 620 stacked along a first direction X, a first bit line BL-1, and a second bit line BL-2. The first bit line BL-1 is located on the side of the first stacked structure 610 away from the second stacked structure 620, and extends along a second direction Y. The second bit line BL-2 is located on the side of the second stacked structure 620 away from the first stacked structure 610, and extends along the second direction Y. The extending directions of the first bit line BL-1 and the second bit line BL-2 can be parallel.

[0098] The semiconductor device 600 also includes a channel structure 410 that extends along a first direction X through the first stacked structure 610 and the second stacked structure 620. The two ends of the channel structure 410 along the first direction X are connected to a first bit line BL-1 and a second bit line BL-2, respectively. The semiconductor device 600 also requires two circuits to connect the first bit line BL-1 and the second bit line BL-2, respectively, to control the first bit line BL-1 and the second bit line BL-2. However, connecting the first bit line BL-1 and the second bit line BL-2 through two circuits requires more metal wires, resulting in higher costs and more complex circuit design.

[0099] Based on this, the semiconductor device 600 provided in some embodiments of this disclosure further includes: a first gate isolation structure 630. The first gate isolation structure 630 extends along a third direction Z and penetrates the first stacked structure 610 and the second stacked structure 620 along a first direction X. The two ends of the first gate isolation structure 630 along the first direction X are respectively connected to a first bit line BL-1 and a second bit line BL-2. The first gate isolation structure 630 electrically connects the first bit line BL-1 and the second bit line BL-2, so that the first bit line BL-1 and the second bit line BL-2 can share a single circuit, which can reduce the use of metal lines, thereby reducing costs and simplifying circuit design.

[0100] Furthermore, since the first gate isolation structure 630 is a structure already present in the semiconductor device 600, connecting the first bit line BL-1 and the second bit line BL-2 through the first gate isolation structure 630 is a reuse of the first gate isolation structure 630. The semiconductor device 600 does not require additional conductive structures to connect the first bit line BL-1 and the second bit line BL-2, and the size of the semiconductor device 600 will not increase, which is beneficial for the miniaturization of the semiconductor device 600.

[0101] In some embodiments, such as Figure 5 and Figure 6 As shown, the first gate isolation structure 630 includes an isolation portion 632 and a connection portion 631. On a plane parallel to the second direction Y and the third direction Z, the connection portion 631 is disposed around the isolation portion 632, and the two ends of the connection portion 631 along the first direction X are respectively connected to the first bit line BL-1 and the second bit line BL-2.

[0102] For example, the isolation portion 632 may be a columnar structure extending along a first direction X through the first stacked structure 610 and the second stacked structure 620. The connecting portion 631 is disposed around the isolation portion 632 so that the isolation portion 632 provides support for the connecting portion 631.

[0103] For example, the connecting portion 631 can be an annular structure, and the isolation portion 632 can fill the gap enclosed by the connecting portion 631 so that the isolation portion 632 can provide support for the connecting portion 631, which is beneficial to improving the structural stability of the first gate isolation structure 630.

[0104] Exemplarily, the constituent material of the connection portion 631 may include a conductive material. Conductive materials include, but are not limited to, one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, and silicides, or other suitable conductive materials. When the constituent material of the connection portion 631 includes a metal, the constituent material of the connection portion 631 may also include titanium nitride. Depositing a layer of titanium nitride on the surface of the metal material helps prevent metal diffusion, and titanium nitride has good adhesion, which helps improve the structural stability of the first gate isolation structure 630.

[0105] For example, the constituent material of the isolation portion 632 may include an insulating material. The insulating material may include one or a combination of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating materials, or may be other suitable insulating materials.

[0106] With the above configuration, the first bit line BL-1 and the second bit line BL-2 can be electrically connected through the connecting part 631, so that the first bit line BL-1 and the second bit line BL-2 can share a circuit, which can reduce the use of metal wires, reduce costs, and simplify circuit design.

[0107] In some embodiments, such as Figure 5 As shown, the dimension of the end of the connecting portion 631 near the second bit line BL-2 in the second direction Y is greater than the dimension of the end of the connecting portion 631 near the first bit line BL-1 in the second direction Y.

[0108] It should be noted that the dimension of the end of the connecting portion 631 near the second bit line BL-2 in the second direction Y can be understood as the maximum width of the end of the connecting portion 631 near the second bit line BL-2 in the second direction Y. The dimension of the end of the connecting portion 631 near the first bit line BL-1 in the second direction Y can be understood as the maximum width of the end of the connecting portion 631 near the first bit line BL-1 in the second direction Y.

[0109] The above configuration increases the surface area of ​​the end of the connecting part 631 near the second bit line BL-2, which helps to increase the contact area between the connecting part 631 and the second bit line BL-2, facilitates the electrical connection between the connecting part 631 and the second bit line BL-2, and also helps to reduce the resistance between the connecting part 631 and the second bit line BL-2, and increase the current intensity between the connecting part 631 and the second bit line BL-2.

[0110] Figure 7 This is a schematic diagram of the structure of a semiconductor device according to some other embodiments. For example... Figure 7As shown, semiconductor devices can increase their storage capacity by adding stacked structures. For example, the first stacked structure 610 may include a first sub-stacked structure 6101 and a second sub-stacked structure 6102 stacked along a first direction X, and the second stacked structure 620 may include a third sub-stacked structure 6201 and a fourth sub-stacked structure 6202 stacked along the first direction X. The second sub-stacked structure 6102 is closer to the third sub-stacked structure 6201 than the first sub-stacked structure 6101, and the third sub-stacked structure 6201 is closer to the second sub-stacked structure 6102 than the fourth sub-stacked structure 6202.

[0111] In some embodiments, such as Figure 7 As shown, the connecting portion 631 may include a first sub-portion 633, a second sub-portion 634, and a third sub-portion 635, which are stacked and connected sequentially along a first direction X. The first sub-portion 633 penetrates the first sub-stack structure 6101, the second sub-portion 634 penetrates the second sub-stack structure 6102 and the third sub-stack structure 6201, and the third sub-portion 635 penetrates the fourth sub-stack structure 6202. The first sub-portion 633, the second sub-portion 634, and the third sub-portion 635 are connected sequentially. Furthermore, the first sub-portion 633 is connected to the first bit line BL-1, and the third sub-portion 635 is connected to the second bit line BL-2.

[0112] For example, the first sub-part 633, the second sub-part 634, and the third sub-part 635 can be an integral structure. It can be understood that the first sub-part 633, the second sub-part 634, and the third sub-part 635 are manufactured in one process step, which helps to enhance the stability of the electrical connection between the first sub-part 633, the second sub-part 634, and the third sub-part 635.

[0113] With the above configuration, the first bit line BL-1 can be electrically connected to the second bit line BL-2 through the first sub-section 633, the second sub-section 634 and the third sub-section 635 to realize the transmission of electrical signals. This allows the first bit line BL-1 and the second bit line BL-2 to share a circuit, which can reduce the use of metal wires, reduce costs and simplify circuit design.

[0114] In some embodiments, such as Figure 7 As shown, the dimension of the end of the first sub-part 633 near the second sub-part 634 in the second direction Y is greater than the dimension of the end of the second sub-part 634 near the first sub-part 633 in the second direction Y.

[0115] Here, the dimension of the end of the first sub-part 633 near the second sub-part 634 in the second direction Y can be understood as, for example Figure 7As shown, in the XY section, the width of the end of the first sub-part 633 near the second sub-part 634. The dimension of the end of the second sub-part 634 near the first sub-part 633 in the second direction Y can be understood as follows: Figure 7 As shown, in the XY section, the width of the end of the second sub-part 634 near the end of the first sub-part 633. Alternatively, it can be understood here that the orthographic projection of the end of the second sub-part 634 near the end of the first sub-part 633 in the first direction X is located within the edge of the orthographic projection of the end of the first sub-part 633 near the end of the second sub-part 634 in the first direction X.

[0116] By setting the connection end of the first sub-part 633 and the second sub-part 634 to be "wide at one end and narrow at the other end", the process window for connecting the first sub-part 633 and the second sub-part 634 is increased, which facilitates the connection between the first sub-part 633 and the second sub-part 634 and helps to improve the stability of the connection between the first sub-part 633 and the second sub-part 634.

[0117] In this embodiment, the dimension of the end of the second sub-part 634 near the third sub-part 635 in the second direction Y is greater than the dimension of the end of the third sub-part 635 near the second sub-part 634 in the second direction Y.

[0118] Here, the dimension of the end of the second sub-part 634 near the third sub-part 635 in the second direction Y can be understood as, for example Figure 7 As shown, in the XY section, the width of the end of the second sub-part 634 near the third sub-part 635. The dimension of the end of the third sub-part 635 near the second sub-part 634 in the second direction Y can be understood as follows: Figure 7 As shown, in the XY section, the width of the end of the third sub-part 635 near the end of the second sub-part 634. Alternatively, it can be understood here that the orthographic projection of the end of the second sub-part 634 near the third sub-part 635 in the first direction X is located within the edge of the orthographic projection of the end of the third sub-part 635 near the second sub-part 634 in the first direction X.

[0119] By setting the connection end of the second sub-part 634 and the third sub-part 635 to be "wide at one end and narrow at the other end", the process window for connecting the second sub-part 634 and the third sub-part 635 is increased, which facilitates the connection between the second sub-part 634 and the third sub-part 635 and helps to improve the stability of the connection between the second sub-part 634 and the third sub-part 635.

[0120] In some embodiments, such as Figure 7 As shown, the dimension of the end of the first sub-part 633 near the second sub-part 634 in the second direction Y is greater than the dimension of the end of the first sub-part 633 away from the second sub-part 634 in the second direction Y.

[0121] In the second direction Y, the end of the first sub-part 633 that is away from the second sub-part 634 is narrower than the end of the first sub-part 633 that is close to the second sub-part 634, which facilitates the connection between the first sub-part 633 and the second sub-part 634 and helps to improve the connection stability between the first sub-part 633 and the second sub-part 634.

[0122] In some embodiments, such as Figure 7 As shown, the dimension of the end of the second sub-part 634 away from the first sub-part 633 in the second direction Y is greater than the dimension of the end of the second sub-part 634 near the first sub-part 633 in the second direction Y.

[0123] In the second direction Y, the end of the second sub-part 634 near the first sub-part 633 is narrower than the end of the second sub-part 634 away from the first sub-part 633, while the end of the second sub-part 634 away from the first sub-part 633 is wider. This facilitates the connection between the first sub-part 633 and the second sub-part 634, as well as the connection between the second sub-part 634 and the third sub-part 635. This improves the connection stability between the first sub-part 633 and the second sub-part 634, and also improves the connection stability between the second sub-part 634 and the third sub-part 635.

[0124] In some embodiments, such as Figure 7 As shown, the dimension of the end of the third sub-part 635 away from the second sub-part 634 in the second direction Y is greater than the dimension of the end of the third sub-part 635 near the second sub-part 634 in the second direction Y.

[0125] In the second direction Y, the end of the third sub-part 635 near the second sub-part 634 is narrower than the end of the third sub-part 635 away from the second sub-part 634, while the end of the third sub-part 635 away from the second sub-part 634 is wider. This facilitates the connection between the third sub-part 635 and the second sub-part 634, as well as the connection between the third sub-part 635 and the second bit line BL-2. This improves the connection stability between the second sub-part 634 and the third sub-part 635, and also improves the connection stability between the third sub-part 635 and the second bit line BL-2.

[0126] In some embodiments, such as Figure 5 As shown, the semiconductor device 600 further includes a first connection structure 701 and a second connection structure 702. In the first direction X, the two ends of the first connection structure 701 are respectively connected to a first bit line BL-1 and a first gate isolation structure 630. In the first direction X, the two ends of the second connection structure 702 are respectively connected to a second bit line BL-2 and a first gate isolation structure 630.

[0127] Specifically, the first connecting structure 701 connects the first bit line BL-1 and the connecting part 631 to its two ends in the first direction X, respectively. The second connecting structure 701 connects the second bit line BL-2 and the connecting part 631 to its two ends in the first direction X, respectively.

[0128] For example, the constituent materials of the first connection structure 701 and the second connection structure 702 may include conductive materials. Conductive materials include, but are not limited to, one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, and silicides, or other suitable conductive materials.

[0129] For example, the dimension of the end of the first connection structure 701 near the first bit line BL-1 in the second direction Y can be larger than the dimension of the end of the first connection structure 701 near the first gate isolation structure 630 in the second direction Y. For example Figure 5 In the first connection structure 701, the shape is wider at the top and narrower at the bottom in the YZ cross section. With the above arrangement, the area of ​​the surface of the first connection structure 701 near the first bit line BL-1 is larger than the area of ​​the surface of the first connection structure 701 near the first gate isolation structure 630.

[0130] With the above configuration, the surface area of ​​the first connecting structure 701 near the first line BL-1 is increased, which facilitates the connection between the first line BL-1 and the first connecting structure 701.

[0131] For example, the dimension of the end of the second connection structure 702 near the second bit line BL-2 in the second direction Y can be larger than the dimension of the end of the second connection structure 702 near the first gate isolation structure 630 in the second direction Y. This arrangement helps to increase the surface area of ​​the second connection structure 702 near the second bit line BL-2, facilitating the connection between the second connection structure 702 and the second bit line BL-2.

[0132] For example, there can be multiple first connection structures 701; for instance, in this embodiment, there are two first connection structures 701. Multiple first connection structures 701 can be spaced apart circumferentially along the first gate isolation structure. Connecting the first bit line BL-1 and the first gate isolation structure 630 with multiple first connection structures 701 helps reduce the resistance between the first connection structure 701 and the first bit line BL-1, and also helps reduce the resistance between the first connection structure 701 and the first gate isolation structure 630, thereby improving the electrical signal strength between the first bit line BL-1 and the gate isolation structure.

[0133] In this embodiment, by setting the first connection structure 701, it is convenient to connect the first bit line BL-1 to the first gate isolation structure 630. By setting the second connection structure 702, it is convenient to connect the second bit line BL-2 to the first gate isolation structure 630, thereby realizing the electrical connection between the first bit line BL-1 and the second bit line BL-2, which is beneficial for the transmission of electrical signals between the first bit line BL-1 and the second bit line BL-2.

[0134] In some embodiments, such as Figure 8 As shown, there are multiple first gate isolation structures 630. These multiple first gate isolation structures 630 are arranged in multiple columns along the second direction Y and in multiple rows along the third direction Z. There are multiple first bit lines BL-1, which are arranged sequentially at intervals along the third direction Z, with each first bit line BL-1 connected to one end of a first gate isolation structure 630. There are multiple second bit lines BL-2, which are arranged sequentially at intervals along the third direction Z, with each second bit line BL-2 connected to the other end of a first gate isolation structure 630.

[0135] For example, a first bit line BL-1 and a second bit line BL-2 can be correspondingly arranged in the first direction X. The orthographic projection of the first bit line BL-1 in the first direction X coincides with or partially overlaps with the orthographic projection of the second bit line BL-2 in the first direction X. The first bit line BL-1 and the second bit line BL-2 opposite to each other in the first direction X can be connected to the same first gate isolation structure 630.

[0136] For example, the number of rows and columns of multiple first gate isolation structures 630 can be designed according to the number of first bit lines BL-1 and second bit lines BL-2, so that the multi-row and multi-column first gate isolation structures 630 can connect multiple first bit lines BL-1 to multiple second bit lines BL-2 in a one-to-one correspondence.

[0137] In this embodiment, multiple first gate isolation structures 630 are connected one-to-one with multiple first bit lines BL-1, and multiple first gate isolation structures 630 are also connected one-to-one with multiple second bit lines BL-2. Through this arrangement, the multiple first gate isolation structures 630 arranged in multiple rows and columns can connect the first bit lines BL-1 and the second bit lines BL-2 one-to-one, allowing the first bit lines BL-1 and the second bit lines BL-2 to share a single circuit. This reduces the use of metal lines, helps lower costs, and simplifies circuit design.

[0138] In some embodiments, such as Figure 8As shown, adjacent rows of first gate isolation structures 630 are staggered in the third direction Z. Here, adjacent rows of first gate isolation structures 630 may be completely staggered in the third direction Z, or they may be partially staggered in the third direction Z. For example, the orthographic projections of adjacent rows of first gate isolation structures 630 in the second direction Y do not overlap, or the orthographic projections of adjacent rows of first gate isolation structures 630 in the second direction Y partially overlap.

[0139] For example, the first gate isolation structures 630 in odd-numbered rows can adopt the same arrangement, and the first gate isolation structures 630 in even-numbered rows can adopt the same arrangement. This can be understood as the orthographic projections of the first gate isolation structures 630 in odd-numbered rows on the second direction Y completely coinciding, and the orthographic projections of the first gate isolation structures 630 in even-numbered rows on the second direction Y completely coinciding. The orthographic projections of the first gate isolation structures 630 in odd-numbered rows on the second direction Y can be connected end-to-end with the orthographic projections of the first gate isolation structures 630 in even-numbered rows on the second direction Y.

[0140] By staggering the adjacent rows of first gate isolation structures 630 in the third direction Z, the first gate isolation structure 630 can connect multiple first bit lines BL-1 and multiple second bit lines BL-2 one by one, so that the first bit line BL-1 and the second bit line BL-2 can share a circuit, which can reduce the use of metal lines, reduce costs, and simplify circuit design.

[0141] In addition, the first stacked structure 610 and the second stacked structure 620 can be divided into multiple memory blocks 103 by the first gate isolation structure 630 with multiple rows and columns.

[0142] In other embodiments, such as Figure 9 As shown, in two adjacent rows of first gate isolation structures 630, one row of first gate isolation structures 630 and the other row of first gate isolation structures 630 are aligned one-to-one in the second direction Y. Here, the two sides of one first gate isolation structure 630 in one row of first gate isolation structures 630 along the third direction Z are aligned with the two sides of one first gate isolation structure 630 in the other row of first gate isolation structures 630 along the third direction Z in the second direction Y. It can be understood that in two adjacent rows of first gate isolation structures 630, the orthographic projection of one row of first gate isolation structures 630 in the second direction Y completely coincides with the orthographic projection of the other row of first gate isolation structures 630 in the second direction Y.

[0143] In this embodiment, we continue to refer to Figure 9At least two rows of adjacent first gate isolation structures 630 can form a first gate isolation structure group 637, and another at least two rows of adjacent first gate isolation structures 630 can form a second gate isolation structure group 638. The multiple rows of first gate isolation structures 630 in the first gate isolation structure group 637 can adopt the same arrangement, so that the multiple rows of first gate isolation structures 630 are aligned one-to-one in the second direction Y. The multiple rows of first gate isolation structures 630 in the second gate isolation structure group 638 can adopt the same arrangement, so that the multiple rows of first gate isolation structures 630 are aligned one-to-one in the second direction Y. The first gate isolation structures 630 in the first gate isolation structure group 637 and the first gate isolation structures 630 in the second gate isolation group 638 are staggered in the third direction Z.

[0144] By staggering the first gate isolation structure 630 in the first gate isolation structure group 637 and the first gate isolation structure 630 in the second gate isolation structure group 638 in the third direction Z, the multi-row and multi-column first gate isolation structure 630 can connect all the first bit lines BL-1 and all the second bit lines BL-2 one by one, so that the first bit lines BL-1 and the second bit lines BL-2 can share a circuit, which can reduce the use of metal lines, reduce costs, and simplify circuit design.

[0145] In some embodiments, such as Figure 8 and Figure 10 As shown, the semiconductor device 600 also includes a dielectric structure 640, which extends through the first stacked structure 610 and the second stacked structure 620 along the first direction X. In the third direction Z, at least one dielectric structure 640 is disposed between two adjacent first gate isolation structures 630.

[0146] "At least one dielectric structure 640 is provided between two adjacent first gate isolation structures 630" can be understood as one dielectric structure 640 being provided between two adjacent first gate isolation structures 630, or multiple dielectric structures 640 being provided between two adjacent first gate isolation structures 630.

[0147] Because the multi-row, multi-column first gate isolation structure 630 separates the first stack structure 610 and the second stack structure 620 into multiple memory blocks 103, and there is a certain gap between two adjacent first gate isolation structures 630 in the third direction Z, if adjacent memory blocks 103 are connected, it will be impossible to select a single memory block 103, causing the semiconductor device 600 to malfunction.

[0148] To better isolate adjacent memory blocks 103, this embodiment provides a dielectric structure 640 between two adjacent first gate isolation structures 630. The dielectric structure 640 is composed of an insulating material, such as silicon oxide. This arrangement improves the isolation effect between adjacent memory blocks 103, prevents them from connecting, ensures the normal operation of the semiconductor device 600, and enhances the storage stability of the semiconductor device 600.

[0149] It should be noted that the dielectric structure 640 is located between two adjacent first gate isolation structures 630 along the third direction Z. In order to further improve the isolation effect between two adjacent memory blocks 103, the two ends of the dielectric structure 640 along the third direction Z can be in contact with the two first gate isolation structures 630 respectively.

[0150] In some embodiments, such as Figure 10 and Figure 11 As shown, on a plane parallel to the second direction Y and the third direction Z, the profile edge of the medium structure 640 cross section includes at least one arcuate edge 641.

[0151] For example, please refer to Figure 10 On a plane parallel to the second direction Y and the third direction Z, the outline edge of the cross-section of the medium structure 640 can be composed of multiple arc-shaped edges 641 connected end to end. Among the multiple arc-shaped edges 641, the curvature of any two arc-shaped edges 641 can be the same or different, and this disclosure does not impose any restrictions on this.

[0152] By designing the position and curvature of the arc edge 641, the dimensions of the dielectric structure 640 in the second direction Y and the third direction Z can be adjusted so that the dielectric structure 640 can better fit the gap between two adjacent first gate isolation structures 630 along the third direction Z. This is beneficial for isolating the mutual interference between two adjacent memory blocks 103 along the second direction Y and improving the storage stability of the semiconductor device 600.

[0153] In some embodiments, such as Figure 7 and Figure 8As shown, the semiconductor device 600 also includes multiple channel structures 410. The channel structures 410 can penetrate the first stacked structure 610 and the second stacked structure 620 along a first direction X. The multiple channel structures 410 are arranged in multiple rows along a third direction Z, and the multiple channel structures 410 are arranged in multiple columns along a second direction Y, with adjacent rows of channel structures 410 staggered in the third direction Z. Here, adjacent rows of channel structures 410 can be completely staggered in the third direction Z, or adjacent rows of channel structures 410 can be partially staggered in the third direction Z. When adjacent rows of channel structures 410 are completely staggered in the third direction Z, the orthographic projections of adjacent rows of channel structures 410 in the second direction Y do not overlap. When adjacent rows of channel structures 410 are partially staggered in the third direction Z, the orthographic projections of adjacent rows of channel structures 410 in the second direction partially overlap.

[0154] Along the second direction Y, multiple channel structures 410 are disposed between two adjacent rows of first gate isolation structures 630. In each of the multiple channel structures 410, a first bit line BL-1 is connected to at least one channel structure 410, and a second bit line BL-2 is connected to at least one channel structure 410. Exemplarily, in each of the multiple channel structures 410, a first bit line BL-1 is connected to one channel structure 410, and a second bit line BL-2 is connected to one channel structure 410. That is, multiple first bit lines BL-1 are connected to multiple channel structures 410 in a one-to-one correspondence, and multiple second bit lines BL-2 are connected to multiple channel structures 410 in a one-to-one correspondence. Alternatively, a first bit line BL-1 is connected to a channel structure 410 in each memory block 103, and multiple channel structures 410 connected to the same first bit line BL-1 are located in the same column; a second bit line BL-2 is connected to a channel structure 410 in each memory block 103, and multiple channel structures 410 connected to the same second bit line BL-2 are located in the same column.

[0155] It should be noted that the number of channel structures 410 in each storage block 103 can be the same or different. For example, storage block 103 may include 2 rows, 4 rows, 6 rows or 8 rows of channel structures 410, and this disclosure does not limit this.

[0156] With the above settings, the multi-row multi-column channel structure 410 can be connected one-to-one with multiple first bit lines BL-1, and the multi-row multi-column channel structure 410 can be connected one-to-one with multiple second bit lines BL-2, thereby controlling and operating the channel structure 410 through the first bit lines BL-1 and the second bit lines BL-2.

[0157] In addition, the staggered arrangement of adjacent two rows of channel structures 410 in the third direction Z is beneficial to increasing the density of multiple channel structures 410 and thus improving the storage density of the semiconductor device 600.

[0158] In some embodiments, such as Figure 8 As shown, multiple first bit lines BL-1 constitute multiple first bit line groups 700, and each first bit line group 700 includes at least two adjacent first bit lines BL-1. In the first direction X, each first bit line BL-1 in the first bit line group 700 overlaps with each first gate isolation structure 630 located in the same column.

[0159] "The first line group 700 includes at least two adjacent first line BL-1" can be understood as a first line group 700 including two or more adjacent first line BL-1.

[0160] Each first line BL-1 in the first line group 700 overlaps with each first gate isolation structure 630 located in the same column in the first direction X. For example, refer to Figure 8 Each first bit line BL-1 in a first bit line group 700 overlaps with each first gate isolation structure 630 located in the first column in the first direction X. That is, the number of first bit lines BL-1 that overlap with each first gate isolation structure 630 located in the same column in the first direction X is the same.

[0161] refer to Figure 7 and Figure 8 The first gate isolation structure 630 is connected to the first bit line BL-1 and the second bit line BL-2 at both ends along the first direction X, so the multiple second bit lines BL-2 can be configured one-to-one with the multiple first bit lines BL-1. Therefore, the number of second bit lines BL-2 that overlap with each of the first gate isolation structures 630 located in the same column in the first direction X is also the same.

[0162] Furthermore, in order to connect all the first bit lines BL-1 of the first bit group 700 to their corresponding second bit lines BL-2, the number of first gate isolation structures 630 overlapping with the first bit group 700 in the first direction X can be the same as the number of first bit lines BL-1 included in the first bit group 700. For example, if the first bit group 700 includes n first bit lines BL-1, then the number of first gate isolation structures 630 overlapping with it in the first direction X is also n. One end of each first gate isolation structure 630 is connected to one first bit line BL-1, and the other end of each first gate isolation structure 630 is connected to one second bit line BL-2.

[0163] With the above settings, the number of first gate isolation structures 630 in a column of first gate isolation structures 630 can be set according to the number of first line BL-1, thereby setting the number of rows and columns of the first gate isolation structures 630, so as to facilitate the design of the arrangement of the first gate isolation structures 630.

[0164] In some embodiments, please refer to Figure 7 and Figure 8 One of the first gate isolation structures 630 in a row of multiple first gate isolation structures 630 that overlap with the first line group 700 is connected to one of the first lines BL-1 in the first line group 700.

[0165] A column of first gate isolation structures 630 can be connected one-to-one with all the first bit lines BL-1 in the first bit line group 700, thereby connecting the first bit line BL-1 and its corresponding second bit line BL-2, achieving electrical connection between the first bit line BL-1 and the second bit line BL-2. The first gate isolation structure is an inherent structure of the semiconductor device, not a new structure. Connecting the first bit line BL-1 and the second bit line BL-2 through the first gate isolation structure is a reuse of the existing structure, which helps to control the size of the semiconductor device 600 in the second direction Y, thus promoting the miniaturization of the semiconductor device 600. Furthermore, the above arrangement reduces metal wiring, lowers the manufacturing cost of the semiconductor device 600, and simplifies the structural design and manufacturing process of the semiconductor device 600.

[0166] In some embodiments, such as Figure 8 As shown, the multiple first gate isolation structures 630 have the same dimensions in the third direction Z. That is, the multiple first gate isolation structures 630 have the same length in the third direction Z. With the above arrangement, the number of first bit lines BL-1 connected to each column of first gate isolation structures 630 can be the same, which makes it easier to set the number and arrangement of the first gate isolation structures 630 according to the number of first bit lines BL-1, and helps to simplify the design of the arrangement of the first gate isolation structures 630. Furthermore, the fact that each first gate isolation structure 630 has the same dimensions in the third direction Z helps to simplify the fabrication process.

[0167] In some embodiments, please refer to Figure 1 and Figure 3The source layer SL is located on one side of the semiconductor structure 200. For example, the source layer SL is located on the lowest plane in the first direction X. One end of the channel structure 410 is connected to the source layer SL. The source layer SL applies a voltage to the channel structure 410 to create a voltage difference across the channel structure 410, thereby driving the channel structure 410 to generate current. However, as users pursue high-capacity and small-size 3D NAND, the storage capacity of the 3D NAND is increased by increasing the length of the channel structure 410 in the first direction X. The increase in the length of the channel structure 410 in the first direction X leads to an increase in the resistance of the channel structure 410 and a decrease in the voltage difference across the two ends of the channel structure 410 along the first direction X. Consequently, the current intensity within the channel structure 410 decreases, making it difficult to meet the device performance requirements of the 3D NAND 10, such as storage speed and response speed.

[0168] Based on this, please refer to some embodiments. Figure 5 and Figure 7 The semiconductor device 600 further includes a source layer SL. The source layer SL is located between the first stacked structure 610 and the second stacked structure 620. That is, the first stacked structure 610, the source layer SL, and the second stacked structure 620 are stacked sequentially along the first direction X.

[0169] Exemplarily, the first stacked structure 610 may include a plurality of first gate layers 611 and a plurality of first dielectric layers 612 alternately stacked along the first direction X. For example, the first gate layers 611 and the first dielectric layers 612 alternately stacked along the first direction X form a plurality of first gate layers 611 and a plurality of first dielectric layers 612 spaced apart from each other. It can also be understood that a first gate layer 611 and a first dielectric layer 612 together constitute a first gate structure pair, and the first stacked structure 610 includes a plurality of first gate structure pairs stacked along the first direction X.

[0170] For example, the number of layers in the first gate layer 611 can be 4, 16, 32, 64, 128, 256, etc. The number of layers in the first dielectric layer 612 can be 4, 16, 32, 64, 128, 256, etc. The thickness of the first gate layer 611 (i.e., the dimension along the first direction X) can be approximately equal to or different from the thickness of the first dielectric layer 612. For example, the thickness of the first dielectric layer 612 is greater than the thickness of the first gate layer 611.

[0171] Exemplarily, the constituent material of the first gate layer 611 may include a conductive material, including but not limited to one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, and silicides, or other suitable conductive materials. In some examples, the first gate layer 611 includes a metal layer, such as a tungsten layer. In some examples, the first gate layer 611 includes a doped polysilicon layer. Polysilicon can be doped to a desired doping concentration using suitable dopant, making the polysilicon a conductive material used as the first gate layer 611.

[0172] Exemplarily, the constituent material of the first dielectric layer 612 may include an insulating material, which may include one or more of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating materials, or may be other suitable insulating materials. Silicon oxynitride has a higher dielectric constant than silicon oxide; for example, at approximately 20°C, the dielectric constant of silicon oxynitride is between 4 and 7. In some examples, the first dielectric layer 612 includes a silicon oxide layer. In some examples, the first dielectric layer 612 includes a silicon oxynitride layer.

[0173] For example, the thickness of the first gate layer 611 (i.e., the dimension along the first direction X) can be between 10nm and 50nm, such as 10nm, 15nm, 18.3nm, 20nm, 25nm, 27.7nm, 30nm, 35nm, 40nm, 45nm, 50nm, etc. Similarly, the thickness of the first dielectric layer 612 (i.e., the dimension along the first direction X) can be between 10nm and 50nm, such as 10nm, 15nm, 18.3nm, 20nm, 25nm, 27.7nm, 30nm, 35nm, 40nm, 45nm, 50nm, etc. The first gate layer 611 can be a gate line G surrounding a string of memory cells (see...). Figure 3 ), and can be used as a word line WL (see Figure 1 It extends laterally (i.e., along the third direction Z).

[0174] In this embodiment, the second stacked structure 620 may include a plurality of second gate layers 621 and a plurality of second dielectric layers 622 alternately stacked along the first direction X. For example, the second gate layers 621 and the second dielectric layers 622 alternately stacked along the first direction X form a plurality of mutually spaced second gate layers 621 and a plurality of second dielectric layers 622. Alternatively, it can be understood that one second gate layer 621 and one second dielectric layer 622 together constitute a second gate structure pair, and the second stacked structure 620 includes a plurality of second gate structure pairs stacked along the first direction X.

[0175] Understandably, the composition, thickness, and number of the second gate layer 621 can be referenced to the example of the composition, thickness, and number of the first gate layer 611 mentioned above. The composition, thickness, and number of the second dielectric layer 622 can be referenced to the example of the composition, thickness, and number of the first dielectric layer 612 mentioned above. However, the composition, thickness, and number of the second gate layer 621 and the first gate layer 611 can be the same or different, and the composition, thickness, and number of the second dielectric layer 622 and the first dielectric layer 612 can be the same or different.

[0176] It should be noted that the number of stacking layers in the first stacking structure 610 and the second stacking structure 620 may be the same or different. For example, the first stacking structure 610 may be composed of multiple stacking structures, and the second stacking structure 620 may also be composed of multiple stacking structures; this disclosure does not impose any limitations on this.

[0177] In this embodiment, reference Figure 5 and Figure 7 The channel structure 410 can penetrate the first stack structure 610, the source layer SL and the second stack structure 620 along the first direction X, and the channel structure 410 is connected to the source layer SL.

[0178] The channel structure 410 has a first end 4101 and a second end 4102 disposed along a first direction X. By disposing the source layer SL between the first stacked structure 610 and the second stacked structure 620, and by having the channel structure 410 penetrate the first stacked structure 610, the source layer SL, and the second stacked structure 620 along the first direction X, the connection point between the source layer SL and the channel structure 410 can be located between the first end 4101 and the second end 4102. Thus, the source layer SL applies a voltage to the channel structure 410, causing a voltage difference to be generated between the connection point of the source layer SL and the channel structure 410 and both the first end 4101 and the second end 4102, thereby driving electron flow in the channel structure 410.

[0179] Compared to a three-dimensional memory where the source layer SL is connected to either the first terminal 4101 or the second terminal 4102, in this embodiment, the source layer SL can simultaneously drive the channel structure 410 upwards and downwards. This shortens the length of the channel structure 410 driven by the source layer SL in the first direction X, thereby increasing the current intensity in the channel structure 410. This improves the problems of increased resistance and decreased voltage difference in the channel structure 410 due to the increased length of the channel structure 410. This configuration helps to increase the current intensity in the channel structure 410, thereby improving the device performance of the semiconductor device 600, such as storage speed and response speed.

[0180] This solution is highly scalable; the number of stacking layers in the first stacking structure 610 or the second stacking structure 620 can be increased to improve the length of the channel structure 410 in the first direction X, thereby increasing the storage capacity of the channel structure 410. Furthermore, the source layer SL is located between the first stacking structure 610 and the second stacking structure 620. While improving the storage capacity of the channel structure 410, it also addresses the issue of weak current intensity in the channel structure 410 due to the increased length.

[0181] It should be noted that the phrase "the source layer SL is located between the first stacked structure 610 and the second stacked structure 620" can be understood as follows: the source layer SL is placed within a dielectric layer of a stacked structure, and the source layer SL divides the stacked structure into the first stacked structure 610 and the second stacked structure 620. Alternatively, it can be understood as the source layer SL being placed between the first stacked structure 610 and the second stacked structure 620.

[0182] In this embodiment, the first gate isolation structure 630 extends along the first direction X through the first stacked structure 610, the source layer SL, and the second stacked structure 620. Since the connection portion 631 of the first gate isolation structure 630 is used to connect the first bit line BL-1 and the second bit line BL-2, the connection portion 631 of the first gate isolation structure 630 is insulated from the source layer to enable the semiconductor device 600 to operate normally.

[0183] In some embodiments, such as Figure 5 As shown, the channel structure 410 includes a channel layer 411 and a functional layer 412, with the functional layer 412 surrounding a portion of the channel layer 411. The channel layer 411 can be made of a semiconductor material, including but not limited to amorphous silicon, polycrystalline silicon, or monocrystalline silicon. The movement or cessation of charge carriers (electrons or holes) within the channel layer 411 can be controlled by the voltage provided by the first gate layer 611 or the second gate layer 621.

[0184] Functional layer 412 is disposed around a portion of channel layer 411. Functional layer 412 may include a tunneling layer 4121, a storage layer 4122, and a barrier layer 4123 disposed sequentially in a direction away from channel layer 411. Carriers in channel layer 411 can tunnel through tunneling layer 4121 into storage layer 4122, storage layer 4122 is configured to store carriers, and barrier layer 4123 is configured to prevent carrier overflow.

[0185] The material of the tunneling layer 4121 may be, but is not limited to, one or more combinations of silicon oxide and silicon oxynitride. In some examples, the tunneling layer 4121 may be a single-layer dielectric, such as a silicon oxide layer. In other examples, the tunneling layer 4121 may be a composite dielectric layer, such as a stacked structure of a first silicon oxide layer, a first silicon oxynitride layer, a second silicon oxynitride layer, and a second silicon oxide layer.

[0186] The material of the barrier layer 4123 may include one or more combinations of silicon oxide, silicon nitride, and high dielectric constant materials. In some examples, the barrier layer 4123 may be a single-layer dielectric, such as a silicon oxide layer. In other examples, the barrier layer 4123 may be a composite dielectric layer, such as a stacked structure of silicon nitride and aluminum oxide layers.

[0187] The storage layer 4122 is configured to store charge carriers. The material of the storage layer 4122 may include silicon nitride, or other suitable materials for storing charge carriers, which are not limited here.

[0188] In this embodiment, the channel layer 411 penetrates the first stacked structure 610, the source layer SL, and the second stacked structure 620 along the first direction X, and is in contact with the source layer SL, so that the source layer SL can apply a voltage to the channel layer 411. The functional layer 412 includes a first portion 4124 and a second portion 4125 located on opposite sides of the source layer SL. The first portion 4124 penetrates the first stacked structure 610 and is in contact with the source layer SL, and the second portion 4125 penetrates the second stacked structure 620 and is in contact with the source layer SL. Here, it can be understood that the source layer SL divides the functional layer 412 into the first portion 4124 and the second portion 4125.

[0189] In this embodiment, the semiconductor device 600 can increase the number of stacked layers in the first stacked structure 610 or the second stacked structure 620, thereby increasing the length of the channel structure 410 in the first direction X and improving the storage capacity of the channel structure 410. The source layer SL is located between the first stacked structure 610 and the second stacked structure 620, and is connected to the channel layer 411. Through this arrangement, while increasing the storage capacity of the channel structure 410, the problem of weak current intensity in the channel structure 410 due to the increased length of the channel structure 410 can be mitigated.

[0190] Since the connection portion 631 is conductive, when the connection portion 631 passes through the first stacked structure 610 and the second stacked structure 620, if the connection portion 631 is connected to the first gate layer 611 or the second gate layer 621, the semiconductor device 600 will not be able to work properly.

[0191] Based on this, in some embodiments, reference is made to Figure 5The first gate isolation structure 630 also includes an isolation layer 636. The isolation layer 636 is located between the connection portion 631 and the first gate layer 611, and the isolation layer 636 is also located between the connection portion 631 and the second gate layer 621.

[0192] For example, the constituent materials of the insulating layer 636 may include an insulating material. The insulating material may include one or a combination of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating materials, or may be other suitable insulating materials.

[0193] An isolation layer 636 is disposed around the connection portion 631 in a plane parallel to the second direction Y and the third direction Z. Exemplarily, the isolation layer 636 may cover the peripheral surface of the connection portion 631, which helps to prevent the connection portion 631 from communicating with the first gate layer 611 and the second gate layer 621, so as to enable the semiconductor device 600 to operate normally and improve the storage stability of the semiconductor device 600.

[0194] Currently, users are seeking high-capacity, small-size 3D storage devices. Please refer to [link / reference]. Figure 1 To increase the capacity of the 3D memory 10, the number of stacked gate lines G increases. However, each gate line G is connected to a gate contact G-CNT. As the number of gate line G layers increases, the number of gate contacts G-CNTs coupled to the gate line G also increases, resulting in an increase in the space occupied by the gate contacts G-CNTs. This leads to an increase in the size of the 3D memory in the third direction Z, which is not conducive to improving the storage density of the 3D memory 10 and hinders the development of the 3D memory 10 to a smaller size.

[0195] Based on this, in some embodiments, such as Figure 12 and Figure 13 As shown, the semiconductor device 600 also includes a plurality of third connection structures 650, which are located on one side of the first stacked structure 610 and the second stacked structure 620. One third connection structure 650 is connected to at least one first gate layer 611, and one third connection structure 650 is connected to at least one second gate layer 621.

[0196] It should be noted that, Figure 13 It's a composite image. Figure 13 The left side of the middle dashed line is Figure 12 Cross-sectional view of BB in the middle. Figure 13 The right side of the middle dashed line is Figure 12 Cross-sectional view of CC.

[0197] In this embodiment, reference Figure 12 and Figure 13The semiconductor device 600 may include a first region 101 and a second region 102 adjacent to each other along a third direction Z. A first stacked structure 610 and a second stacked structure 620 may both be located in the first region 101, and a third connection structure 650 may be located in the second region 102. The third connection structure 650 is connected to at least one first gate layer 611, which can be understood as the third connection structure 650 being connected to one first gate layer 611, or the third connection structure 650 being connected to multiple first gate layers 611. The third connection structure 650 is connected to at least one second gate layer 621, which can be understood as the third connection structure 650 being connected to one second gate layer 621, or the third connection structure 650 being connected to multiple second gate layers 621. This disclosure uses the connection of the third connection structure 650 to one first gate layer 611 and to one second gate layer 621 as examples for explanation and illustration.

[0198] For example, the constituent material of the third connection structure 650 may include a conductive material. The conductive material includes, but is not limited to, one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicides, or other suitable conductive materials.

[0199] In this embodiment, a third connection structure 650 can be connected to a first gate layer 611 in the first stacked structure 610 and a second gate layer 621 in the second stacked structure 620. Furthermore, the third connection structure 650 can be connected to the peripheral interconnect layer 130 to enable the transmission of electrical signals between the first gate layer 611, the second gate layer 621, and the peripheral interconnect layer 130. Exemplarily, the third connection structure 650 can be connected to the peripheral interconnect layer 130 via contacts. In this embodiment, a first gate layer 611 and a second gate layer 621 can share a single third connection structure 650. Compared to the one-to-one connection between the first gate layer 611 and gate line contacts G-CNTs, and the one-to-one connection between the second gate layer 621 and gate line contacts G-CNTs, the number of third connection structures 650 is less than the number of gate line contacts G-CNTs. Therefore, the space occupied by the third connection structure 650 is less than the space occupied by the gate line contacts G-CNTs, which is beneficial for improving the storage density of the semiconductor device 600 and for the miniaturization of the semiconductor device 600.

[0200] Furthermore, this solution offers strong scalability. For example, when the semiconductor device 600 includes more stacked structures, such as 4, 6, or 8 stacked structures, the third connection structure 650 can be connected to a gate layer in each stacked structure. Through this configuration, even with the addition of more stacked structures, the number of third connection structures 650 and their occupied space will not increase, which is beneficial for improving the storage density of the semiconductor device 600 and for its development towards larger capacity and smaller size.

[0201] In some embodiments, such as Figure 13 As shown, the third connection structure 650 includes: a connection post 651, at least one first connection layer 652, and at least one second connection layer 653. The connection post 651 extends along a first direction X. The first connection layer 652 is parallel to a second direction Y, and one first connection layer 652 connects the connection post 651 and a first gate layer 611. The second connection layer 653 is parallel to the second direction Y, and one second connection layer 653 connects the connection post 651 and a second gate layer 621.

[0202] In this embodiment, in the YZ plane, the first connection layer 652 can be disposed around and connected to the connection post 651. A first connection layer 652 is used to connect the connection post 651 and a first gate layer 611, as can be seen from [reference needed]. Figure 8 In this embodiment, the first gate layer 611 may also extend along a third direction Z, for example, the first gate layer 611 may extend along a third direction Z to the second region 102, while the first connection layer 652 may extend along the second direction Y and the third direction Z. The first connection layer 652 located in the second region 102 may be connected to the portion of the first gate layer 611 extending into the second region 102. That is, the first connection layer 652 and the first gate layer 611 may be connected in the second direction Y. It should be noted that the first connection layer 652 is used to connect the first gate layer 611 and the connection post 651. The specific connection method between the first connection layer 652 and the first gate layer 611 includes, but is not limited to, the connection method provided in this embodiment, and this disclosure does not limit it.

[0203] Please refer to Figure 12 and Figure 13 In the YZ plane, the cross-section of the connecting post 651 can be, for example, circular, and the cross-section of the first connecting layer 652 can be, for example, annular. The first connecting layer 652 can be arranged around the connecting post 651 and connected to the connecting post 651. The outer edge of the first connecting layer 652 can be connected to the first gate layer 611.

[0204] Similarly, in the YZ plane, the second connection layer 653 can be disposed around and connected to the connection post 651. One second connection layer 653 connects the connection post 651 and a second gate layer 621. The second gate layer 621 can extend along the third direction Z to the second region 102, while the second connection layer 653 is parallel to both the second direction Y and the third direction Z. The second connection layer 653 can be connected to the portion of the second gate layer 621 extending into the second region 102; for example, the second connection layer 653 and the second gate layer 621 can be connected in the second direction Y. It should be noted that the second connection layer 653 is used to connect the second gate layer 621 and the connection post 651. The specific connection methods between the second connection layer 653 and the second gate layer 621 include, but are not limited to, the connection methods provided in this embodiment, and this disclosure does not limit them.

[0205] In the YZ plane, the cross-section of the connecting post 651 can be, for example, circular, and the cross-section of the second connecting layer 653 can be, for example, annular. The second connecting layer 653 can be disposed around the connecting post 651 and connected to the connecting post 651. The outer edge of the second connecting layer 653 can be connected to the second gate layer 621.

[0206] It should be noted that the third connection structure 650 includes at least one first connection layer 652 and at least one second connection layer 653. This can be understood as the third connection structure 650 including one first connection layer 652, or multiple first connection layers 652; the third connection structure 650 including one second connection layer 653, or multiple second connection layers 653. When the third connection structure 650 includes multiple first connection layers 652, the multiple first connection layers 652 can be spaced apart along the first direction X; when the third connection structure 650 includes multiple second connection layers 653, the multiple second connection layers 653 can be spaced apart along the first direction X. The embodiments described herein use a third connection structure 650 including one first connection layer 652 and one second connection layer 653 as an example for explanation.

[0207] In this embodiment, the first connection layer 652 connects the first gate layer 611 to the connection post 651, and the second connection layer 653 connects the second gate layer 621 to the connection post 651. The connection post 651 connects to the peripheral interconnect layer 130 to enable the transmission of electrical signals between the first gate layer 611, the second gate layer 621, and the peripheral interconnect layer 130. With this configuration, one first gate layer 611 and one second gate layer 621 in this embodiment can share a single third connection structure 650. Compared to the one-to-one connection between the first gate layer 611 and the gate line contacts G-CNTs, and the one-to-one connection between the second gate layer 621 and the gate line contacts G-CNTs, the number of third connection structures 650 is less than the number of gate line contacts G-CNTs. Therefore, the space occupied by the third connection structure 650 is less than the space occupied by the gate line contacts G-CNTs, which is beneficial for improving the storage density of the semiconductor device 600 and for the miniaturization of the semiconductor device 600.

[0208] Furthermore, this solution offers strong scalability. For example, when the semiconductor device 600 includes more stacked structures, such as 4, 6, or 8 stacked structures, the third connection structure 650 can connect to a gate layer in each stacked structure by increasing the number of connection layers, such as adding a third, fourth, or fifth connection layer. Through this configuration, even with more stacked structures, the number of third connection structures 650 does not increase, nor does the space occupied by the third connection structures 650 increase. This is beneficial for improving the storage density of the semiconductor device 600 and for its development towards larger capacity and smaller size.

[0209] In this embodiment, the first gate layer 611 furthest from the second stacked structure 620 among the plurality of first gate layers 611 can be set as the bottom select gate of the first stacked structure 610, and the first gate layer 611 closest to the second stacked structure 620 among the plurality of first gate layers 611 can be set as the top select gate of the first stacked structure 610. With the above settings, the semiconductor device 600 can further select to read or write to the memory node of the first stacked structure 610 through the top select gate and the bottom select gate of the first stacked structure 610.

[0210] Similarly, the second gate layer 621 furthest from the first stacked structure 610 among the plurality of second gate layers 621 can be set as the top select gate of the second stacked structure 620, and the second gate layer 621 closest to the first stacked structure 610 among the plurality of second gate layers 621 can be set as the bottom select gate of the second stacked structure 620. With the above settings, the semiconductor device 600 can further select the memory node of the second stacked structure 620 for reading or writing through the top select gate and the bottom select gate of the second stacked structure 620.

[0211] Similarly, if more stacked structures are formed, top select gates and bottom select gates can be set in multiple gate layers of the stacked structure to select a memory node in a certain stacked structure.

[0212] In some embodiments, such as Figure 13 As shown, the connecting post 651, the first connecting layer 652, and the second connecting layer 653 are an integral structure. This can be understood as the connecting post 651, the first connecting layer 652, and the second connecting layer 653 being manufactured in a single process step. This enhances the stability of the electrical connection between the connecting post 651 and the first connecting layer 652, and also enhances the stability of the electrical connection between the connecting post 651 and the second connecting layer 653.

[0213] In some embodiments, such as Figure 13 As shown, the semiconductor device 600 further includes a third stacked structure 670 and a fourth stacked structure 680 stacked along a first direction X. The third stacked structure 670 and the fourth stacked structure 680 are located on one side of the first stacked structure 610 and the second stacked structure 620 along a third direction Z.

[0214] For example, the third stack structure 670 and the fourth stack structure 680 may be located in the second region 102.

[0215] The third stack structure 670 includes a third dielectric layer 671 and a fourth dielectric layer 672 alternately stacked along the first direction X. That is, the third dielectric layer 671 and the fourth dielectric layer 672 alternately stacked along the first direction X form a plurality of third dielectric layers 671 and a plurality of fourth dielectric layers 672 spaced apart from each other.

[0216] Understandably, the third stack structure 670 is adjacent to the first stack structure 610 along the third direction Z. When the first stack structure 610 includes multiple sub-stack structures, the third stack structure 670 may also include multiple sub-stack structures accordingly.

[0217] The fourth stacking structure 680 includes a fifth dielectric layer 681 and a sixth dielectric layer 682 that are alternately stacked along the first direction X. That is, the fifth dielectric layer 681 and the sixth dielectric layer 682 that are alternately stacked along the first direction X form a plurality of fifth dielectric layers 681 and a plurality of sixth dielectric layers 682 that are spaced apart from each other.

[0218] Understandably, the fourth stack structure 680 may be adjacent to the second stack structure 620 along the third direction Z. When the second stack structure 620 includes multiple sub-stack structures, the fourth stack structure 680 may also correspondingly include multiple sub-stack structures.

[0219] The connecting post 651 extends through the third stacked structure 670 and the fourth stacked structure 680 along the first direction X. At least one third dielectric layer 671 is connected to at least one first interconnect layer 652, and at least one fifth dielectric layer 681 is connected to at least one second interconnect layer 653. Here, the first interconnect layer 652 connected to the third dielectric layer 671 can be connected to the first gate layer 611, and the second interconnect layer 653 connected to the fifth dielectric layer 681 can be connected to the second gate layer 621.

[0220] Exemplarily, the third dielectric layer 671 can be connected to the first gate layer 611, and the fourth dielectric layer 672 can be connected to the first dielectric layer 612. Furthermore, the fourth dielectric layer 672 can be made of the same material as the first dielectric layer 612, and further, the fourth dielectric layer 672 can be disposed in the same layer as the first dielectric layer 612. "Same layer" refers to multiple patterns on the same pattern layer, where the pattern layer is a film layer formed through a single patterning process. A patterning process is a process capable of forming at least one pattern of a certain shape. For example, a thin film is formed on a substrate using any of various film deposition processes such as deposition, coating, or sputtering, and then the thin film is patterned to form a film layer containing at least one pattern, referred to as a pattern layer. The patterning steps include: coating photoresist, exposure, development, etching, and photoresist stripping. In this embodiment, the positional relationship of multiple patterns belonging to the same pattern layer is referred to as "same layer".

[0221] For example, the fifth dielectric layer 681 can be connected to the second gate layer 621, and the sixth dielectric layer 682 can be connected to the second dielectric layer 622. Furthermore, the sixth dielectric layer 682 can be made of the same material as the second dielectric layer 622, and further, the sixth dielectric layer 682 can be disposed in the same layer as the second dielectric layer 622. For example, the first dielectric layer 612, the second dielectric layer 622, the fourth dielectric layer 672, and the sixth dielectric layer 682 are all made of oxides, while the third dielectric layer 671 and the fifth dielectric layer 681 are both made of nitrides.

[0222] refer to Figure 1The process of forming G-CNTs is quite challenging because each G-CNT needs to penetrate to a different gate layer.

[0223] In this embodiment, the connecting post 651 of the third connection structure 650 penetrates the third stacked structure 670 and the fourth stacked structure 680. Compared with penetrating G-CNTs to different gate layers, the process difficulty of fabricating the third connection structure 650 is lower. Therefore, it is beneficial to reduce the process difficulty of fabricating the semiconductor device 600 and improve the fabrication efficiency of the semiconductor device 600.

[0224] In some embodiments, such as Figure 13 As shown, the source layer SL is located between the third stack structure 670 and the fourth stack structure 680, and the connecting post 651 penetrates the source layer SL. The third connection structure also includes a first isolation layer 654, which surrounds the connecting post 651 and is located between the connecting post 651 and the source layer SL. The first isolation layer 654 can cover the peripheral surface of the connecting post 651, isolating the connecting post 651 from the source layer SL and preventing electrical connection between the connecting post 651 and the source layer SL. This helps protect the normal operation of the semiconductor device 600 and improves the storage stability of the semiconductor device 600.

[0225] In some embodiments, such as Figure 13 As shown, the third connection structure 650 also includes a second isolation layer 655 and a third isolation layer 656. The second isolation layer 655 is located on the side of the first connection layer 652 closest to the second connection layer 653, and it surrounds the connection post 651. For example, the second isolation layer 655 can cover the peripheral surface of the connection post 651 to isolate the connection post 651, preventing leakage current between the connection post 651 and other conductive structures, thus improving the storage stability of the semiconductor device 600.

[0226] Furthermore, the third isolation layer 656 is located on the side of the second connection layer 653 away from the first connection layer 652, and the third isolation layer 656 is disposed around the connection post 651. For example, the third isolation layer 656 can cover the peripheral surface of the connection post 651 to isolate the connection post 651 and prevent leakage current from occurring between the connection post 651 and other conductive structures, which is beneficial to improving the storage stability of the semiconductor device 600.

[0227] In some embodiments, such as Figure 13As shown, the dimension of the end of the second insulating layer 655 away from the first connecting layer 652 in the second direction Y is greater than the dimension of the end of the second insulating layer 655 near the first connecting layer 652 in the second direction Y. In the second direction Y, the second insulating layer 655 has a certain thickness, and the thickness of the end of the second insulating layer 655 near the connecting post 651 can be greater than the thickness of the end of the second insulating layer 655 near the first connecting layer 652. This is beneficial for further improving the isolation effect on the end of the connecting post 651 near the connecting post 651.

[0228] See also Figure 13 In the second direction Y, the third isolation layer 656 has a certain thickness, and the thickness of the end of the third isolation layer 656 away from the connecting post 651 can be greater than the thickness of the end of the third isolation layer 656 near the connecting post 651. This is beneficial to further improve the isolation effect of the third isolation layer 656 on the end of the connecting post 651 away from the connecting post 651.

[0229] For example, the constituent materials of the second insulating layer 655 and the third insulating layer 656 may include insulating materials. The insulating material may be, for example, one or more combinations of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other insulating materials. The constituent materials of the second insulating layer 655 and the third insulating layer 656 may be the same or different.

[0230] In some embodiments, reference Figure 13 The third connection structure 650 further includes a fourth isolation layer 657 and a fifth isolation layer 658. The fourth isolation layer 657 may be disposed around the connection post 651, and the fourth isolation layer 657 is located between the connection post 651 and the first gate layer 611. By providing the fourth isolation layer 657, the connection post 651 is isolated from the first gate layer 611, enabling the semiconductor device 600 to operate normally and improving the storage stability of the semiconductor device 600.

[0231] The fifth isolation layer 658 may be disposed around the connection post, and the fifth isolation layer 658 is located between the connection post 651 and the second gate layer 621. By providing the fifth isolation layer 658, the connection post 651 and the second gate layer 621 are isolated, enabling the semiconductor device 600 to operate normally and improving the storage stability of the semiconductor device 600.

[0232] In some embodiments, such as Figure 12 and Figure 13As shown, the first stacked structure 610 and the second stacked structure 620 can constitute the first region 101, and the third stacked structure 670 and the fourth stacked structure 680 constitute the second region 102. The semiconductor device 600 also includes a second gate isolation structure 6302. The second gate isolation structure 6302 penetrates the third stacked structure 670 and the fourth stacked structure 680 along a first direction X, and penetrates the second region 102 along a third direction Z.

[0233] For example, there may be multiple second gate isolation structures 6302. Multiple second gate isolation structures 6302 are spaced apart along a second direction Y. One second gate isolation structure 6302 and a plurality of adjacent first gate isolation structures 630 are located in the same row.

[0234] With the above configuration, the second gate isolation structure 6302 can isolate different memory blocks 103 (reference). Figure 8 The corresponding second zone 102 is isolated to prevent electrical signal interference between different storage blocks 103, thereby improving the storage stability of the semiconductor device 600.

[0235] In some embodiments, such as Figure 14 As shown, the first stacked structure 610, the source layer SL, and the second stacked structure 620 together constitute a repeating structure 690. There can be multiple repeating structures 690, which are stacked along a first direction X. The source layers SL in the multiple repeating structures 690 can be interconnected to facilitate electrical signal transmission between them.

[0236] It should be noted that the number of stacking layers of multiple repeating structures 690 can be the same or different. It can be understood that the number of stacking layers of multiple first stacking structures 610 can be the same or different, and the number of stacking layers of multiple second stacking structures 620 can be the same or different. This disclosure does not impose any restrictions on this.

[0237] In some embodiments, such as Figure 12 , Figure 13 and Figure 14 As shown, the semiconductor device 600 also includes a peripheral circuit layer 660. The peripheral circuit layer 660 is located on the side of the first line BL-1 away from the first stack structure 610, and the peripheral circuit layer 660 is connected to the first line BL-1.

[0238] For example, the peripheral circuit layer 660 may include at least one layer of circuit structure, which, through the circuit structure (e.g., metal wiring) and other interconnect structures, enables coupling with device structures such as the channel structure 410, the first bit line BL-1 (or the second bit line BL-2), and the third connection structure 650, to achieve electrical signal transmission between the peripheral circuit layer 660 and other device structures. The peripheral circuit layer 660 may also include an interlayer dielectric to isolate the circuit structure. The interlayer dielectric may be made of a dielectric material. Dielectric materials include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0239] With the above configuration, the peripheral circuit layer 660 can transmit electrical signals between the first bit line BL-1 and the second bit line BL-2.

[0240] Among the multiple repeating structures 690, the repeating structure 690 located at the top or bottom is electrically connected to the peripheral circuit layer 660. That is, the multiple repeating structures 690 can share a single peripheral circuit layer 660, thereby enabling operations such as storage or retrieval of the channel structure 410 in the multiple repeating structures 690.

[0241] This disclosure also provides a method for fabricating a semiconductor device in some embodiments, which are described below in conjunction with... Figures 15-21 This paper explains the fabrication method of a semiconductor device.

[0242] Figure 15 This is a flowchart illustrating a method for fabricating a semiconductor device according to some embodiments. Figure 15 As shown, some embodiments of this disclosure provide a method for preparing a storage device, including: S1 to S4.

[0243] S1. Form a first stacked structure and a second stacked structure that are stacked along a first direction.

[0244] In this step, refer to Figure 16 A first stacked structure 710 can be formed on a semiconductor layer. The first region 101 of the first stacked structure 710 includes a plurality of first sacrificial layers 711 and a plurality of first dielectric layers 612 alternately stacked along a first direction X. The first region 101 of the first stacked structure 710 is adjacent to the second region 102 of the first stacked structure 710.

[0245] For example, a first dielectric layer 612 and a first sacrificial layer 711 can be alternately formed on the semiconductor layer 300 by a deposition process. The deposition process includes, but is not limited to, one or more thin film deposition processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0246] The semiconductor layer 300 may include silicon (e.g., monocrystalline silicon, polycrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), and / or any other suitable semiconductor material.

[0247] The constituent materials of the first dielectric layer 612 and the first sacrificial layer 711 may include insulating materials, which may include one or more of silicon oxide, silicon nitride, silicon oxynitride and high dielectric constant insulating materials, or other suitable insulating materials.

[0248] Since the first sacrificial layer 711 needs to be removed in subsequent preparation steps, the composition of the first sacrificial layer 711 needs to be different from that of the first dielectric layer 612 to prevent damage to the first dielectric layer 612 during the removal of the first sacrificial layer 711. This embodiment uses silicon oxide as the composition of the first dielectric layer 612 and silicon nitride as the composition of the first sacrificial layer 711 as an example for explanation.

[0249] refer to Figure 16 After forming the first stacked structure 710, a portion of the first stacked structure 710 is removed to form a first channel hole 751 and a first gate slit 761. Both the first channel hole 751 and the first gate slit 761 penetrate the first region 101 of the first stacked structure 710. The first gate slit 761 is located on one side of the first channel hole 751 along the second direction Y.

[0250] In this step, the first channel via 751 and the first gate slit 761 can be formed by any suitable process. For example, a patterned photoresist layer can be formed on the first stacked structure 710. The patterned photoresist layer can expose the portions of the first stacked structure 710 used to form the first channel via 751 and the first gate slit 761. A suitable etching process can be performed to remove the portions of the first stacked structure 710 used to form the first channel via 751 and the first gate slit 761. For example, the etching process may include a dry etching process.

[0251] After forming the first channel hole 751 and the first gate slit 761, the patterned photoresist layer on the first stacked structure 710 can be removed, for example, by planarizing the surface of the first stacked structure 710 by chemical mechanical polishing (CMP) to remove the patterned photoresist layer on the first stacked structure 710.

[0252] After removing the patterned photoresist layer on the first stacked structure 710, a deposition process can be used to fill the first channel via 751 and the first gate slit 761 with a sacrificial material, such as carbon, so that a second sacrificial layer 730 can be formed on the first stacked structure 710 in subsequent fabrication steps.

[0253] It should be noted that, in order to facilitate the determination of the location of the first channel hole 751, a structural post 740 can be formed on the semiconductor layer before the first stacked structure 710 is formed. When the first channel hole 751 is subsequently formed, the first channel hole 751 can penetrate through the first stacked structure 710 to the structural post 740, so as to facilitate the determination of the location of the first channel hole 751.

[0254] refer to Figure 16 After forming the first channel hole 751 and the first gate slit 761, a second sacrificial layer 730 is formed on the first stacked structure 710, and the second sacrificial layer 730 and the first stacked structure 710 are stacked together along the first direction X.

[0255] In this step, a second sacrificial layer 730 can be formed on the first stacked structure 710 by employing one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD. For example, the material of the second sacrificial layer 730 can be polycrystalline silicon.

[0256] refer to Figure 16 After forming the second sacrificial layer 730, a second stacked structure 720 is formed on the second sacrificial layer 730. The second stacked structure 720 is located on the side of the second sacrificial layer 730 away from the first stacked structure 710. The first region of the second stacked structure 720 includes a plurality of third sacrificial layers 721 and a plurality of second dielectric layers 622 alternately stacked in the first direction X. The first region 101 of the second stacked structure 720 is adjacent to the second region 102 of the second stacked structure 720.

[0257] In this step, a second dielectric layer 622 and a third sacrificial layer 721 can be alternately formed on the second sacrificial layer 730 by employing one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD.

[0258] The constituent materials of the second dielectric layer 622 and the third sacrificial layer 721 may include insulating materials, which may include one or more of silicon oxide, silicon nitride, silicon oxynitride and high dielectric constant insulating materials, or other suitable insulating materials.

[0259] Since the third sacrificial layer 721 needs to be removed in subsequent preparation steps, the composition of the third sacrificial layer 721 must be different from that of the second dielectric layer 622 to prevent damage to the second dielectric layer 622 during the removal of the third sacrificial layer 721. This embodiment uses silicon oxide as the composition of the second dielectric layer 622 and silicon nitride as the composition of the third sacrificial layer 721 as an example for explanation.

[0260] Continue to refer to Figure 16 After forming the second stacked structure 720, a portion of the second stacked structure 720 and the second sacrificial layer 730 are removed to form a second channel via 752 and a second gate slit 762. The second channel via 752 is connected to the first channel via 751, and the second channel via 752 and the first channel via 751 together constitute the channel via 750. The second gate slit 762 is connected to the first gate slit 761, and the second gate slit 762 and the first gate slit 761 together constitute the gate slit 760.

[0261] In this step, for example, a dry etching process can be used to remove a portion of the second stacked structure 720 and a portion of the second sacrificial layer 730 to form a second channel via 752 and a second gate slit 762. The second channel via 752 penetrates the second stacked structure 720 and the second sacrificial layer 730, and is connected to the first channel via 751. The first channel via 751 and the second channel via 752 together constitute the channel via 750. The second gate slit 762 penetrates the second stacked structure 720 and the second sacrificial layer 730, and is connected to the first gate slit 761. The first gate slit 761 and the second gate slit 762 together constitute the gate slit 760.

[0262] After forming the second channel aperture 752 and the second gate slit 762, the sacrificial material in the first channel aperture 751 and the first gate slit 761 can be removed. For example, when the sacrificial material comprises carbon, the process of removing the sacrificial material located within the first channel aperture 751 and the first gate slit 761 may include ashing to remove all the sacrificial material within the first channel aperture 751 and the first gate slit 761.

[0263] In other embodiments, please refer to Figure 17 The step of forming the first stacked structure 710 may include: forming a first sub-stacked structure 7101.

[0264] In this step, for example, a deposition process can be used to alternately form a first dielectric layer 612 and a first sacrificial layer 711 on a semiconductor layer to form a first sub-stack structure 7101.

[0265] After forming the first sub-stack structure 7101, a portion of the first sub-stack structure 7101 is removed to form a third channel via 753 and a third gate slit 763. Both the third channel via 753 and the third gate slit 763 penetrate the first region 101 of the first sub-stack structure 7101, and the third gate slit 763 is located on one side of the third channel via 753 along the second direction Y.

[0266] In this step, refer to Figure 17 For example, a dry etching process can be used to remove part of the first sub-stack structure 7101 to form the third channel hole 753 and the third gate slit 763.

[0267] After forming the third channel hole 753 and the third gate slit 763, a deposition process can be used to fill the third channel hole 753 and the third gate slit 763 with a sacrificial material, such as carbon, so that a second sub-stack structure 7102 can be formed on the first sub-stack structure 7101 in subsequent fabrication steps.

[0268] Continue to refer to Figure 17 After forming the third channel hole 753 and the third gate slit 763, a second sub-stack structure 7102 is formed, which is stacked with the first sub-stack structure 7101 along the first direction X. The second sub-stack structure 7102 and the first sub-stack structure 7101 together constitute the first stack structure 710.

[0269] In this step, for example, a deposition process can be used to alternately form a first dielectric layer 612 and a first sacrificial layer 711 on the first sub-stack structure 7101 to form a second sub-stack structure 7102.

[0270] Continue to refer to Figure 17 After forming the second sub-layer structure 7102, a second sacrificial layer 730 can be formed on the second sub-layer structure 7102 by a deposition process. After forming the second sacrificial layer 730, a second layer structure 720 is formed. Forming the second layer structure 720 may include forming a third sub-layer structure 7201, wherein the third sub-layer structure 7201 and the second sacrificial layer 730 are stacked along a first direction X.

[0271] In this step, such as Figure 17 As shown, a deposition process can be used to alternately form a second dielectric layer 622 and a third sacrificial layer 721 on the side of the second sacrificial layer 730 away from the second sub-stacked structure 7102 to form a third sub-stacked structure 7201.

[0272] like Figure 17 As shown, after forming the third sub-stack structure 7201, the method further includes: removing a portion of the second sub-stack structure 7102, a portion of the second sacrificial layer 730, and a portion of the third sub-stack structure 7201 to form a fourth channel via 754 and a fourth gate slit 764. The fourth channel via 754 penetrates the second sub-stack structure 7102, the second sacrificial layer 730, and the third sub-stack structure 7201 to the third channel via 753. The fourth gate slit 764 penetrates the second sub-stack structure 7102, the second sacrificial layer 730, and the third sub-stack structure 7201 to the third gate slit 763.

[0273] In this step, for example, a dry etching process can be used to remove part of the second sub-stack structure 7102, part of the second sacrificial layer 730 and part of the third sub-stack structure 7201 to form the fourth channel hole 754 and the fourth gate slit 764.

[0274] After forming the fourth channel via 754 and the fourth gate slit 764, a deposition process can be used to fill the fourth channel via 754 and the fourth gate slit 764 with a sacrificial material, such as carbon, to facilitate the subsequent formation of the fourth sub-layer structure 7202 on the third sub-layer structure 7201 in subsequent fabrication steps. Furthermore, the sacrificial material filling the fourth channel via 754 and the fourth gate slit 764 can be the same as the sacrificial material filling the third channel via 753 and the third gate slit 763, which facilitates their removal in a single process step.

[0275] Please refer to Figure 18 After forming the fourth channel hole 754 and the fourth gate slit 764, the method further includes forming a fourth sub-stack structure 7202, wherein the fourth sub-stack structure 7202 and the third sub-stack structure 7201 are stacked together along the first direction X.

[0276] In this step, for example, a deposition process can be used to alternately form a second dielectric layer 622 and a third sacrificial layer 721 on the side of the third sub-stack structure 7201 away from the second sacrificial layer 730 to form a fourth sub-stack structure 7202.

[0277] Continue to refer to Figure 18 After forming the fourth sub-stack structure 7202, the method further includes: removing a portion of the fourth sub-stack structure 7202 to form a fifth channel via 755 and a fifth gate slit 765. The fifth channel via 755 penetrates the fourth sub-stack structure 7202 and connects to the fourth channel via 754. The third channel via 753, the fourth channel via 754, and the fifth channel via 755 together constitute a channel via 750. The fifth gate slit 765 penetrates the fourth sub-stack structure 7202 and connects to the fourth gate slit 764. The third gate slit 763, the fourth gate slit 764, and the fifth gate slit 765 together constitute a gate slit 760.

[0278] In this step, a dry etching process can be used to remove part of the fourth sub-layer structure 7202 to form the fifth channel via 755 and the fifth gate slit 765. Subsequently, the sacrificial material within the third channel via 753, the fourth channel via 754, the third gate slit 763, and the fourth gate slit 764 is removed. For example, when the sacrificial material includes carbon, the process for removing the sacrificial material may include ashing to remove all the sacrificial material located within the third channel via 753, the fourth channel via 754, the third gate slit 763, and the fourth gate slit 764, so that the third channel via 753, the fourth channel via 754, and the fifth channel via 755 are connected and together form the channel via 750, and the third gate slit 763, the fourth gate slit 764, and the fifth gate slit 765 are connected and together form the gate slit 760.

[0279] refer to Figure 18 and Figure 19 After the channel hole is formed, a functional layer 412 and a channel layer 411 are formed sequentially in the channel hole. The functional layer 412 and the channel layer 411 together constitute the channel structure 410. The channel structure 410 penetrates the first stacked structure 710, the second sacrificial layer 730 and the second stacked structure 720.

[0280] In this step, refer to Figure 18 and Figure 19 For example, a functional layer 412 and a channel layer 411 can be sequentially formed within the channel via 750 using one or more thin-film deposition processes, including but not limited to PVD, CVD, and ALD, with the functional layer 412 surrounding the channel layer 411. Forming the functional layer 412 within the channel via 750 includes sequentially forming a barrier layer 4123, a storage layer 4122, and a tunneling layer 4121 within the channel via 750. Exemplarily, the material of the tunneling layer 4121 can be, but is not limited to, one or more combinations of silicon oxide and silicon oxynitride. The material of the barrier layer 4123 can include one or more combinations of silicon oxide, silicon nitride, and high-dielectric-constant materials. The material of the storage layer 4122 can include silicon nitride, or other suitable materials for storing charge carriers. The material of the channel layer 411 can be, but is not limited to, amorphous silicon, polycrystalline silicon, or monocrystalline silicon.

[0281] After the channel structure 410 is formed, the second sacrificial layer 730 is replaced with the source layer SL.

[0282] refer to Figure 18 and Figure 19This step includes removing a portion of the second sacrificial layer 730 to form a first fill space 731, which exposes a portion of the functional layer 412. Exemplarily, a wet etching process, such as by injecting an etchant into the gate slit 760, can be used to remove a portion of the second sacrificial layer 730.

[0283] refer to Figure 18 , Figure 19 and Figure 20 After forming the first filling space 731, the method further includes: removing a portion of the functional layer 412 through the first filling space 731, dividing the functional layer 412 into a first part 4124 (see reference). Figure 5 Part 2 and Part 4125 (Reference) Figure 5 ), of which the first part 4124 (reference) Figure 5 ) penetrating the first stacked structure 710, the second part 4125 (reference) Figure 5 It penetrates the second stacked structure 720.

[0284] In this step, for example, a wet etching process can be used to remove the functional layer 412 exposed in the first filling space 731 by injecting an etchant into the gate slit 760 and the first filling space 731, and to expose part of the channel layer 411.

[0285] refer to Figure 18 , Figure 19 and Figure 20 After removing part of the functional layer 412 through the first filling space 731, a semiconductor material, such as polysilicon, can be filled into the first filling space 731 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a source layer SL. Furthermore, the source layer SL is connected to the channel layer 411 exposed in the first filling space 731.

[0286] It should be noted here that in the step of forming the second sacrificial layer 730, polycrystalline silicon material can be deposited using a deposition process to form the second sacrificial layer 730. This can be understood as the composition of the second sacrificial layer 730 being the same as that of the source layer SL. Therefore, after the source layer SL is formed in the first filled space 731, the source layer SL is connected to the remaining second sacrificial layer 730; at this point, the remaining second sacrificial layer 730 is also considered the source layer SL.

[0287] refer to Figure 20 and Figure 21 After forming the source layer SL, the first sacrificial layer 711 is replaced with the first gate layer 611, and the third sacrificial layer 721 is replaced with the second gate layer 621.

[0288] refer to Figure 20 and Figure 21 In this step, a wet etching process can be used to remove the first sacrificial layer 711 and the third sacrificial layer 721 through the gate slit 760. Then, a conductive material can be deposited at the location of the original first sacrificial layer 711 to form the first gate layer 611, and a conductive material can be deposited at the location of the original third sacrificial layer 721 to form the second gate layer 621. Exemplarily, the conductive material includes, but is not limited to, one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, and silicides, or other suitable conductive materials. In some examples, the constituent material of the first gate layer 611 may include a doped polysilicon layer. The polysilicon can be doped to a desired doping concentration using suitable dopant, making the polysilicon a conductive material used as the first gate layer 611.

[0289] After replacing the first sacrificial layer 711 with the first gate layer 611 and the third sacrificial layer 721 with the second gate layer 621, the first region 101 of the first stacked structure 710 constitutes the first stacked structure 610, and the first region 101 of the second stacked structure 720 constitutes the second stacked structure 620 (see reference). Figure 13 ).

[0290] The semiconductor device 600 prepared by the above method shortens the length of the channel structure 410 driven by the source layer SL in the first direction X. This can improve the problem of increased resistance and reduced voltage difference of the channel structure 410 caused by the increase in the length of the channel structure 410. It is beneficial to improve the current intensity in the channel structure 410, thereby improving the device performance such as the storage speed and response speed of the semiconductor device 600.

[0291] S2. A first gate isolation structure is formed, which extends through the first stacked structure and the second stacked structure along a first direction.

[0292] refer to Figure 20 and Figure 21 This step may include sequentially forming an isolation layer 636, a connection portion 631, and an isolation portion 632 in the gate slit 760. The isolation layer 636 is located between the connection portion 631 and the source layer SL, between the two connection portions 631 and the first gate layer 611, and between the connection portion 631 and the second gate layer 621. Furthermore, in a plane parallel to the second direction Y and the third direction Z, the isolation layer 636 is disposed around the connection portion 631, and the connection portion 631 is disposed around the isolation portion 632.

[0293] It should be noted that after filling the first filling space 731 with semiconductor material to form the source layer SL, semiconductor material will adhere to the sidewalls of the gate slit 760. To facilitate the subsequent removal of the first sacrificial layer 711 through the gate slit 760, an etching process, such as a wet etching process, can be used to remove the semiconductor material adhered to the sidewalls of the gate slit 760. In the above steps, a portion of the source layer SL will be removed. After replacing the first sacrificial layer 711 with the first gate layer 611 and the third sacrificial layer 721 with the second gate layer 621, conductive material will adhere to the sidewalls of the gate slit 760. To prevent the multiple first gate layers 611 and the multiple second gate layers 621 from communicating with each other, an etching process, such as a wet etching process, can be used to remove the conductive material adhered to the sidewalls of the gate slit 760 through the gate slit 760, and a portion of the first gate layer 611 and a portion of the second gate layer 621 will be removed along the second direction Y. Here, the size of the removed first gate layer 611 in the second direction Y is greater than the size of the removed source layer SL in the second direction Y, and the size of the removed second gate layer 621 in the second direction Y is greater than the size of the removed source layer SL in the second direction Y.

[0294] In this step, for example, an insulating material can be deposited within the gate slit 760 to form an isolation layer 636, which covers the sidewalls of the gate slit 760, using one or more thin-film deposition processes, including but not limited to PVD, CVD, and ALD. After forming the isolation layer 636, a conductive material can be deposited within the gate slit 760 to form a connection portion 631, followed by a deposition process to deposit an insulating material within the gate slit 760 to form an isolation portion 632.

[0295] S3. A first line is formed. The first line is located on the side of the first stacked structure away from the second stacked structure. The first line extends along the second direction. The first gate isolation structure extends along the third direction. The second direction intersects with the first direction. The third direction intersects with the plane containing the first direction and the second direction. One end of the first gate isolation structure along the first direction is connected to the first line.

[0296] refer to Figure 20 , Figure 21 and Figure 13In this step, for example, a first connection structure 701 can be formed by deposition at the end of the first gate isolation structure 630 away from the second stacked structure 620. One end of the first connection structure 701 along the first direction X is connected to the connection portion 631 of the first gate isolation structure 630. A first bit line BL-1 is formed by deposition on the side of the first connection structure 701 away from the first gate isolation structure 630, and the first bit line BL-1 is connected to the other end of the first connection structure 701 along the first direction X. The first bit line BL-1 can be connected to the first gate isolation structure 630 through the first connection structure 701.

[0297] S4. A second bit line is formed. The second bit line is located on the side of the second stacked structure away from the first stacked structure. The second bit line extends along the second direction. The other end of the first gate isolation structure is connected to the second bit line along the first direction.

[0298] refer to Figure 20 , Figure 21 and Figure 13 In this step, for example, a second connection structure 702 can be formed by deposition on the side of the first gate isolation structure 630 away from the first stacked structure 610. The second connection structure 702 is connected to the connection portion 631 of the first gate isolation structure 630. A second bit line BL-2 is formed by deposition on the side of the second connection structure 702 away from the first gate isolation structure 630, and the second bit line BL-2 is connected to the second connection structure 702. The first bit line BL-1 and the second bit line BL-2 are connected to the two ends of the second connection structure 702 along the first direction X, respectively. The second bit line BL-2 can be connected to the first gate isolation structure 630 through the second connection structure 702. This enables electrical signal transmission between the first bit line BL-1 and the second bit line BL-2.

[0299] The semiconductor device 600 obtained by the above preparation method connects the first bit line BL-1 and the second bit line BL-2 through the first gate isolation structure 630. This allows the first bit line BL-1 and the second bit line BL-2 to share a single circuit, reducing the number of metal lines and thus lowering the manufacturing cost.

[0300] In some embodiments, reference Figure 20 , Figure 21 and Figure 13When removing part of the stacked structure to form the channel hole 750, the connecting hole 791 can be formed simultaneously. The connecting hole 791 penetrates the second region 102 of the first stacked structure 710 and the second region 102 of the second stacked structure 720. The second region 102 of the first stacked structure 710 includes a plurality of third dielectric layers 671 and a plurality of fourth dielectric layers 672 alternately stacked along the first direction X. The second region 102 of the second stacked structure 720 includes a plurality of fifth dielectric layers 681 and a plurality of sixth dielectric layers 682 alternately stacked along the first direction X.

[0301] refer to Figure 20 , Figure 21 and Figure 13 After forming the first gate isolation structure 630 and before forming the first bit line BL-1, portions of the third dielectric layer 671 and the fifth dielectric layer 681 are removed to form a second fill space 792 and a third fill space 793. The second fill space 792 exposes at least one first gate layer 611, and the third fill space 793 exposes at least one second gate layer 621. The second fill space 792 and the third fill space 793 communicate with the connection hole 750. Conductive material is filled into the connection hole 750 to form a third connection structure 650.

[0302] In this step, part of the third and fifth dielectric layers can be removed using an etching process, such as wet etching. A deposition process can be used to fill the connection holes with conductive material to form the third connection structure. The third connection structure formed through the above steps can be connected to a first gate layer and simultaneously to a second gate layer. Compared to the one-to-one connection between the first gate layer 611 and the gate contact G-CNT, and the one-to-one connection between the second gate layer 621 and the gate contact G-CNT, the number of third connection structures 650 is less than the number of gate contact G-CNTs. Therefore, the space occupied by the third connection structure 650 is less than the space occupied by the gate contact G-CNT, which is beneficial for increasing the storage density of the semiconductor device 600 and for the miniaturization of the semiconductor device 600.

[0303] Figure 22 This is a block diagram of a storage system according to some embodiments. Figure 23 This is a block diagram of a storage system according to some other embodiments. Please refer to... Figure 22 and Figure 23 This disclosure also provides a storage system 1000 in some embodiments, which includes a controller 20 and a semiconductor device 600 provided in the above embodiments. The controller 20 is coupled to the semiconductor device 600 to control the semiconductor device 600 to store data.

[0304] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0305] In some embodiments, see Figure 22 The storage system 1000 includes a controller 20 and a semiconductor device 600, and the storage system 1000 can be integrated into a memory card. Exemplarily, the semiconductor device 600 can be a memory with a three-dimensional structure (3D NAND).

[0306] Among them, memory cards include any one of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital Memory Card (SD device) card, and UFS.

[0307] In other embodiments, see Figure 23 The storage system 1000 includes a controller 20 and multiple semiconductor devices 600, and the storage system 1000 is integrated into a solid state drive (SSD device).

[0308] In some embodiments of the storage system 1000, the controller 20 is configured to operate in a low duty cycle environment, such as an SD device card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0309] In other embodiments, the controller 20 is configured to operate in a high duty cycle environment in an SSD device or eMMC used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as in enterprise storage arrays.

[0310] In some embodiments, controller 20 may be configured to manage data stored in semiconductor device 600 and communicate with external devices (e.g., a host). In some embodiments, controller 20 may also be configured to control the operation of semiconductor device 600, such as read, erase, and program operations. In some embodiments, controller 20 may also be configured to manage various functions relating to data stored or to be stored in semiconductor device 600, including at least one of bad block management, garbage collection, logic-to-physical address translation, and wear leveling. In some embodiments, controller 20 is also configured to process error correction codes relating to data read from or written to semiconductor device 600.

[0311] Of course, controller 20 can also perform any other suitable functions, such as formatting semiconductor device 600; for example, controller 20 can communicate with external devices (e.g., hosts) through at least one of various interface protocols.

[0312] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESD Device I) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0313] The controller 20 in the above embodiments may be, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0314] In this embodiment, the storage system 1000 includes the semiconductor device 600 provided in some of the above embodiments, which is beneficial for improving the storage density of the storage system 1000 and improving the device performance such as the response speed of the storage system 1000. In addition, it can reduce the use of metal wires and reduce the manufacturing cost.

[0315] This disclosure also provides an electronic device in some embodiments. Figure 24 This is a block diagram of an electronic device according to some embodiments. For example... Figure 24 As shown, the electronic device 3000 includes a motherboard 2000 and a storage system 1000 provided in some of the above embodiments. The motherboard 2000 is electrically connected to the storage system 1000. In addition, the electronic device 3000 may also include at least one of a central processing unit (CPU) and a cache.

[0316] For example, the electronic device 3000 can be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0317] In this embodiment, the electronic device 3000 may include the storage system 1000 provided in some of the above embodiments, which is beneficial for improving the storage density of the electronic device 3000, for the development of the electronic device 3000 towards large capacity and small size, and for improving the device performance such as response speed. In addition, it can also reduce the use of metal wires and reduce manufacturing costs.

[0318] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: A first stacked structure and a second stacked structure are stacked along a first direction; The first bit line is located on the side of the first stack structure away from the second stack structure, and the first bit line extends along a second direction, which intersects the first direction. The second bit line is located on the side of the second stack structure away from the first stack structure, and the second bit line extends along the second direction; A first gate isolation structure extends along a third direction and penetrates the first stacked structure and the second stacked structure along the first direction, wherein the third direction intersects the plane containing the first direction and the second direction; The first gate isolation structure is connected to the first bit line and the second bit line at its two ends along the first direction, respectively.

2. The semiconductor device according to claim 1, characterized in that, The first gate isolation structure includes an isolation portion and a connection portion. On a plane parallel to the second direction and the third direction, the connection portion is disposed around the isolation portion, and the two ends of the connection portion along the first direction are respectively connected to the first bit line and the second bit line.

3. The semiconductor device according to claim 2, characterized in that, The dimension of the end of the connecting portion near the second bit line in the second direction is greater than the dimension of the end of the connecting portion near the first bit line in the second direction.

4. The semiconductor device according to claim 2, characterized in that, The first stacking structure includes a first sub-stack structure and a second sub-stack structure stacked along the first direction. The second stacking structure includes a third sub-stack structure and a fourth sub-stack structure stacked along the first direction. The second sub-stack structure is closer to the third sub-stack structure than the first sub-stack structure, and the third sub-stack structure is closer to the second sub-stack structure than the fourth sub-stack structure. The connecting portion includes: a first sub-part, a second sub-part, and a third sub-part stacked and connected sequentially along the first direction; the first sub-part penetrates the first sub-stack structure; the second sub-part penetrates the second sub-stack structure and the third sub-stack structure; and the third sub-part penetrates the fourth sub-stack structure; the first sub-part is connected to the first bit line, and the third sub-part is connected to the second bit line.

5. The semiconductor device according to claim 4, characterized in that, The dimension of the end of the first sub-part near the second sub-part in the second direction is greater than the dimension of the end of the second sub-part near the first sub-part in the second direction; The dimension of the end of the second sub-part near the third sub-part in the second direction is greater than the dimension of the end of the third sub-part near the second sub-part in the second direction.

6. The semiconductor device according to claim 5, characterized in that, The dimension of the end of the first sub-part closer to the second sub-part in the second direction is greater than the dimension of the end of the first sub-part farther from the second sub-part in the second direction; And / or, the dimension of the end of the second sub-part away from the first sub-part in the second direction is greater than the dimension of the end of the second sub-part near the first sub-part in the second direction; And / or, the dimension of the end of the third sub-part away from the second sub-part in the second direction is greater than the dimension of the end of the third sub-part near the second sub-part in the second direction.

7. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: A first connection structure, wherein in the first direction, the two ends of the first connection structure are respectively connected to the first bit line and the first gate isolation structure; The second connection structure, in the first direction, has its two ends connected to the second bit line and the first gate isolation structure, respectively.

8. The semiconductor device according to claim 7, characterized in that, The number of the first connection structures is multiple, and the multiple first connection structures are arranged at circumferential intervals along the first gate isolation structure.

9. The semiconductor device according to claim 7, characterized in that, The dimension of the end of the first connection structure near the first bit line in the second direction is greater than the dimension of the end of the first connection structure near the first gate isolation structure in the second direction.

10. The semiconductor device according to claim 1, characterized in that, The number of the first gate isolation structures is multiple; the multiple first gate isolation structures are arranged in multiple columns along the second direction and in multiple rows along the third direction. The number of first bit lines is multiple, and the multiple first bit lines are arranged sequentially at intervals along the third direction; one first bit line is connected to one end of one first gate isolation structure. The number of second bit lines is multiple, and the multiple second bit lines are arranged sequentially at intervals along the third direction; one second bit line is connected to the other end of one of the first gate isolation structures.

11. The semiconductor device according to claim 10, characterized in that, The first gate isolation structures in two adjacent rows are staggered upwards on the third side.

12. The semiconductor device according to claim 10, characterized in that, The semiconductor device further includes a plurality of dielectric structures, which penetrate the first stacked structure and the second stacked structure along the first direction; In the third direction, at least one of the dielectric structures is disposed between two adjacent first gate isolation structures.

13. The semiconductor device according to claim 10, characterized in that, The semiconductor device further includes: a plurality of channel structures, the channel structures extending through the first stacked structure and the second stacked structure; Multiple channel structures are arranged in multiple rows along the third direction, and multiple channel structures are arranged in multiple columns along the second direction, with adjacent rows of channel structures staggered in the third direction; Along the second direction, multiple rows of the channel structures are disposed between two adjacent rows of the first gate isolation structures; In the multiple channel structures, a first bit line is connected to at least one of the channel structures, and a second bit line is connected to at least one of the channel structures.

14. The semiconductor device according to claim 10, characterized in that, Multiple first bit lines constitute multiple first bit line groups, and each first bit line group includes at least two adjacent first bit lines. In the first direction, each of the first bit lines in the first bit line group overlaps with each of the first gate isolation structures located in the same column.

15. The semiconductor device according to claim 14, characterized in that, One of the first bit lines in the first bit line group is connected to one of the first gate isolation structures in a column of the plurality of first gate isolation structures that overlap with the first bit line group.

16. The semiconductor device according to claim 15, characterized in that, The plurality of the first gate isolation structures have the same dimensions in the third direction.

17. The semiconductor device according to claim 13, characterized in that, The semiconductor device further includes a source layer, the source layer being located between the first stacked structure and the second stacked structure; The first gate isolation structure penetrates the source layer, and the connection portion is insulated from the source layer; The channel structure penetrates the source layer and is connected to the source layer.

18. The semiconductor device according to claim 17, characterized in that, The channel structure includes a channel layer and a functional layer, wherein the functional layer is disposed around a portion of the channel layer; The channel layer penetrates the first stacked structure, the source layer, and the second stacked structure along the first direction, and is in contact with the source layer; The functional layer includes a first part and a second part located on opposite sides of the source layer. The first part penetrates the first stacked structure and contacts the source layer, and the second part penetrates the second stacked structure and contacts the source layer.

19. The semiconductor device according to claim 17, characterized in that, The first stacked structure includes a first gate layer and a first dielectric layer alternately stacked along the first direction; the second stacked structure includes a second gate layer and a second dielectric layer alternately stacked along the first direction. The first gate isolation structure further includes an isolation layer, which is located between the connection portion and the first gate layer, between the connection portion and the source layer, and between the connection portion and the second gate layer, and the isolation layer is disposed around the connection portion.

20. The semiconductor device according to claim 1, characterized in that, The first stacked structure includes a first gate layer and a first dielectric layer alternately stacked along the first direction; the second stacked structure includes a second gate layer and a second dielectric layer alternately stacked along the first direction. The semiconductor device further includes a plurality of third connection structures located on one side of the first stacked structure and the second stacked structure, one of the third connection structures being connected to at least one of the first gate layers, and one of the third connection structures being connected to at least one of the second gate layers.

21. The semiconductor device according to claim 20, characterized in that, The semiconductor structure further includes: a third stacked structure and a fourth stacked structure stacked along the first direction, the third stacked structure and the fourth stacked structure being located on one side of the first stacked structure and the second stacked structure along the third direction, the third stacked structure including a plurality of third dielectric layers and a plurality of fourth dielectric layers stacked alternately along the first direction, and the fourth stacked structure including a plurality of fifth dielectric layers and a plurality of sixth dielectric layers stacked alternately along the first direction; The third connection structure includes: a connection post, at least one first connection layer, and at least one second connection layer; the connection post extends through the third stack structure and the fourth stack structure; the first connection layer is parallel to the third direction and the second direction, the first connection layer connects the connection post and a first gate layer, and the first connection layer is connected to a third dielectric layer; the second connection layer is parallel to the third direction and the second direction, the second connection layer connects the connection post and a second gate layer, and the second connection layer is connected to a fifth dielectric layer.

22. The semiconductor device according to claim 20, characterized in that, The first stacked structure and the second stacked structure constitute a first region, and the third stacked structure and the fourth stacked structure constitute a second region, with the second region located on one side of the first region along the third direction; The semiconductor structure also includes: The second gate isolation structure extends through the third stacked structure and the fourth stacked structure along the first direction, and extends through the second region along the third direction.

23. The semiconductor device according to claim 1, characterized in that, The first stacked structure and the second stacked structure together constitute a repeating structure, and there are multiple repeating structures, which are stacked along the first direction.

24. The semiconductor device according to any one of claims 1-23, characterized in that, Also includes: The peripheral circuit layer is located on the side of the first bit line away from the first stack structure, and the peripheral circuit layer is connected to the first bit line.

25. A method for fabricating a semiconductor device, characterized in that, include: A first stacked structure and a second stacked structure are formed by stacking them along a first direction; A first gate isolation structure is formed, which extends through the first stacked structure and the second stacked structure along the first direction; A first bit line is formed, the first bit line is located on the side of the first stack structure away from the second stack structure, the first bit line extends along the second direction, the first gate isolation structure extends along the third direction, the second direction intersects the first direction, the third direction intersects the plane where the first direction and the second direction are located, and one end of the first gate isolation structure along the first direction is connected to the first bit line. A second bit line is formed, which is located on the side of the second stack structure away from the first stack structure. The second bit line extends along the second direction, and the other end of the first gate isolation structure along the first direction is connected to the second bit line.

26. The method for fabricating a semiconductor device according to claim 25, characterized in that, The formation of the first stacked structure and the second stacked structure arranged in a first direction includes: A first stacked structure is formed, wherein a first region of the first stacked structure includes a plurality of first sacrificial layers and a plurality of first dielectric layers alternately stacked along the first direction, and the first region of the first stacked structure is adjacent to a second region of the first stacked structure. A second sacrificial layer is formed, and the second sacrificial layer and the first stacked structure are stacked together along the first direction; A second stacked structure is formed, the second stacked structure is located on the side of the second sacrificial layer away from the first stacked structure, the first region of the second stacked structure includes a plurality of third sacrificial layers and a plurality of second dielectric layers alternately stacked along the first direction, and the first region of the second stacked structure is adjacent to the second region of the second stacked structure; The first sacrificial layer is replaced with the first gate layer, and the third sacrificial layer is replaced with the second gate layer.

27. The method for fabricating a semiconductor device according to claim 26, characterized in that, After the formation of the first stacked structure and before the formation of the second sacrificial layer, the method further includes: A portion of the first stacked structure is removed to form a first channel hole, the first channel hole being located in a first region of the first stacked structure; After the formation of the second stacked structure and before the formation of the channel structure, the method further includes: A portion of the second stacked structure and a portion of the second sacrificial layer are removed to form a second channel hole, the second channel hole being located in the first region of the second stacked structure, and the second channel hole and the first channel hole together constitute a channel hole; A functional layer and a channel layer are formed sequentially within the channel hole, and the functional layer and the channel layer together constitute the channel structure.

28. The method for fabricating a semiconductor device according to claim 25, characterized in that, The formation of the first stacked structure includes: Forming the first sub-layered structure; A portion of the first sub-stack structure is removed to form a third channel hole, the third channel hole being located in the first region of the first sub-stack structure; A second sub-layer structure is formed, and the second sub-layer structure is stacked with the first sub-layer structure along the first direction; The formation of the second layered structure includes: Forming a third sub-layered structure; A portion of the second sub-stack structure, a portion of the second sacrificial layer, and a portion of the third sub-stack structure are removed to form a fourth channel hole, which communicates with the third channel hole; A fourth sub-layer structure is formed, wherein the fourth sub-layer structure and the third sub-layer structure are stacked together along the first direction; A portion of the fourth sub-layer structure is removed to form a fifth channel hole, which is connected to the fourth channel hole. The third channel hole, the fourth channel hole, and the fifth channel hole together constitute a channel hole. A functional layer and a channel layer are formed sequentially within the channel hole, and the functional layer and the channel layer together constitute the channel structure.

29. The method for fabricating a semiconductor device according to claim 27 or 28, characterized in that, After the functional layer and the channel layer are sequentially formed within the channel via, and before the first sacrificial layer is replaced with the first gate layer, the method further includes: A portion of the second sacrificial layer is removed to form a first fill space, which exposes a portion of the functional layer. A portion of the functional layer is removed by filling the first space; A source layer is formed in the first filling space.

30. The method for fabricating a semiconductor device according to claim 29, characterized in that, Removing a portion of the stacked structure to form a channel aperture further includes: forming a gate slit, the gate slit being located in a first region of the first stacked structure and a first region of the second stacked structure, and the gate slit being located on one side of the channel aperture along the second direction.

31. The method for fabricating a semiconductor device according to claim 30, characterized in that, The removal of a portion of the second sacrificial layer to form the first filling space includes: A portion of the second sacrificial layer is removed through the gate slit.

32. The method for fabricating a semiconductor device according to claim 30, characterized in that, The formation of the first gate isolation structure includes: An isolation layer, a connection portion, and an isolation portion are sequentially formed within the gate slit. The isolation layer is located between the connection portion and the source layer, between the first stacked structure and the connection portion, and between the second stacked structure and the connection portion. The isolation layer is disposed around the connection portion. The connection portion is disposed around the isolation portion on a plane parallel to the second direction and the third direction.

33. The method for fabricating a semiconductor device according to claim 32, characterized in that, After forming the first gate isolation structure and before forming the first bit line, the method further includes: A first connection structure is formed, and one end of the first connection structure along the first direction is connected to the first gate isolation structure; The formation of the first line includes: Connect the first bit line to the other end of the first connection structure along the first direction; After the formation of the first bit line and before the formation of the second bit line, the method further includes: A second connection structure is formed, and one end of the second connection structure along the first direction is connected to the first gate isolation structure; The formation of the second bit line includes: The second bit line is connected to the other end of the second connection structure along the first direction.

34. The method for fabricating a semiconductor device according to claim 30, characterized in that, Removing part of the stacked structure to form a channel hole also includes: A connecting hole is formed, which penetrates the second region of the first stacked structure and the second region of the second stacked structure. The second region of the first stacked structure includes a plurality of third dielectric layers and a plurality of fourth dielectric layers that are alternately stacked along the first direction. The second region of the second stacked structure includes a plurality of fifth dielectric layers and a plurality of sixth dielectric layers that are alternately stacked along the first direction. After forming the first gate isolation structure and before forming the first bit line, the method further includes: Partial removal of the third dielectric layer and the fifth dielectric layer to form a second fill space and a third fill space, the second fill space exposing at least one of the first gate layer, the third fill space exposing at least one of the second gate layer, the second fill space communicating with the connection hole, and the third fill space communicating with the connection hole; The connection hole is filled with conductive material to form a third connection structure.

35. A storage system, characterized in that, include: The semiconductor device as described in any one of claims 1-24; A controller is coupled to the semiconductor device to control the semiconductor device to store data.

36. An electronic device, characterized in that, Includes a motherboard and a storage system as described in claim 35 disposed on the motherboard.

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