Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof, and the semiconductor structure comprises a driving chip which comprises a first top surface and a first bottom surface which are oppositely disposed, and the first top surface is provided with a first bonding pad; the logic chip comprises a second top surface and a second bottom surface which are oppositely arranged, and the second top surface is provided with a second bonding pad; and the driving chip and the logic chip are bonded through the first bonding pad and the second bonding pad. Through bonding, the conductive columns and the rewiring layer, the bonding interfaces of the driving chip and the logic chip are in gap connection, and the transmission path between the driving chip and the logic chip is shortened.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, in particular, to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] Display Driver IC (DDIC) is the core chip of modern display technologies such as LCD, OLED, Micro-LED, etc., mainly responsible for converting digital image signals into electrical signals to control pixel points. In terms of market size, the DDIC industry has shown strong development momentum. However, with the development of technology, the process upgrade of its core modules is facing severe challenges. The core functional modules of DDIC mainly include TCON (Timing Controller), Source Driver / Data Driver, Gate Driver / Scan Driver, and Power Management Module. These modules are the key components of DDIC to realize signal processing, pixel driving, and power control. With the continuous improvement of the resolution of display panels, the number of pixel points presents an exponential growth, and the process nodes of each core module of DDIC have to continue to advance to advanced processes. Currently, the process nodes of these modules have been upgraded from mature processes in the early stage to 28nm, and are iterating towards 22nm.

[0003] In this process, the contradiction of process cost is particularly prominent. The HV / MV (High Voltage / Medium Voltage) power driving module in DDIC is the key part to ensure the stable power supply of the display panel, but its requirements for the process are significantly different from other logic modules. In the prior art, part of the HV / MV power driving module and other logic modules (such as TCON, SRAM storage unit, etc.) are produced together using 28nm or more advanced processes. However, although advanced processes can bring certain performance benefits, using advanced processes for HV / MV power driving modules will generate additional processing costs, because advanced processes have higher process complexity, longer production flow, and greater equipment investment. SUMMARY

[0004] In view of the above problems existing in the prior art of forming a full-color display screen, the present application provides a semiconductor structure, a preparation method thereof, and a display device, which are used to solve the problems of difficulty in effectively dissipating heat of high-power devices, difficulty in achieving effective temperature uniformity, and limitation of size cost in the prior art.

[0005] To achieve the above object and other related objects, one aspect of the present application provides a semiconductor structure, which comprises:

[0006] The semiconductor structure, characterized in that it comprises:

[0007] A driving chip, comprising a first top surface and a first bottom surface arranged oppositely, wherein the first top surface is provided with a first bonding pad;

[0008] A logic chip, comprising a second top surface and a second bottom surface arranged oppositely, wherein the second top surface is provided with a second bonding pad;

[0009] The driving chip and the logic chip are bonded through the first bonding pad and the second bonding pad.

[0010] Optionally, the logic chip has a size larger than that of the driving chip, and the second top surface of the logic chip further has a bonding blank area.

[0011] Optionally, the semiconductor structure further comprises an extension end located in the bonding blank area of the logic chip.

[0012] Optionally, the driving chip comprises a high-voltage driving chip, a medium-voltage driving chip, and a low-voltage driving chip.

[0013] Optionally, the semiconductor structure further comprises a dielectric layer, wherein the dielectric layer comprises a first dielectric layer and a second dielectric layer, the first dielectric layer is located on the first top surface of the driving chip, and the second dielectric layer is located on the second top surface of the logic chip.

[0014] Optionally, the semiconductor structure further comprises a rewiring layer, wherein the rewiring layer comprises a first rewiring layer and a second rewiring layer, the first rewiring layer is located in the first dielectric layer, and the second rewiring layer is located in the second dielectric layer.

[0015] Optionally, the semiconductor structure further comprises a conductive pillar, wherein the conductive pillar comprises a first conductive pillar and a second conductive pillar, the first conductive pillar is located on the first top surface of the driving chip, the second conductive pillar is located on the second top surface of the logic chip, and the first conductive pillar and the second conductive pillar are electrically connected.

[0016] In another aspect, the application provides a method for preparing a semiconductor structure, comprising the following steps:

[0017] providing a first wafer, and preparing a plurality of driving chips on the first wafer;

[0018] providing a second wafer, and preparing a plurality of logic chips on the second wafer;

[0019] cutting the first wafer to form a plurality of driving chip dies;

[0020] bonding the plurality of driving chip dies to the second wafer;

[0021] cutting the second wafer.

[0022] Optionally, after the plurality of driving chip dies are bonded to the second wafer, a filling layer is formed by applying a filling material in the interface gap between the driving chip and the logic chip.

[0023] The semiconductor structure, the preparation method thereof and the display device provided by the application have at least the following beneficial technical effects:

[0024] In the semiconductor structure, the driving chip and the logic chip are bonded through the Cu-Cu hybrid bonding, the vertical interconnection of the conductive column and the re-wiring layer, and the transmission path is shortened. The driving chip die is bonded to the logic wafer, which breaks through the limitation of the traditional single wafer process on different modules, and more functional units can be integrated in a unit area. The expansion bonding area reserved by the logic chip can add driving channels, integrate sensor interfaces or expand storage capacity according to requirements. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 A structure diagram of the semiconductor structure provided by the application is shown.

[0026] Figures 2-5 A structure diagram of the semiconductor structure preparation method provided by the embodiment two is shown.

[0027] REFERENCE NUMERALS

[0028] 10, driving chip; 11, first top surface; 111, first bonding pad; 12, first bottom surface; 13, driving unit; 20, logic chip; 21, second top surface; 211, second bonding pad; 22, second bottom surface; 23, expansion end; 24, storage unit; 30, medium layer; 31, first medium layer; 32, second medium layer; 40, re-wiring layer; 41, first re-wiring layer; 42, second re-wiring layer; 50, conductive column 50; 51, first conductive column; 52, second conductive column; 60, filling layer. DETAILED DESCRIPTION

[0029] The embodiments of the application are described below through specific and concrete examples. Those skilled in the art can easily understand other advantages and effects of the application from the disclosure of the specification. The application can also be implemented or applied through other different specific embodiments, and each detail in the specification can be modified or changed based on different views and applications without departing from the spirit of the application.

[0030] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components, the shape, quantity, positional relationship and proportion of each component can be arbitrarily changed under the premise of realizing the technical solution of this invention, and the layout of the components may also be more complex.

[0031] Example 1

[0032] This embodiment provides a semiconductor structure, such as Figure 1 As shown, the semiconductor structure of this embodiment includes a driver chip 10 and a logic chip 20. The driver chip 10 includes a first top surface 11 and a first bottom surface 12 disposed opposite to each other. The first top surface 11 is provided with a first bonding pad 111 for realizing electrical connection and physical bonding. The logic chip 20 includes a second top surface 21 and a second bottom surface 22 disposed opposite to each other. The second top surface 21 is provided with a second bonding pad 211. The driver chip 10 and the logic chip 20 are bonded together through the first bonding pad 111 and the second bonding pad 211, realizing a tight connection and efficient signal transmission between them.

[0033] Generally, driver chips 10 are typically categorized into high-voltage (HV), medium-voltage (MV), and low-voltage (LV) driver chips based on different application scenarios and requirements. The appropriate driver chip is selected according to actual needs. Driver chip 10 includes a driver unit 13, which amplifies and converts the input signal to drive external devices or circuits to operate normally. Logic chip 20 generally includes static random access memory (SRAM), dynamic random access memory (DRAM), etc. Logic chip 20 includes storage units 24, which achieve efficient data storage and access through complex circuit design and layout.

[0034] Optionally, such as Figure 1 As shown, the size of the logic chip 20 is larger than that of the driver chip 10. This means that, in addition to the area bonded to the driver chip 10, a portion of the second top surface 21 of the logic chip 20 is reserved as an unoccupied area, namely the bonding blank area. The bonding blank area provides the possibility for further expansion of the semiconductor structure and enhancement of its functions.

[0035] Optionally, the semiconductor structure also includes an extension terminal 23, which is located in the bonding blank area of ​​the logic chip 20. The extension terminal 23 includes multiple bonding pads and signal interfaces, which can be used to connect to external control chips (such as main controllers) and can also be adapted to customized functions in different application scenarios (such as multi-panel collaborative driving and sensor data access), significantly improving the scenario adaptability of the structure.

[0036] Optionally, such as Figure 1 As shown, the semiconductor structure of this embodiment further includes a dielectric layer 30 to enhance the insulation performance and bonding stability between the two chips. Specifically, the dielectric layer 30 includes a first dielectric layer 31 and a second dielectric layer 32. The first dielectric layer 31 is located on the first top surface 11 of the driver chip 10, and the second dielectric layer 32 is located on the second top surface 21 of the logic chip 20. Specifically, the first dielectric layer 31 covers the first bonding pad 111 and its edge area; the second dielectric layer 32 covers the second bonding pad 211 and its edge area. Optionally, the dielectric layer 30 is made of a polymer or silicon oxide with a low dielectric constant. The dielectric layer 30 provides electrical insulation between adjacent pads, buffers stress during the bonding process to prevent pad damage, and provides a flat bonding interface for subsequent bonding.

[0037] Optionally, the semiconductor structure of this embodiment further includes a redistribution layer, which includes a first redistribution layer 41 and a second redistribution layer 42. The first redistribution layer 41 is located within the first dielectric layer 31, and the second redistribution layer 42 is located within the second dielectric layer 32. The redistribution layer reconnects the original signal ports inside the chip to the bonding pads through metal wiring, avoiding integration obstacles caused by native interface incompatibility; and directly connects the arithmetic units of the logic chip 20 to the signal input terminals of the driver chip 10 through RDL, shortening the transmission distance and reducing signal delay and loss.

[0038] Optionally, the semiconductor structure in this embodiment further includes conductive pillars, including a first conductive pillar 51 and a second conductive pillar 52. One end of the first conductive pillar 51 is connected to the first redistribution layer 41, and the other end is connected to the first bonding pad 111, so as to vertically lead the circuit signals (such as power modules and core driving units) buried inside the driver chip 10 to the bonding surface, avoiding the problem of long signal paths caused by traditional wire bonding; one end of the second conductive pillar 52 is connected to the second redistribution layer 42, and the other end is connected to the second bonding pad 211, so as to realize the efficient output of signals from the memory units and arithmetic units inside the logic chip. Optionally, the conductive pillars are filled with highly conductive materials such as highly conductive metals (such as copper, aluminum, gold), conductive composite materials, and doped polysilicon, and are used in conjunction with an insulating liner (such as silicon oxide) to achieve electrical isolation from the silicon substrate. Their diameter is usually in the range of 5-10 μm, supporting high-density interconnection, which is one of the core technologies of high-density integration.

[0039] Optionally, the semiconductor structure of the embodiment further comprises a filling layer 60 to further enhance the stability and reliability of the structure, the filling layer 60 is located at the bonding interface of the driving chip 10 and the logic chip 20. The filling material of the filling layer 60 includes epoxy resin, polyimide, inorganic molecular material, etc. Not only can it fill the tiny gap between the bonding interface, but also provide additional mechanical support to prevent the chip from being damaged due to external stress during use. At the same time, the filling layer 60 can also play a certain sealing role to prevent moisture or other harmful substances from entering the inside of the chip, thereby prolonging the service life of the chip.

[0040] The semiconductor structure provided by the application bonds the chip to the wafer, avoids the waste of chips caused by bonding the wafer to the wafer, and adopts bonding pad bonding, vertical interconnection, and rewiring layer to shorten the transmission path of the driving unit to the storage chip; and the area of the logic chip is greater than that of the driving chip, and the bonding blank area can additionally place the expansion end.

[0041] Embodiment two

[0042] The embodiment also provides a preparation method of a semiconductor structure, as shown in Figures 2-5 The preparation method of the semiconductor structure of the embodiment comprises:

[0043] providing a first wafer, and preparing a plurality of driving chips on the first wafer;

[0044] providing a second wafer, and preparing a plurality of logic chips on the second wafer;

[0045] cutting the first wafer to form a plurality of driving chip dies;

[0046] bonding the plurality of driving chip dies to the second wafer;

[0047] cutting the second wafer.

[0048] Specifically, as shown in Figure 2As shown, step S1: A first wafer is provided, and multiple driver chips 10 are fabricated on the first wafer. Generally, the first wafer is a silicon-based wafer, and the diameter can be selected as 8 inches or 12 inches. The specific size is determined according to the production capacity requirements and equipment compatibility. Multiple driver chips are batch-fabricated on the first wafer through semiconductor front-end processes. The specific steps include: substrate pretreatment: the surface of the first wafer is cleaned to remove surface impurities, oxide layers, etc., to ensure that the wafer surface is clean and flat, providing a good foundation for subsequent processes; epitaxial growth: silicon epitaxial layers with specific doping concentrations are grown according to the requirements of the driver chips, such as high-resistivity epitaxial layers required for HV driver chips; core circuit fabrication: the core circuit of the driver chip is fabricated through processes such as photolithography, etching, and ion implantation, including high-voltage driver units (HV) and medium-voltage driver units (MV). The transistor structure, power management module, and internal interconnect wiring of the low-voltage drive unit (LV) are included; transistor structures of different voltage levels are fabricated to meet the needs of different application scenarios; optionally, the fabrication of dielectric and wiring layers is also included: a first dielectric layer material, including silicon oxide, silicon nitride, etc., is deposited on the surface of the circuit structure, and through-holes are made by photolithography and etching, followed by the fabrication of the first redistribution layer (RDL) by sputtering and electroplating process to achieve the initial signal extraction of the internal signal of the drive chip; optionally, the fabrication of conductive pillars is also included. If the drive chip needs to achieve vertical interconnection through conductive pillars, the first hole is made by deep silicon etching process at this stage, followed by the deposition of an insulating substrate (such as silicon oxide) and a barrier layer (such as tantalum, titanium), and the filling of conductive material (such as copper) to form the first conductive pillar, which is connected to the first redistribution layer.

[0049] Step S2: Provide a second wafer and fabricate a plurality of logic chips 20 on the second wafer.

[0050] A second wafer is provided, optionally a silicon-based wafer, selected according to the logic chip manufacturing process requirements. For example, a 12-inch wafer is often used for 28nm processes. Multiple logic chips are mass-produced using advanced processes, specifically including: logic circuit and memory cell fabrication: using higher precision photolithography (such as extreme ultraviolet lithography EUV), ion implantation, thin film deposition and other processes to fabricate the core units of the logic chip, including SRAM (static RAM), DRAM (dynamic RAM) memory arrays, and timing control, arithmetic logic and other circuits; optionally, it also includes dielectric layer and wiring layer fabrication: depositing a second dielectric layer (the material matches the first dielectric layer to ensure bonding compatibility) and fabricating a second redistribution layer to realize the signal extraction and path optimization inside the logic chip; optionally, the fabrication of via pillars: etching second holes and filling them with conductive material to form second conductive pillars, connecting to the second redistribution layer.

[0051] Step S3: As Figure 3 As shown, the first wafer is cut to form multiple driver chip dies.

[0052] Specifically, the first wafer is fixed on a blue film (ultraviolet curing film) to ensure the flatness of the wafer and the non-displacement of the chip array, and to protect the non-bonding surface (first bottom surface 12) from damage; a laser cutting machine (suitable for thin wafers or high-precision cutting) or a diamond blade cutting machine is used to cut along the cutting path between the driving chips to separate individual driving chip dies.

[0053] Optionally, the driving chip dies are also detected and screened, including checking the appearance of the dies (whether there are cracks, missing corners, pad damage), and verifying the electrical function of the dies through probe testing, screening out qualified driving chip dies, and marking and removing unqualified dies.

[0054] Step 4: as shown in Figure 4 The plurality of driving chip dies are bonded to the second wafer.

[0055] The qualified driving chip dies are bonded one by one to the logic chips of the second wafer to realize the physical and electrical interconnection of the two, specifically including: pretreating the first wafer and the second wafer, including cleaning the bonding surface, and aligning the alignment marks to ensure the bonding position accuracy; using the suction nozzle of a high-precision bonder (positioning accuracy <1 μm) to pick up the qualified driving chip dies, and accurately aligning the first bonding pads of the dies with the second bonding pads of the logic chips on the second wafer through a visual recognition system; specifically, according to the bonding material, the corresponding process is selected, such as Cu-Cu hybrid bonding which requires applying temperature (200-300°C) and pressure (10-MPa) in a vacuum environment to make the copper pads diffuse and fuse to form ohmic contact; if it is gold bump bonding, intermetallic bonding is realized through thermal compression or ultrasonic process;

[0056] Optionally, after the bonding is completed, a filling material (such as epoxy resin, silicone rubber) is applied to the bonding interface gap (the area not covered by the bonding pads) between the driving chips and the logic chips, and a filling layer is formed by baking and curing to realize gap sealing, stress buffering and mechanical strength enhancement.

[0057] Optionally, the connection quality of the bonding interface (whether there are voids or fake welds) is detected by X-ray, and the signal conduction between the driving chips and the logic chips is verified by electrical testing to ensure the reliability of the interconnection.

[0058] Step S5: as shown in Figure 5 The second wafer is cut.

[0059] The second wafer after the bonding is cut to obtain independent semiconductor structure products, specifically including: attaching a cutting film on the back surface (the second bottom surface of the logic chip) of the second wafer, or performing temporary bonding reinforcement (for a thin wafer) to prevent the chips from falling off or deforming during cutting; cutting along the cutting path between the logic chips to separate single semiconductor structure units integrated with the driving chip and the logic chip;

[0060] Specifically, if the logic chip reserves the expansion end 23, it is necessary to ensure that the cutting does not damage the bonding pads of the expansion end;

[0061] Optionally, the semiconductor structure units after cutting are subjected to final testing (FT), including full-function verification (such as driving signal output, logic operation, and storage read-write cooperation) and reliability testing (such as temperature cycling and damp heat testing) to screen out qualified products; unqualified units are marked and removed.

[0062] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A semiconductor structure, characterized in that, include: The driver chip includes a first top surface and a first bottom surface disposed opposite to each other, and the first top surface is provided with a first bonding pad; A logic chip includes a second top surface and a second bottom surface disposed opposite to each other, and a second bonding pad is disposed on the second top surface; The driver chip and the logic chip are bonded together via the first bonding pad and the second bonding pad.

2. The semiconductor structure according to claim 1, characterized in that, The logic chip is larger than the driver chip, and the second top surface of the logic chip also has a bonding blank area.

3. The semiconductor structure according to claim 2, characterized in that, It also includes an extension terminal located in the bonding blank area of ​​the logic chip.

4. The semiconductor structure according to claim 1, characterized in that, The driving chip includes: a high-voltage driving chip, a medium-voltage driving chip, and a low-voltage driving chip.

5. The semiconductor structure according to claim 1, characterized in that, It also includes a dielectric layer, which comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is located on the first top surface of the driver chip and the second dielectric layer is located on the second top surface of the logic chip.

6. The semiconductor structure according to claim 5, characterized in that, It also includes a rerouting layer, which includes a first rerouting layer and a second rerouting layer, wherein the first rerouting layer is located within the first dielectric layer and the second rerouting layer is located within the second dielectric layer.

7. The semiconductor structure according to claim 5, characterized in that, It also includes conductive pillars, which include a first conductive pillar and a second conductive pillar. The first conductive pillar is located on the first top surface of the driver chip, and the second conductive pillar is located on the second top surface of the logic chip. The first conductive pillar and the second conductive pillar are electrically connected.

8. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A first wafer is provided, and a plurality of driver chips are fabricated on the first wafer; A second wafer is provided, on which multiple logic chips are fabricated; The first wafer is diced to form multiple driver chip dies; The plurality of driver chip dies are bonded to the second wafer; The second wafer is then diced.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, After bonding the plurality of driver chip dies to the second wafer, the process further includes applying a filling material to the interface gap between the driver chip and the logic chip to form a filling layer.

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