Image sensor chip board-level fan-out type packaging structure and packaging method

Abstract

The application discloses a kind of image sensor chip board level fan-out type packaging structure and packaging method, the packaging structure includes: dielectric encapsulation chip unit, including image sensor chip and transparent dielectric protective layer, transparent dielectric protective layer is set on image sensor chip, and its corresponding image sensor chip Conductive terminal position has conductive via; Plastic package, dielectric encapsulation chip unit is covered;First metal rewiring layer, it is set on transparent dielectric protective layer, and it is electrically connected with the conductive terminal of image sensor chip by conductive via;Second metal rewiring layer, it is set on the side of plastic package, away from first metal rewiring layer, and it is electrically connected with first metal rewiring layer by interconnection via on plastic package;External electrical connection structure, it is electrically connected with second metal rewiring layer.The application is cooperated with board level TMV by transparent dielectric protective layer, realizes the low cost, high reliability, high density interconnection packaging of CIS chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor chip packaging, in particular to an image sensor chip board-level fan-out packaging structure and a packaging method. BACKGROUND

[0002] With the explosive growth of applications such as intelligent mobile phone multi-camera systems, automatic driving high-precision sensing, and medical image diagnosis, the market demand for high-resolution CMOS image sensors (CIS) has surged. Such sensors need to support tens of millions of pixels and high-speed data throughput, resulting in a sharp increase in the number of I / O pins (>1000 pins), and thus the packaging technology of image sensor chips faces the dual challenges of cost control and multi-pin integration. The current mainstream high-end CIS packaging relies on through-silicon via (TSV) technology to achieve vertical interconnection, but its inherent defects have become an industry bottleneck:

[0003] TSV needs to go through complex processes such as silicon deep hole etching, sidewall insulation layer deposition, barrier layer / seed layer sputtering, and copper plating filling, which requires high equipment investment and high yield management difficulty, resulting in packaging costs accounting for more than 30% of the total chip cost;

[0004] Deep silicon etching can easily cause wafer warping, affecting reliability;

[0005] TSV technology has size limitations, and the aperture and aspect ratio of TSV restrict the improvement of I / O density, making it difficult to meet the multi-pin requirements of high-resolution CIS chips.

[0006] To reduce costs and increase efficiency, board-level fan-out packaging (FOPLP) has become a new choice. It uses a rectangular panel substrate (such as 510mm x 515mm), which can greatly increase the effective packaging area, improve processing efficiency and capacity, and reduce the packaging cost of individual chips, which is particularly significant for large-size and high-pixel CIS chips. FOPLP forms a reconfiguration layer by molding on the side of the chip, and a high-density redistribution layer (RDL) is made on the molding surface to achieve I / O pin fan-out expansion. However, the existing FOPLP technology has key defects in CIS packaging:

[0007] Generally, the traditional light transmission scheme (such as glass cover plate) is used, which is prone to interface cracking due to thermal expansion mismatch and cannot be compatible with panel-level molding processes;

[0008] The mainstream FOPLP uses a relatively complex electroplated copper pillar structure to achieve vertical interconnection, which still has relatively high process complexity and cost.

[0009] The plastic package through-hole (TMV) technology is considered as a key to break through the bottleneck, which directly laser drills and metallizes on the plastic package material, reduces the process compared with the TSV, has low equipment cost, and supports micro-hole pitch. However, the TMV in the CIS package faces many problems, such as: the front high-precision RDL needs wafer-level lithography precision, and the board-level processing precision of the TMV cannot meet the alignment demand, causing the risk of interconnection short circuit; the carbonized debris generated by laser ablation of the plastic package material may contaminate the photosensitive area; the traditional light-transmitting protective layer such as glass cannot cooperate with the TMV / RDL, resulting in redundant light-transmitting structure and reliability degradation.

[0010] Therefore, the industry urgently needs a packaging technology that effectively integrates the TMV technology and the CIS chip on the board-level platform. SUMMARY

[0011] To solve the above technical problems, the purpose of the present application is to provide an image sensor chip board-level fan-out packaging structure and a packaging method. The present application realizes low-cost, high-reliability and high-density interconnection packaging of high-resolution CIS chips through the cooperative design of wafer-level transparent dielectric protective layer and board-level TMV, and completely solves the core problems of high cost, poor reliability and insufficient precision in the prior art.

[0012] To achieve the above technical purposes and effects, the present application realizes the following technical solutions:

[0013] The present application further provides a packaging method of an image sensor chip board-level fan-out packaging structure, comprising the following steps:

[0014] Step one, providing an image sensor wafer, the front surface of the image sensor wafer comprising a photosensitive area and a conductive terminal; forming a transparent dielectric protective layer on the front surface of the image sensor wafer, and forming a conductive via on the transparent dielectric protective layer corresponding to the conductive terminal of the image sensor wafer, and then cutting to obtain a single dielectric packaging chip unit comprising an image sensor chip and a transparent dielectric protective layer;

[0015] Step two, fixing the front surface of the dielectric packaging chip unit downward on a plastic package support board, and packaging with a plastic package body;

[0016] Step three, removing the plastic package support board, forming a first metal redistribution layer on the transparent dielectric protective layer, and the first metal redistribution layer is electrically connected with the conductive terminal of the image sensor chip through the conductive via and extends to the surface of the plastic package body;

[0017] Step four, forming an interconnection via in the plastic package body to expose the first metal redistribution layer;

[0018] Step five, forming a second metal redistribution layer on the side of the plastic package which is away from the first metal redistribution layer, the second metal redistribution layer is electrically connected with the first metal redistribution layer through the interconnection via;

[0019] Step six, forming an external electrical connection structure on the second metal redistribution layer.

[0020] Further, the material of the transparent dielectric protective layer is a photosensitive material or a non-photosensitive material, and the conductive via is formed by any of the following ways:

[0021] If the material of the transparent dielectric protective layer is a photosensitive material, the conductive via is formed by using an exposure and development process;

[0022] If the material of the transparent dielectric protective layer is a non-photosensitive material, the conductive via is formed by using a laser drilling process.

[0023] Further, the transparent dielectric protective layer is a polymer dielectric film, and exemplary materials thereof include but are not limited to polyimide, benzocyclobutene (BCB) or transparent epoxy resin.

[0024] Further, in step two, the dielectric packaged chip unit is fixed on the plastic package support board by a temporary bonding glue.

[0025] Further, step three further comprises:

[0026] forming a transparent dielectric cover layer on the first metal redistribution layer and the transparent dielectric protective layer.

[0027] Further, the material of the transparent dielectric cover layer is a photosensitive material or a non-photosensitive material, and the transparent dielectric cover layer is formed by any of the following ways:

[0028] If the material of the transparent dielectric cover layer is a photosensitive material, the transparent dielectric cover layer is formed by using a whole-surface exposure, development and curing way;

[0029] If the material of the transparent dielectric cover layer is a non-photosensitive material, the transparent dielectric cover layer is formed by curing.

[0030] Further, the transparent dielectric cover layer is a polymer dielectric film, and exemplary materials thereof include but are not limited to polyimide, benzocyclobutene (BCB) or transparent epoxy resin.

[0031] Further, step five further comprises:

[0032] forming a solder resist layer on the surface of the second metal redistribution layer and the plastic package, and forming an opening in the solder resist layer corresponding to the position of the second metal redistribution layer;

[0033] The external electrical connection structure formed in step six is electrically connected with the second metal redistribution layer through the opening.

[0034] Further, step six further comprises:

[0035] After the external electrical connection structure is completed, a single image sensor chip panel-level fan-out package structure is obtained through a cutting process.

[0036] In another aspect, the present application provides an image sensor chip panel-level fan-out package structure, comprising:

[0037] a dielectric encapsulation chip unit comprising an image sensor chip and a transparent dielectric protective layer, the front surface of the image sensor chip having a photosensitive area and conductive terminals; the transparent dielectric protective layer is arranged on the front surface of the image sensor chip, and the transparent dielectric protective layer has conductive vias corresponding to the positions of the conductive terminals of the image sensor chip;

[0038] a plastic encapsulation body covering the side surface and the back surface of the dielectric encapsulation chip unit;

[0039] a first metal redistribution layer arranged on the transparent dielectric protective layer, and the first metal redistribution layer is electrically connected with the conductive terminals of the image sensor chip through the conductive vias; the first metal redistribution layer extends to the surface of the plastic encapsulation body;

[0040] a second metal redistribution layer arranged on the side of the plastic encapsulation body away from the first metal redistribution layer; the plastic encapsulation body further has an interconnection via corresponding to the position of the first metal redistribution layer; the second metal redistribution layer is electrically connected with the first metal redistribution layer through the interconnection via;

[0041] an external electrical connection structure electrically connected with the second metal redistribution layer.

[0042] Further, the image sensor chip panel-level fan-out package structure further comprises a transparent dielectric cover layer and a solder mask layer; the transparent dielectric cover layer covers the surface of the first metal redistribution layer and the transparent dielectric protective layer; the solder mask layer covers the surface of the second metal redistribution layer and the plastic encapsulation body, and the solder mask layer has an opening corresponding to the position of the second metal redistribution layer; the external electrical connection structure is electrically connected with the second metal redistribution layer through the opening.

[0043] Further, the external electrical connection structure is one of a tin ball, a copper pillar bump, or a solder bump.

[0044] The present application has the following beneficial effects:

[0045] 1. Significant cost reduction and process simplification are achieved

[0046] The application discards the high-cost and complex through-silicon via (TSV) process (deep silicon etching, insulation / barrier / seed layer deposition, copper filling, etc.), but adopts the formation of through holes (TMV and wafer-level through holes) on the plastic package body and the transparent dielectric protective layer, thereby greatly reducing the cost.

[0047] The application adopts a board-level fan-out platform, performs plastic packaging and subsequent interconnection structure fabrication on a plastic packaging support board, fully utilizes the high-efficiency processing advantage of a large-size panel, significantly improves the number of packaged chips per unit area, and reduces the packaging cost of a single chip.

[0048] In the packaging method of the application, high-precision and high-cost steps (transparent dielectric protective layer deposition, conductive via formation, high-precision first metal redistribution layer) are completed at the wafer level, and the wafer-level photolithography precision is used to ensure the protection of the photosensitive area and the alignment of the key interconnection. Low-precision and low-cost large-area steps (plastic packaging, TMV hole, second metal redistribution layer, external electrical connection structure) are completed at the board level, so that the best balance between cost and performance is achieved.

[0049] 2. Reliability is improved

[0050] The application adopts a wafer-level deposited transparent dielectric protective layer to directly cover the photosensitive area and form a conductive via, replacing the traditional separately attached glass cover plate. The thermal expansion coefficient of the transparent dielectric protective layer material is more easily close to that of the chip and the subsequent plastic package body, solving the problem of interface delamination and cracking of the glass cover plate caused by large CTE difference during high-low temperature cycle or reflow soldering.

[0051] In the application, the photosensitive area and conductive terminals of the image sensor chip are completely covered and protected by the wafer-level formed transparent dielectric protective layer before plastic packaging; this effectively prevents the plastic packaging material from penetrating or contaminating the extremely sensitive photosensitive area and conductive terminals (metal pads) during the high-temperature and high-pressure plastic packaging process, ensuring the optical performance and electrical connection reliability of the image sensor chip.

[0052] The first metal redistribution layer in the application is fabricated on the flat wafer-level transparent dielectric protective layer after the plastic packaging support board is removed; this inherits the ultra-high photolithography alignment precision of the wafer-level process, ensuring that the first metal redistribution layer and the conductive terminals on the image sensor chip are precisely and reliably electrically connected through the wafer-level formed conductive via, solving the problem that the existing board-level process and TMV technology cannot meet the CIS alignment requirements.

[0053] 3. High-density interconnection and optical performance guarantee are achieved

[0054] The present application combines wafer-level high-precision first metal redistribution layer and board-level TMV interconnection, which can realize fine-pitch vertical interconnection and fan-out wiring. The first metal redistribution layer extends to the surface of the plastic package, providing reliable connection anchor points for TMV holes. The second metal redistribution layer performs fan-out on the other side of the plastic package, and finally leads out a large number of I / O through external electrical connection structure. This double-layer RDL+TMV structure meets the interconnection requirements of high-resolution CIS chips with more than 1000 pins.

[0055] The present application uses a wafer-level deposited transparent dielectric protective layer to directly adhere to the chip photosensitive area, which has high light transmittance, low stress and low impurity characteristics, providing the best optical window and protection for the photosensitive area, avoiding the intermediate adhesive layer required by traditional glass cover plates, reducing light loss and interface reflection / scattering, and improving imaging quality.

[0056] Overall, the present application realizes low-cost, high-reliability, and high-density interconnection packaging of high-resolution CIS chips through wafer-level transparent dielectric protective layer and board-level TMV collaborative design, and completely solves the core problems of high cost, poor reliability, and insufficient precision in the prior art. BRIEF DESCRIPTION OF DRAWINGS

[0057] Figure 1 The structure obtained by step S1 of the embodiment of the present application is shown in the schematic diagram.

[0058] Figure 2 The structure obtained by step S2 of the embodiment of the present application is shown in the schematic diagram.

[0059] Figure 3 The structure obtained by step S3 of the embodiment of the present application is shown in the schematic diagram.

[0060] Figure 4 The structure obtained by step S4 of the embodiment of the present application is shown in the schematic diagram.

[0061] Figure 5 The structure obtained by step S5 of the embodiment of the present application is shown in the schematic diagram.

[0062] Figure 6 The structure obtained by step S6 of the embodiment of the present application is shown in the schematic diagram.

[0063] Figure 7 The structure obtained by step S7 of the embodiment of the present application is shown in the schematic diagram.

[0064] Figure 8 The structure obtained by step S8 of the embodiment of the present application is shown in the schematic diagram.

[0065] Figure 9 The structure obtained by step S9 of the embodiment of the present application is shown in the schematic diagram.

[0066] Figure 10This is a schematic diagram of the structure obtained in step S10 of an embodiment of the present invention.

[0067] Figure 11 This is a schematic diagram of the structure obtained in step S11 of an embodiment of the present invention.

[0068] Wherein, 10: image sensor wafer, 101: photosensitive area, 102: conductive terminal, 103: image sensor chip; 20: transparent dielectric protective layer, 201: conductive via; 30: molding compound, 301: interconnect via; 40: first metal redistribution layer; 50: transparent dielectric cover layer; 60: second metal redistribution layer; 70: solder mask layer, 701: opening; 80: external electrical connection structure; 90: temporary bonding adhesive; 100: molding support substrate. Detailed Implementation

[0069] The technical solutions of the present invention will be clearly and completely described below with reference to specific embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0070] like Figures 1 to 11 As shown, the present invention provides a packaging method for an image sensor chip-level fan-out package structure, comprising the following steps:

[0071] Step 1, as follows Figures 1 to 2 As shown, an image sensor wafer 10 is provided. The front side of the image sensor wafer 10 includes a photosensitive area 101 and a conductive terminal 102. A transparent dielectric protective layer 20 is formed on the front side of the image sensor wafer 10 by coating or lamination, and a conductive via 201 is formed on the transparent dielectric protective layer 20 corresponding to the conductive terminal 102 of the image sensor wafer 10. The above structure is then subjected to wafer grinding, thinning, and cutting to obtain a single dielectric packaged chip unit including an image sensor chip 103 and a transparent dielectric protective layer 20.

[0072] The coating process for forming the transparent dielectric protective layer 20 includes spin coating, spray coating, slot coating, etc., and the applicable material is a flowable liquid dielectric resin. The material of the transparent dielectric protective layer 20 is a photosensitive material or a non-photosensitive material. Preferably, the transparent dielectric protective layer 20 is a polymer dielectric film, and exemplary materials include, but are not limited to, polyimide, benzocyclobutene (BCB), or transparent epoxy resin. The transparent dielectric protective layer 20 forms the conductive via 201 in any of the following ways:

[0073] If the transparent dielectric protective layer 20 is made of a photosensitive material, a conductive via 201 is formed by an exposure and development process.

[0074] If the material of the transparent dielectric protection layer 20 is a non-photosensitive material, a laser drilling process is used to form the conductive via hole 201.

[0075] Step two, as shown, the front of the multiple dielectric packaging chip units is fixed on the plastic packaging support board 100 in turn by the temporary bonding glue 90, and is packaged with the plastic packaging body 30. Figures 3 to 4

[0076] Step three, as shown, the plastic packaging support board 100 (the temporary bonding glue 90 is also removed) is removed by thermal disassembly or laser disassembly, the first metal redistribution layer 40 is formed on the transparent dielectric protection layer 20, and the first metal redistribution layer 40 is electrically connected with the conductive terminal 102 of the image sensor chip 103 through the conductive via hole 201 and extends to the surface of the plastic packaging body 30. Figure 5

[0077] As shown in the figure, step three also includes: Figure 6

[0078] A transparent dielectric cover layer 50 is formed on the first metal redistribution layer 40 and the transparent dielectric protection layer 20 by film pressing. The material of the transparent dielectric cover layer 50 is a photosensitive material or a non-photosensitive material; preferably, the transparent dielectric cover layer 50 is a polymer dielectric film, and its exemplary materials include but are not limited to: polyimide, benzocyclobutene (BCB), or transparent epoxy resin. The transparent dielectric cover layer 50 forms a complete structure by any of the following ways:

[0079] If the material of the transparent dielectric cover layer 50 is a photosensitive material, the transparent dielectric cover layer 50 with a complete structure is formed by full-face exposure, development, and curing; wherein the exposure can excite molecular chain crosslinking; the development can dissolve the uncrosslinked small molecules; and the curing is completely crosslinked by heat.

[0080] If the material of the transparent dielectric cover layer 50 is a non-photosensitive material, the transparent dielectric cover layer 50 with a complete structure is formed by curing.

[0081] Step four, as shown, the interconnection via hole 301 (TMV hole) is made on the side of the plastic packaging body 30 away from the first metal redistribution layer 40 by laser drilling or mechanical drilling, and the first metal redistribution layer 40 is exposed. Figure 7 Step five, as shown, the second metal redistribution layer 60 is formed on the side of the plastic packaging body 30 away from the first metal redistribution layer 40 by physical vapor deposition, electroplating or chemical plating, and the second metal redistribution layer 60 is electrically connected with the first metal redistribution layer 40 through the interconnection via hole 301.

[0082] Figure 8 ​​​​​

[0083] As shown in Figure 9 Step five also includes:

[0084] A solder resist layer 70 is formed on the surface of the second metal redistribution layer 60 and the plastic package 30 by coating or film pressing, and the material of the solder resist layer 70 is solder resist ink, polyimide or ABF. An opening 701 is formed on the solder resist layer 70 corresponding to the position of the second metal redistribution layer 60 to expose part of the second metal redistribution layer 60. If the material of the solder resist layer 70 is photosensitive material, the opening 701 is made by exposure and development; if the material of the solder resist layer 70 is non-photosensitive material, the opening 701 is made by laser drilling.

[0085] Step six, as shown in Figure 10 An external electrical connection structure 80 is formed corresponding to the position of the opening 701 of the solder resist layer 70, and the external electrical connection structure 80 is electrically connected with the second metal redistribution layer 60. The external electrical connection structure 80 is one of a tin ball, a copper pillar bump or a solder bump;

[0086] As shown in Figure 11 After the external electrical connection structure 80 is made, a single image sensor chip board-level fan-out package structure is obtained by a cutting process.

[0087] As shown in Figure 11 The image sensor chip board-level fan-out package structure obtained by the above packaging method includes:

[0088] A dielectric packaging chip unit includes an image sensor chip 103 and a transparent dielectric protective layer 20. The front surface of the image sensor chip 103 has a photosensitive area 101 and a conductive terminal 102. The transparent dielectric protective layer 20 is arranged on the front surface of the image sensor chip 103, and the transparent dielectric protective layer 20 has a conductive via 201 corresponding to the position of the conductive terminal 102 of the image sensor chip 103;

[0089] A plastic package 30 covers the side surface and the back surface of the dielectric packaging chip unit;

[0090] A first metal redistribution layer 40 is arranged on the transparent dielectric protective layer 20, and the first metal redistribution layer 40 is electrically connected with the conductive terminal 102 of the image sensor chip 103 through the conductive via 201. The first metal redistribution layer 40 extends to the surface of the plastic package 30;

[0091] A transparent dielectric cover layer 50 covers the surface of the first metal redistribution layer 40 and the transparent dielectric protective layer 20;

[0092] A second metal redistribution layer 60 is disposed on a side of the plastic package 30 opposite the first metal redistribution layer 40; the plastic package 30 also has an interconnection via hole 301 corresponding to the position of the first metal redistribution layer 40; the second metal redistribution layer 60 is electrically connected to the first metal redistribution layer 40 through the interconnection via hole 301;

[0093] A solder resist layer 70 covers the surface of the second metal redistribution layer 60 and the plastic package 30, and the solder resist layer 70 has an opening 701 corresponding to the position of the second metal redistribution layer 60;

[0094] An external electrical connection structure 80 is electrically connected to the second metal redistribution layer 60 through the opening 701 in the solder resist layer 70.

[0095] The transparent dielectric protective layer 20 is a polymer dielectric film, and exemplary materials thereof are preferably polyimide, benzocyclobutene (BCB), or transparent epoxy resin.

[0096] The transparent dielectric protective layer 20 is a polymer dielectric film, and exemplary materials thereof are preferably polyimide, benzocyclobutene (BCB), or transparent epoxy resin.

[0097] The external electrical connection structure 80 is one of a tin ball, a copper pillar bump, or a solder bump.

[0098] Embodiment

[0099] As shown in Figures 1 to 11 A packaging method of a board-level fan-out type packaging structure of an image sensor chip, comprising the following steps:

[0100] S1, as shown in Figure 1 An image sensor wafer 10 is provided, the front surface of the image sensor wafer 10 including a light-sensitive region 101 and a conductive terminal 102; a transparent dielectric protective layer 20 is formed on the front surface of the image sensor wafer 10 by spraying, and a conductive via hole 201 is formed on the transparent dielectric protective layer 20 corresponding to the conductive terminal 102 of the image sensor wafer 10;

[0101] The material of the transparent dielectric protective layer 20 is photosensitive polyimide, and the conductive via hole 201 is formed by an exposure and development process.

[0102] S2, as shown in Figure 2 The structure formed in step S1 is sequentially subjected to wafer grinding and thinning and cutting to obtain a single dielectric packaging chip unit including an image sensor chip 103 and a transparent dielectric protective layer 20.

[0103] S3, as shown in Figure 3 The front surface of the plurality of dielectric packaging chip units is fixed to a plastic package support board 100 by a temporary bonding glue 90.

[0104] S4, as Figure 4 As shown, molding compound is covered on the molding support substrate 100 to form a molding body 30, which encapsulates the sides and back of the dielectric packaged chip unit.

[0105] S5, such as Figure 5 As shown, the plastic encapsulation support substrate 100 is removed (the temporary bonding adhesive 90 is also removed), and a first metal redistribution layer 40 is formed on the transparent dielectric protective layer 20. The first metal redistribution layer 40 is electrically connected to the conductive terminal 102 of the image sensor chip 103 through the conductive via 201 and extends to the surface of the encapsulation body 30.

[0106] S6, such as Figure 6 As shown, a transparent dielectric capping layer 50 is formed on the first metal redistribution layer 40 and the transparent dielectric protective layer 20 by lamination. The transparent dielectric capping layer 50 is made of transparent epoxy resin, which is cured to form a complete film layer.

[0107] S7, such as Figure 7 As shown, interconnect vias 301 (TMV vias) are formed on the side of the molding compound 30 away from the first metal redistribution layer 40 by laser drilling, thus exposing the first metal redistribution layer 40.

[0108] S8, such as Figure 8 As shown, a second metal redistribution layer 60 is formed on the side of the molding compound 30 facing away from the first metal redistribution layer 40 by physical vapor deposition. The second metal redistribution layer 60 is electrically connected to the first metal redistribution layer 40 through interconnect vias 301.

[0109] S9, such as Figure 9 As shown, a solder resist layer 70 is formed on the surfaces of the second metal redistribution layer 60 and the molding compound 30 by coating. The solder resist layer 70 is made of solder resist ink. An opening 701 is formed in the solder resist layer 70 at the position corresponding to the second metal redistribution layer 60 by exposure and development to expose a portion of the second metal redistribution layer 60.

[0110] S10, such as Figure 10 As shown, an external electrical connection structure 80 (solder ball) is formed at the opening 701 position of the corresponding solder mask layer 70 by means of balling or printing solder paste and reflowing. The external electrical connection structure 80 is electrically connected to the second metal redistribution layer 60.

[0111] S11, such as Figure 11 As shown, a single image sensor chip board-level fan-out package structure is obtained through a cutting process.

[0112] like Figure 11As shown, the package method of the above embodiment obtains a board-level fan-out type package structure of an image sensor chip, which comprises:

[0113] a dielectric package chip unit comprising an image sensor chip 103 and a transparent dielectric protective layer 20, the front surface of the image sensor chip 103 having a photosensitive region 101 and conductive terminals 102; the transparent dielectric protective layer 20 is arranged on the front surface of the image sensor chip 103, and the transparent dielectric protective layer 20 has conductive vias 201 corresponding to the positions of the conductive terminals 102 of the image sensor chip 103; wherein the transparent dielectric protective layer 20 is a polyimide protective layer;

[0114] a plastic package body 30 covering the side surface and the back surface of the dielectric package chip unit;

[0115] a first metal redistribution layer 40 arranged on the transparent dielectric protective layer 20, and the first metal redistribution layer 40 is electrically connected with the conductive terminals 102 of the image sensor chip 103 through the conductive vias 201; the first metal redistribution layer 40 extends to the surface of the plastic package body 30;

[0116] a transparent dielectric cover layer 50 covering the surface of the first metal redistribution layer 40 and the transparent dielectric protective layer 20; the transparent dielectric cover layer 50 is a transparent epoxy resin layer;

[0117] a second metal redistribution layer 60 arranged on the side of the plastic package body 30 away from the first metal redistribution layer 40; the plastic package body 30 also has an interconnection via 301 corresponding to the position of the first metal redistribution layer 40; the second metal redistribution layer 60 is electrically connected with the first metal redistribution layer 40 through the interconnection via 301;

[0118] a solder resist layer 70 made of solder resist ink, which covers the surface of the second metal redistribution layer 60 and the plastic package body 30, and the solder resist layer 70 has an opening 701 corresponding to the position of the second metal redistribution layer 60;

[0119] an external electrical connection structure 80 electrically connected with the second metal redistribution layer 60 through the opening 701 of the solder resist layer 70. The external electrical connection structure 80 of this embodiment is a tin ball.

[0120] It is apparent for those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, but can be implemented in other concrete forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be considered as exemplary and not restrictive, and the scope of the present application is defined by the appended claims rather than the above description, and all changes falling within the meaning and range of equivalents of the claims are intended to be embraced therein.

[0121] Furthermore, it should be understood that although the specification is described in terms of embodiments, not every embodiment includes every feature described. The specification can include implicit combinations of explicitly mentioned features and / or explicit combinations of implicitely mentioned features. Each embodiment depends on the explicit combinations of features and / or the implicit combinations of features made specifically within that embodiment, and each such embodiment can be combined with every other such embodiment to create further embodiments.

Claims

1. A packaging method for an image sensor chip-level fan-out package structure, characterized in that, Includes the following steps: Step 1: Provide an image sensor wafer, the front side of which includes a photosensitive area and conductive terminals; form a transparent dielectric protective layer on the front side of the image sensor wafer, and form conductive vias on the transparent dielectric protective layer corresponding to the conductive terminals of the image sensor wafer; then cut to obtain a single dielectric packaged chip unit including an image sensor chip and a transparent dielectric protective layer; wherein, the transparent dielectric protective layer is a polymer dielectric film; Step 2: Fix the dielectric packaged chip unit face down on the plastic packaging support substrate and encapsulate it with a plastic package. Step 3: Remove the plastic encapsulation support substrate, form a first metal redistribution layer on the transparent dielectric protective layer, and the first metal redistribution layer is electrically connected to the conductive terminals of the image sensor chip through the conductive vias and extends to the surface of the plastic encapsulation body; Step 4: Form interconnect vias within the molding compound to expose the first metal redistribution layer; Step 5: A second metal redistribution layer is formed on the side of the molding compound opposite to the first metal redistribution layer. The second metal redistribution layer is electrically connected to the first metal redistribution layer through the interconnect via. Step six: Form an external electrical connection structure on the second metal redistribution layer.

2. The packaging method for an image sensor chip-level fan-out package structure according to claim 1, characterized in that, The transparent dielectric protective layer is made of a photosensitive material or a non-photosensitive material, and the conductive via is formed in any of the following ways: If the transparent dielectric protective layer is made of a photosensitive material, conductive vias are formed using an exposure and development process. If the transparent dielectric protective layer is made of a non-photosensitive material, a laser drilling process is used to form conductive vias.

3. The packaging method for an image sensor chip-level fan-out package structure according to claim 1, characterized in that, In step two, the dielectric encapsulated chip unit is fixed to the plastic encapsulation support substrate using temporary bonding adhesive.

4. The packaging method for an image sensor chip-level fan-out package structure according to claim 1, characterized in that, Step three also includes: A transparent dielectric overlay is formed on the first metal redistribution layer and the transparent dielectric protective layer.

5. The packaging method for an image sensor chip-level fan-out package structure according to claim 4, characterized in that, The transparent dielectric coating layer is made of a photosensitive material or a non-photosensitive material, and it is formed in any of the following ways: If the transparent dielectric coating is made of a photosensitive material, a transparent dielectric coating with a complete structure is formed by full-area exposure, development, and curing. If the material of the transparent dielectric capping layer is a non-photosensitive material, a transparent dielectric capping layer with a complete structure is formed by curing.

6. The packaging method for an image sensor chip-level fan-out package structure according to claim 1, characterized in that, Step five also includes: A solder resist layer is formed on the surface of the second metal redistribution layer and the molding compound, and an opening is formed in the solder resist layer at the position corresponding to the second metal redistribution layer; The external electrical connection structure formed in step six is ​​electrically connected to the second metal redistribution layer through the opening.

7. The packaging method for an image sensor chip-level fan-out package structure according to claim 1, characterized in that, Step six also includes: After the external electrical connection structure is fabricated, a single image sensor chip board-level fan-out package structure is obtained through a cutting process.

8. A fan-out package structure at the chip level for an image sensor, characterized in that, include: A dielectric-encapsulated chip unit includes an image sensor chip and a transparent dielectric protective layer. The front side of the image sensor chip has a photosensitive area and conductive terminals. The transparent dielectric protective layer is disposed on the front side of the image sensor chip, and the transparent dielectric protective layer has conductive vias at positions corresponding to the conductive terminals of the image sensor chip. The transparent dielectric protective layer is a polymer dielectric film. A molding compound that covers the sides and back of the dielectric packaged chip unit; A first metal redistribution layer is disposed on the transparent dielectric protective layer, and the first metal redistribution layer is electrically connected to the conductive terminals of the image sensor chip through the conductive via; the first metal redistribution layer extends to the surface of the molding compound; A second metal redistribution layer is disposed on the side of the molding compound opposite to the first metal redistribution layer; the molding compound also has interconnect vias corresponding to the positions of the first metal redistribution layer; the second metal redistribution layer is electrically connected to the first metal redistribution layer through the interconnect vias; An external electrical connection structure is electrically connected to the second metal redistribution layer.

9. The image sensor chip-level fan-out packaging structure according to claim 8, characterized in that, It also includes a transparent dielectric capping layer and a solder resist layer; the transparent dielectric capping layer covers the surface of the first metal redistribution layer and the transparent dielectric protective layer; the solder resist layer covers the surface of the second metal redistribution layer and the molding compound, and the solder resist layer has an opening at the position corresponding to the second metal redistribution layer; the external electrical connection structure is electrically connected to the second metal redistribution layer through the opening.

10. The image sensor chip-level fan-out packaging structure according to claim 8, characterized in that, The external electrical connection structure is one of solder balls, copper pillar bumps, or solder bumps.

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