A high-speed data acquisition system for a distributed device

Abstract

The application provides a high-speed data acquisition system of distributed devices, and relates to the technical field of high-speed data acquisition and communication, which is characterized in that a plurality of FPGA network cards are inserted into a tower type data monitor in parallel, each network card is directly connected with a monitor CPU through a PCIe interface and is interconnected with each photovoltaic inverter in point-to-point mode through an optical fiber via an SFP optical port, thereby forming a star type high-speed acquisition topology; the FPGA network card internally receives the alternating current side current instantaneous value, time stamp and abnormal state bit uploaded by the inverter at a preset rate in real time and immediately writes the data into a local DDR3 cache area; the BRAM in the FPGA chip is divided into a low sampling real-time channel and a high sampling non-real-time channel, the CPU reads the high sampling segment on demand in a question and answer mode through the PCIe and simultaneously refreshes the low sampling waveform in real time for local display and rapid out-of-limit alarm, the data monitor stores the complete waveform to a hard disk and forwards the waveform to a superior platform through Ethernet, thereby being used for subsequent ripple, harmonic and transient stability analysis, and realizing accurate positioning of a fault device according to a plurality of device current sequences.

Description

Technical Field

[0001] This invention relates to the field of high-speed data acquisition and communication technology, and more specifically to a high-speed data acquisition system for a distributed device. Background Technology

[0002] With the continuous increase in the penetration rate of distributed renewable energy, power electronic devices, represented by photovoltaic inverters, are no longer simply power generation units, but key nodes directly involved in the voltage and frequency regulation of microgrids. Practice shows that instantaneous ripple, dynamic response lag, or occasional abnormal oscillations in the inverter's output current can induce voltage flicker, frequency shift, and even harmonic amplification at the grid connection point within milliseconds, leading to protection malfunctions, sensitive load tripping, and even local grid instability. Meanwhile, microgrid topologies are scattered and interconnected, with dozens of inverters often connected to a single distribution transformer. When a device experiences a latent fault due to aging power devices, drifting filter parameters, or control program malfunction, its electrical characteristics are only reflected in the sudden current changes within a few hundred microseconds before and after the fault.

[0003] Specifically, in a distributed photovoltaic (PV) microgrid system, distributed PV power generation devices (power electronic devices) are the core components. The quality of their output current directly affects the stability, frequency, and load reliability of the microgrid. Fluctuations, ripple, and dynamic response characteristics of their output current can cause grid voltage fluctuations, frequency shifts, and even harmonic pollution, thus affecting the normal operation of sensitive equipment and potentially leading to localized grid failures. Furthermore, when a PV power generation device fails, its exact location within the microgrid needs to be quickly identified. Therefore, the microgrid system requires, on the one hand, monitoring the output current quality of distributed PV power generation devices, including current ripple and frequency stability; and on the other hand, real-time monitoring of data from multiple distributed PV power generation devices to provide a computational basis for microgrid fault location.

[0004] However, current traditional data acquisition solutions rely on centralized RTUs or low-speed collectors to poll inverter registers at Hertz-level rates. This not only results in the loss of critical transient information due to excessively long sampling intervals, but also leads to data queuing and congestion from multiple devices due to limited bus bandwidth, making it impossible to form a strictly synchronized time-stamped sequence, thus creating a "blind spot" for fault tracing. Furthermore, existing solutions generally adopt a flat architecture of "local caching + Ethernet upload," where the inverter-side microprocessor must handle both control and communication, limiting cache depth. Once the background initiates batch reads, TCP congestion or retransmissions can easily slow down the control loop, creating "acquisition-control" conflicts. Storing high-sampling-rate waveforms on a local SD card presents drawbacks such as difficult plugging and unplugging for maintenance, easily corrupted file systems, and a lack of real-time triggering mechanisms. Even more challenging is that in outdoor high-temperature, high-humidity, and strong electromagnetic interference scenarios, gigabit links based on RJ45 are prone to packet loss and latency jitter, leading to non-strict alignment of data across multiple nodes and a loss of benchmark for subsequent harmonic responsibility allocation and fault location algorithms.

[0005] In view of the above, this application is hereby submitted. Summary of the Invention

[0006] The present invention provides a high-speed data acquisition system for a distributed device, which can at least partially improve the above-mentioned problems.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] A high-speed data acquisition system for a distributed device includes: a data monitoring component, a display component, a distributed component, and an FPGA component. The output terminal of the distributed component is connected to the input terminal of the FPGA component, the data terminal of the FPGA component is connected to the data terminal of the data monitoring component, and the display terminal of the data monitoring component is electrically connected to the input terminal of the display component.

[0009] The data monitoring component is configured to perform the following steps by executing a computer program stored internally:

[0010] Data is acquired from the BRAM memory module in the FPGA component, and the data is then processed and evaluated.

[0011] When the abnormal operating status bit is determined to be abnormal or a high sampling rate data reading command for a specific time period is detected by the host computer, a data reading command is sent to the FPGA component through the PCIe interface and the BRAM memory module.

[0012] The high-sampling-rate data in the DDR3 memory chip transmitted by the FPGA component according to the data read command is obtained in batches and stored in the storage area. The received data is stored in the hard disk module 16 and transmitted to the host computer through the Ethernet interface for display by the data monitor.

[0013] In summary, the core of the high-speed data acquisition system for distributed devices—the data monitor—can be constructed from a tower server, equipped with several high-speed FPGA network cards. These high-speed FPGA network cards achieve high-speed communication with several distributed device controllers via SFP interfaces and fiber optic cables. A DDR3 module is used for high-speed caching of monitoring data, and data is uploaded via a BRAM module and a PCIe interface. This system can be applied to distributed photovoltaic microgrid systems, capable of detecting the output current quality of distributed photovoltaic power generation devices and monitoring the current data of multiple devices in real time, thereby achieving quality monitoring and fault location of the distributed photovoltaic microgrid system.

[0014] Specifically, this invention addresses the stringent requirements of distributed photovoltaic microgrids for current quality and fault location, constructing a three-tiered star architecture of "monitor—FPGA network card—inverter": The tower-type data monitor expands the FPGA network card through multiple PCIe×8 parallel expansions. Each network card is directly connected point-to-point to the corresponding inverter via eight lens-type SFP optical ports through optical fiber, completely eliminating the bandwidth bottleneck and electromagnetic interference of traditional RS-485 / 100Mbps Ethernet polling; The FPGA side receives instantaneous current values, timestamps, and abnormal status bits at a rate of 100 kHz without interruption, and with the help of the DDR3 dual-zone circular cache mechanism, it simultaneously retains the "latest segment" and the "before and after the fault" key segments within the millisecond scale, realizing data first landing and then arbitration; The on-chip BRAM is further divided into a 1 kHz real-time channel and a 100 kHz non-real-time channel. The CPU reads back the high-sampled segments on demand through PCIe in a question-and-answer manner, which not only reduces the bus pressure but also ensures the complete waveform required for background analysis. The system can simultaneously manage dozens of inverters on a single monitor node, fully capturing transient characteristics such as sudden changes in current ripple, harmonic amplification, and power step jumps. It also achieves precise fault location based on multi-device synchronized time-stamp sequences. The entire process of acquisition, caching, transmission, and storage is solidified in hardware logic, with physical isolation between the control and communication loops to eliminate "acquisition-control" conflicts. The overall solution, centered on "high-speed optical port + hardware caching + query-response readback," resolves the three major contradictions in microgrid scenarios: high sampling rate, multi-node parallelism, and no loss of abnormal transients. It provides a highly reliable and scalable data foundation for current quality monitoring, harmonic responsibility allocation, and rapid operation and maintenance of distributed renewable energy power plants. Attached Figure Description

[0015] Figure 1This is a schematic diagram of the architecture of a high-speed data acquisition system for a distributed device provided in an embodiment of the present invention.

[0016] Figure 2 This is a schematic diagram of the architecture of the high-speed FPGA network card provided in an embodiment of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0018] refer to Figure 1 As shown, the first embodiment of the present invention discloses a high-speed data acquisition system for a distributed device, which includes: a data monitoring component 1, a display component, a distributed component, and an FPGA component. The output terminal of the distributed component is connected to the input terminal of the FPGA component, the data terminal of the FPGA component is connected to the data terminal of the data monitoring component 1, and the display terminal of the data monitoring component 1 is electrically connected to the input terminal of the display component.

[0019] The data monitoring component 1 includes a data monitor CPU 11, a PCIe card slot 13, a memory module 15, a hard disk module 16, an Ethernet interface 17, and a display interface 14. The data monitor CPU 11 is connected to the FPGA component through the PCIe card slot 13. The data terminal of the data monitor CPU 11 is electrically connected to the data terminals of the memory module 15 and the hard disk module 16. The data monitor CPU 11 communicates with an external host computer through the Ethernet interface 17. The data monitor CPU 11 is connected to the display component through the display interface 14.

[0020] The distributed component includes multiple distributed photovoltaic power generation devices 2 and optical fibers 3, and each of the distributed photovoltaic power generation devices 2 is connected to the FPGA component through the optical fiber 3.

[0021] Please see Figure 2The FPGA component includes multiple high-speed FPGA network cards 12 corresponding to the distributed photovoltaic power generation device 2. Each high-speed FPGA network card 12 includes multiple DDR3 memory chips 121, one FPGA chip 122, multiple SFP photoelectric conversion modules 123, and one PCIe interface 124. The PCIe interface 124 is engaged with the PCIe slot 13. The FPGA chip 122 is connected to the data monitor CPU 11 through the PCIe interface 124. The FPGA chip 122 is connected to the distributed photovoltaic power generation device 2 through the SFP photoelectric conversion module 123 and the optical fiber 3. The data terminal of the FPGA chip 122 is electrically connected to the data terminal of the DDR3 memory chip 121.

[0022] The DDR3 memory chip 121 has a cyclic overlay storage area and an abnormal sampling data storage area, which are divided into multiple intervals for data storage of multiple distributed photovoltaic power generation devices 2.

[0023] The BRAM memory module built into the FPGA chip 122 is divided into a 1kHz low sampling rate storage area and a 100kHz high sampling rate storage area. The 1kHz low sampling rate storage area and the 100kHz high sampling rate storage area are further divided into multiple intervals, which are used for data storage of multiple distributed photovoltaic power generation devices 2.

[0024] The display assembly includes a display 4 and a display connection cable 5. The display 4 is connected to the display interface 14 via the display connection cable 5.

[0025] In this embodiment, to address the engineering requirements for monitoring the output current quality and locating faults in distributed photovoltaic (PV) devices within a distributed PV microgrid, a high-precision, high-speed, real-time distributed power data acquisition solution needs to be developed. Specifically, the high-speed data acquisition system for the distributed devices can acquire operational data from multiple distributed devices in real-time at high speed, accurately capturing instantaneous current changes and ripple characteristics to ensure stable system operation and rapid fault location and repair. This solution can be effectively applied to quality monitoring and fault location in distributed PV microgrid systems.

[0026] Specifically, a standard tower server is installed next to the power distribution cabinet in the distribution area as the data monitoring component 1, and the data monitor serves as the main device for data storage, relay, and analysis processing. The server motherboard has four PCIe x8 slots for horizontally inserting four high-speed FPGA network cards 12, and more slots can be configured to accommodate several FPGA network cards, depending on the actual situation. The server's built-in memory module 15 and hard disk module 16 are connected to the data monitor CPU 11 via onboard cables, forming a two-level storage system of temporary buffer and long-term disk persistence. The display component connects to the display interface 14 on the server's back panel using the included display cable 5, providing a graphical interface locally without additional configuration.

[0027] Several high-speed FPGA network cards 12 based on PCIe and SFP photoelectric conversion modules 123 serve as data transmission functional boards. The FPGA network cards connect to the data monitor via the PCIe interface 124 for high-speed data access. They also connect to distributed devices via the SFP photoelectric conversion modules 123 and their associated optical fibers 3 to achieve high-speed data access and acquire high-sampling-rate, high-speed operating data from the distributed devices. Furthermore, the FPGA network cards are equipped with several DDR3 memory chips, enabling high-speed data caching. The FPGA network cards utilize BRAM memory modules and the PCIe interface 124 to achieve non-real-time data interaction between the DDR3 memory and the data monitor. Each FPGA network card is configured with multiple SFP photoelectric conversion modules 123 and interacts with several distributed devices in a star topology.

[0028] In this embodiment, each high-speed FPGA network card 12 has an SFP photoelectric conversion module 123 interface on its panel corresponding to the number of distributed photovoltaic power generation devices 2. This interface is connected one-to-one with the optical port of the corresponding inverter via the matching optical fiber 3 to complete physical layer signal transmission. The PCIe interface 124 on the other end of the FPGA network card is aligned with the server's PCIe card slot 13 and pressed down to achieve power supply and data bus connectivity. The entire hardware installation process involves only two steps: inserting the card and inserting the optical fiber 3, resulting in minimal on-site construction. During operation, the distributed photovoltaic power generation device 2 collects AC side current data at a rate of 100kHz and adds abnormal status bits in real time. This data is then serially transmitted to the FPGA network card via the optical fiber 3 through its own SFP photoelectric conversion module 123. After receiving the data, the FPGA chip 122 first writes the normal frames into the cyclic overwrite storage area of ​​the DDR3 storage chip 121. When an abnormal status bit is detected, the data from the same channel is immediately switched to the abnormal sampling data storage area to prevent subsequent data from overwriting critical segments. The DDR3 memory chip 121's cyclic overlay storage area and abnormal sampling data storage area are pre-divided into multiple segments, each corresponding to a distributed photovoltaic power generation device 2, to achieve multi-channel data isolation; the FPGA chip 122's built-in BRAM memory module is also divided into a 1kHz low sampling rate storage area and a 100kHz high sampling rate storage area, and each is further subdivided into intervals equal to the number of devices, ensuring that low sampling real-time monitoring and high sampling post-reading of different channels do not interfere with each other.

[0029] The CPU in the data monitor is directly connected to the FPGA chip 122 in the FPGA network card via PCIe interface 124, enabling high-speed data interaction between the CPU 11 and the FPGA network card. The data monitor is connected to the monitor 4 via HDMI interface, allowing for local observation and processing of data. The CPU of the data monitor can store the acquired data in the memory module and hard disk module for data storage and real-time display. In addition, the data monitor can transmit the data stored in the hard disk module via Ethernet port for further data transmission, summary analysis, etc. Specifically, the CPU 11 of the data monitor periodically reads the 1kHz low sampling rate storage area via the PCIe bus in an interrogation-response manner, updating the screen of the monitor 4 in real time for maintenance personnel to observe the current curve locally. When detailed analysis of the waveform of a certain period is required, the CPU issues a read command to the FPGA through the same PCIe channel. The FPGA retrieves the corresponding segment from the DDR3 abnormal sampling data storage area, relays it through the 100kHz high sampling rate storage area, and then uploads it in batches at a lower rate to the memory module 15, and finally writes it to the hard disk module 16 for storage. The entire process does not require the inverter to stop generating electricity or the storage medium to be replaced. The DDR3 memory chip 121 of the FPGA network card has one part of its storage area used for cyclic overlay data storage and another part used for abnormal sampling data storage. The former can store data of a fixed time length prior to the current moment, while the latter can store sampling data within a short time interval before and after abnormal data under special conditions. The cyclic overlay data storage area and the abnormal sampling data storage area of ​​the DDR3 memory chip 121 are divided into several equal-capacity intervals for data storage of several distributed devices.

[0030] Furthermore, the FPGA network card interacts with the data monitor via the on-chip BRAM memory and PCIe interface 124. A portion of the BRAM memory is dedicated to storing 1 kHz low-sampling-rate real-time transmitted data for observing the real-time sampling waveforms of the distributed device; another portion stores 100 kHz high-sampling-rate non-real-time transmitted data for further sampling data quality analysis or pre- and post-fault sampling data analysis; and a portion of the BRAM memory is used to receive commands from the data monitor. Moreover, the FPGA network card can achieve non-real-time data transmission of cached data within a certain time period through a query-response mechanism. Specifically, it forwards data cached in DDR3 to the data monitor CPU 11 at a relatively low communication rate via the BRAM memory and PCIe interface 124.

[0031] The FPGA retrieves data from DDR3 in batches and packets according to the data read instructions from the host computer of the data monitor and fills it into the BRAM memory. The FPGA network card can realize the real-time transmission of low sampling rate data to the data monitor. That is, the FPGA further samples the high sampling rate data received by the SFP photoelectric conversion module 123 to obtain low sampling rate data, and forwards it to the data monitor CPU 11 in real time through the FPGA's on-chip BRAM memory and PCIe interface 124. The CPU realizes data storage and real-time display functions by driving the memory module 15, hard disk module, and display interface 14. In the entire process, the system adopts a local high-speed caching and non-real-time data transmission mechanism based on a question-and-answer mechanism. With the above steps, the system can provide a user-friendly monitoring with millisecond-level refresh on the local screen, and can also retain complete 100kHz sampling records in the background. This provides a synchronous and continuous data source for microgrid current quality assessment and fault equipment location, realizing true high-speed acquisition and reliable operation and maintenance in distributed photovoltaic scenarios.

[0032] Preferably, before acquiring the data within the BRAM memory module of the FPGA component, the method further includes:

[0033] When the distributed photovoltaic power generation device 2 is generating electricity via inverter, the voltage and current data of the AC side and DC side are collected in real time at a preset sampling rate.

[0034] A preliminary judgment is made on the local operating status to obtain the abnormal operating status bit, where an abnormal operating status bit of 1 indicates an abnormality and an abnormal operating status bit of 0 indicates normality.

[0035] The distributed photovoltaic power generation device 2 controls the acquisition rate data, timestamp data, and abnormal operation status bits to be sent to the FPGA chip 122 in real time through the optical fiber 3 and the SFP photoelectric conversion module 123.

[0036] In this embodiment, a data monitor with four PCIe×8 card slots, a 2TB hard drive capacity, 32GB memory capacity, one 10 Gigabit Ethernet interface 17, and one HDMI interface is used as the main body of the system for explanation. The FPGA network card uses an XC7K325TFFG900-2 chip as the FPGA chip 122, supporting parallel data processing. Four MT41K128M16JT chips are used as DDR3 storage chips 121, with a storage capacity of 128 MB. The FPGA network card uses a 10 Gigabit multi-mode SFP photoelectric conversion module—AXS85-192-M3—as its SFP photoelectric conversion module 123, with one FPGA network card equipped with eight SFP photoelectric conversion modules 123. The FPGA network card has one PCIe×8 interface. One data monitor carries four FPGA network cards through four PCIe×8 card slots, and each network card connects to four distributed devices through four SFP photoelectric conversion modules 123. The data monitor is connected to the display 4 via an HDMI interface and an HDMI cable, and to the Ethernet via a 10 Gigabit Ethernet interface 17. In this embodiment, the distributed device is a distributed photovoltaic power generation device 2, i.e., an inverter device, which needs to be equipped with the same model of SFP photoelectric conversion module 123.

[0037] Specifically, when the distributed photovoltaic power generation device 2 enters the inverter power generation mode, its internal controller collects and digitizes the voltage and current data of the AC and DC sides in real time at a preset sampling rate of 100kHz. At the same time, the controller makes a preliminary judgment on the local operating status and generates an abnormal operating status bit—if overcurrent, overvoltage, or temperature exceeds the limit, the status bit is set to 1, otherwise it is set to 0. Subsequently, the distributed photovoltaic power generation device 2 sends the collected 100kHz sampling rate data, timestamp data, and abnormal operating status bit to the FPGA chip 122 in real time through the optical fiber 3 and the SFP photoelectric conversion module 123.

[0038] Preferably, it further includes: after receiving the acquisition rate data, timestamp data and abnormal operating status bit sent by the distributed photovoltaic power generation device 2, the FPGA chip 122 judges the abnormal operating status bit;

[0039] When the abnormal operating status bit is determined to be 0, the received data is stored in the cyclic overwrite storage area of ​​the DDR3 memory chip 121 using the cyclic overwrite storage method.

[0040] When the abnormal operation status bit is determined to be 1, the data is stored in the abnormal sampling data storage area;

[0041] The received SFP data is stored at a sampling rate of 1kHz in the 1kHz low sampling rate storage area of ​​the FPGA chip 122.

[0042] In this embodiment, after receiving data, the FPGA chip 122 immediately writes normal data into the cyclic overwrite storage area of ​​the DDR3 memory chip 121 and writes abnormal data into the abnormal sampling data storage area according to the value of the abnormal operating status bit, thereby realizing hardware-level latching of key waveforms. Through this preprocessing, the system ensures that abnormal segments are completely preserved before reading the BRAM memory module in the background, providing reliable and lossless raw data for the real-time monitoring of the subsequent display components and the fault location of the data monitoring component 1, significantly improving the current quality monitoring accuracy and fault tracing efficiency of the distributed photovoltaic microgrid.

[0043] Specifically, after the distributed photovoltaic power generation device 2 injects the sampling stream into the FPGA chip 122, the internal logic of the chip first performs a single clock cycle judgment on the abnormal operating status bit that accompanies the frame: if the bit is 0, it means that the inverter is in the normal operating range, and the FPGA immediately enables the cyclic overwrite write pointer to write the complete sampling data into the cyclic overwrite storage area of ​​the DDR3 storage chip 121 in a first-in-first-out manner, continuously retaining the waveform of the most recent fixed duration, which ensures that the background can retrieve historical trends at any time, and avoids the storage space being filled without limit; if the abnormal operating status bit is 1, the write pointer immediately switches to the abnormal sampling data storage area, and subsequent data of the same channel is continuously written until the abnormal flag is removed or the preset segment length is reached, thereby completely latching the current state before and after the fault, eliminating the segment loss problem caused by "over-limit - communication delay - data refresh" in the traditional solution. Meanwhile, the FPGA performs hardware-level sampling of the received SFP data stream, downsampling the original 100kHz samples by taking one out of every 100 samples to obtain 1kHz low-sampling-rate data, which is then written to the 1kHz low-sampling-rate storage area of ​​the on-chip BRAM in real time. This low-sampling stream is periodically read by the data monitor CPU 11 through the PCIe interface 124 to drive the display component to scroll and refresh the current curve, allowing maintenance personnel to observe the latest operating conditions with millisecond-level latency without waiting for large data back from the background. Through a hardware pipeline of "first determine the status, then divide the path, and downsample and buffer simultaneously," the system achieves cyclical refresh of normal waveforms, permanent recording of abnormal segments, and smooth display of real-time curves without increasing the software burden on the inverter side, significantly improving the fault visibility and maintenance response speed of distributed photovoltaic microgrids.

[0044] The data monitoring component 1 is configured to perform the following steps by executing a computer program stored internally:

[0045] S1, acquire the data in the BRAM memory module of the FPGA component, and perform judgment processing on the data;

[0046] S2, when the abnormal operating status bit is determined to be abnormal or a high sampling rate data reading instruction for a specific time period is detected by the host computer, the data reading instruction is sent to the FPGA component through the PCIe interface 124 and the BRAM memory module.

[0047] S3: The high-sampling-rate data in the batch storage area of ​​the DDR3 memory chip 121 transmitted by the FPGA component according to the data read command is obtained, the received data is stored in the hard disk module 16, and transmitted to the host computer via the Ethernet interface 17 for display using a data monitor. Here, Ethernet is used for further data transmission (to other computers), and the display on the host computer is completed independently by the data monitor. (The host computer is a software host computer within the data monitor.)

[0048] Specifically, in this embodiment, the data monitor CPU 11, while cyclically reading 1kHz low sampling rate data from the BRAM memory module through the PCIe interface 124 and its driver, judges the abnormal operating status bit attached to each frame. Once an abnormal bit is detected, or a high sampling rate data read instruction for a specific time period is received from the host computer via the Ethernet interface 17, the CPU immediately sends a data read instruction to the FPGA through the PCIe interface 124. After receiving the instruction, the FPGA selectively retrieves the corresponding segments from the high sampling rate data batch storage area of ​​the DDR3 memory chip 121 according to the instruction issued by the data monitor, relays them through the BRAM, and sends them back to the CPU in packets. The CPU writes the returned data to the hard disk module 16. The data monitor and the FPGA network card achieve non-real-time complete transmission of 100kHz high sampling rate data within a specific time period through an interrogation-response method. The data is then sent to the host computer for display via the Ethernet interface 17, enabling further data transmission. The data monitor can realize functions such as quality classification and fault device location of the distributed photovoltaic microgrid system by monitoring the current data of multiple devices. Therefore, the system only triggers high sampling rate data back transmission when there is an anomaly or when the host computer requests it, which reduces the bus load and ensures that key waveforms are archived and displayed in a timely manner, thereby improving the fault visibility and maintenance efficiency of distributed photovoltaic microgrids.

[0049] In summary, this system uses a tower-type data monitor with multiple FPGA network cards inserted in parallel. Each network card is directly connected to the host CPU via PCIe x8 and interconnected point-to-point with each photovoltaic inverter via an eight-channel lens-type SFP optical port through fiber optic cable 3, forming a star-shaped high-speed acquisition topology. The FPGA network cards internally receive the instantaneous AC current value, timestamp, and abnormal status bits uploaded by the inverters at a rate of 100 kHz in real time, and immediately write them to the local DDR3 cache. The loop overlay area continuously stores the most recent data of a fixed duration, while the abnormal area locks short segments before and after the fault, implementing a "cache first, then arbitrate" mechanism. The FPGA's on-chip BRAM is divided into a 1 kHz low-sampling real-time channel and a 100 kHz high-sampling non-real-time channel. The CPU reads back the high-sampling segments on demand via PCIe in a question-and-answer manner, while simultaneously refreshing the low-sampling waveform in real time at a rate of 1 kHz for local display and rapid over-limit alarms. The data monitor writes the complete waveform to disk. The TB hard drive forwards data to the upper-level platform via 10 Gigabit Ethernet for subsequent ripple, harmonic, and transient stability analysis, and enables precise fault location based on multi-device current sequences. The system solves the problems of peak loss, bandwidth conflicts, and timestamp misalignment inherent in traditional low-speed polling. It can capture sudden changes in current ripple within millisecond-level windows, providing a reliable data foundation for the high-quality operation and maintenance of distributed microgrids. Furthermore, it addresses the data congestion problem associated with high-sampling-rate data aggregation from multiple devices to some extent, providing a reliable data acquisition platform for monitoring data quality and fault diagnosis of distributed devices.

[0050] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A high-speed data acquisition system for a distributed device, characterized in that, include: The system includes a data monitoring component, a display component, a distributed component, and an FPGA component. The output of the distributed component is connected to the input of the FPGA component, the data terminal of the FPGA component is connected to the data terminal of the data monitoring component, and the display terminal of the data monitoring component is electrically connected to the input of the display component. The DDR3 memory chip's cyclic overlay memory area and abnormal sampling data storage area are divided into multiple sections, which are used for data storage of multiple distributed photovoltaic power generation devices. The data monitoring component is configured to perform the following steps by executing a computer program stored internally: Data is acquired from the BRAM memory module in the FPGA component, and the data is then processed and evaluated. When the abnormal operating status bit is determined to be abnormal or a high sampling rate data reading command for a specific time period is detected by the host computer, a data reading command is sent to the FPGA component through the PCIe interface and the BRAM memory module. The high-sampling-rate data in the DDR3 memory chip transmitted by the FPGA component according to the data read command is obtained in batches and stored in the storage area. The received data is stored in the hard disk module and transmitted to the host computer through the Ethernet interface for display using a data monitor. Before acquiring the data within the BRAM memory module of the FPGA component, the process also includes: When a distributed photovoltaic power generation device generates electricity via inverter, it collects voltage and current data on both the AC and DC sides in real time at a preset sampling rate. A preliminary judgment is made on the local operating status to obtain the abnormal operating status bit, where an abnormal operating status bit of 1 indicates an abnormality and an abnormal operating status bit of 0 indicates normality. The distributed photovoltaic power generation device is controlled to send the acquisition rate data, timestamp data, and abnormal operation status bits to the FPGA chip in real time through optical fiber and SFP photoelectric conversion module. After receiving the acquisition rate data, timestamp data and abnormal operating status bit sent by the distributed photovoltaic power generation device, the FPGA chip judges the abnormal operating status bit. When the abnormal operating status bit is determined to be 0, the received data is stored in the cyclic overwrite storage area of ​​the DDR3 memory chip using the cyclic overwrite storage method. When the abnormal operation status bit is determined to be 1, the data is stored in the abnormal sampling data storage area; The received SFP data is stored at a sampling rate of 1kHz in the 1kHz low sampling rate storage area of ​​the FPGA chip.

2. The high-speed data acquisition system for a distributed device according to claim 1, characterized in that, The data monitoring component includes a data monitor CPU, a PCIe card slot, a memory module, a hard disk module, an Ethernet interface, and a display interface. The data monitor CPU is connected to the FPGA component through the PCIe card slot. The data terminal of the data monitor CPU is electrically connected to the data terminals of the memory module and the hard disk module. The data monitor CPU communicates with an external host computer through the Ethernet interface. The data monitor CPU is connected to the display component through the display interface.

3. The high-speed data acquisition system for a distributed device according to claim 2, characterized in that, The distributed component includes multiple distributed photovoltaic power generation devices and optical fibers, with each distributed photovoltaic power generation device connected to the FPGA component via an optical fiber.

4. The high-speed data acquisition system for a distributed device according to claim 3, characterized in that, The FPGA component includes multiple high-speed FPGA network cards corresponding to the distributed photovoltaic power generation device. Each high-speed FPGA network card includes multiple DDR3 memory chips, an FPGA chip, multiple SFP photoelectric conversion modules, and a PCIe interface. The PCIe interface is connected to a PCIe card slot. The FPGA chip is connected to the data monitor CPU through the PCIe interface. The FPGA chip is connected to the distributed photovoltaic power generation device through the SFP photoelectric conversion modules and optical fibers. The data terminal of the FPGA chip is electrically connected to the data terminal of the DDR3 memory chip.

5. The high-speed data acquisition system for a distributed device according to claim 4, characterized in that, The FPGA chip's built-in BRAM memory module is divided into a 1kHz low sampling rate storage area and a 100kHz high sampling rate storage area. The 1kHz low sampling rate storage area and the 100kHz high sampling rate storage area are further divided into multiple intervals, which are used for data storage of multiple distributed photovoltaic power generation devices.

6. The high-speed data acquisition system for a distributed device according to claim 2, characterized in that, The display assembly includes a display and a display connection cable, wherein the display is connected to a display interface via the display connection cable.

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