Implementation method of LabVIEW-based Sic power semiconductor dipulse test software
By optimizing the hardware design and software integration with the LabVIEW platform, the problems of measurement accuracy, response speed, compatibility, and automation in the power semiconductor dual-pulse test system were solved, achieving efficient and accurate testing and data analysis.
Patent Information
- Application Number
- CN202510611484.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-13
- Publication Date
- 2025-12-23
AI Technical Summary
Existing power semiconductor dual-pulse test systems suffer from problems such as insufficient measurement accuracy, slow response speed, poor equipment and software compatibility, complex operation, and low degree of automation. In particular, the test results are prone to large errors under high frequency, high voltage, or high current conditions, and the system has low stability and efficiency.
By optimizing hardware design and software integration with the LabVIEW platform, modular hardware structure, signal conditioning, and data processing are achieved, providing an intuitive user interface and automated operation functions. Combined with intelligent algorithms to analyze test data, test accuracy, response speed, system compatibility, and automation level are improved.
It significantly improves testing accuracy and response speed, enhances system compatibility and stability, simplifies operation procedures, increases automation, reduces human error, and achieves efficient automated testing and data analysis.
Smart Images
Figure CN121187628A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power semiconductor double-pulse testing technology, specifically to an implementation method of SiC power semiconductor double-pulse testing software based on LabVIEW. Background Technology
[0002] With the continuous development of modern power electronics technology and the increasing demand for high efficiency, the importance and need for double-pulse testing are gradually increasing. The software implementation method for double-pulse testing of power semiconductors based on LabVIEW mainly involves performing double-pulse testing on power semiconductors through the LabVIEW platform. This method can measure parameters such as switching characteristics, conduction characteristics, and switching losses of power semiconductors under specific conditions. This testing method involves designing dedicated testing instruments and data acquisition equipment, and writing programs on the LabVIEW platform to implement signal control, data acquisition, and processing.
[0003] Disadvantages of existing technology: Insufficient test accuracy: Existing dual-pulse test systems may have problems with low measurement accuracy, especially under high frequency, high voltage or high current, the accuracy of the test signal may be affected to a certain extent, thus leading to errors in the test results.
[0004] Slow response speed: Traditional testing systems may be insufficient in real-time data processing or rapid response capabilities. Due to the high-frequency switching characteristics involved, these systems may be limited in processing speed and real-time performance, resulting in poor timeliness of test results.
[0005] Equipment and software compatibility issues: In existing systems, the hardware and software may not work together tightly enough, leading to poor system stability and difficulty in achieving precise control and data acquisition. Particularly in terms of hardware expandability, adding new measurement modules may impact system compatibility and stability.
[0006] Complex operation: Traditional testing systems may require operators to have high levels of professional knowledge and skills, and the user interface is not user-friendly, making them difficult to use.
[0007] Low level of automation: Existing technologies may require a lot of manual intervention, resulting in a low level of automation and intelligence in the testing process, making it impossible to achieve efficient automated testing and result analysis.
[0008] Therefore, in order to correct the above-mentioned defects, we propose an implementation method for SiC power semiconductor double-pulse test software based on LabVIEW. Summary of the Invention
[0009] This invention addresses the technical problem by proposing a LabVIEW-based method for implementing dual-pulse testing software for SiC power semiconductors, achieving the following: 1. Improved testing accuracy: Through optimized hardware design and precise signal conditioning, combined with LabVIEW's powerful data processing capabilities, this invention significantly improves testing accuracy, reduces errors, and ensures accurate measurement of the switching characteristics and losses of power semiconductors; 2. Enhanced response speed: Through efficient signal acquisition and real-time data processing technology, this invention significantly improves the system's response speed, enabling rapid acquisition and analysis of high-frequency pulse signals, adapting to rapidly changing switching behavior; 3. Enhanced system compatibility: This invention designs a more modular hardware structure, allowing for seamless integration between different devices and software modules, enhancing system compatibility and stability, and facilitating hardware expansion and upgrades; 4. Simplified operation process: This invention optimizes the interface design on the LabVIEW platform, providing a more intuitive and user-friendly interface, and adds automated operation functions, reducing operational difficulty, improving testing efficiency, and reducing human error; 5. Increased automation level: This invention designs an automated testing process and combines intelligent algorithms to analyze test data, enabling efficient automated testing, data acquisition, and analysis, greatly improving the automation level of the testing process and reducing manual intervention.
[0010] To achieve the above objectives, the present invention provides the following technical solution: a method for implementing SiC power semiconductor double-pulse testing software based on LabVIEW, mainly including software integrated control and calculation of various configuration parameters in the software. The software-integrated control is based on LabVIEW for switching between three channels: signal generator, oscilloscope, discharge resistor, and inductor UVW. The software-integrated control includes configuring the parameters of the signal generator and oscilloscope, bus voltage, pulse width configuration, selecting the required test phase, and controlling start and stop. The calculation of each configuration parameter in the software is mainly based on the analysis and calculation of the .csv file data obtained from the test. The calculation of each configuration parameter in the software is based on the csv file data automatically exported by the oscilloscope, which is divided into Vgs (gate voltage), Ids (drain source current), Vds (drain source voltage), Ids_Upper (upper MOSFET drain source current), and Vds_Upper (lower MOSFET drain source voltage). Each parameter is analyzed according to the calculation formula and the calculation difficulties.
[0011] Furthermore, the parameters exported from the Csv file are based on the set StartTime, T1, T2, T3, and StopTime to determine the time nodes. The activation parameters are calculated based on the edge of the second activation, with the time node being StartTime+T1+T2. The deactivation parameters are calculated based on the edge of the first deactivation, with the time node being StartTime+T1. The reverse recovery parameters are calculated based on the edge of the second activation, with the time node being StartTime+T1+T2.
[0012] Furthermore, for the calculation of each configuration parameter in the aforementioned component, the basic parameters must first be obtained, including the Idsm channel current test value, the gate turn-on voltage test value Vgm, and the VDC bus voltage. The Vgm gate turn-on voltage test value is calculated from the average of the two turn-on voltage test values; The bus voltage VDC is calculated from the average of the three bus voltages. The Idsm channel current test value is obtained from the falling edge of the first turn-on time node, and the IF value is obtained by averaging the Idsm channel current test values.
[0013] Furthermore, the control principle for the pulse width configuration is as follows: Adjust the width of the first pulse to obtain the required switching current; The current at the moment the second pulse width turns on is equivalent to the current at the moment the first pulse turns off.
[0014] Furthermore, the activation parameters for Vgs are as follows: Rise time tr: During the second activation, I d =0.1I dsm ~0.9I dsm Time; Activation delay td(on): When activating for the second time, V gs =0.1V gm ~I d =0.1I dsm Time; Turn-on voltage change rate dv / dton: V during the second turn-on ds =0.7V dc ~0.5V dc The rate of change of voltage within the range; Rate of change of turn-on current di / dton: During the second turn-on, I d =0.1I dsm ~0.9I dsm The rate of change of current within the range; Enabling loss Eon: I d =0.1I dsm~V ds =0.1V dc Within a certain time period, The integral; System parasitic inductance (The magnitude of parasitic inductance not only affects the transient voltage and current of the chip, but also its heat dissipation): During the second turn-on, measure the di / dt of the IGBT collector current Ic, and simultaneously measure the drop ΔVce in the Vce waveform of this bridge arm. When measuring di / dt, a relatively straight segment of the Ic waveform should be selected to avoid distortion. After determining the above parameters, the system parasitic inductance is: .
[0015] Furthermore, the activation parameters for Vgs are as follows: Off delay td(off): V gs =0.9V gm ~I d =0.9I dsm Time; Fall time tf: I d =0.9I dsm ~0.1I dsm Time; Shutdown time tooff: T f +T d(off) ; Turn-off loss Eoff: V ds =0.1V dc~ I d =0.1I dsm Within a certain time, V ds *I d The integral; Rate of change of turn-off current di / dtoff: I d =0.9I dsm ~0.1I dsm The rate of change of current within the range; Turn-off voltage change rate dv / dtoff: V ds =0.5V dc ~0.7V dc The rate of change of voltage within the range.
[0016] Furthermore, the reverse recovery parameters of Vgs are as follows: Reverse recovery voltage spike Vmax: The voltage spike VF (i.e., Vgsm) generated on the diode by stray inductance. It is the voltage spike generated on the diode by stray inductance after the second turn-on of the IGBT and the reverse recovery current. di / dt of reverse recovery current: The rate of change of the diode reverse recovery current from 90% of the rated current (IF) to 90% of the peak reverse recovery current (IRRM) during the second turn-on of the IGBT and the leading edge of the reverse recovery current; Peak power of reverse recovery loss: The product curve of VF and Irr can be obtained by using the Math function of an oscilloscope. The maximum value of this curve when the IGBT is turned on for the second time is the peak power of reverse recovery loss. VF: That is, Vgm.
[0017] Compared with the prior art, the beneficial effects of the present invention are: 1. Improved testing accuracy: By optimizing hardware design and precise signal conditioning, combined with LabVIEW's powerful data processing capabilities, this invention can significantly improve testing accuracy, reduce errors, and ensure accurate measurement of the switching characteristics and losses of power semiconductors.
[0018] 2. Improved response speed: Through efficient signal acquisition and real-time data processing technology, this invention can significantly improve the system's response speed, enabling rapid acquisition and analysis of high-frequency pulse signals and adapting to rapidly changing switching behavior.
[0019] 3. Enhanced system compatibility: This invention features a more modular hardware structure, enabling seamless integration between different devices and software modules, enhancing system compatibility and stability, and facilitating hardware expansion and upgrades.
[0020] 4. Simplified operation process: This invention optimizes the interface design on the LabVIEW platform, provides a more intuitive and user-friendly interface, and adds automated operation functions to reduce the difficulty of operation, improve testing efficiency, and reduce human error.
[0021] 5. Enhanced Automation: This invention designs an automated testing process and combines it with intelligent algorithms to analyze test data, enabling efficient automated testing, data collection and analysis, greatly improving the automation level of the testing process and reducing manual intervention. Attached Figure Description
[0022] Figure 1 This is a diagram illustrating the software integration control in this invention; Figure 2 This is a parameter diagram exported from the Csv file in this invention; Figure 3 The waveforms of various parameters of this invention are shown below; Figure 4 This is a waveform diagram of the Vgm gate turn-on voltage test value in this invention; Figure 5 This is a waveform diagram of the bus voltage VDC in this invention; Figure 6 This is a waveform diagram of Idsm in this invention; Figure 7 This is the IF waveform diagram in this invention; Figure 8 This is a diagram illustrating the reverse recovery parameters in this invention; Figure 9 The diagram shows the reverse recovery waveform in this invention, where the dashed waveform represents the current on the MOS transistor, and the arrow represents the reverse recovery process. Figure 10 This is a waveform diagram of the reverse recovery of the lower current of the MOS transistor in this invention; Figure 11 This is the reverse recovery voltage spike diagram in this invention; Figure 12 This is an enlarged view of the reverse recovery voltage spike in this invention. Detailed Implementation
[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0024] This invention provides a technical solution: A method for implementing a LabVIEW-based dual-pulse test software for Sic power semiconductors is presented, which solves the technical problems of software implementation and parameter calculation for dual-pulse testing of power semiconductors using LabVIEW-based signal generators, oscilloscopes, and discharge mechanisms.
[0025] The parameter calculation is based on the pulse width of the double pulse, the time interval between the double pulses, the sampling rate, etc.
[0026] The parameter calculations include turn-on parameters, turn-off parameters, and reverse recovery parameters. Turn-on parameters include turn-on positive voltage, turn-on negative voltage, rise time, turn-on delay, turn-on time, maximum turn-on current, rate of change of turn-on current, rate of change of turn-on voltage, turn-on loss, and parasitic inductance. Turn-off parameters include turn-off negative voltage, fall time, turn-off delay, turn-off time, rate of change of turn-off voltage, rate of change of turn-off current, turn-off loss, peak turn-off voltage, and peak turn-off current. Reverse recovery parameters include reverse recovery current, reverse recovery voltage spike, reverse recovery charge, reverse recovery time, reverse recovery energy, IF current, and rate of change of IF current.
[0027] Specifically: In terms of software integration and control, the three-channel switching of signal generator, oscilloscope, discharge resistor, and inductor UVW is based on LabVIEW, and the parameter calculation is mainly based on the analysis and calculation of the .csv file data obtained from the test.
[0028] Firstly, in terms of software integration and control, such as Figure 1 As shown, the left side shows the parameter configuration of the signal generator and oscilloscope, the selection of the phase to be tested, and the start and stop of the test. It also realizes the conduction and cut-off of the discharge resistor circuit branch. Simply put, you only need to configure the parameters of the signal generator and oscilloscope, the bus voltage, the pulse width configuration, select the required test phase, and control the start and stop. The other steps have been written into the program and automatically compiled, making the operation simple.
[0029] For parameter calculations, based on the CSV file data automatically exported by the oscilloscope, the parameters are divided into Vgs (drive voltage), Ids (drain-source current), Vds (drain-source voltage), Ids_Upper (upper MOSFET drain-source current), and Vds_Upper (lower MOSFET drain-source voltage), such as... Figure 1 The right side (incomplete, to be supplemented later) analyzes various parameters based on the calculation formula and the difficulties in calculation. The parameters are shown in the lower right corner of the figure, including all the parameters mentioned in Part 1.
[0030] The parameters exported from the .csv file are based on the set StartTime, T1, T2, T3, StopTime, and other time nodes. The activation parameters are calculated based on the edge of the second activation, with a time node of StartTime + T1 + T2. The deactivation parameters are calculated based on the edge of the first deactivation, with a time node of StartTime + T1. The reverse recovery parameters are calculated based on the edge of the second activation, with a time node of StartTime + T1 + T2. Because the probe acquisition has a delay, probe delay calibration must be performed before testing. This is crucial for the accuracy of the subsequent data acquisition time nodes. After calibration, waveform acquisition and parameter calculation can proceed. (e.g.) Figure 2 The pink waveform represents Ids (drain current), the yellow waveform represents Vgs (gate voltage), and the blue waveform represents Vds (drain voltage). Figure 3 The green waveform in the middle is Ids_Upper (upper transistor drain current). (ld: channel current, Idsm: channel current test value; Vgs: gate voltage, Vgm: gate turn-on voltage test value; Vds: drain-source voltage, VDC: bus voltage.
[0031] First, basic parameters need to be obtained, such as the Idsm channel current test value, the gate turn-on voltage test value Vgm, and the VDC bus voltage, etc. Figure 4 As shown, the red highlighted position represents the Vgm gate turn-on voltage test value, which is calculated from the average of the two turn-on voltage test values. Figure 5 As shown, the red highlighted area represents the bus voltage VDC, which is calculated from the average of the three bus voltages. Figure 6 As shown, the red-marked position is Idsm, which is obtained from the starting point of the falling edge of the first activation time node, as shown below. Figure 7 As shown, the red-highlighted position is IF, which is obtained from the average value of Idsm.
[0032] The above is the overall plan. The following content introduces the principles and details that need attention.
[0033] The control principle of two pulse widths: Adjust the first pulse width to obtain the required switching operating current. The second pulse should be as short as possible. The current at the moment the second pulse turns on is equivalent to the current at the moment the first pulse turns off (due to the change in current of the load inductance).
[0034] The activation parameters for Vgs are as follows: Rise time tr: During the second activation, I d =0.1I dsm ~0.9I dsm Time; Activation delay td(on): When activating for the second time, V gs =0.1V gm ~I d =0.1I dsm Time; Turn-on voltage change rate dv / dton: V during the second turn-on ds =0.7V dc ~0.5V dc The rate of change of voltage within the range; Rate of change of turn-on current di / dton: During the second turn-on, I d =0.1I dsm ~0.9I dsm The rate of change of current within the range; Enabling loss Eon: I d =0.1I dsm ~V ds =0.1V dc Within a certain time period, The integral; System parasitic inductance (The magnitude of parasitic inductance not only affects the transient voltage and current of the chip, but also its heat dissipation): During the second turn-on, measure the di / dt of the IGBT collector current Ic, and simultaneously measure the drop ΔVce in the Vce waveform of this bridge arm. When measuring di / dt, a relatively straight segment of the Ic waveform should be selected to avoid distortion. After determining the above parameters, the system parasitic inductance is: .
[0035] The activation parameters for Vgs are as follows: Off delay td(off): V gs =0.9V gm ~I d =0.9I dsm Time; Fall time tf: I d =0.9I dsm ~0.1I dsm Time; Shutdown time tooff: T f +T d(off) ; Turn-off loss Eoff: V ds =0.1V dc~ I d =0.1I dsm Within a certain time, V ds *I d The integral; Rate of change of turn-off current di / dtoff: I d =0.9I dsm ~0.1I dsm The rate of change of current within the range; Turn-off voltage change rate dv / dtoff: V ds =0.5V dc ~0.7V dc The rate of change of voltage within the range.
[0036] like Figure 8 As shown, the reverse recovery parameters of Vgs are as follows: The reverse recovery parameter is used to evaluate whether the SiC MOSFET is in a safe operating region. The turn-on time of the lower IGBT is the key time to examine the switching characteristics of the anti-parallel diode of the upper IGBT. The lower IGBT is selected for calculation.
[0037] Reverse recovery voltage spike Vmax: The voltage spike VF (i.e., Vgsm) generated on the diode by stray inductance. It is the voltage spike generated on the diode by stray inductance after the second turn-on of the IGBT and the reverse recovery current. di / dt of reverse recovery current: The rate of change of the diode reverse recovery current from 90% of the rated current (IF) to 90% of the peak reverse recovery current (IRRM) during the second turn-on of the IGBT and the leading edge of the reverse recovery current; Peak power of reverse recovery loss: The product curve of VF and Irr can be obtained by using the Math function of an oscilloscope. The maximum value of this curve when the IGBT is turned on for the second time is the peak power of reverse recovery loss. VF: That is, Vgm.
[0038] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A method for implementing LabVIEW-based Sic power semiconductor double-pulse test software, characterized in that: Mainly including software integrated control and software in each configuration parameter calculation, The software integrated control is based on LabVIEW to switch signal generator, oscilloscope, discharge resistance and inductance UVW three ways, and the software integrated control is configured with parameters of the signal generator and the oscilloscope, bus voltage, pulse width configuration, required test phase selection and start-stop control. The software in each configuration parameter calculation is mainly based on analysis and calculation of the.csv file data obtained by testing, and the.csv file data automatically exported by the oscilloscope is divided into Vgs, Ids, Vds, Ids_Upper and Vds_Upper according to the calculation formula and calculation difficulty analysis of each parameter.
2. The implementation method of Sic power semiconductor double pulse test software based on LabVIEW according to claim 1, characterized in that: The parameters exported by the Csv file are based on the time nodes of StartTime, T1, T2, T3 and StopTime, the turn-on parameter is calculated according to the second turn-on edge, the time node is StartTime+T1+T2, the turn-off parameter is calculated according to the first turn-off edge, the time node is StartTime+T1, and the reverse recovery parameter is calculated according to the second turn-on edge, the time node is StartTime+T1+T2.
3. The implementation method of Sic power semiconductor double pulse test software based on LabVIEW according to claim 1, characterized in that: For the calculation of each configuration parameter in the piece, the basic parameters including Idsm channel current test value, gate turn-on voltage test value Vgm and VDC bus voltage are first obtained. The Vgm gate turn-on voltage test value is calculated by the average of two turn-on voltage test values. The bus voltage VDC is calculated by the average of three bus voltage values. The Idsm channel current test value is obtained from the starting point of the first turn-on time node falling edge, and the IF value is obtained by the average of the Idsm channel current test value.
4. The implementation method of Sic power semiconductor double pulse test software based on LabVIEW according to claim 1, characterized in that: The control principle of the pulse width configuration is as follows: Adjust the first pulse width to obtain the required switching working current; The current at the second pulse width opening moment is equivalent to the current at the first pulse turn-off.
5. The implementation method of Sic power semiconductor double pulse test software based on LabVIEW according to claim 1, characterized in that: The turn-on parameter of Vgs is as follows: Rise time tr: time for the current to reach 0.9 I from 0.1 I d on the second turn-on dsm dsm Turn-on delay td(on): the time from the second turn-on to V gs = 0.1 V gm ~I d = 0.1 I dsm = 0.1 I Turn-on voltage change rate dv / dt on : second time, V ds = 0.7 V dc = 0.5 V dc dv / dt on : 0.5 V Turn-on current change rate di / dton: second time, I d = 0.1 I dsm ~ 0.9 I dsm current change rate within the range Turn-on loss Eon: I d = 0.1 I dsm V ds = 0.1 V dc over a time period of the integral of System parasitic inductance (The size of the parasitic inductance will not only affect the transient voltage and current of the chip, but also affect the heat loss of the chip): the second time, measure the di / dt of the IGBT collector current Ic, and measure the drop△Vce in the Vce waveform of this bridge arm. In the process of measuring di / dt, a straight section of Ic waveform needs to be selected to avoid distortion. After the above parameters are determined, the system parasitic inductance is: 。 6. The method for implementing LabVIEW-based Sic power semiconductor double-pulse test software according to claim 1, characterized in that: The turn-on parameter of Vgs is as follows: Turn-off delay td(off): V gs = 0.9V gm ~I d = 0.9I dsm time; fall time tf: 1 d = 0.9 I dsm ~ 0.1 I dsm time; Turn-off time toff: T f + T d(off) ; Turn-off loss Eoff: V ds = 0.1 V dc~ I d = 0.1 I dsm over a time of V ds * I d integral; Turn-off current change rate di / dtoff: I d = 0.9 I dsm ~ 0.1 I dsm a current change rate within the range Off voltage change rate dv / dtoff: V ds = 0.5 V dc ~ 0.7 V dc a voltage change rate within a range of 7. The method for implementing LabVIEW-based Sic power semiconductor double-pulse test software according to claim 1, characterized in that: The reverse recovery parameter of Vgs is as follows: Reverse recovery voltage peak Vmax: the voltage peak VF (i.e. Vgsm) generated by the stray inductance on the diode after the second turn-on of the IGBT and the reverse recovery current, the voltage peak generated by the stray inductance on the diode; Reverse recovery current di / dt: the current change rate in the time period from the rated current (IF) 90% to the reverse recovery current peak value (IRRM) 90% before the second turn-on of the IGBT and the reverse recovery current; Reverse recovery loss peak power: the product curve of VF and Irr can be obtained by the Math function of the oscilloscope, and the maximum value of the curve at the second turn-on of the IGBT is the reverse recovery loss peak value; VF: i.e. Vgm.