A display method, electronic equipment and readable storage medium

Abstract

The application relates to the technical field of terminals, in particular to a display method, an electronic device and a readable storage medium. In the method, if it is detected that the electronic device is in an abnormal display scenario when running an application program, for example, the frequency of a crystal oscillator is abnormal or the display frame rate of the application program is a display frame rate corresponding to a non-fixed frame rate position, so that the processor works at a high working frequency, the display frame rate sent to the processor is gradually reduced until the working frequency of the processor corresponds to the load of the processor and is in a normal range, that is, there is no abnormal display scenario. In this way, the power consumption of the electronic device can be reduced and the heating problem can be improved.

Description

Technical Field

[0001] This application relates to the field of terminal technology, and in particular to a display method, electronic device, and readable storage medium. Background Technology

[0002] When electronic devices run high-performance applications, such as games, these applications can display their visuals at different frame rates. The frame rate refers to the number of frames displayed per second. Normally, games use a fixed frame rate tier to ensure stable display across different hardware configurations. For example, fixed frame rate tiers might include 30 frames per second (FPS), 60 FPS, 70 FPS, 90 FPS, and 120 FPS.

[0003] However, in some scenarios, if an application's frame rate is abnormal, the electronic device's scheduling system will send a higher frame rate than the application actually requires to the processor to generate and display the corresponding image. For example, the application might actually require a target frame rate of 66 FPS, but the electronic device's scheduling system might send a fixed frame rate of 70 FPS, close to 66 FPS, to the processor to generate and display the corresponding image. The processor is the core execution unit of the scheduling system, responsible for executing tasks and process scheduling specified by the system. Therefore, when the scheduling system sends an increased frame rate to the processor to generate and display the image, the processor's operating frequency also increases, leading to increased power consumption and increased processor heat.

[0004] Furthermore, when a processor overheats, it will activate a frequency reduction protection mechanism to lower the temperature, which means reducing the processor's operating frequency. This can cause stuttering or lag in electronic devices, for example... Figure 1 A schematic diagram of a game application interface is shown, such as... Figure 1 As shown in the game interface 101 of the mobile phone 10, the game application interface is lagging and prompts the user that the game interface is loading, which affects the user's gaming experience. Summary of the Invention

[0005] To address the aforementioned problems, this application provides a display method, an electronic device, and a readable storage medium.

[0006] In a first aspect, embodiments of this application provide a display method, the method comprising: detecting that a first application running on an electronic device is in an abnormal display scenario, wherein the abnormal display scenario includes: the processor of the electronic device meets a frequency adjustment condition, wherein the frequency adjustment condition is related to the processor's load rate and operating frequency; reducing a first display frame rate to be sent to the processor to a second display frame rate, and sending the second display frame rate to the processor, wherein the second display frame rate is used by the processor to control the display screen of the first application.

[0007] It can be understood that the first display frame rate may refer to the display frame rate applied when the first application that makes the electronic device run is in an abnormal display scenario, as mentioned in the embodiments of this application.

[0008] Based on the display method provided in this application, when an electronic device is running an application with high performance requirements, by detecting the processor's load and operating frequency, it is possible to quickly identify abnormal display scenarios when the electronic device is running the application, and adjust the display frame rate sent to the processor for different abnormal display scenarios. This allows the processor's operating frequency to decrease accordingly with the decrease in the display frame rate, effectively improving the increased power consumption and heat generation problem of the electronic device caused by the processor being in a state of continuous low load and high frequency.

[0009] In one possible implementation of the first aspect above, the frequency adjustment conditions include: the load rate of the processor running the first application is within a first load rate range, and the processor's operating frequency is not within a first operating frequency range, wherein the first operating frequency range corresponds to the first load rate range.

[0010] In this embodiment, the first load rate range can refer to the preset load range corresponding to the low load mentioned in this embodiment, and the first operating frequency range can refer to the preset frequency range corresponding to the low frequency mentioned in this embodiment. When the electronic device is running under low load, the corresponding operating frequency of the electronic device is usually also low. If the electronic device is running under low load, but the processor of the electronic device is running at a high frequency, it can be said that the current electronic device is in an abnormal display state and the processor is in a high power consumption state.

[0011] In one possible implementation of the first aspect described above, the processor includes multiple processing cores, and the load rate of the processor running the first application is determined by: determining the processor load rate based on the sum of the core load rates of the multiple processing cores, wherein the core load rate of the first processing core among the multiple processing cores is related to the highest operating frequency of the first processing core, the operating frequency at which the first processing core runs the first application within a first duration, and the duration for which the first processing core runs at each operating frequency.

[0012] In this embodiment, the processor may include multiple processing cores, such as small cores, medium cores, large cores, T cores, and super-large cores. When the electronic device runs a first application, the processing of different threads of the first application can be based on different processing cores. Therefore, the sum of the core load rates of each processing core when running the first application is the processor load rate, which is also the processor load rate when running the first application.

[0013] In one possible implementation of the first aspect above, the core load rate of the first processing core is determined by: obtaining the first equivalent computing power of the first processing core in the processor, wherein the first equivalent computing power is the ratio of the highest operating frequency of the first processing core to the highest operating frequency of a reference processing core in the processor, and the reference processing core is the processing core with the highest computing power in the processor; obtaining the first computing power sum of the first processing core when running the first application within a first duration, wherein the first computing power sum is the sum of the computing power of the first processing core when running the first application at least once within the first duration based on the first operating frequency; the core load rate of the first processing core is the product of the first equivalent computing power and the first computing power.

[0014] In this embodiment of the application, taking a small core as an example, the first equivalent computing power can refer to R mentioned in this embodiment of the application. (小核) The equivalent computing power R of small cores (小核) =F max(小核) / F max(超大核) Among them, F max(小核) This refers to the highest frequency of the small core, F. max(超大核) This refers to the highest frequency of the super-large core. It can be understood that the equivalent computing power of the small core can be calculated by using the highest frequency of the super-large core as a reference frequency.

[0015] Furthermore, the computing power of the processing core at various operating frequencies when running the first application and the C mentioned in the embodiments of this application... (小核) "Task" can refer to the first application, or the thread of the first application. The computing power of the task running at various frequencies of the small core can also refer to the C mentioned in the embodiments of this application. (小核) C (小核) =(F1) (小核) / F max(小核) )*T1 (小核) +…+(Fn (小核) / F max(小核) )*Tn (小核) Specifically, Fn (小核) It can refer to the frequency at which the task runs on the small core, Tn (小核) This refers to the duration for which a task runs at a certain frequency on a small core, C. (小核) It can be calculated by summing the computing power corresponding to each working frequency of the task running on the small core.

[0016] Based on this, the product of the equivalent computing power of the small core and the sum of the computing power of the processing core at each operating frequency when running the first application is used as the core load rate of the small core when running the first application.

[0017] It is understandable that, given that a processor comprises multiple processing cores, the calculation of the load rate for other cores such as medium cores, large cores, tertiary cores, and super-large cores can refer to the calculation process for the load rate of small cores described above. Furthermore, the processor load rate of an electronic device running the first application can be the sum of the core load rates of the first application running on each processing core.

[0018] In one possible implementation of the first aspect above, the electronic device includes a frame rate control module and a scheduling module; detecting that the first application running on the electronic device is in an abnormal display scenario includes: the scheduling module acquiring the processor's load rate and operating frequency, and sending them to the frame rate control module; the frame rate control module determining that the first application running on the electronic device is in an abnormal display scenario based on the load rate and operating frequency; the frame rate control module reducing the first display frame rate to a second display frame rate, and sending the second display frame rate to the scheduling module, and the scheduling module sending the second display frame rate to the processor.

[0019] In one possible implementation of the first aspect described above, the electronic device further includes a display synthesis module; reducing the first display frame rate to be sent to the processor to a second display frame rate and sending the second display frame rate to the processor includes: a frame rate control module acquiring the first display frame rate, and the frame rate control module sending a query message to the display synthesis module to query the time interval of the hardware VSYNC signal; the display synthesis module responding to the query message acquiring the time interval of the hardware VSYNC signal and sending the time interval of the hardware VSYNC signal to the frame rate control module; the frame rate control module determining whether the time interval of the hardware VSYNC signal is greater than or equal to (1 / first display frame rate); the frame rate control module determining that the time interval of the hardware VSYNC signal is greater than or equal to (1 / first display frame rate), and reducing the first display frame rate to the second display frame rate using a first debugging parameter; and the frame rate control module sending the second display frame rate to a scheduling module, and the scheduling module sending the second display frame rate to the processor.

[0020] It is understood that the first debugging parameter may refer to 0.1 FPS or the like mentioned in the embodiments of this application, and is not limited here.

[0021] It is understood that the first display frame rate may refer to 60Hz mentioned in the embodiments of this application, and the second display frame rate may refer to 59Hz mentioned in the embodiments of this application, without limitation.

[0022] In this embodiment, the frame rate anomaly monitoring module only obtains the hardware VSYNC signal from the display synthesis module 301 via the binder when it detects that it is currently in an abnormal display scene, instead of continuously monitoring the hardware VSYNC signal, which can reduce the waste of communication resources.

[0023] In one possible implementation of the first aspect above, the frame rate control module determines whether the time interval of the hardware VSYNC signal is greater than or equal to (1 / first display frame rate), and further includes: the frame rate control module determines that the time interval of the hardware VSYNC signal is less than (1 / first display frame rate), and uses the second debugging parameter to reduce the first display frame rate to the third display frame rate, and the frame rate control module sends the third display frame rate to the scheduling module, and the scheduling module sends the third display frame rate to the processor.

[0024] It is understood that the second debugging parameter may refer to 1 FPS or the like mentioned in the embodiments of this application, and is not limited here.

[0025] It is understood that the first display frame rate may also refer to 70Hz mentioned in the embodiments of this application, and the third display frame rate may refer to 66Hz mentioned in the embodiments of this application, without limitation.

[0026] Secondly, embodiments of this application provide a display method, the method comprising: displaying the display screen of a first application at a first display frame rate; detecting that the first application is in an abnormal display scenario, wherein the abnormal display scenario includes at least one of an abnormal crystal oscillator frequency of the electronic device and a display frame rate of the first application not belonging to a preset frame rate; and displaying the display screen of the first application at a second display frame rate.

[0027] In one possible implementation of the second aspect above, detecting that the first application is in an abnormal display scenario includes: acquiring the time interval of the hardware VSYNC signal, and determining whether the time interval of the hardware VSYNC signal is greater than or equal to (1 / first display frame rate); corresponding to the time interval of the hardware VSYNC signal being greater than or equal to (1 / first display frame rate), determining that the crystal oscillator frequency of the electronic device is abnormal; corresponding to the time interval of the hardware VSYNC signal being less than (1 / first display frame rate), determining that the display frame rate of the first application does not belong to at least one of the preset frame rates.

[0028] In one possible implementation of the second aspect above, determining that the crystal oscillator frequency of the electronic device is abnormal when the time interval corresponding to the hardware VSYNC signal is greater than or equal to (1 / first display frame rate) includes: reducing the first display frame rate based on the first debugging parameters to obtain a second display frame rate, and displaying the display screen of the first application at the second display frame rate.

[0029] In one possible implementation of the second aspect above, the time interval corresponding to the hardware VSYNC signal is less than (1 / first display frame rate), determining that the display frame rate of the first application does not belong to at least one of the preset frame rates includes: reducing the first display frame rate based on the second debugging parameter to obtain a third display frame rate, and displaying the display screen of the first application at the third display frame rate; wherein, the first debugging parameter is less than the second debugging parameter.

[0030] Thirdly, embodiments of this application provide an electronic device including a processor and a memory, the memory including physical memory and secondary memory, for storing instructions executed by one or more processors of the electronic device; and the processor for executing the instructions to implement the display method provided by the first aspect and various possible implementations of the first aspect, the second aspect, and various possible implementations of the second aspect.

[0031] Fourthly, embodiments of this application provide a readable storage medium storing instructions that, when executed on an electronic device, cause the electronic device to perform the display method provided by the first aspect and various possible implementations of the first aspect, the second aspect, and various possible implementations of the second aspect.

[0032] Fifthly, embodiments of this application also provide a computer program product, including a computer program / instruction that, when executed by a processor, implements the display method provided by the first aspect and various possible implementations of the first aspect, the second aspect, and various possible implementations of the second aspect.

[0033] The beneficial effects of the third to fifth aspects mentioned above can be referred to the relevant descriptions in the first aspect and its various possible implementations, as well as the second and third aspects, which will not be repeated here. Attached Figure Description

[0034] Figure 1 A schematic diagram of the interface of a game application is shown according to the method provided in the embodiments of this application;

[0035] Figure 2 An architecture diagram of an electronic device is shown based on the method provided in the embodiments of this application;

[0036] Figure 3A A schematic diagram illustrating the display frame rate when running a game application is shown according to the method provided in the embodiments of this application.

[0037] Figure 3B According to the method provided in the embodiments of this application, a pie chart of CPU operating frequency when running a game application is shown.

[0038] Figure 4AA schematic diagram of a signal under an abnormal crystal oscillator frequency state is shown according to the method provided in the embodiments of this application.

[0039] Figure 4B According to the method provided in the embodiments of this application, a schematic diagram of the display frame rate when running a game application is shown;

[0040] Figure 4C According to the method provided in the embodiments of this application, a pie chart of the CPU operating frequency when running a game application is shown;

[0041] Figure 5 According to the method provided in the embodiments of this application, an interactive schematic diagram of various modules in an electronic device architecture is shown;

[0042] Figure 6 A flowchart illustrating a display method is shown based on the method provided in the embodiments of this application.

[0043] Figure 7 A schematic diagram of a scenario for launching a game application is shown according to the method provided in the embodiments of this application;

[0044] Figure 8 According to the method provided in the embodiments of this application, a flowchart illustrating a query for CPU load information and frequency information is shown.

[0045] Figure 9 A schematic diagram of the structure of an electronic device 100 is shown according to the method provided in the embodiments of this application. Detailed Implementation

[0046] The illustrative embodiments of this application include, but are not limited to, a display method, an electronic device, and a readable storage medium.

[0047] It is understood that the electronic devices in the embodiments of this application may also be referred to as terminals, user equipment (UE), mobile stations (MS), mobile terminals (MT), etc. Terminal devices may be mobile phones, smart TVs, wearable devices, tablets, computers with wireless transceiver capabilities, virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, etc.

[0048] It is understood that the embodiments of this application are applicable to various applications installed in electronic devices, such as high-performance applications like game applications, video playback applications, and video editing applications. For ease of description, the following description uses a game application as an example, but is not limited to game applications.

[0049] The following explains some of the terms or concepts used in the embodiments of this application.

[0050] (1) Display frame rate

[0051] Display frame rate refers to the number of frames displayed per second during video playback or screen display. The unit of display frame rate is FPS, which is the number of frames displayed per second. Common display frame rates include 30 FPS, 60 FPS, 70 FPS, 90 FPS, 120 FPS, etc. In short, the higher the display frame rate, the more frames are displayed per second, and the faster the frame output speed.

[0052] (2) Output frame

[0053] Frame output refers to generating and displaying image frames at a certain display frame rate. In scenarios such as video games, animation production, and video playback, the process by which electronic devices generate image frames at a certain display frame rate and output them to a monitor or screen for display is called frame output.

[0054] As mentioned earlier, if an application's frame output is abnormal, the electronic device's scheduling system will control the processor to generate and display the corresponding frame rate at a rate higher than the application's actual display frame rate. The processor is the core execution unit of the scheduling system, responsible for executing tasks and process scheduling specified by the system. Therefore, when the scheduling system controls the processor to generate and display the corresponding frame rate at a rate higher than the application's actual display frame rate, the processor's operating frequency will also increase, leading to increased power consumption and overheating of the electronic device's processor.

[0055] The following is based on Figure 2 The diagram of the electronic device illustrates the specific process by which the scheduling system control processor generates and displays the corresponding screen.

[0056] It is understandable that the scheduling system mentioned above can refer to the following text. Figure 2 The scheduling module 402 shown is shown.

[0057] In this embodiment of the application, Android can be used TMThe system architecture is divided into four main layers: the application layer, the native layer, the hardware abstraction layer (HAL), and the hardware layer. Each layer is responsible for different functions and tasks, and they work together to realize Android. TM The system's full functionality.

[0058] Application layer 20 may include a series of application packages. For example, in this embodiment, the application package may include game application 201.

[0059] The local layer 30 may include a display compositing module (serfaceflinger) 301 and a frame rate monitoring module 302, etc. The display compositing module 301 is mainly responsible for receiving image frames from the application and then sending them to the hardware composer (HWC) 401 for compositing. The frame rate control module 302 can issue the display frame rate to the scheduling module 402 when scheduling relevant processes of the application.

[0060] The hardware abstraction layer 40 may include a hardware compositor 401, a scheduling and management (artificial intelligence, AI) module 402, etc. The hardware compositor 401 receives image frames from the display compositing module 301 and composites them into an image to be displayed. Furthermore, the hardware compositor 401 can return the image to be displayed to the display compositing module 301, which then sends it to the display module 501 for display. The scheduling module 402 can receive the display frame rate from the frame rate control module 302 and then forward it to the central processing unit 502.

[0061] Hardware layer 50 may include a display module 501 and a central processing unit 502. The display module 501 can display the image to be displayed sent by the display compositing module 301. It can be understood that the display module 501 may refer to a display device such as a liquid crystal display (LCD) or an OLED display. The central processing unit 502 can control the display compositing module 301, the hardware compositor 401, and the display module 501 to collaboratively generate and display the corresponding screen of the application based on the display frame rate issued by the scheduling module 402.

[0062] In some solutions, if a game application experiences frame rate anomalies, such as when the target display frame rate is a non-fixed frame rate tier (the target display frame rate could refer to the actual frame rate required by the game application), the frame rate control module 302 of the electronic device will increase the display frame rate sent to the scheduling module 402 to the nearest fixed frame rate tier. For example, if the target display frame rate of the game application is 66 FPS, the frame rate control module 302 increases 66 FPS to 70 FPS and then sends 70 FPS to the scheduling module 402. The scheduling module 402 will then control the processor to display the corresponding screen of the application based on 70 FPS. The specific process may include:

[0063] 1. The frame rate control module 302 obtains the target display frame rate of the game application. In some embodiments, the target display frame rate of the game application can be obtained based on the frame rate control module 302. For example, the target display frame rate of the game application is 66 FPS, where 66 FPS is the actual display frame rate required by the game application.

[0064] 2. If the frame rate control module 302 detects an abnormal target display frame rate in the game application, it adjusts the display frame rate sent to the scheduling management module 402. In some embodiments, if the frame rate control module 302 detects that the target display frame rate of the game application is 66 FPS, and 66 FPS is a non-fixed frame rate level, then it can be determined that the target display frame rate of the game application is abnormal. Therefore, the frame rate control module 302 can adjust 66 FPS to a fixed frame rate level of 70 FPS, which is close to 66 FPS, and send 70 FPS to the scheduling management module 402.

[0065] 3. The scheduling management module 402 sends the 70 FPS issued by the frame rate control module 302 to the central processing unit 502.

[0066] 4. The central processing unit 502 controls the corresponding screen of the display application based on the 70 FPS issued by the scheduling and management module 402.

[0067] However, because the display frame rate sent to the scheduling management module 402 is higher than the target display frame rate actually required by the game application, the scheduling module 402, which originally only needed to use a 66FPS scheduling processor to control the display of the game application's corresponding screen, now needs to use a 70FPS scheduling processor. As a result, since the central processing unit 502 is the core execution unit of the scheduling module 402, the operating frequency of the central processing unit 502 also increases, leading to increased power consumption and heat generation in the electronic device.

[0068] For example, Figure 3A This illustrates a frame rate diagram when running a game application, such as... Figure 3AAs shown in the diagram, curve 301 represents the target frame rate (FPS) actually required by the game application, and curve 302 represents the operating frequency (Hz) of the electronic device's central processing unit (CPU). Curve 301 shows that the game application actually requires a target frame rate of 66 FPS. However, curve 302 shows that during the 5 minutes of running the game application, the electronic device's CPU operating frequency remained at 2515MHz. 2515MHz is the CPU's maximum operating frequency, indicating that the CPU was running the game application at its highest frequency, thus also indicating that the current frame rate of the game application was greater than 66 FPS. Furthermore, through... Figure 3B The pie chart showing CPU operating frequency during game application operation also reveals that the CPU operates at its highest frequency of 2515MHz for 100% of the time during a certain period of game application operation. This increases the power consumption of electronic devices.

[0069] In other solutions, an abnormal crystal oscillator frequency in an electronic device can lead to a decrease in the target display frame rate of a game application. The crystal oscillator frequency provides a stable clock reference for the electronic device. An abnormal crystal oscillator frequency can cause unstable clock signals, preventing the electronic device's system from operating at the predetermined rate. This can result in a decrease in the speed of graphics rendering, data processing, and other operations, thus lowering the target display frame rate. For example, if an abnormal crystal oscillator frequency causes the application's target display frame rate to drop from 60 FPS to 59 FPS, and 59 FPS is a non-fixed frame rate, the frame rate control module 302 will increase the display frame rate sent to the scheduling module 402 to the nearest fixed frame rate level. For instance, the frame rate control module 302 might increase 59 FPS to 60 FPS and then send 60 FPS to the scheduling module 402. The scheduling module 402 will then control the processor to display the corresponding screen of the application based on 60 FPS. The specific process may include:

[0070] 1. The frame rate control module 302 obtains the target display frame rate of the game application. In some embodiments, the target display frame rate of the game application can be obtained based on the frame rate control module 302. For example, the target display frame rate of the game application is 59 FPS.

[0071] 2. If the frame rate control module 302 detects that the target display frame rate of 59 FPS in the game application is abnormal due to the abnormal crystal oscillator frequency of the electronic device, it will adjust the display frame rate sent to the scheduling module 402.

[0072] In some solutions, if the frame rate control module 302 detects that the target display frame rate of 59 FPS for the game application is not a fixed frame rate level, it can adjust 59 FPS to 60 FPS and send 60 FPS to the scheduling management module 402.

[0073] It's understandable that the crystal oscillator frequency of electronic devices is typically 60Hz. If the crystal oscillator malfunctions, its frequency will become abnormal, for example, changing from 60Hz to 59Hz. When the crystal oscillator frequency of an electronic device is abnormal, it will cause the target display frame rate of a game application to decrease, for example, from 60FPS to 59FPS. Figure 4A A schematic diagram of a signal under abnormal crystal oscillator frequency conditions is shown, such as... Figure 4A As shown, the crystal oscillator period is 16ms 882us 659ns. Under normal circumstances, the crystal oscillator frequency is 60Hz, corresponding to a period of 16.6ms. However, 16ms 882us 659ns is greater than 16.6ms, meaning (1 / 16ms 882us 659ns) is less than (1 / 16.6ms), indicating an abnormal crystal oscillator frequency that cannot reach 60Hz. An abnormal crystal oscillator frequency will reduce the target frame rate of the game application, for example, from 60FPS to 59FPS. It can be understood that the signal time interval is also called the signal period.

[0074] 3. The scheduling module 402 sends the 60 FPS issued by the frame rate control module 302 to the central processing unit 502.

[0075] 4. The central processing unit 502 controls the corresponding screen of the display application based on the 60 FPS issued by the scheduling and management module 402.

[0076] However, because the display frame rate sent to the scheduling module 402 is greater than the target display frame rate actually required when running the game application, the scheduling module 402, which originally only needed to schedule the processor at 59 FPS to control the display of the game application's corresponding screen, now needs to schedule the processor at 60 FPS to control the display of the game application's corresponding screen. Thus, since the central processing unit 502 is the core execution unit of the scheduling module 402, the operating frequency of the central processing unit 502 also increases, leading to increased power consumption and heat generation in the electronic device.

[0077] For example, Figure 4B This illustrates another example of frame rate changes when running a game application, such as... Figure 4AAs shown in the diagram, curve 401 represents the frame rate (FPS) of the game application, and curve 402 represents the CPU operating frequency (Hz) of the electronic device. Curve 401 shows that the game application's displayed frame rate is 59 FPS. However, curve 402 shows that during the 5 minutes of running the game application, the electronic device's CPU operating frequency remained at 2323MHz. 2323MHz indicates that the CPU is running the game application at a high frequency, thus suggesting that the displayed frame rate of the game application is greater than 59 FPS. Furthermore, through... Figure 4C Another pie chart showing CPU operating frequencies during game application operation also illustrates that, over a period of time while running a game application, the CPU operates at a high frequency of 2323MHz for a significant 89.94% of the time, while the CPU operates in the normal frequency range of 844MHz to 2188MHz for approximately 10.06% of the time. This increases the power consumption of electronic devices.

[0078] To address the aforementioned issues, this application provides a display method. In this method, if an abnormal display scenario is detected when an electronic device is running an application, such as a crystal oscillator malfunction or the application's display frame rate not corresponding to a fixed frame rate level, causing the processor to operate at a higher frequency, the display frame rate sent to the processor is gradually reduced until the processor's operating frequency corresponds to the processor's load and is within the normal range, i.e., there is no abnormal display scenario.

[0079] For example, in some embodiments, it can be determined whether an abnormal scenario is occurring by judging whether the processor's operating frequency corresponds to the processor's load. Specifically, in the embodiments of this application, the processor may include small cores, medium cores, T cores, and super-large cores. It can be understood that small cores, medium cores, large cores, T cores, and super-large cores are terms used in processor design to describe different core types, representing processor cores with different performance and energy efficiency levels. Small cores typically refer to energy-efficient cores, used for handling lightweight tasks such as browsing web pages and checking emails to save power and reduce device heat. Large cores typically refer to performance cores, primarily used for handling high-load tasks such as running large software, performing 3D graphics rendering, and playing games. Medium cores typically refer to cores with a performance level between small and large cores, mainly suitable for medium-load scenarios. T cores typically refer to a specific type of core used in a specific chip or architecture. Super-large cores typically refer to high-performance processor cores, mainly used in high-end servers or workstations and other devices requiring extremely high computing power.

[0080] Furthermore, different processing cores can handle different thread tasks, including rendering threads and logic threads. That is, processor load can include rendering thread load and logic thread load. Processor load has preset load ranges and corresponding load levels. For example, low load preset range [x1, x2] corresponds to load level 1; medium load preset range [x3, x4] corresponds to load level 2; and high load preset range [x5, x6] corresponds to load level 3. In addition, different processing cores of the processor also have preset frequency ranges and corresponding frequency levels. For example, low frequency preset range [f1, f2] corresponds to frequency level 1; medium frequency preset range [f3, f4] corresponds to frequency level 2; and high frequency preset range [f5, f6] corresponds to frequency level 3.

[0081] It is understood that the specific calculation method for processor load will be explained in detail below using formula (1).

[0082] Therefore, if the processor load and frequency are detected as "low load, high frequency" when running a game application, it can be determined that the current game application is in an abnormal display scenario. Conversely, if the processor load and frequency are detected as "low load, low frequency" or "high load, high frequency," it can be determined that the current game application is in a normal display scenario.

[0083] Furthermore, in this embodiment, different reduction amounts can be used to adjust the display frame rate for abnormal display scenarios caused by different reasons. For example, for crystal oscillator malfunctions, since the error range of crystal oscillators is relatively small and the system design has a certain tolerance range, the impact on the display frame rate of game applications is relatively small when a crystal oscillator malfunctions, such as reducing the target display frame rate of the game application from 60 FPS to 59 FPS. Therefore, for abnormal display scenarios caused by crystal oscillator malfunctions, the display frame rate sent to the processor can be reduced by a first debugging parameter with a smaller adjustment range, such as 0.1 FPS. As another example, if the target display frame rate of the game application is not the display frame rate corresponding to a fixed frame rate level, for example, if the target display frame rate of the game application is 66 FPS, and the difference between the target display frame rate and the fixed frame rate level of 70 FPS is greater than 1, then for game applications whose target display frame rate is not the display frame rate corresponding to a fixed frame rate level, the display frame rate sent to the processor can be reduced by a second debugging parameter with a larger adjustment range, such as 1 FPS.

[0084] Furthermore, to determine whether the abnormal display scenario is caused by a crystal oscillator malfunction or an abnormal target display frame rate, the time interval of the hardware vertical synchronization (VSYNC) signal can be obtained. By comparing the time interval of the hardware VSYNC signal with (1 / display frame rate), the cause of the electronic device's abnormal display scenario can be determined. Here, (1 / display frame rate) refers to the time required to display one frame. The hardware VSYNC signal controls the display screen's refresh rate. In addition, the hardware VSYNC signal is, to a certain extent, a specific application and representation of the crystal oscillator signal in the display system, utilizing the accurate clock signal provided by the crystal oscillator to ensure the synchronization and smoothness of the display data. When the display screen completes the refresh of one frame, it sends a hardware VSYNC signal. Upon receiving the hardware VSYNC signal, the processor begins rendering the next frame and waits for the next hardware VSYNC signal to arrive before sending the newly rendered content for display.

[0085] Under normal circumstances, if the crystal oscillator is working properly, the time interval of the hardware VSYNC signal should be less than (1 / display frame rate), that is, the display refresh rate is greater than the display frame rate. This ensures that when the hardware VSYNC signal arrives, the processor has already completed the rendering of the frame to be displayed, and thus the rendered frame to be displayed can be displayed.

[0086] Conversely, if the crystal oscillator is faulty, the time interval of the hardware VSYNC signal will be greater than (1 / display frame rate), meaning the screen refresh rate is less than the display frame rate. In this case, when the hardware VSYNC signal arrives, the processor has not yet completed the rendering of the frame to be displayed, and therefore the frame to be displayed cannot be displayed.

[0087] Thus, after determining that the electronic device is in an abnormal display scenario, if the time interval of the hardware VSYNC signal is greater than (1 / display frame rate), it can be determined that the abnormal display scenario is caused by an abnormal crystal oscillator frequency, and the display frame rate of the game application is reduced based on the first preset parameter. If the time interval of the hardware VSYNC signal is less than (1 / display frame rate), it can be determined that the abnormal display scenario is caused by an abnormal target display frame rate of the current application, and the display frame rate of the game application is reduced based on the second preset parameter.

[0088] The above solution can quickly identify abnormal display scenarios of electronic devices by detecting processor load information and operating frequency information during game application runtime. It can also adjust the display frame rate sent to the processor for different abnormal display scenarios, thereby reducing the operating frequency of the electronic device's processor accordingly. This effectively improves the increased power consumption and heat generation problem of electronic devices caused by the processor continuously running at high frequencies.

[0089] based on Figure 2 The software architecture diagram shown is as follows: Figure 5 According to the method provided in the embodiments of this application, an interactive schematic diagram of various modules in an electronic device architecture is shown.

[0090] refer to Figure 5 In some embodiments of this application, the frame rate control module 302 may further include a frame rate anomaly monitoring module 3021 and a frame rate adjustment module 3022. The frame rate anomaly monitoring module 3021 can obtain load and frequency information of the running game application through the scheduling module 402, and determine that the running game application is in an abnormal display scenario based on the load and frequency information. Furthermore, the frame rate anomaly monitoring module 3021 needs to determine the cause of the abnormal display scenario. It obtains the hardware VSYNC signal from the display synthesis module 301 to determine the time interval of the hardware VSYNC signal, compares the time interval of the hardware VSYNC signal with (1 / display frame rate), and determines the cause. Then, the frame rate adjustment module 3022 can reduce the display frame rate sent to the scheduling module 402 using different debugging parameters for different causes, and the scheduling module 402 then sends the reduced display frame rate to the central processing unit 502.

[0091] It is understood that the software architecture of the electronic device illustrated in the embodiments of this application does not constitute a specific limitation on the electronic device. In other embodiments of this application, the electronic device may include more than Figure 2 or Figure 5 The diagram shows more or fewer components, or combinations of some components, or splitting of some components, or different arrangements of components. The components shown can be implemented in hardware, software, or a combination of software and hardware.

[0092] Based on the above Figure 5 The architecture diagram shown below, combined with... Figure 6 The flowchart shown below details the technical solution of this application.

[0093] Figure 6 A flowchart illustrating a display method is shown according to an embodiment of this application. It can be understood that... Figure 6 The process shown can be executed by electronic devices such as mobile phones. To avoid repetition, the executing entity of each step will not be described again when introducing the execution content of each step below.

[0094] refer to Figure 6 The specific process includes:

[0095] S601: Launch the game application.

[0096] In some embodiments of this application, for example, Figure 7The diagram illustrates a scenario for launching a game application. By clicking on the game application 7011 on the main interface 701 of the mobile phone 10, the mobile phone 10 launches the game application 701 and displays the game interface 702 corresponding to the game application 7011.

[0097] It is understandable that the game interface can be different game interfaces corresponding to the game application, and this is not limited here. Furthermore, for the same game application, due to differences in the complexity of different game screens, rendering requirements, scene content, and other factors, the actual target display frame rate required for different game screens will be different.

[0098] S602: Determine if the display is in an abnormal state.

[0099] In some embodiments of this application, after the game application is launched, the frame rate detection module 3021 can detect whether the game application is in an abnormal display state.

[0100] If the judgment result is yes, proceed to step S603 to obtain the time interval of the hardware VSYNC signal.

[0101] If the result is negative, the process ends.

[0102] It is understood that the frame rate anomaly detection module 3021 can determine whether the electronic device is in an abnormal display state when running a game application by obtaining CPU load and frequency information based on the scheduling module 402. Specifically, the frame rate anomaly detection module 3021 can obtain CPU load and frequency information when the electronic device is running a game application through the scheduling module 402.

[0103] For example, Figure 8 This diagram illustrates a flowchart for querying CPU load and frequency information. It can be understood that... Figure 8 The execution entity of the illustrated process can be the scheduling module 402. Specifically, it includes:

[0104] S801: Received a message querying CPU load and frequency information.

[0105] In some embodiments of this application, the scheduling module 402 receives a query message from the frame rate anomaly detection module 3021 that queries CPU load information and frequency information.

[0106] S802: Determine whether the time elapsed since the last query of CPU load and frequency information is greater than or equal to the first time elapsed threshold.

[0107] In some embodiments of this application, when the scheduling module 402 receives a query message from the frame rate anomaly detection module 3021 requesting the acquisition of CPU load information and frequency information, the scheduling module 402 can first determine whether the time elapsed since the last query of CPU load information and frequency information is greater than or equal to a first time elapsed threshold. For example, the first time elapsed threshold can be 200ms.

[0108] If the judgment result is yes, then proceed to S803 to query CPU load and frequency information.

[0109] If the result is negative, proceed to S804 to retrieve the CPU load and frequency information from the previous query.

[0110] S803: Query CPU load and frequency information.

[0111] In some embodiments of this application, when it is determined that the time elapsed since the last query of CPU load information and frequency information exceeds a first time elapsed threshold, the scheduling module 402 can re-query the current CPU load information and frequency information, and return the currently queried CPU load information and frequency information to the frame rate anomaly detection module 3021.

[0112] S804: Retrieves the CPU load and frequency information from the last query.

[0113] In some embodiments of this application, when it is determined that the time elapsed since the last query of CPU load information and frequency information is less than a first time elapsed threshold, the scheduling module 402 can directly obtain the CPU load information and frequency information queried in the last query and return the CPU load information and frequency information queried in the last query to the frame rate anomaly detection module 3021.

[0114] It is understood that the example of a first duration threshold of 200ms in this application embodiment is merely an illustrative example. In other embodiments, the first duration threshold may be other durations, which are not limited here.

[0115] In addition, in this embodiment of the application, the scheduling module 402 can calculate the CPU load information using formula (1).

[0116] task_util = [L (小核) +L (中核) +L (大核) +L (T核) +L (超大核) ]*1024 / T (窗口时间) (1)

[0117] In formula (1), `task` refers to the task threads running on different processing cores of the game application, and `task_util` refers to the total processor load during the game application's runtime. Taking `task` running on a small core as an example, L... (小核) L represents the load percentage of the task running on the small core. (小核) =R (小核) *C (小核) Among them, R (小核) C can represent the relative computing power of small cores. (小核) This can represent the sum of computing power of a task running at various operating frequencies on a small core. Furthermore, R... (小核) =F max(小核) / F max(超大核) F max(小核) This refers to the highest frequency of the small core, F. max(超大核) This refers to the highest frequency of the super-large core. C (小核) =(F1) (小核) / F max(小核) )*T1 (小核) +…+(Fn (小核) / F max(小核) )*Tn (小核) , Fn (小核) This refers to the frequency at which the task runs on the small core, Tn. (小核) This refers to the duration for which a task runs at a certain frequency on a small core, C. (小核) The computing power of the task running on each operating frequency of the small core can be summed. Then, by multiplying the relative computing power of the small core by the sum of the load rates of the task running on each frequency of the small core, the load rate of the task running on the small core can be obtained.

[0118] It's understandable that calculating the CPU load rate of a game application running on the medium core, large core, tertiary core, and super-large core can be done by referring to the process for calculating the small core load rate, which will not be repeated here. Furthermore, the load rate when running a game application can be the sum of the load rates of the game application running on the small core, the medium core, the large core, and the super-large core.

[0119] Furthermore, in formula (1), 1024 represents the maximum frequency threshold, in Hz. Window time typically refers to a certain time interval during which a game application runs. In this application, after obtaining the load rate of the game application running within the window time, it can be divided based on the maximum frequency threshold of 1024Hz, thereby determining whether the load rate of the game application running within the window time is low load, medium load, or high load, without any limitation.

[0120] In some embodiments of this application, the CPU load and frequency information can be pre-divided into three equal parts. For example, the CPU load can be divided into low, medium, and high levels. If the CPU load is in the range of [1, 321], it is considered a low load with a corresponding load level of 1; if the CPU load is in the range of [322, 644], it is considered a medium load with a corresponding load level of 1; and if the CPU load is in the range of [644, 966], it is considered a high load with a corresponding load level of 3. It is understood that the CPU load can include rendering thread load, logic thread load, etc., and is not limited here.

[0121] For example, based on task_util = [L (小核) +L (中核) +L (T核) +L (超大核) ]* / T (窗口时间) The processor load rate is obtained as x0. Multiplying x0 by 1024Hz allows the load rate to be mapped to any one of the intervals [1, 321], [322, 644], and [644, 966] mentioned above. This allows us to determine whether the processor load rate is low, medium, or high.

[0122] It is understood that the division of CPU load levels into three equal parts in this embodiment, and the numerical values ​​of each CPU load level corresponding to the interval, are merely illustrative examples. In other embodiments, the CPU load may be divided into intervals according to other equal parts, and the values ​​of each interval may be different, which is not limited here.

[0123] In addition, the frequency of the processing core in an electronic device can be divided into three equal parts. For example, the frequency of a medium-sized core or a large core can be divided into three equal parts: low frequency, corresponding to frequency level 1; medium frequency, corresponding to frequency level 2; and high frequency, corresponding to frequency level 3.

[0124] After obtaining CPU load and frequency information (i.e., CPU load and CPU operating frequency) through the scheduling module 402, the scheduling module 402 can further feed back the CPU load and CPU frequency to the frame rate anomaly monitoring module 3021. The frame rate anomaly monitoring module 3021 can compare the CPU load with a preset CPU load range to determine that the CPU load is low; and compare the CPU frequency with a preset frequency range to determine that the CPU operating frequency is high. Based on this, the frame rate anomaly monitoring module 3021 can determine that the electronic device is in an abnormal display state of "low load, high frequency" when running a game application.

[0125] In this embodiment of the application, after the frame rate anomaly monitoring module 3021 obtains CPU load information and frequency information based on the scheduling module 402, it can store the CPU load information and frequency information in its message queue.

[0126] S603: Time interval for acquiring the hardware VSYNC signal.

[0127] In some embodiments of this application, based on S604, when it is determined that the electronic device is running a game application and is in an abnormal display state of "low load, high frequency", the frame rate anomaly monitoring module 3021 obtains the time interval of the query hardware VSYNC signal through the display synthesis module 301.

[0128] It is understandable that the frame rate anomaly detection module 3021 can query the hardware VSYNC signal by communicating with the display composition module 301 via binder. The binder is an Android component. TM This is a mechanism for inter-process communication (IPC) in the system. Through the binder, the frame rate anomaly monitoring module 3021 can communicate with the display synthesis module 301 to exchange data and requests. In this embodiment, the frame rate anomaly monitoring module 3021 only sends a request to the display synthesis module 301 to query the hardware VSYNC signal via the binder when it detects an abnormal display scene, instead of continuously monitoring the hardware VSYNC signal, thus reducing the waste of communication resources.

[0129] It can be understood that the hardware VSYNC signal is a synchronization signal emitted after completing a vertical refresh cycle. This signal indicates that the display module 501 has completed one refresh cycle and is about to begin the next refresh cycle. The main function of the hardware VSYNC signal is to synchronize the refresh of the display module 501 and the frame rendering of the display compositing module 301. After the display compositing module 301 completes the rendering of a frame, it needs to wait for the arrival of the hardware VSYNC signal before sending the newly rendered frame to the display module 501 for display. For example, if the frequency of the hardware VSYNC signal is 60Hz, then the time interval of the hardware VSYNC signal is 1 second divided by 60, which is 16.67ms, meaning that the display module 501 refreshes once every 16.67ms.

[0130] S604: Determine whether the time interval of the hardware VSYNC signal is greater than (1 / display frame rate).

[0131] In some embodiments of this application, the frame rate anomaly monitoring module 3021 can compare the time interval of the acquired hardware VSYNC signal with (1 / display frame rate) to determine whether the time interval of the hardware VSYNC signal is greater than (1 / display frame rate), thereby determining the cause of the abnormal display scenario when the electronic device is running a game application. It can be understood that the display frame rate refers to the display frame rate sent to the scheduling module 402 when running a game application.

[0132] If the judgment result is yes, then proceed to step S605 and reduce the display frame rate when running the game application according to the first preset parameter.

[0133] If the judgment result is negative, proceed to step S607 and reduce the display frame rate when running the game application according to the second preset parameter.

[0134] Under normal circumstances, if the crystal oscillator frequency of the electronic device is normal, the time interval of the hardware VSYNC signal should be less than (1 / display frame rate) to ensure that the current screen refresh is completed before the next frame of data arrives. Here, (1 / display frame rate) represents the time interval between each frame. If the time interval of the hardware VSYNC signal is greater than (1 / display frame rate), then the display module 501 may not have completed the display of the current frame before receiving the next hardware VSYNC signal, resulting in the previous and next frames being displayed simultaneously. Therefore, the time interval of the hardware VSYNC signal should generally be less than (1 / display frame rate).

[0135] Therefore, after determining that the electronic device is in an abnormal display scenario when running a game application, if the time interval of the hardware VSYNC signal is greater than (1 / display frame rate), it can be determined that the abnormal display scenario is caused by the abnormal crystal oscillator frequency, and the display frame rate when running the game application is reduced based on the first preset parameter.

[0136] If the time interval of the hardware VSYNC signal is determined to be less than (1 / display frame rate), it can be determined that the current application's target display frame rate is abnormal, causing the electronic device to be in an abnormal display scenario, and the display frame rate when running the game application is reduced based on the second preset parameter.

[0137] S605: Reduce the display frame rate when running game applications according to the first preset parameter.

[0138] In some embodiments of this application, when it is determined that the abnormal display scenario of the electronic device is caused by an abnormal crystal oscillator frequency, the frame rate adjustment module 3022 can reduce the display frame rate sent to the scheduling module 402 by a first preset parameter, and send the adjusted display frame rate based on the first preset parameter to the scheduling module 402.

[0139] For example, if the first preset parameter is 0.1 FPS, and assuming the display frame rate sent to the scheduling module 402 is 60 FPS, then the frame rate adjustment module 3022 can subtract 0.1 FPS from 60 FPS to obtain 59 FPS, and send 59 FPS to the scheduling module 402. The scheduling module 402 can then send the adjusted display frame rate of 59 FPS to the central processing unit 502, which in turn controls the generation and display of the corresponding game application screen based on this 59 FPS.

[0140] In addition, after the frame rate adjustment module 3022 sends the adjusted display frame rate based on the first preset parameters to the scheduling module 402, the frame rate control module 302 can clear the CPU load information and frequency information in the message queue.

[0141] It is understood that in the embodiments of this application, the first preset parameter of 0.1 FPS is only an exemplary description. In other embodiments, the first preset parameter may also be 0.2 FPS, 0.3 FPS, etc., which are not limited here.

[0142] S606: Determine if the display is in an abnormal state.

[0143] It is understandable that the process of determining whether a display is in an abnormal state can refer to the aforementioned S602.

[0144] If the judgment result is yes, then return to S605 and reduce the display frame rate when running the game application according to the first preset parameter.

[0145] If the result is negative, the process ends.

[0146] S607: Reduce the display frame rate when running game applications according to the second preset parameter.

[0147] In some embodiments of this application, when it is determined that the abnormal display scenario of the electronic device is caused by an abnormal target display frame rate of the game application itself, the frame rate adjustment module 3022 can reduce the display frame rate sent to the scheduling module 402 by a second preset parameter, and send the display frame rate adjusted based on the second preset parameter to the scheduling module 402.

[0148] For example, if the second preset parameter is 1 FPS, and the display frame rate sent to the scheduling module 402 is 70 FPS, then the frame rate adjustment module 3022 can calculate 70 FPS - 1 FPS = 69 FPS and send 69 FPS to the scheduling module 402. It can also send 69 FPS to the central processing unit 502, and the central processing unit 502 will control the generation and display of the corresponding screen of the game application based on 69 FPS.

[0149] In addition, after the frame rate adjustment module 3022 sends the adjusted display frame rate based on the second preset parameters to the scheduling module 402, the frame rate control module 302 can clear the CPU load information and frequency information in the message queue.

[0150] It is understood that in the embodiments of this application, the second preset parameter of 1 FPS is only an exemplary description. In other embodiments, the second preset parameter may also be 2 FPS, 3 FPS, etc., which are not limited here.

[0151] Furthermore, it can be understood that in the embodiments of this application, the first preset parameter is less than the second preset parameter.

[0152] S608: Determine if the display is in an abnormal state.

[0153] It is understandable that the process of determining whether a display is in an abnormal state can refer to the aforementioned S602.

[0154] If the judgment result is yes, then proceed to S607 and reduce the display frame rate when running the game application according to the second preset parameter.

[0155] If the result is negative, the process ends.

[0156] The display method provided in this application can quickly identify abnormal display scenarios when an electronic device is running applications with high performance requirements by detecting the processor's load and frequency. The method can then adjust the display frame rate sent to the processor for different abnormal display scenarios, thereby reducing the processor's operating frequency in response to the decrease in the display frame rate. This effectively reduces the power consumption of the electronic device and improves its heat dissipation.

[0157] further, Figure 9 A schematic diagram of the structure of an electronic device 100 is shown according to some embodiments of this application. The display methods mentioned in the embodiments of this application can be implemented based on the electronic device 100.

[0158] like Figure 9As shown, the electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, a headphone jack 170D, a sensor module 180, buttons 190, a motor 191, an indicator 192, a camera 193, a display screen 194, a subscriber identification module (SIM) card interface 195, a communication device 196, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, a barometric pressure sensor 180C, a magnetic sensor 180D, an accelerometer sensor 180E, a proximity sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, and a color temperature sensor 180N, etc.

[0159] Processor 110 may include one or more processing units, such as: application processor (AP), microcontroller unit (MCU), modem processor, graphics processing unit (GPU), image signal processor (ISP), controller, video codec, digital signal processor (DSP), baseband processor, and / or neural network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors.

[0160] The controller can generate operation control signals based on the instruction opcode and timing signals to complete the control of instruction fetching and execution.

[0161] The processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in the processor 110 may store data that the processor 110 has just used or that is being reused. If the processor 110 needs to use the instruction or data again, it can retrieve it directly from the memory. This avoids repeated accesses, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0162] In some embodiments, the processor 110 may be used to execute the display methods provided in the various embodiments of this application.

[0163] USB port 130 is a USB standard compliant interface, specifically a Mini USB port, Micro USB port, or USB Type-C port. USB port 130 can be used to connect a charger to charge terminal device 100, and can also be used for data transfer between terminal device 100 and peripheral devices. It can also be used to connect headphones for audio playback. This interface can also be used to connect other electronic devices, such as AR devices.

[0164] The charging management module 140 receives charging input from the charger. While charging the battery 142, the charging management module 140 can also supply power to the terminal device 100 through the power management module 141.

[0165] The power management module 141 is used to connect the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140 to power the processor 110, internal memory 121, display 194, camera 193, and wireless communication module 160, etc.

[0166] The wireless communication function of electronic device 100 can be realized through antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, modem processor and baseband processor, etc.

[0167] Antenna 1 and antenna 2 are used to transmit and receive electromagnetic wave signals, that is, wireless carrier information.

[0168] The mobile communication module 150 can provide solutions for wireless communication, including 2G / 3G / 4G / 5G, applied to the terminal device 100. The mobile communication module 150 may include at least one filter, switch, power amplifier, low noise amplifier (LNA), etc. The mobile communication module 150 can receive electromagnetic waves via antenna 1, and perform filtering, amplification, and other processing on the received electromagnetic waves before transmitting them to a modem processor for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modem processor and convert it into electromagnetic waves for radiation via antenna 1.

[0169] The wireless communication module 160 can provide solutions for wireless communication applications on the terminal device 100, including wireless local area networks (WLANs) (such as Wi-Fi), Bluetooth (BT), near field communication (NFC), global navigation satellite system (GNSS), frequency modulation (FM), infrared (IR), and ultra-wideband (UWB). The wireless communication module 160 can be one or more devices integrating at least one communication processing module. The wireless communication module 160 can receive electromagnetic waves via antenna 2, filter and amplify the received electromagnetic waves, and transmit them to a modem processor for demodulation. The wireless communication module 160 can also amplify the signal modulated by the modem processor and convert it into electromagnetic waves for radiation via antenna 2.

[0170] Electronic device 100 implements interface display functions through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing, connected to the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations and for graphics rendering. Processor 110 may include one or more GPUs, which execute program instructions to generate or modify display information.

[0171] Display screen 194 is used to display images, videos, etc. Display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a mini-LED, a micro-LED, a micro-OLED, a quantum dot light-emitting diode (QLED), etc.

[0172] Camera 193 is used to capture still images or videos.

[0173] The external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the terminal device 100. The external memory card communicates with the processor 110 through the external memory interface 120 to perform data storage functions.

[0174] Internal memory 121 can be used to store executable program code, including instructions, such as those in the aforementioned memory 103. Internal memory 121 may include a program storage area and a data storage area. The program storage area may store the operating system, at least one application program required for a function, etc. The data storage area may store data created during the use of terminal device 100, such as control identifiers of security controls, screenshot redraw policy identifiers corresponding to security controls, and patterns, images, and text corresponding to screenshot redraw policies. In addition, internal memory 121 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, universal flash storage (UFS), etc. The processor 110 executes various functional applications of terminal device 100 by running instructions stored in internal memory 121 and / or instructions stored in memory located in processor 110.

[0175] Electronic device 100 can implement audio functions through audio module 170, speaker 170A, receiver 170B, microphone 170C, headphone jack 170D, and application processor.

[0176] Touch sensor 180K, also known as a "touch device," can be located on display screen 194. The touch sensor 180K and display screen 194 together form a touchscreen, also known as a "touchscreen." Touch sensor 180K detects touch operations applied to or near it. It transmits the detected touch operation to the application processor to determine the type of touch event. Visual output related to the touch operation can be provided through display screen 194.

[0177] Motor 191 can generate vibration alerts.

[0178] Indicator 192 can be an indicator light, used to indicate charging status, power changes, or to indicate messages, missed calls, notifications, etc.

[0179] The SIM card interface 195 is used to connect the SIM card.

[0180] It is understood that the structure of the electronic device 100 shown in the embodiments of this application does not constitute a specific limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may include more or fewer components than shown, or combine some components, or split some components, or have different component arrangements. The components shown may be implemented in hardware, software, or a combination of software and hardware.

[0181] This application also provides a program product that, when executed on a terminal device, enables the terminal device to implement the communication methods provided in the foregoing embodiments.

[0182] This application also provides a readable storage medium storing one or more programs, which, when executed by a terminal device, enable the terminal device to implement the display methods provided in the foregoing embodiments.

[0183] The embodiments disclosed in this application can be implemented in hardware, software, firmware, or a combination of these implementation methods. Embodiments of this application can be implemented as computer programs or program code executable on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0184] Program code can be applied to input instructions to execute the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor. The program code can be implemented using a high-level programming language or an object-oriented programming language to communicate with the processing system.

[0185] When necessary, the program code can also be implemented using assembly language or machine language. In fact, the mechanism described in this application is not limited to any particular programming language. In either case, the language can be a compiled language or an interpreted language.

[0186] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may be implemented as instructions carried or stored thereon on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed via a network or through other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form, including but not limited to floppy disks, optical disks, CD-ROMs, magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic cards or optical cards, flash memory, or tangible machine-readable storage for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in the form of electrical, optical, acoustic, or other forms of propagated signals. Therefore, machine-readable media includes any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a machine-readable (e.g., computer-readable) form.

[0187] In the accompanying drawings, certain structural or methodological features are shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be necessary. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular figure does not imply that such features are required in all embodiments, and in some embodiments, these features may be omitted or may be combined with other features.

[0188] It should be noted that all units / modules mentioned in the device embodiments of this application are logical units / modules. Physically, a logical unit / module can be a physical unit / module, a part of a physical unit / module, or a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important factor; the combination of functions implemented by these logical units / modules is the key to solving the technical problem proposed in this application. Furthermore, to highlight the innovative aspects of this application, the above-described device embodiments of this application have not introduced units / modules that are not closely related to solving the technical problem proposed in this application. This does not mean that the above-described device embodiments do not contain other units / modules.

[0189] It should be noted that in the examples and description of this patent, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, the phrase "comprising a defined element" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. While this application has been illustrated and described with reference to certain preferred embodiments, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the scope of this application.

Claims

1. A display method, characterized in that, The method includes: The first application running on the electronic device is detected to be in an abnormal display scenario, wherein the abnormal display scenario includes: the processor of the electronic device meets the frequency adjustment conditions. The frequency adjustment conditions include: the load rate of the processor running the first application is within a first load rate range, and the operating frequency of the processor is not within a first operating frequency range. The first operating frequency range corresponds to the first load rate range. The load rate is the sum of the core load rates of multiple core processors in the processor. The operating frequency is the operating frequency of the processor when running the first application. The first display frame rate to be sent to the processor is reduced to a second display frame rate, and the second display frame rate is sent to the processor. The first display frame rate is the display frame rate when the first application is in the abnormal display scenario, and the second display frame rate is the display frame rate obtained by reducing the first display frame rate based on the first debugging parameters. The second display frame rate is used by the processor to control the display of the first application.

2. The method according to claim 1, characterized in that, The processor includes multiple processing cores, and, The load rate of the processor running the first application is determined in the following way: The load rate of the processor is determined based on the sum of the core load rates of the multiple processing cores. The core load rate of the first processing core among the plurality of processing cores is related to the highest operating frequency of the first processing core, the operating frequency at which the first processing core runs the first application within a first time period, and the duration of the first processing core running at each operating frequency.

3. The method according to claim 2, characterized in that, The core load rate of the first processing core is determined in the following way: The first equivalent computing power of the first processing core in the processor is obtained, wherein the first equivalent computing power is the ratio of the highest operating frequency of the first processing core to the highest operating frequency of the reference processing core in the processor, and the reference processing core is the processing core with the highest computing power in the processor. The first computing power of the first processing core when running the first application within a first time period is obtained, wherein the first computing power is the sum of the computing power of the first processing core when running the first application at least once within the first time period based on a first working frequency; The core load rate of the first processing core is the product of the first equivalent computing power and the first computing power.

4. The method according to claim 1, characterized in that, The electronic device includes a frame rate control module and a scheduling module; The detection that the first application running on the electronic device is in an abnormal display scenario includes: The scheduling module obtains the processor's load rate and operating frequency, and sends them to the frame rate control module; The frame rate control module determines, based on the load rate and operating frequency, that the first application running on the electronic device is in an abnormal display scenario. The frame rate control module reduces the first display frame rate to the second display frame rate and sends the second display frame rate to the scheduling module, which then sends the second display frame rate to the processor.

5. The method according to claim 1, characterized in that, The electronic device also includes a display synthesis module; The step of reducing the first display frame rate to be sent to the processor to a second display frame rate and sending the second display frame rate to the processor includes: The frame rate control module obtains the first display frame rate, and, The frame rate control module sends a query message to the display synthesis module to query the time interval of the hardware VSYNC signal. In response to the query message, the display synthesis module obtains the time interval of the hardware VSYNC signal and sends the time interval of the hardware VSYNC signal to the frame rate control module. The frame rate control module determines whether the time interval of the hardware VSYNC signal is greater than or equal to (1 / first display frame rate). The frame rate control module determines that the time interval of the hardware VSYNC signal is greater than or equal to (1 / first display frame rate), and uses the first debugging parameter to reduce the first display frame rate to the second display frame rate. The frame rate control module sends the second display frame rate to the scheduling module, and the scheduling module sends the second display frame rate to the processor.

6. The method according to claim 5, characterized in that, The frame rate control module determines whether the time interval of the hardware VSYNC signal is greater than or equal to (1 / first display frame rate), and also includes: The frame rate control module determines that the time interval of the hardware VSYNC signal is less than (1 / first display frame rate), and uses the second debugging parameter to reduce the first display frame rate to the third display frame rate. The frame rate control module sends the third display frame rate to the scheduling module, and the scheduling module sends the third display frame rate to the processor.

7. A display method, characterized in that, The method includes: The display screen of the first application is displayed at a first display frame rate, wherein the first display frame rate is the display frame rate when the first application is in an abnormal display scenario; The first application is detected to be in an abnormal display scenario, wherein the abnormal display scenario includes at least one of the following: the crystal oscillator frequency of the electronic device is abnormal, and the display frame rate of the first application is not a preset frame rate. The detection that the first application is in an abnormal display scenario includes: Obtain the time interval of the hardware VSYNC signal, and determine whether the time interval of the hardware VSYNC signal is greater than or equal to (1 / first display frame rate). If the time interval corresponding to the hardware VSYNC signal is greater than or equal to (1 / first display frame rate), it is determined that the crystal oscillator frequency of the electronic device is abnormal. If the time interval corresponding to the hardware VSYNC signal is less than (1 / first display frame rate), it is determined that the display frame rate of the first application does not belong to at least one of the preset frame rates, wherein the preset frame rate is the display frame rate corresponding to a fixed frame rate level; In the event of an abnormal crystal oscillator frequency in the electronic device, the first display frame rate is reduced based on the first debugging parameters to obtain a second display frame rate, and the display screen of the first application is displayed at the second display frame rate. If the display frame rate of the first application is not among at least one of the preset frame rates, the first display frame rate is reduced based on the second debugging parameter to obtain a third display frame rate, and the display screen of the first application is displayed at the third display frame rate. Wherein, the first debugging parameter is less than the second debugging parameter.

8. An electronic device, characterized in that, include: The processor and memory, the memory including physical memory and secondary memory, are used to store instructions executed by one or more processors of the terminal device; And a processor, configured to execute the instructions to cause the terminal device to implement the display method according to any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by the electronic device, causes the electronic device to implement the display method according to any one of claims 1 to 7.

10. A computer program product, characterized in that, Includes a computer program / instruction that, when the computer program product is run on an electronic device, causes the electronic device to perform the display method according to any one of claims 1 to 7.

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