Electronic device

Abstract

The invention provides an electronic device which comprises a display panel, a driving circuit and a processor circuit. The display panel is used for displaying images. The driving circuit is used for driving the display panel to display an image according to the image data. The processor circuit is used for outputting image data to the driving circuit. The drive circuit outputs a request signal to the processor circuit to request the processor circuit to output the image data. The driving circuit adjusts the frame rate of the image according to the image data.

Description

Technical Field

[0001] This invention relates to an electronic device with a display function. Background Technology

[0002] With the development of display technology, display panels have been widely used in various electronic devices. In handheld electronic devices, the application processor primarily transmits image data to the display driver chip to display the image on the display panel. However, the continuous image updates of the display panel not only consume a lot of power but also reduce the usage time of handheld electronic devices. Summary of the Invention

[0003] The present invention provides an electronic device whose image frame rate can be adjusted step by step to avoid the image frame rate being directly adjusted from the initial frame rate to the target frame rate, thereby generating an excessive frame rate difference and affecting the display quality.

[0004] The electronic device of this invention includes a display panel, a driving circuit, and a processor circuit. The display panel is used to display images. The driving circuit drives the display panel to display images according to image data. The processor circuit outputs image data to the driving circuit. The driving circuit outputs a request signal to the processor circuit to request the processor circuit to output image data. The driving circuit adjusts the frame rate of the image according to the image data.

[0005] To make the foregoing better understood, several embodiments accompanied by accompanying drawings are described in detail below. Attached Figure Description

[0006] Figure 1 A schematic diagram of an electronic device according to an embodiment of the present invention is shown.

[0007] Figure 2 Show Figure 1 A block diagram of the electronic device in the embodiment.

[0008] Figure 3 Show Figure 2 A schematic diagram of the waveforms of each operation signal in the embodiment.

[0009] Figure 4 A waveform diagram of each operation signal according to another embodiment of the present invention is shown.

[0010] Figure 5 A waveform diagram of each operation signal according to another embodiment of the present invention is shown.

[0011] Figure 6 A waveform diagram of each operation signal according to another embodiment of the present invention is shown.

[0012] Figure 7 A waveform diagram of each operation signal according to another embodiment of the present invention is shown.

[0013] Explanation of icon numbers

[0014] 100: Electronic devices;

[0015] 110: Application processor;

[0016] 120: Drive circuit;

[0017] 130: Display panel;

[0018] ACT, ACT', ACT_1, ACT_2, ACT_3, ACT_4: Active frames;

[0019] CC1, CC2, CC3: Time unit signals;

[0020] cyc1, cyc2, cyc3: Time units;

[0021] DL: Time Delay;

[0022] DP: Display period;

[0023] DT, LBR, LBW, TX: Signals;

[0024] EVFP, EVFP', EVFP_N+1, EVFP_N+2, EVFP_N+3: Extended vertical leading edge period;

[0025] HSD: Image data;

[0026] HSP: Horizontal Synchronization Signal;

[0027] RD: Reading period;

[0028] T1(N), T1(N+1), T1(N+2), T1(N+3): During the frame;

[0029] T2: The time interval between frames;

[0030] T3, T4: Periods;

[0031] TE: Tear signal;

[0032] REQ, REQ_1, REQ_2, REQ_3, REQ_4: request signal;

[0033] TG: Timing-generated signal;

[0034] TP: Touch Time Unit;

[0035] TP_INT: Stop signal;

[0036] TP_TX: Drive signal;

[0037] TP_UT: Touch time signal;

[0038] VFP, VFP': During the vertical frontal period;

[0039] VBP: Vertical trailing edge period;

[0040] VS, VS': Pulses of the vertical synchronization signal;

[0041] VSP, VSP': Vertical synchronization signals;

[0042] W: Width;

[0043] WR: Write period. Detailed Implementation

[0044] The following embodiments are provided to describe the present disclosure in detail, but the present disclosure is not limited to the provided embodiments, and the provided embodiments can be suitably combined. The terms "coupling" or "connecting" as used in this specification (including the claims) may refer to any direct or indirect connection. For example, "the first device is coupled to the second device" should be interpreted as "the first device is directly connected to the second device" or "the first device is indirectly connected to the second device through other devices or connecting members." Additionally, the term "signal" may refer to current, voltage, charge, temperature, data, electromagnetic waves, or any one or more signals.

[0045] Figure 1 A schematic diagram of an electronic device according to an embodiment of the present invention is shown. Figure 2 Show Figure 1 A block diagram of the electronic device in the embodiment. Figure 3 Show Figure 2 The waveform diagrams of the various operation signals in the embodiment are shown below. Please refer to... Figures 1 to 3 The electronic device 100 includes an application processor 110, a driving circuit 120, and a display panel 130. The application processor 110 is coupled to the driving circuit 120. The driving circuit 120 is coupled to the display panel 130. In this embodiment, the application processor 110 is used as an example of a processor circuit; however, in different types of electronic devices, the processor circuit may be other hardware with processor functions.

[0046] In this embodiment, the application processor 110 outputs a vertical synchronization signal (VSP), image data (HSD), and a scan signal (EM) to the driving circuit 120. The driving circuit 120 drives the display panel 130 to display an image based on the VSP, HSD, and EM. Furthermore, the driving circuit 120 can also output a request signal (REQ) to the application processor 110, actively requesting the application processor 110 to output the image data (HSD). Then, the driving circuit 120 adjusts the frame rate of the image based on the HSD.

[0047] In electronic device 100, application processor 110 and drive circuit 120 can transmit signals via Mobile Industry Processor Interface (MIPI). The transmission modes can be mainly divided into command mode and video mode.

[0048] In command mode, the driver circuit 120, acting as either a display chip or a touch display chip, can output a tearing effect signal TE to the application processor 110 via its pins. The application processor 110 determines whether to output image data to the driver circuit 120 based on the signal level. Therefore, in command mode, the start time of each frame's data transmission can be controlled by the tearing effect signal TE. In video mode, the application processor 110 continuously outputs image data to the driver circuit 120, regardless of whether it receives the tearing effect signal TE.

[0049] In this embodiment, the driving circuit 120 can use the original tear signal TE as the request signal REQ. Whether in command mode or video mode, the driving circuit 120 can use the request signal REQ to notify the application processor 110 to output image data, thereby controlling the start time of each frame of data transmission.

[0050] Alternatively, in another embodiment, the driver circuit 120 may also have an additional pin. In video mode, the driver circuit 120 uses this additional pin to transmit a request signal REQ to the application processor 110, notifying it to output image data. In command mode, the driver circuit 120 can use the original pin to transmit a tear signal TE to the application processor 110, notifying it to output image data.

[0051] In this embodiment, the display panel 130 is, for example, an adaptive refresh panel (ARP) capable of retaining images for extended periods. The electronic device 100 with the ARP panel can operate in variable refresh rate (VRR) mode to achieve power saving. For example, the drive circuit 120 can control the image frame rate based on the image data HSD. Figure 3 In this embodiment, the initial frame rate of the image is 120Hz, and the target frame rate is 60Hz. The image frame rate can be gradually reduced from 120Hz to 90Hz, 72Hz, and finally 60Hz. This avoids directly reducing the image frame rate from the initial 120Hz to the target 60Hz, which could affect display quality. In another embodiment, the target frame rate can be reduced to as low as 1Hz. This invention does not impose any limitation on the image frame rate.

[0052] In addition, Figure 3 In this process, the vertical front porch (VFP) period between frames can be extended to gradually reduce the frame rate of the image. Specifically, T1 represents the duration of each frame, and T2 represents the time interval between each active frame. For example, the time interval T2 of the Nth frame corresponds to the VFP period, the vertical synchronization period (VS), and the VBP period. During the frame period T1(N) of the Nth frame, the frame rate of the image is 120Hz, and the high-level request signal REQ corresponds to the VFP period. The driver circuit 120 outputs a high-level request signal REQ during the time interval T2 to request the application processor 110 to prepare to transmit the image data of the N+1th frame.

[0053] Next, during frame period T1(N+1) of the (N+1)th frame, the frame rate of the image is 90Hz, and the high-level request signal REQ corresponds to the extended vertical leading edge period EVFP_N+1. The driver circuit 120 outputs the high-level request signal REQ during time interval T2 to request the application processor 110 to prepare to transmit image data in the (N+2)th frame. Here, time interval T2 of the (N+1)th frame corresponds to the vertical leading edge period EVFP_N+1, the vertical synchronization period VS, and the vertical trailing edge period VBP.

[0054] Similarly, during frame periods T1(N+2) and T1(N+3) of frames N+2 and N+3, the operation of the drive circuit 120 outputting a high-level request signal REQ in time interval T2 to request the application processor 110 to prepare to transmit image data can be carried out in the same manner. During frame periods T1(N+2) and T1(N+3) of frames N+2 and N+3, the duration of the extended vertical leading edge periods EVFP_N+2 and EVFP_N+3 is approximately equal to an integer multiple of the period of the scan signal EM, which is 2 times and 3 times respectively in this example. The duration of the high-level request signal REQ is approximately equal to one period of the scan signal EM.

[0055] Therefore, in VRR mode, the drive circuit 120 can actively request the application processor 110 to transmit the image data of the next frame through the request signal REQ during the extended vertical leading edge, so as to gradually reduce the frame rate of the image, thereby optimizing the display effect and achieving the purpose of saving power.

[0056] In this embodiment, the electronic device 100 may be an electronic device with display and touch sensing functions. In another embodiment, the electronic device 100 may be, but is not limited to, a smartphone, a non-smartphone, a wearable electronic device, a tablet computer, a personal digital assistant, a laptop computer, and other portable electronic devices that can operate independently and have display, touch sensing, and fingerprint sensing functions. In another embodiment, the electronic device 100 may be, but is not limited to, a portable or non-portable electronic device in a vehicle intelligent system. In another embodiment, the electronic device 100 may be, but is not limited to, a smart home appliance, such as a television, computer, refrigerator, washing machine, telephone, induction cooker, table lamp, etc.

[0057] In this embodiment, the application processor 110 is a processor with computing capabilities. Alternatively, the application processor 110 can be designed using a hardware description language (HDL) or any other digital circuit design method familiar to those skilled in the art, and can be a hardware circuit implemented using a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), or an application-specific integrated circuit (ASIC). Furthermore, sufficient teaching, advice, and implementation instructions regarding the hardware architecture of the application processor 110 can be obtained by referring to common knowledge in the art.

[0058] In this embodiment, the driving circuit 120 may be a RAMless touch and display driver integrated circuit (TDDI), which can drive the display panel 130 to perform display and touch sensing functions, but the present invention is not limited thereto. When the driving circuit 120 is implemented as a single-chip integrated circuit that can drive and control the display panel 130 to perform display and touch sensing operations, the display panel 130 may include a control circuit, which may be a micro-controller-based core to perform all control activities of display and touch sensing operations. The control circuit may include at least one of a timing controller, a touch controller, digital circuitry, and other controllers or processors of the display driving circuit.

[0059] In this embodiment, the display panel 130 may be a self-emissive display panel, such as an organic light-emitting diode (OLED) display panel. In other embodiments, the display panel 130 may also be a display panel including micro LEDs or mini LEDs. The display panel 130 may also be a non-self-emissive display panel, such as a liquid crystal display panel. This invention does not limit the type of display panel.

[0060] Figure 4 A waveform diagram of each operation signal according to another embodiment of the present invention is shown. Please refer to... Figure 2 and Figure 4 ,exist Figure 4 In this diagram, VSP is the vertical synchronization signal output from application processor 110 to drive circuit 120, HSP is the horizontal synchronization signal output from application processor 110 to drive circuit 120, and HSD is the horizontal synchronization data (image data) output from application processor 110 to drive circuit 120. Application processor 110 can output the above signals to drive circuit 120 through Mobile Industry Processor Interface (MIPI); however, this invention does not limit the type of signal transmission interface.

[0061] In this embodiment, during period T3, the application processor 110 continuously outputs image data HSD to the driving circuit 120 to update the image content, and the frame rate of the image is maintained at 120Hz.

[0062] Next, during period T4, the image data HSD includes multiple active frames ACT_1 to ACT_4. The driving circuit 120 can reduce the image frame rate from 120Hz to 1Hz based on the active frames ACT_1 to ACT_4. The active frames ACT_1 to ACT_4 contain information about the image content to be displayed. Therefore, the driving circuit 120 first outputs request signals REQ_1 to REQ_4 to the application processor 110 to request the application processor 110 to transmit the image data HSD. The driving circuit 120 then uses the image data HSD transmitted by the application processor 110 as the basis for frequency reduction, gradually reducing the image frame rate from 120Hz to 1Hz.

[0063] Specifically, during period T4, the driver circuit 120 outputs a request signal REQ_1 to the application processor 110, and the application processor 110 outputs an active frame ACT_1 to the driver circuit 120 accordingly. The driver circuit 120 then reduces the frame rate of the image from 120Hz to 75Hz based on the active frame ACT_1. Next, the driver circuit 120 outputs a request signal REQ_2 to the application processor 110, and the application processor 110 outputs an active frame ACT_2 to the driver circuit 120 accordingly. The driver circuit 120 then reduces the frame rate of the image from 75Hz to 20Hz based on the active frame ACT_2. Similarly, the driver circuit 120 sequentially outputs request signals REQ_3 and REQ_4 to the application processor 110, and then gradually reduces the frame rate of the image from 20Hz and 10Hz to 1Hz based on the active frames ACT_3 and ACT_4 output by the application processor 110. Therefore, in this embodiment, the driving circuit 120 can sequentially reduce the image frame rate from 120Hz, 75Hz, 20Hz, and 10Hz to 1Hz according to the active frames ACT_1 to ACT_4. In this way, the image frame rate can be directly reduced from the initial frame rate of 120Hz to the target frame rate of 1Hz, which would affect the display quality.

[0064] Furthermore, during period T4, the image content of the image data (i.e., active frames ACT_1 to ACT_4) can remain the same without being updated. Therefore, the application processor 110 can enter a sleep state to further achieve power saving.

[0065] On the other hand, TP_TX is a drive signal used by the drive circuit 120 to drive the display panel 130 to perform the touch sensing function, and TP_INT is a stop signal used by the drive circuit 120 to stop the display panel 130 from performing the touch sensing function. At this time, the display panel 130 reports the touch sensing result to the drive circuit 120. In this embodiment, the touch sensing report rate is maintained at, for example, 240Hz, but this invention is not limited thereto. Furthermore, to maintain normal reporting, the drive circuit 120 avoids the reporting time when transmitting request signals REQ_1 to REQ_4.

[0066] Figure 5 A waveform diagram of each operation signal according to another embodiment of the present invention is shown. Please refer to... Figure 5 , Figure 5 This embodiment illustrates how to determine the transmission timing and width of the request signal REQ. For example, the driving circuit 120 in this embodiment uses a long horizontal scanning timing (long H timing) mechanism to drive the display panel 130 to perform display and touch sensing functions.

[0067] Specifically, the touch time signal TP_UT indicates that the display panel 130 can be roughly divided into multiple touch units (e.g., 10), and TP represents the touch sensing time for each touch unit (hereinafter referred to as touch time unit TP). That is, the driving circuit 120 drives at least one touch unit of the display panel 130 to perform a touch sensing operation within the touch time unit TP, wherein the touch unit includes one or more touch sensing electrodes or touch sensors. When the multiple touch units complete the touch sensing operation, it indicates that the driving circuit 120 has performed a complete scan of the display panel 130. The signal TP_INT indicates that the touch sensing reporting rate in this embodiment is maintained at 240Hz.

[0068] In addition, the signal DT includes multiple display terms DP. Between every two display terms DP, there is a term called a touch term, during which the driving circuit 120 outputs a signal TX to drive the display panel 130 to perform touch sensing operations.

[0069] On the other hand, the signal LBW indicates that the application processor 110 continuously writes data to the line buffer of the driver circuit 120 during the write period WR, where the write period WR corresponds to the active frame ACT period of the image data HSD. In the signal LBR, the display panel 130 can begin touch sensing after the display data read period RD is read from the line buffer. In touch and display driver integrated circuits without random access memory, the capacity of the line buffer is usually insufficient to store the image data of an entire frame. Therefore, as indicated by the signal DT, the display time of an entire frame of image data is distributed across multiple display periods DP, and the touch sensing operation can be performed after each display period DP.

[0070] Next, in the vertical sync signal VSP (first vertical sync signal), every two pulses VS define a frame period with a frame rate of 48Hz. Each frame period includes the active frame ACT period and the extended vertical leading edge period EVFP, which is indicated in the horizontal sync data HSP. The driving circuit 120 can internally generate a vertical sync signal VSP' (second vertical sync signal) and a timing generation signal TG based on the vertical sync signal VSP and the image data HSD. The vertical sync signal VSP' and the timing generation signal TG serve as timing references within the driving circuit 120 to synchronize with the application processor 110.

[0071] Furthermore, since the application processor 110 must first write data to the line buffer and then the driver circuit 120 reads data from the line buffer, the vertical synchronization signal VSP' has a time delay DL compared to the vertical synchronization signal VSP in order to ensure that the driver circuit 120 can smoothly read data from the line buffer without timing errors. This time delay DL can be the write or read time of one or more line buffers.

[0072] Correspondingly, the driver circuit 120 can determine the timing of the falling edge of the request signal REQ based on the time length of the time delay DL preceding the pulse VS' of the vertical synchronization signal VSP'. Then, the driver circuit 120 determines the width W of the request signal REQ based on the wake-up time of the application processor 110. In this way, the driver circuit 120 can determine the transmission timing and width W of the request signal REQ.

[0073] In this embodiment, the application processor 110 outputs image data HSD to the driver circuit 120 using a default time unit cyc1. For example, to achieve high-precision frequency adjustment, after receiving the request signal REQ, the application processor 110 uses the duration of the touch time unit TP as the time unit cyc1 and outputs the vertical synchronization signal VSP and image data HSD to the driver circuit 120, as shown in the time unit signal CC1. The duration (i.e., width) of the time unit cyc1 is equal to the duration of the touch time unit TP. That is, the active frame ACT and the extended vertical leading edge period EVFP are both positive integer multiples of the time unit cyc1, and the pulse VS of the vertical synchronization signal VSP roughly corresponds to the boundary between two adjacent time units cyc1.

[0074] Therefore, the drive circuit 120 can determine the transmission timing and width W of the request signal REQ in the above manner, and output the request signal REQ to the application processor 110 during the extended vertical leading edge period of EVFP'. Then, the application processor 110 transmits the image data of the next frame using the touch time unit TP as the time unit cyc1, so as to gradually reduce the frame rate of the image, thereby optimizing the display effect and achieving the purpose of saving power.

[0075] Figure 6 A waveform diagram of each operation signal according to another embodiment of the present invention is shown. Please refer to... Figure 6 In this embodiment, the frame rate of the image is 60Hz. After receiving the request signal REQ, the application processor 110 outputs the vertical synchronization signal VSP and image data HSD to the drive circuit 120, using the duration of the active frame ACT as the time unit cyc2, as shown in the time unit signal CC2. The duration (i.e., width) of the time unit cyc2 is equal to the duration of the active frame ACT. That is, the duration of the active frame ACT and the extended vertical leading edge period EVFP are both positive integer multiples of the time unit cyc2, and the pulse VS of the vertical synchronization signal VSP roughly corresponds to the boundary between the two time units cyc2.

[0076] Figure 7 A waveform diagram of each operation signal according to another embodiment of the present invention is shown. Please refer to... Figure 7 In this embodiment, the driving circuit 120 uses a long V timing mechanism to drive the display panel 130 to perform display and touch sensing functions. The driving circuit 120 performs a single scan of the display panel 130 after a complete display period (DP). The stop signal TP_INT indicates that the touch sensing reporting rate in this embodiment remains at 120Hz.

[0077] On the other hand, in this embodiment, after receiving the request signal REQ, the application processor 110 outputs the vertical synchronization signal VSP and image data HSD to the drive circuit 120 using the sum of the active frame ACT and the vertical leading edge period VFP as the time unit cyc3, as shown by the time unit signal CC3. The duration (i.e., width) of the time unit cyc3 is equal to the sum of the active frame ACT and the vertical leading edge period VFP. That is, the sum of the active frame ACT and the vertical leading edge period VFP is a positive integer multiple of the time unit cyc3, the extended vertical leading edge period EVFP is a positive integer multiple of the time unit cyc3, and the pulse VS of the vertical synchronization signal VSP roughly corresponds to the boundary between the two time units cyc3.

[0078] Furthermore, the driver circuit 120 can determine the timing of the falling edge of the request signal REQ based on the pulse VS' of the vertical synchronization signal VSP'. In this example, the timing of the falling edge is equal to the pulse VS' of the vertical synchronization signal VSP'. Next, the driver circuit 120 determines the width W of the request signal REQ based on the wake-up time of the application processor 110. In this way, the driver circuit 120 can determine the transmission timing and width W of the request signal REQ.

[0079] In summary, in the embodiments of the present invention, frame rate control is primarily driven by the driving circuit. The driving circuit outputs a request signal to the processor circuit, which then outputs image data to the driving circuit using a default time unit. In this way, the driving circuit gradually reduces the image frame rate, which not only saves power but also prevents the image frame rate from dropping directly from the initial frame rate to the target frame rate, thus avoiding excessive frame rate differences that could affect display quality. Furthermore, to maintain normal call detection, the driving circuit avoids the call detection time when transmitting the request signal, ensuring uninterrupted touch sensing operation.

[0080] Those skilled in the art will be able to make various modifications and variations to the disclosed embodiments without departing from the scope or spirit of this disclosure. In view of the foregoing, it is intended that this disclosure cover modifications and variations, provided that such modifications and variations fall within the scope of the following claims and their equivalents.

Claims

1. An electronic device comprising: Display panel, used to display images; A driving circuit is used to drive the display panel to display the image based on the image data; as well as A processor circuit is used to output the image data to the driving circuit, wherein the driving circuit outputs a request signal to the processor circuit to request the processor circuit to output the image data, and the driving circuit adjusts the frame rate of the image according to the image data.

2. The electronic device according to claim 1, wherein the image data includes a plurality of active frames, and the driving circuit reduces the frame rate of the image according to the plurality of active frames.

3. The electronic device according to claim 2, wherein the driving circuit sequentially reduces the frame rate of the image from a first frame rate and a second frame rate to a third frame rate according to the plurality of active frames, wherein the second frame rate is lower than the first frame rate and the third frame rate is lower than the second frame rate.

4. The electronic device according to claim 3, wherein the image content of the plurality of active frames is identical.

5. The electronic device according to claim 4, wherein the processor circuit enters a sleep state.

6. The electronic device of claim 1, wherein the processor circuit outputs the image data to the driving circuit in a default time unit.

7. The electronic device according to claim 6, wherein the processor circuit outputs the image data to the driving circuit using the duration of the touch time unit as the time unit.

8. The electronic device according to claim 7, wherein the driving circuit drives at least one touch unit of the display panel to perform a touch sensing operation in the touch time unit.

9. The electronic device according to claim 6, wherein the processor circuit outputs the image data to the driving circuit using the duration of the active frame as the time unit.

10. The electronic device of claim 9, wherein the image data includes the active frame, and the active frame includes information about the image content.

11. The electronic device of claim 6, wherein the processor circuit outputs the image data to the driving circuit using the sum of the active frame and the vertical leading edge as the time unit.

12. The electronic device of claim 6, wherein the processor circuit is further configured to output a first vertical synchronization signal to the drive circuit, and the pulses of the first vertical synchronization signal correspond in timing to the boundary between two adjacent time units.

13. The electronic device of claim 1, wherein the processor circuit is further configured to output a first vertical synchronization signal to the driving circuit, the driving circuit generating a second vertical synchronization signal based on the first vertical synchronization signal, wherein the driving circuit determines the timing of the signal edge of the request signal based on the pulse of the second vertical synchronization signal.

14. The electronic device of claim 13, wherein the second vertical synchronization signal has a time delay relative to the first vertical synchronization signal, and the driving circuit further determines the timing of the signal edge of the request signal according to the time delay.

15. The electronic device of claim 13, wherein the driving circuit determines the width of the request signal based on the wake-up time of the processor circuit.

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