Display panel and display device

Abstract

This invention proposes a display panel and a display device. The display panel includes multiple rows of scan lines, multiple columns of data lines, multiple rows of signal coupling lines, and multiple sub-pixels. Each sub-pixel is connected to the data lines, scan lines, and signal coupling lines. The sub-pixel includes a thin-film transistor, a liquid crystal capacitor, and a charging / discharging capacitor. The sub-pixel operates in a first time period and a second time period. In the first time period, the pixel group receives two initial grayscale voltages and a first voltage signal. The two liquid crystal capacitors of the pixel group are charged to two initial grayscale voltages with opposite polarities. The coupling effect of the two initial grayscale voltages on the common electrode voltage cancels each other out, reducing crosstalk and flicker of the display panel. In the second time period, the pixel group receives a second voltage signal, and the two liquid crystal capacitors of the pixel group charge or discharge simultaneously, changing the grayscale voltage to the target grayscale voltage, thereby improving side-view brightness and contrast.

Description

Technical Field

[0001] This invention belongs to the field of display technology, and particularly relates to a display panel and a display device. Background Technology

[0002] With the development of display technology, a VAC technology has been proposed. VAC technology uses algorithm optimization to replace the original grayscale with high and low grayscale. While maintaining the relationship between grayscale and brightness when viewed directly, it reduces the brightness when viewed from the side, further improving the brightness and contrast when viewed from the side, and enhancing the richness of the picture.

[0003] However, after splitting the original grayscale into high and low grayscale, the parasitic capacitance coupling between the high and low grayscale in the vertical direction is enhanced, causing the voltage of the common electrode to change due to coupling, resulting in crosstalk and flickering on the display panel. Summary of the Invention

[0004] The purpose of this invention is to provide a display panel that solves the problems of crosstalk and flickering that occur when traditional display panels use VAC technology.

[0005] A first aspect of this invention provides a display panel, including multiple columns of parallel data lines and multiple rows of parallel scan lines. The multiple columns of data lines and the multiple rows of scan lines are intersected. A sub-pixel is disposed between two adjacent columns of data lines and two adjacent rows of scan lines. The sub-pixel is connected to an adjacent data line and a scan line. The display panel also includes multiple rows of signal coupling lines. A row of signal coupling lines is disposed between two adjacent rows of scan lines. The sub-pixel is also connected to an adjacent signal coupling line.

[0006] The sub-pixel includes a thin-film transistor, a liquid crystal capacitor, and a charging / discharging capacitor. The upper plate of the liquid crystal capacitor and the upper plate of the charging / discharging capacitor are connected to the corresponding data line and scan line through the thin-film transistor. The lower plate of the liquid crystal capacitor is used to input the first common electrode voltage. The lower plate of the charging / discharging capacitor is connected to the signal coupling line. Two sub-pixels in each of two adjacent columns constitute a pixel group.

[0007] Each of the sub-pixels operates sequentially in a first time period and a second time period. In the first time period, the scan line and two data lines corresponding to the pixel group input a row scan signal and two initial gray level voltages with opposite polarities. The absolute value of the voltage difference between two adjacent initial gray level voltages and the voltage of the first common electrode is equal. The signal coupling line corresponding to the pixel group inputs a first voltage signal.

[0008] During the second time period, the scan line and two data lines corresponding to the pixel group are cut off from input signals, and the signal coupling line corresponding to the pixel group is input with a second voltage signal that is opposite in polarity to the first voltage signal. The grayscale voltages of the two liquid crystal capacitors in the pixel group are charged and discharged and transformed to the first target grayscale voltage and the second target grayscale voltage with opposite polarities.

[0009] Optionally, the pixel group includes a first sub-pixel and a second sub-pixel, wherein the grayscale voltage corresponding to the first sub-pixel is a first initial grayscale voltage and a first target grayscale voltage in the first time period and the second time period, respectively, and the grayscale voltage corresponding to the second sub-pixel is a second initial grayscale voltage and a second target grayscale voltage in the first time period and the second time period, respectively.

[0010] When the first absolute value of the voltage difference between the first target gray level voltage and the first common electrode voltage is greater than the second absolute value of the voltage difference between the first initial gray level voltage and the first common electrode voltage, and the third absolute value of the voltage difference between the second target gray level voltage and the first common electrode voltage is less than the fourth absolute value of the voltage difference between the second initial gray level voltage and the first common electrode voltage, the first voltage signal is less than the second voltage signal.

[0011] When the first absolute value of the voltage difference between the first target gray level voltage and the first common electrode voltage is less than the second absolute value of the voltage difference between the first initial gray level voltage and the first common electrode voltage, and the third absolute value of the voltage difference between the second target gray level voltage and the first common electrode voltage is greater than the fourth absolute value of the voltage difference between the second initial gray level voltage and the first common electrode voltage, the first voltage signal is greater than the second voltage signal.

[0012] Optionally, the display panel includes an array substrate, a liquid crystal layer, and a color filter substrate stacked sequentially.

[0013] The array substrate is provided with the data line, the scan line, the thin film transistor, the metal layer and a plurality of pixel electrodes. The pixel electrodes are connected to the scan line and the data line respectively through the thin film transistor. The metal layer includes a plurality of metal lines arranged in an array, and each metal line is disposed opposite to a pixel electrode.

[0014] The upper electrode of the liquid crystal capacitor and the upper electrode of the charging and discharging capacitor are pixel electrodes, and the lower electrode of the charging and discharging capacitor is the metal wire.

[0015] The color filter substrate includes a first common electrode layer and a color filter layer stacked together, and the lower electrode of the liquid crystal capacitor is the first common electrode layer.

[0016] Optionally, a gate layer is disposed on the array substrate, the gate layer is disposed opposite to the pixel electrode, the gate layer is used to dispose of the scan line, and the metal line is disposed on the gate layer and spaced apart from the scan line.

[0017] A second aspect of the present invention provides a display device, including a driving circuit and a display panel as described above, wherein the driving circuit and the display panel are connected, and the driving circuit is configured to output a corresponding row scan signal, a grayscale voltage, a first voltage signal and a second voltage signal to the display panel.

[0018] Optionally, the driving circuit is specifically used for:

[0019] The original grayscale of the pixel group is obtained, and the two initial grayscale voltages, the first target grayscale voltage and the second target grayscale voltage corresponding to the pixel group are determined based on the original grayscale.

[0020] In the first time period, the line scan signal and two initial gray level voltages with opposite polarities are output to the scan line and two data lines corresponding to the pixel group, and the first voltage signal is output to the signal coupling line corresponding to the pixel group.

[0021] During the second time period, a second voltage signal is output to the signal coupling line to charge and discharge the grayscale voltages of the two liquid crystal capacitors in the pixel group and transform the first target grayscale voltage and the second target grayscale voltage.

[0022] Optionally, the driving circuit is further configured to:

[0023] Obtain the two initial grayscale voltages corresponding to each pixel group in the current row, and compare the first voltage difference between the two initial grayscale voltages of each pixel group.

[0024] The pixel group with the smallest first voltage difference is set as the target pixel group, and the second voltage difference between the first voltage signal and the second voltage signal is determined based on the first voltage difference of the target pixel group, so that the third voltage difference between the first target gray level voltage and the second target gray level voltage of each pixel group in the current row is greater than a preset value.

[0025] The product of the second voltage difference and the first voltage difference of the target pixel group is proportional to the preset value.

[0026] Optionally, the third voltage difference between the first target grayscale voltage and the second target grayscale voltage is greater than a preset value;

[0027] The driving circuit is also used for:

[0028] Obtain the first target grayscale voltage and the second target grayscale voltage corresponding to each pixel group in the current row, and compare the third voltage difference between the first target grayscale voltage and the second target grayscale voltage of each pixel group;

[0029] The pixel group with the smallest third voltage difference is set as the target pixel group, and the second initial grayscale voltage of the target pixel group is determined based on the ratio of the preset value and the second voltage difference. The second voltage difference is the voltage difference between the first voltage signal and the second voltage signal.

[0030] Optionally, the display device further includes a backlight module, and the driving circuit is also connected to the backlight module;

[0031] The driving circuit is also used for:

[0032] During the first time period, the backlight module is controlled to light up;

[0033] During the second time period, the backlight module is controlled to turn off;

[0034] In the third period following the second period, the backlight module is controlled to light up.

[0035] Optionally, the driving circuit includes:

[0036] A backlight driving circuit is connected to the backlight module. The backlight driving circuit is used to drive the backlight module to light up or turn off according to the first control signal.

[0037] The driving circuit of the display panel is connected to the display panel. The driving circuit of the display panel is used to output a corresponding row scan signal, a data signal, a corresponding first voltage signal, and a second voltage signal according to the second control signal.

[0038] The control circuit is connected to the backlight driving circuit and the display panel driving circuit respectively. The control circuit is used to output a first control signal and a second control signal according to the original grayscale of the received pixel group.

[0039] The beneficial effects of the present invention embodiments compared with the prior art are as follows: The above-mentioned display panel includes multiple rows of scan lines, multiple columns of data lines, multiple rows of signal coupling lines, and multiple sub-pixels. Each sub-pixel is connected to the data lines, scan lines, and signal coupling lines. The sub-pixel includes a thin-film transistor, a liquid crystal capacitor, and a charging / discharging capacitor. The charging / discharging capacitor is connected to the thin-film transistor and the signal coupling line, respectively. Two sub-pixels in two adjacent columns form a pixel group. The sub-pixels operate in a first time period and a second time period. In the first time period, the pixel group receives two initial grayscale voltages and a first voltage signal. The two liquid crystal capacitors of the pixel group are charged to two initial grayscale voltages with opposite polarities. The coupling effect of the two initial grayscale voltages on the common electrode voltage cancels each other out, reducing crosstalk and flicker of the display panel. In the second time period, the pixel group receives a second voltage signal. The two liquid crystal capacitors of the pixel group charge or discharge simultaneously, and the grayscale voltage changes to the target grayscale voltage, improving the side-view brightness and contrast. Attached Figure Description

[0040] Figure 1 This is a grayscale diagram of a traditional display panel that does not use VAC technology.

[0041] Figure 2 A grayscale diagram of a traditional display panel using VAC technology;

[0042] Figure 3 A schematic diagram illustrating the brightness of sub-pixels in a traditional display panel using VAC technology;

[0043] Figure 4 This is a schematic diagram of the structure of a display panel based on a traditional Stripe architecture.

[0044] Figure 5 This is a schematic diagram of the brightness of a subpixel in a traditional Stripe architecture display panel.

[0045] Figure 6 This is a schematic diagram of signal waveforms in a traditional Stripe architecture display panel;

[0046] Figure 7 This is a schematic diagram of a first structure of a display panel provided in Embodiment 1 of the present invention;

[0047] Figure 8 This is a circuit diagram of a sub-pixel provided in Embodiment 1 of the present invention;

[0048] Figure 9 This is a schematic diagram of the structure of the main pixel and the secondary pixel provided in Embodiment 1 of the present invention;

[0049] Figure 10 These are schematic diagrams of signal waveforms of the display devices provided in Embodiments 1 and 2 of the present invention;

[0050] Figure 11 This is a schematic diagram of a second structure of the display panel provided in Embodiment 1 of the present invention;

[0051] Figure 12 This is a schematic diagram of a first structure of the gate layer provided in Embodiment 1 of the present invention;

[0052] Figure 13 This is a schematic diagram of a second structure of the gate layer provided in Embodiment 1 of the present invention;

[0053] Figure 14 This is a schematic diagram of a first module of the display device provided in Embodiment 2 of the present invention;

[0054] Figure 15 This is a schematic diagram of a second module of the display device provided in Embodiment 2 of the present invention;

[0055] Figure 16 This is a schematic diagram of a third module of the display device provided in Embodiment 2 of the present invention;

[0056] Figure 17 This is a schematic diagram of the first process of the driving method for the display panel provided in Embodiment 3 of the present invention;

[0057] Figure 18 This is a schematic diagram of a second process for driving a display panel according to Embodiment 3 of the present invention;

[0058] Figure 19 This is a schematic diagram of the third process of the display panel driving method provided in Embodiment 3 of the present invention.

[0059] The figures in the diagram are labeled as follows:

[0060] 100, Display panel; 200, Driving circuit; 300, Backlight module; 210, Backlight driving circuit; 220, Driving circuit of display panel; 230, Control circuit; 110, Array substrate; 120, Color filter substrate; 130, Liquid crystal layer; 10, Sub-pixel; 11, Pixel electrode; 12, Metal line; 13, Gate layer; 101, Main pixel; 102, Sub-pixel; 103, Pixel group;

[0061] G1, First scan line; G2, Second scan line; G3, Third scan line; S1, First data line; S2, Second data line; S3, Third data line; S4, Fourth data line; Lc1, First signal coupling line; Lc2, Second signal coupling line; Lc3, Third signal coupling line;

[0062] T1, Thin Film Transistor; Clc, Liquid Crystal Capacitor; Cst, Storage Capacitor; Cps, Charge / Discharge Capacitor;

[0063] CFVCOM, first common electrode voltage; AVCOM, second common electrode voltage; LED, backlight; V1, first voltage signal; V2, second voltage signal;

[0064] t0, fourth time period; t1, first time period; t2, second time period; t3, third time period; t11, charging time of sub-pixels when the row scan signal is input. Detailed Implementation

[0065] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0066] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0067] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0068] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0069] Example 1

[0070] A first aspect of the present invention provides a display panel 100.

[0071] VAC technology's grayscale splitting refers to splitting the original grayscale (e.g., 128) into two sub-grayscale values, for example, ... Figure 1 The original grayscale levels shown are split into the following: Figure 2 The two sub-grayscale values ​​shown have different corresponding grayscale voltage values. For example... Figure 1 The original gray levels shown are 128 gray levels and can be decomposed into Figure 2 The two sub-grayscale values ​​shown are H=160 and L=96, as follows: Figure 3 As shown, the two sub-grayscale values ​​after splitting include a high value (H) and a low value (L). The grayscale voltage corresponding to the split grayscale value is assigned to two sub-pixels 10 in two adjacent columns. When the human eye looks directly at the screen, because the sub-pixels 10 are very dense, the H and L values ​​will be visually merged together and perceived as the original grayscale brightness (such as 128), but the side-view brightness and contrast are improved.

[0072] like Figure 4 As shown, Figure 4 For a stripe-structured display panel 100, the sub-pixel 10 in the i-th row and j-th column is connected to the scan line in the i-th row and the data line in the j-th column. For example, the sub-pixel 10 in the first row and first column is connected to the scan line in the first row and the data line in the first column.

[0073] When VAC technology is applied to the Stripe architecture display panel 100, such as Figure 5 As shown, the split grayscale voltage is input to sub-pixel 10, and the final display brightness of sub-pixel 10 is bright, dark, bright, dark, which causes the problem of screen crosstalk.

[0074] Specifically, such as Figure 6 As shown, taking the first data line S1 and the second data line S2 as examples, the dashed lines represent the grayscale voltage after grayscale splitting, and the solid lines represent the grayscale voltage before splitting. When scanning to the first row, the adjacent first data line S1 and the second data line S2 input grayscale voltages with opposite polarities after splitting. At this time, the common electrode voltage is coupled up, and the sub-pixel 10 corresponding to the positive polarity grayscale voltage is darker, while the sub-pixel 10 corresponding to the negative polarity grayscale voltage is brighter. When scanning to the second row, the adjacent first data line S1 and the second data line S2 input grayscale voltages with opposite polarities after splitting. At this time, the common electrode voltage is coupled down, and the sub-pixel 10 corresponding to the positive polarity grayscale voltage is brighter, while the sub-pixel 10 corresponding to the negative polarity grayscale voltage is darker. Therefore, after grayscale splitting is enabled, the positive and negative polarity coupling of the grayscale voltage to the common electrode layer is not symmetrical, and the effect of the common electrode voltage being coupled cannot be offset, resulting in crosstalk in this row.

[0075] Furthermore, since the data lines are arranged parallel to the common electrode layer, when a grayscale voltage is input to the data lines, the charge diffuses in the vertical direction, which will exacerbate the coupling changes of the common electrode voltage.

[0076] To solve the aforementioned crosstalk problem, in this embodiment, as follows: Figure 7As shown, the display panel includes multiple columns of parallel data lines and multiple rows of parallel scan lines. The multiple columns of data lines and multiple rows of scan lines are intersected. A sub-pixel 10 is provided between two adjacent columns of data lines and two adjacent rows of scan lines. The sub-pixel 10 is connected to an adjacent data line and a scan line.

[0077] The display panel adopts a Stripe architecture. Multiple parallel data lines, such as the first data line S1, second data line S2, third data line S3, and fourth data line S4, and multiple parallel scan lines, such as the first scan line G1, second scan line G2, and third scan line G3, are arranged in parallel. These multiple data lines and scan lines intersect to form multiple pixel areas. Each pixel area has a sub-pixel 10, which is connected to adjacent data lines and scan lines. Specifically, the sub-pixel 10 in the i-th row and j-th column is connected to the scan line in the i-th row and the data line in the j-th column. For example, the sub-pixel 10 in the first row and first column is connected to the first scan line G1 and the first data line S1, and the sub-pixel in the second row and second column is connected to the second scan line G2 and the second data line S2, etc. The multiple scan lines are used to connect to an external driving circuit and input row scan signals sequentially. The multiple data lines are used to connect to an external driving circuit and input multiple data signals. The sub-pixel activates upon receiving the row scan signal and generates corresponding image information under the drive of the data signal.

[0078] The display panel also includes multiple rows of signal coupling lines. A row of signal coupling lines is provided between two adjacent rows of scan lines. Sub-pixels 10 are also connected to adjacent signal coupling lines. For example, a first signal coupling line Lc1 is provided between the first scan line G1 and the second scan line G2, and a second signal coupling line Lc2 is provided between the second scan line G2 and the third scan line G3. The signal coupling lines in the i-th row are connected to each sub-pixel 10 in the i-th row. For example, each sub-pixel 10 in the first row is connected to the first signal coupling line Lc1, and each sub-pixel 10 in the second row is connected to the second signal coupling line Lc2.

[0079] Signal coupling lines are used to connect to external signal sources or drive circuits and to input high and low voltage signals.

[0080] like Figure 8 As shown, sub-pixel 10 includes a thin-film transistor T1, a liquid crystal capacitor Clc, and a charging / discharging capacitor Cps. The upper plates of the liquid crystal capacitor Clc and the charging / discharging capacitor Cps are connected to the corresponding data lines and scan lines through the thin-film transistor T1. The lower plate of the liquid crystal capacitor Clc is used to input the first common electrode voltage CFVCOM. The lower plate of the charging / discharging capacitor Cps is connected to the signal coupling line. Two sub-pixels 10 in each adjacent column constitute a pixel group 103.

[0081] Each sub-pixel 10 operates sequentially in the first time period t1 and the second time period t2. In the first time period t1, the scan line and two data lines corresponding to the pixel group 103 input the row scan signal and two initial gray level voltages with opposite polarities. The absolute value of the voltage difference between two adjacent initial gray level voltages and the first common electrode voltage CFVCOM is equal. The signal coupling line corresponding to the pixel group 103 inputs the first voltage signal V1.

[0082] During the second time period t2, the scan lines and two data lines corresponding to pixel group 103 cut off the input signals, and the signal coupling line corresponding to pixel group 103 inputs a second voltage signal V2 with the opposite polarity to the first voltage signal V1. The grayscale voltages of the two liquid crystal capacitors Clc in pixel group 103 are charged and discharged and transformed to the first target grayscale voltage and the second target grayscale voltage with opposite polarities.

[0083] In this embodiment, the first common electrode voltage CFVCOM is the common electrode voltage applied to the common electrode layer on the color filter substrate 120 in the display panel 100. Gray level voltages greater than the first common electrode voltage CFVCOM are positive gray level voltages, and gray level voltages less than the first common electrode voltage CFVCOM are negative gray level voltages.

[0084] Two sub-pixels 10 in each pair of adjacent columns form a pixel group 103. When grayscale is split using VAC, the two target grayscale voltages after splitting the original grayscale voltage are output to the two sub-pixels 10 in the pixel group 103. For example, if the original grayscale is 128 and the corresponding grayscale voltage is 8V, then the split grayscale can be 160 and 96. The sum of the grayscale after the difference is equal to twice the original grayscale, and the corresponding voltages can be 14.4V and 4.8V respectively.

[0085] Among the two target grayscale voltages after splitting, the target grayscale voltage with a larger voltage difference from the first common electrode voltage CFVCOM can be set as the first grayscale voltage, and the sub-pixel 10 corresponding to the first grayscale voltage can be defined as the main pixel 101. The target grayscale voltage with a smaller voltage difference from the first common electrode voltage CFVCOM can be set as the second grayscale voltage, and the sub-pixel 10 corresponding to the second grayscale voltage can be defined as the secondary pixel 102.

[0086] When the corresponding driving circuit 200 is working, it determines the two original gray level voltages corresponding to the first time period t1 and the first target gray level voltage and the second target gray level voltage corresponding to the second time period t2 based on the received original gray level and the corresponding original gray level voltage.

[0087] For example, if the original grayscale is 128 grayscale and the original grayscale voltage is 8V, then the first target grayscale after splitting is 160 grayscale and the second target grayscale is 96 grayscale, with corresponding first target grayscale voltages of 14.4V and 4.8V respectively. For the same sub-pixel 10, the polarity of the initial grayscale voltage and the target grayscale voltage input in the first time period t1 and the second time period t2 is the same. When the same sub-pixel 10 switches from the first time period t1 to the second time period t2, the initial grayscale voltage with positive polarity is amplified or attenuated to the target grayscale voltage with positive polarity, or the initial grayscale voltage with negative polarity is amplified or attenuated to the target grayscale voltage with negative polarity.

[0088] Meanwhile, based on the split first target grayscale voltage and the second target grayscale voltage, the two initial grayscale voltages can be determined. The voltage difference between the two initial grayscale voltages can be equal to or less than the voltage difference between the two target grayscale voltages. For example, if the two original grayscale voltages are 12V and 4V respectively, with a voltage difference of 8V, the two target grayscale voltages can be 14.4V and 4.8V respectively, with a voltage difference of 9.6V. Alternatively, the two target grayscale voltages can be 14V and 6V respectively, with a voltage difference of 8V.

[0089] When scanning to the pixel row containing pixel group 103, such as Figure 10 As shown, in the first time period t1, the scan line inputs a line scan signal, the thin-film transistor T1 of sub-pixel 10 is turned on, and two initial grayscale voltages are input to the data line. The initial grayscale voltages are transmitted to the liquid crystal capacitor Clc and the charging / discharging capacitor Cps via the thin-film transistor T1. The voltage differences between the two initial grayscale voltages and the first common electrode voltage CFVCOM are opposite and equal in absolute value. For example, if the first common electrode voltage CFVCOM is 8V, the two initial grayscale voltages are 12V and 4V respectively, and the voltage differences are 4V and -4V respectively. The two initial grayscale voltages are input to... In sub-pixel 10, simultaneously, the signal coupling line inputs a first voltage signal V1, such as a low-level signal. At this time, the liquid crystal capacitor Clc and the charging / discharging capacitor Cps are charged. Here, t11 represents the charging time of sub-pixel 10 when the row scan signal is input. The charge is distributed according to the capacitance ratio. At this time, the data lines of two adjacent columns input two initial grayscale voltages with opposite polarities and equal voltage differences compared to the first common electrode voltage CFVCOM. The coupling effect of the first common electrode voltage CFVCOM cancels each other out, reducing crosstalk and flicker of the display panel 100.

[0090] Then, the line scan moves to the next line, and sub-pixel 10 enters the second time period t2. Sub-pixel 10 in this line stops receiving the line scan signal and data signal. At this time, the signal coupling line inputs the second voltage signal V2. The charge stored in the charging and discharging capacitor Cps is released through the capacitive coupling effect, and the sub-pixel 10 is charged or discharged. For example, if a high-level signal is input, the charging and discharging capacitor Cps discharges and the charge is superimposed on the liquid crystal capacitor Clc. The gray level voltage of the liquid crystal capacitor Clc rises to the target gray level voltage. Correspondingly, the two sub-pixels 10 in the pixel group 103 are transformed to the first target gray level voltage and the second target gray level voltage, respectively. For example, the initial gray level voltage of 12V is increased to 14.4V, and the corresponding first target gray level is 160 gray level. The other initial gray level voltage of 4V is increased to 4.8V, and the corresponding second target gray level is 96 gray level. This achieves high and low gray level separation and improves the side-view brightness and contrast.

[0091] Different original gray levels correspond to different target gray level voltages. Therefore, the target gray level voltage may be amplified or attenuated compared to the initial gray level voltage. Correspondingly, the first voltage signal V1 and the second voltage signal V2 can be selected according to the changing direction of the target gray level voltage and the initial gray level voltage.

[0092] In an optional embodiment, the pixel group 103 includes a first sub-pixel and a second sub-pixel. The grayscale voltage corresponding to the first sub-pixel is a first initial grayscale voltage and a first target grayscale voltage in the first time period t1 and the second time period t2, respectively. The grayscale voltage corresponding to the second sub-pixel is a second initial grayscale voltage and a second target grayscale voltage in the first time period t1 and the second time period t2, respectively.

[0093] The corresponding driving circuit 200 can input voltage signals of corresponding magnitudes in the first time period t1 and the second time period t2, respectively, according to the change direction of the initial gray level and target gray level voltage of each sub-pixel 10.

[0094] Among them, such as Figure 9As shown, taking two sub-pixels 10 in the first row, first column, and second column as examples, the first sub-pixel in the first row, first column is the primary pixel 101, which has higher brightness, and the second sub-pixel in the first row, second column is the secondary pixel 102, which has lower brightness. The first absolute value of the voltage difference between the first target grayscale voltage and the first common electrode voltage CFVCOM is greater than the second absolute value of the voltage difference between the first initial grayscale voltage and the first common electrode voltage CFVCOM, and the third absolute value of the voltage difference between the second target grayscale voltage and the first common electrode voltage CFVCOM is less than the voltage difference between the second initial grayscale voltage and the first common electrode voltage CFVCOM. When the fourth absolute value is reached, that is, the target gray level voltage of the first sub-pixel and the second sub-pixel is pulled up compared to the initial gray level voltage. At this time, the first sub-pixel and the second sub-pixel need to be charged in the second time period t2. That is, in the first time period t1, the first voltage signal V1 is a low level signal, and in the second time period t2, the second voltage signal V2 is a high level signal. By changing the voltage signal magnitude of the signal coupling line, the terminal voltage of the charging and discharging capacitor Cps is increased, thereby charging the liquid crystal capacitor Clc, so that the first sub-pixel reaches the first target gray level voltage corresponding to the main pixel 101, and the second sub-pixel reaches the second target gray level voltage corresponding to the secondary pixel 102.

[0095] Conversely, taking the two sub-pixels 10 in the second row, first column, and second column as examples, the first sub-pixel in the first row, second column is the primary pixel 101, which has higher brightness, while the second sub-pixel in the first row, first column is the secondary pixel 102, which has lower brightness. The first absolute value of the voltage difference between the first target grayscale voltage and the first common electrode voltage CFVCOM is less than the second absolute value of the voltage difference between the first initial grayscale voltage and the first common electrode voltage CFVCOM, and the third absolute value of the voltage difference between the second target grayscale voltage and the first common electrode voltage CFVCOM is greater than the voltage difference between the second initial grayscale voltage and the first common electrode voltage CFVCOM. At the fourth absolute value, that is, the target gray level voltage of the first sub-pixel and the second sub-pixel shifts down compared to the initial gray level voltage. At this time, the first sub-pixel and the second sub-pixel need to be charged in the second time period t2. That is, the first voltage signal V1 is a high level signal in the first time period t1, and the second voltage signal V2 is a low level signal in the second time period t2. By changing the magnitude of the voltage signal of the signal coupling line, the terminal voltage of the charging and discharging capacitor Cps is lowered, thereby discharging the liquid crystal capacitor Clc, so that the second sub-pixel reaches the second target gray level voltage corresponding to the main pixel 101, and the first sub-pixel reaches the first target gray level voltage corresponding to the secondary pixel 102.

[0096] The magnitudes of the first voltage signal V1 and the second voltage signal V2 can be set according to requirements. For example, the voltage of the second voltage signal V2 is 3V and the voltage of the first voltage signal V1 is 0V.

[0097] The size of the charging and discharging capacitor Cps can be set according to requirements. In order to ensure that the gray level voltage of sub-pixel 10 is coupled and amplified to the target gray level in the second time period t2, in an optional embodiment, the capacitance of the charging and discharging capacitor Cps is 1.5 to 2 times that of the liquid crystal capacitor Clc.

[0098] For example, if the initial grayscale voltage is 12V, when switching to the second voltage signal V2 in the second time period t2, the voltage change of the liquid crystal capacitor Clc is ΔV=(V0*Clc) / (Clc+Cps), where V0 represents the change in the level signal. If the capacitance of the liquid crystal capacitor Clc is 30fF, then the capacitance of the charging and discharging capacitor Cps is 45fF-60fF. This ensures that the gain of the initial grayscale voltage in the second time period t2 meets the requirements, such as a gain of 1.2 times, to compensate the low grayscale difference of the data line input to a high grayscale difference, while avoiding excessive capacitance that could cause response delay.

[0099] Meanwhile, the signal coupling line and the data line are arranged orthogonally to avoid the generation of cross parasitic capacitance, and the frequency of the level signal on the signal coupling line changes in the first time period t1 and the second time period t2 respectively, and its driving frequency is twice the frequency of the data signal on the data line.

[0100] Furthermore, in order to store the charge during data writing, such as Figure 8 As shown, sub-pixel 10 also includes a storage capacitor Cst, the upper plate of which is connected to the thin-film transistor T1, and the lower plate of which is used to input the second common electrode voltage AVCOM.

[0101] The second common electrode voltage AVCOM is the common electrode voltage applied to the common electrode layer on the array substrate 110 of the display panel 100, and the first common electrode voltage CFVCOM and the second common electrode voltage AVCOM are equal.

[0102] In this embodiment, the liquid crystal capacitor Clc is typically formed by the pixel electrode 11 and a common electrode layer on the color filter substrate 120; the storage capacitor Cst is typically formed by the pixel electrode 11 and a common electrode layer on the array substrate 110; and the charge / discharge capacitor Cps can be formed by corresponding electrode layers and the pixel electrode 11. In an optional embodiment, such as... Figure 11 As shown, the display panel 100 includes an array substrate 110, a liquid crystal layer 130 and a color filter substrate 120 stacked sequentially.

[0103] The array substrate 110 is provided with data lines, scan lines, thin-film transistors T1, a second common electrode layer, a metal layer, and multiple pixel electrodes 11. The pixel electrodes 11 are connected to the scan lines and data lines respectively through the thin-film transistors T1. Figure 8As shown, the metal layer includes multiple arrayed metal lines 12, and the metal lines 12 and the second common electrode layer are respectively disposed opposite to the pixel electrode 11;

[0104] The upper electrode of the liquid crystal capacitor Clc, the upper electrode of the storage capacitor Cst, and the upper electrode of the charging and discharging capacitor Cps are pixel electrodes 11, the lower electrode of the storage capacitor Cst is the second common electrode layer, and the lower electrode of the charging and discharging capacitor Cps is a metal line 12.

[0105] The color filter substrate 120 includes a first common electrode layer and a color filter layer stacked together, and the lower electrode of the liquid crystal capacitor Clc is the first common electrode layer.

[0106] In this embodiment, the liquid crystal capacitor Clc in the sub-pixel 10 is formed by the first common electrode layer and the pixel electrode 11 on the color filter substrate 120. When a driving voltage is applied to both ends of the liquid crystal capacitor Clc, the liquid crystal capacitor Clc drives the liquid crystal of the liquid crystal layer 130 to deflect. The storage capacitor Cst is formed by the second common electrode layer and the pixel electrode 11 on the array substrate 110 and performs charge storage.

[0107] Meanwhile, an additional metal layer is provided on the array substrate 110. The metal layer is composed of multiple arrayed metal lines 12. The metal lines 12 are arranged in the array according to the array arrangement structure of the sub-pixels 10. Each metal line 12 corresponds to the pixel electrode 11 of a sub-pixel. Each metal line 12 and each pixel electrode 11 respectively form the charging and discharging capacitor Cps of each sub-pixel 10. The metal lines 12 are connected to the signal coupling line and are correspondingly input to the first voltage signal V1 and the second voltage signal V2.

[0108] The pixel electrode 11 array is arranged on the array substrate 110. The pixel electrode 11 can be a four-domain structure or an eight-domain structure. The thin film transistor T1 is located between adjacent pixel electrodes 11 and is connected to the data line and the scan line respectively. At the same time, the data line can be arranged in the same layer as the pixel electrode 11 or in a different layer. The data line and the scan line are arranged in different layers. The scan line is arranged in a different layer from the pixel electrode 11. The second common electrode layer can be arranged in the same layer as the data line or in a different layer.

[0109] The metal layer is set on a different layer from the pixel electrode 11 and on a different layer from the data line to avoid cross-parasitic capacitance between the metal layer and the data line.

[0110] By setting a metal layer, a corresponding charging and discharging capacitor Cps can be formed, and grayscale changes of sub-pixels 10 can be achieved, reducing the coupling pull of the common electrode voltage and improving side-view brightness and contrast.

[0111] The positions of the metal layer and the data lines and scan lines can be correspondingly set. In an optional embodiment, such as... Figure 12As shown, a gate layer 13 is disposed on the array substrate, and the gate layer 13 is disposed opposite to the pixel electrode 11. The gate layer 13 is used to set the scan line, and the metal line 12 is disposed on the gate layer 13 and spaced apart from the scan line.

[0112] In this embodiment, the gate layer 13 is used to set scan lines in the display panel 100. At the same time, the gate layer 13 is reused as a metal layer, and metal lines 12 are synchronously set on the gate layer 13 to form a charging and discharging capacitor Cps with the common electrode. No additional metal layer is required, which simplifies the interlayer structure of the array substrate 110. The metal lines 12 are connected to the signal coupling lines and are correspondingly input to the first voltage signal V1 and the second voltage signal V2.

[0113] Furthermore, to further simplify the array substrate structure, in an optional embodiment, such as Figure 13 As shown, the signal coupling lines are set on the same layer as the scan lines and are alternately spaced with the scan lines.

[0114] In this embodiment, the signal coupling line and the scan line are disposed on the same layer of the gate layer 13, and the signal coupling line is connected to the metal line 12 of the corresponding row to transmit the first voltage signal V1 or the second voltage signal V2. The signal coupling line and the scan line are alternately arranged. By setting the signal coupling line on the gate layer 13, the interlayer structure of the array substrate can be reduced, and the connection between the signal coupling line and the metal line 12 can be facilitated, avoiding the problem of cross-layer hole connection.

[0115] The beneficial effects of this invention compared to the prior art are as follows: The display panel 100 includes scan lines, data lines, signal coupling lines, and sub-pixels 10 arranged in an array. Each sub-pixel 10 is connected to the data lines, scan lines, and signal coupling lines. Each sub-pixel 10 includes a thin-film transistor T1, a liquid crystal capacitor Clc, and a charging / discharging capacitor Cps. The charging / discharging capacitor Cps is connected to the thin-film transistor T1 and the signal coupling lines, respectively. Two sub-pixels 10 in two adjacent columns form a pixel group 103. The sub-pixels 10 operate in the first time period t1 and the second time period t2. During the first time period t1, the pixel group 103 receives two initial grayscale voltages and a first voltage signal V1. The two liquid crystal capacitors Clc of the pixel group 103 are charged to two initial grayscale voltages with opposite polarities. The coupling effect of the two initial grayscale voltages on the common electrode voltage cancels each other out, reducing crosstalk and flicker of the display panel 100. During the second time period t2, the pixel group 103 receives a second voltage signal V2. The two liquid crystal capacitors Clc of the pixel group 103 are charged or discharged simultaneously, and the grayscale voltage changes to the target grayscale voltage, improving the side-view brightness and contrast.

[0116] Example 2

[0117] A second aspect of the present invention provides a display device, such as... Figure 14As shown, the display device includes a driving circuit 200 and a display panel 100. The specific structure of the display panel 100 is as described in the above embodiments. Since this display device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be described in detail here. The driving circuit 200 is used to output the corresponding row scan signal, grayscale voltage, first voltage signal V1, and second voltage signal V2 to the display panel 100.

[0118] In this embodiment, the driving circuit 200 may include a timing controller, a level generation circuit, a gate driving circuit, and a source driving circuit. The timing controller determines the initial grayscale voltage and the target grayscale voltage of the sub-pixel 10 based on the received original grayscale. In the first time period t1 and the second time period t2, the timing controller controls the level generation circuit to output the corresponding level signal and controls the gate driving circuit and the source driving circuit to output the corresponding line scanning signal and data signal, thereby enabling the two liquid crystal capacitors Clc of the pixel group 103 to be charged to two initial grayscale voltages with opposite polarities in the first time period t1. The coupling effect of the two initial grayscale voltages on the common electrode voltage cancels each other out, reducing crosstalk and flicker of the display panel 100. In the second time period t2, the two liquid crystal capacitors Clc of the pixel group 103 are charged or discharged simultaneously, and the grayscale voltage changes to the target grayscale voltage, improving the side-view brightness and contrast.

[0119] In an optional embodiment, the driving circuit 200 is specifically used for:

[0120] The original grayscale of pixel group 103 is obtained, and the two initial grayscale voltages, the first target grayscale voltage and the second target grayscale voltage corresponding to pixel group 103 are determined based on the original grayscale.

[0121] During the first time period t1, the row scanning signal and two initial grayscale voltages with opposite polarities are output to the scan line and two data lines corresponding to the pixel group 103, and the first voltage signal V1 is output to the signal coupling line corresponding to the pixel group 103.

[0122] During the second time period t2, a second voltage signal V2 is output to the signal coupling line to charge and discharge the grayscale voltages of the two liquid crystal capacitors Clc in the pixel group 103 and change the first target grayscale voltage and the second target grayscale voltage, respectively.

[0123] In this embodiment, when the driving circuit 200 is working, it determines the two original grayscale voltages corresponding to the first time period t1 and the first target grayscale voltage and the second target grayscale voltage corresponding to the second time period t2 based on the received original grayscale and the corresponding original grayscale voltage.

[0124] For example, if the original grayscale is 128 grayscale and the original grayscale voltage is 8V, then the first target grayscale after splitting is 160 grayscale and the second target grayscale is 96 grayscale, with corresponding first target grayscale voltages of 14.4V and 4.8V respectively. For the same sub-pixel 10, the polarity of the initial grayscale voltage and the target grayscale voltage input in the first time period t1 and the second time period t2 is the same. When the same sub-pixel 10 switches from the first time period t1 to the second time period t2, the initial grayscale voltage with positive polarity is amplified or attenuated to the target grayscale voltage with positive polarity, or the initial grayscale voltage with negative polarity is amplified or attenuated to the target grayscale voltage with negative polarity.

[0125] The driving circuit 200 can determine two initial grayscale voltages based on the split first target grayscale voltage and second target grayscale voltage. The voltage difference between the two initial grayscale voltages can be equal to or less than the voltage difference between the two target grayscale voltages. For example, if the two initial grayscale voltages are 12V and 4V respectively, the voltage difference is 8V, and the two target grayscale voltages can be 14.4V and 4.8V respectively, the voltage difference is 9.6V. Alternatively, the two target grayscale voltages can be 14V and 6V respectively, the voltage difference is 8V.

[0126] When scanning to the pixel row containing pixel group 103, such as Figure 10 As shown, during the first time period t1, the driving circuit 200 outputs a row scanning signal to the scan line and two initial grayscale voltages to two adjacent data lines. The voltage difference between the two initial grayscale voltages and the first common electrode voltage CFVCOM is opposite and the absolute value is equal. For example, if the first common electrode voltage CFVCOM is 8V, the two initial grayscale voltages are 12V and 4V respectively, and the voltage difference is 4V and -4V respectively. The two initial grayscale voltages are input to the sub-pixel 10. At the same time, the driving circuit 200 outputs a first voltage signal V1 to the signal coupling line, for example, a low-level signal. At this time, the liquid crystal capacitor Clc and the charging and discharging capacitor Cps are charged, and the charge is distributed according to the capacitance ratio. At this time, the two initial grayscale voltages with opposite polarities and equal voltage differences compared to the first common electrode voltage CFVCOM are input to the adjacent data lines. The coupling effect of the first common electrode voltage CFVCOM cancels each other out, reducing crosstalk and flicker of the display panel 100.

[0127] Then, the line scan moves to the next line, and sub-pixel 10 enters the second time period t2. The driving circuit 200 cuts off the output of the input line scan signal and data signal to the sub-pixel 10 of the current line, and outputs the second voltage signal V2 to the signal coupling line. The charge stored in the charging and discharging capacitor Cps is released through the capacitive coupling effect, and the sub-pixel 10 is charged or discharged. For example, if a high-level signal is input, the charging and discharging capacitor Cps discharges and superimposes the charge onto the liquid crystal capacitor Clc. The gray level voltage of the liquid crystal capacitor Clc rises to the target gray level voltage. Correspondingly, the two sub-pixels 10 in the pixel group 103 are transformed to the first target gray level voltage and the second target gray level voltage, respectively, thereby realizing the separation of high and low gray levels and improving the side-view brightness and contrast.

[0128] Furthermore, the driving circuit 200 can input voltage signals of corresponding magnitudes in the first time period t1 and the second time period t2, respectively, according to the change direction of the initial gray level and target gray level voltage of each sub-pixel 10.

[0129] In order to improve the contrast, the third voltage difference between the first target gray level voltage and the second target gray level voltage obtained by the pixel group 103 must be greater than a preset value, for example, the third voltage difference is greater than 5V. Therefore, the initial gray level voltage of each pixel group 103 and the corresponding first voltage signal V1 and second voltage signal V2 must be set accordingly to meet the requirements of the target gray level voltage.

[0130] Therefore, in one alternative embodiment, the drive circuit 200 is further configured to:

[0131] The drive circuit 200 is also used for:

[0132] Obtain the two initial grayscale voltages corresponding to each pixel group 103 in the current row, and compare the first voltage difference between the two initial grayscale voltages of each pixel group 103.

[0133] The pixel group 103 with the smallest first voltage difference is set as the target pixel group, and the second voltage difference between the first voltage signal V1 and the second voltage signal V2 is determined based on the first voltage difference of the target pixel group, so that the third voltage difference between the first target gray level voltage and the second target gray level voltage of each pixel group 103 in the current row is greater than a preset value.

[0134] The product of the second voltage difference and the first voltage difference of the target pixel group is proportional to a preset value.

[0135] In this embodiment, each pixel group 103 in each row determines the corresponding two initial gray level voltages based on the original gray level. For example, assuming that the gray level is divided into 256, 0~127 is the negative polarity gray level, and 128~255 is the positive polarity gray level.

[0136] Assuming the original grayscale of the first pixel group 103 in the current row is grayscale 130, the two initial grayscale levels that can be initially set are grayscale 132 and grayscale 123, with corresponding grayscale voltages of 9V and 7V respectively. The original grayscale of the second pixel group 103 in the current row is grayscale 140, and the two initial grayscale levels that can be initially set are grayscale 142 and grayscale 133, with corresponding grayscale voltages of 10V and 6V respectively.

[0137] If the fixed gain is set as described above, for example, 1.5 times, the voltage difference of the first pixel group 103 is 2V. The first target gray level voltage and the second target gray level voltage after gain amplification are 13.5V and 10.5V respectively. The third voltage difference between the first target gray level voltage and the second target gray level voltage after amplification is 3V, which is less than the preset value, resulting in low contrast.

[0138] The voltage difference of the second pixel group 103 is 4V. The first target gray level voltage and the second target gray level voltage of the gain amplification are 15V and 9V respectively. After amplification, the third voltage difference between the first initial gray level voltage and the second initial gray level voltage is 6V, which is greater than the preset value, resulting in high contrast.

[0139] The second voltage difference between the first voltage signal V1 and the second voltage signal V2 determines the voltage change of the two liquid crystal capacitors in the pixel group 103, which in turn determines the amplification gain of the two original grayscale voltages in the pixel group 103. The larger the second voltage difference between the first voltage signal V1 and the second voltage signal V2, the larger the amplification gain, and the larger the first target grayscale voltage and the second target grayscale voltage are, as well as the larger the third voltage difference.

[0140] Therefore, in order to improve the consistency of contrast of each pixel group 103 in the current row, the driving circuit 200 determines two initial gray level voltages symmetrical to the first common electrode voltage according to the original gray level, calculates the first voltage difference between the two initial gray level voltages of each pixel group 103, compares the first voltage difference corresponding to each pixel group 103, and selects the pixel group 103 with the smallest first voltage difference as the target pixel group. Based on the target pixel group and the preset value, the magnitude and voltage difference of the first voltage signal V1 and the second voltage signal V2 are determined.

[0141] For example, in the current row, the two initial gray levels of the target pixel group with the smallest first voltage difference are gray levels 132 and 123, corresponding to two gray level voltages of 9V and 7V respectively, with a preset value of 5V. At this time, the amplification gain needs to be set to at least 2.5. When the second voltage difference between the original first voltage signal V1 and the second voltage signal V2 is 3V, the amplification gain of 1.2 does not meet the requirements. At this time, the second voltage difference between the first voltage signal V1 and the second voltage signal V2 is increased. According to the proportional relationship, the second voltage difference is at least 6.25V. At this time, the amplification gain of each pixel group 103 is 2.5V. The first voltage difference of the initial gray level voltage of other pixel groups 103 is greater than the first voltage difference of the target pixel group. That is, after the gain is amplified at the same time, the third voltage difference of the two target gray level voltages of other pixel groups 103 is greater than the preset value, and the target contrast is achieved, thus improving the contrast consistency.

[0142] Alternatively, in another optional embodiment, the amplification gain can be fixed while the initial grayscale voltage of different pixel groups 103 can be selected and set. The driving circuit 200 is also used for:

[0143] Obtain the first target grayscale voltage and the second target grayscale voltage corresponding to each pixel group 103 in the current row, and compare the third voltage difference between the first target grayscale voltage and the second target grayscale voltage of each pixel group 103.

[0144] The pixel group 103 with the smallest third voltage difference is set as the target pixel group, and the magnitude of the second initial grayscale voltage of the target pixel group is determined based on the ratio of the third voltage difference and the second voltage difference of the target pixel group. The second voltage difference is the voltage difference between the first voltage signal V1 and the second voltage signal V2.

[0145] In this embodiment, the amplification gain is fixed, and the two initial gray level voltages corresponding to each original gray level are selected and adjusted. For example, the original gray level of the first pixel group 103 in the current row is gray level 130, and the two initial gray levels are initially set to gray levels 132 and 123. The corresponding two gray level voltages are 9V and 7V, respectively. After the gain is amplified by, for example, 1.5 times, the first target gray level voltage and the second target gray level voltage are 13.5V and 10.5V, respectively. After amplification, the third voltage difference between the first target gray level voltage and the second target gray level voltage is 3V, which is less than the preset value, resulting in low contrast.

[0146] The original grayscale of the second pixel group 103 in the current row is grayscale 140. The two initial grayscale levels are set to grayscale 142 and grayscale 133, with corresponding grayscale voltages of 10V and 6V respectively. After gain amplification, for example by 1.5 times, the first target grayscale voltage and the second target grayscale voltage are 15V and 9V respectively. After amplification, the third voltage difference between the first target grayscale voltage and the second target grayscale voltage is 6V, which is greater than the preset value, resulting in high contrast.

[0147] To achieve contrast consistency, the driving circuit 200 also acquires the first target grayscale voltage and the second target grayscale voltage corresponding to each pixel group 103 in the current row, compares the third voltage difference between the first target grayscale voltage and the second target grayscale voltage of each pixel group 103, sets the pixel group 103 with the smallest third voltage difference as the target pixel group, and determines the magnitude of the second initial grayscale voltage of the target pixel group based on the ratio of the preset value and the second voltage difference.

[0148] For example, in the current row, the two target grayscale voltages of the target pixel group with the smallest third voltage difference are 13.5V and 10.5V respectively. At this time, the preset value is determined, the second voltage ratio determines the amplification gain, and the two initial grayscale voltages of the target pixel are determined according to the preset value and the ratio of the second voltage difference.

[0149] For example, assuming the preset value is 6V, and the second voltage difference is 3V, the amplification gain is 1.5V. At this time, the preset value and the second voltage difference are proportional to the ratio of the preset value and the amplification gain. Thus, the voltage difference between the two initial grayscale voltages of the target pixel group is determined to be 4V. In this case, the two initial grayscale voltages of the target pixel group can be set to 10V and 6V respectively. The two updated initial grayscale levels are 142 grayscale and 133 grayscale. After amplification, the third voltage difference between the first initial grayscale voltage and the second initial grayscale voltage is 6V, which is greater than the preset value, resulting in high contrast.

[0150] Furthermore, to improve display quality and reduce crosstalk, in an optional embodiment, such as Figure 15 As shown, the display device also includes a backlight module 300, and the driving circuit 200 is also connected to the backlight module 300.

[0151] The drive circuit 200 is also used for:

[0152] During the first time period t1, control the backlight module 300 to light up;

[0153] During the second time period t2, control the backlight module 300 to turn off;

[0154] In the third time period t3, following the second time period t2, the backlight module 300 is controlled to light up.

[0155] In this embodiment, as Figure 10 As shown, the driving circuit 200 uses a PWM modulation method to control the backlight module 300. In the first time period t1, the scan line inputs the horizontal scanning signal, the data line inputs two initial grayscale voltages, and at the same time, the signal coupling line inputs the first voltage signal V1, and controls the backlight module 300 to light up, providing backlight LED.

[0156] Then, during the second time period t2, due to changes in the voltage signal, the voltage of the common electrode may change when the voltage of the signal coupling line changes, which may cause crosstalk. To address this, the drive circuit 200 controls the backlight module 300 to turn off and stop providing backlight LED. At this time, the influence of the signal coupling line on the crosstalk of the common electrode is reduced.

[0157] Then, in the third time period t3, the compensated target grayscale voltage is maintained, and the backlight module 300 is turned on to provide backlight. The display panel 100 turns on to display the image, and the signal coupling line level is maintained until the next cycle.

[0158] The display device can also operate in the fourth time period t0, which is ahead of the first time period t1. The fourth time period t0 is the initial time period in one frame cycle of sub-pixel 10. At this time, the driving circuit 200 controls the backlight module 300 to turn off and outputs the first voltage signal V1 to the signal coupling line. There is no data signal or line scanning signal input, and sub-pixel 10 is in the display state.

[0159] The driving circuit 200 can be configured according to the structure of the backlight module 300 and the display panel 100. In an optional embodiment, such as... Figure 16 As shown, the driving circuit 200 includes:

[0160] The backlight driving circuit 210 is connected to the backlight module 300. The backlight driving circuit 210 is used to drive the backlight module 300 to light up or turn off according to the first control signal.

[0161] The driving circuit 220 of the display panel is connected to the display panel 100. The driving circuit 220 of the display panel is used to output a corresponding row scan signal, a data signal, and a corresponding first voltage signal V1 and second voltage signal V2 according to the second control signal.

[0162] The control circuit 230 is connected to the backlight driving circuit 210 and the display panel driving circuit 220 respectively. The control circuit 230 is used to output a first control signal and a second control signal according to the original grayscale of the received pixel group 103.

[0163] In this embodiment, the control circuit 230 determines the two original grayscale voltages corresponding to the first time period t1 and the first target grayscale voltage and the second target grayscale voltage corresponding to the second time period t2 based on the received original grayscale and the corresponding original grayscale voltage.

[0164] In the first time period t1, the corresponding first control signal is output to the backlight driving circuit 210, thereby driving the backlight module 300 to light up and provide backlight LED, and outputting the corresponding second control signal to the driving circuit 220 of the display panel, so that the driving circuit 220 of the display panel outputs the first voltage signal V1, the line scan signal and the data signal to the sub-pixel 10.

[0165] Then, when switching to the second time period t2, the corresponding first control signal is output to the backlight driving circuit 210, thereby driving the backlight module 300 to turn off and stop providing backlight LED, and outputting the corresponding second control signal to the display driving circuit 200, so that the display panel driving circuit 220 outputs the second voltage signal V2.

[0166] Then, in the third time period t3, the corresponding first control signal is output to the backlight driving circuit 210, thereby driving the backlight module 300 to light up and provide backlight LED, and outputting the corresponding second control signal to the display driving circuit 200, so that the display panel driving circuit 220 outputs the second voltage signal V2 to provide backlight LED, the display panel 100 turns on the display screen, and the level of the signal coupling line is maintained until the next cycle.

[0167] The backlight driving circuit 210 can adopt a corresponding switching power supply circuit, switching circuit, etc., and the driving circuit 220 of the display panel can include a timing controller, a level generation circuit, a gate driving circuit, and a source driving circuit.

[0168] The timing controller determines the initial grayscale voltage and target grayscale voltage of sub-pixel 10 based on the received original grayscale. In the first time period t1 and the second time period t2, it controls the level generation circuit to output the corresponding voltage signal, and controls the gate driving circuit and the source driving circuit to output the corresponding row scanning signal and data signal, respectively. This enables the two liquid crystal capacitors Clc of pixel group 103 to be charged to two initial grayscale voltages with opposite polarities in the first time period t1. The coupling effect of the two initial grayscale voltages on the common electrode voltage cancels each other out, reducing crosstalk and flicker of the display panel 100. In the second time period t2, the two liquid crystal capacitors Clc of pixel group 103 are charged or discharged simultaneously, and the grayscale voltage changes to the target grayscale voltage, improving the side-view brightness and contrast.

[0169] Example 3

[0170] A third aspect of this invention provides a driving method for a display device, applied to the display device described above, such as... Figure 17 As shown, the driving method for the display device includes:

[0171] S10. Obtain the original grayscale of pixel group 103, and determine the two initial grayscale voltages, the first target grayscale voltage and the second target grayscale voltage corresponding to pixel group 103 based on the original grayscale.

[0172] S20. In the first time period t1, output the line scanning signal and two initial gray level voltages with opposite polarities to the scan line and two data lines corresponding to the pixel group 103, and output the first voltage signal V1 to the signal coupling line corresponding to the pixel group 103 to control the backlight module 300 to light up.

[0173] S30. In the second time period t2, output the second voltage signal V2 to the signal coupling line to charge and discharge the grayscale voltages of the two liquid crystal capacitors Clc in the pixel group 103 respectively and change the first target grayscale voltage and the second target grayscale voltage, and control the backlight module 300 to turn off.

[0174] S40, in the third time period t3 after the second time period t2, control the backlight module 300 to light up.

[0175] In this embodiment, when driving the display device to work, the two original grayscale voltages corresponding to the first time period t1 and the first target grayscale voltage and the second target grayscale voltage corresponding to the second time period t2 are determined according to the received original grayscale and the corresponding original grayscale voltage.

[0176] For example, if the original grayscale is 128 grayscale and the original grayscale voltage is 8V, then the first target grayscale after splitting is 160 grayscale and the second target grayscale is 96 grayscale, with corresponding first target grayscale voltages of 14.4V and 4.8V respectively. For the same sub-pixel 10, the polarity of the initial grayscale voltage and the target grayscale voltage input in the first time period t1 and the second time period t2 is the same. When the same sub-pixel 10 switches from the first time period t1 to the second time period t2, the initial grayscale voltage with positive polarity is amplified or attenuated to the target grayscale voltage with positive polarity, or the initial grayscale voltage with negative polarity is amplified or attenuated to the target grayscale voltage with negative polarity.

[0177] Meanwhile, based on the split first target grayscale voltage and the second target grayscale voltage, the two initial grayscale voltages can be determined. The voltage difference between the two initial grayscale voltages can be equal to or less than the voltage difference between the two target grayscale voltages. For example, if the two original grayscale voltages are 12V and 4V respectively, with a voltage difference of 8V, the two target grayscale voltages can be 14.4V and 4.8V respectively, with a voltage difference of 9.6V. Alternatively, the two target grayscale voltages can be 14V and 6V respectively, with a voltage difference of 8V.

[0178] When scanning to the pixel row containing pixel group 103, such as Figure 10As shown, during the first time period t1, the row scan signal is output to the scan line, and two initial grayscale voltages are output to two adjacent data lines. The voltage difference between the two initial grayscale voltages and the first common electrode voltage CFVCOM is opposite and the absolute value is equal. For example, if the first common electrode voltage CFVCOM is 8V, the two initial grayscale voltages are 12V and 4V respectively, and the voltage difference is 4V and -4V respectively. The two initial grayscale voltages are input to the sub-pixel 10. At the same time, the first voltage signal V1 is output to the signal coupling line, and the backlight module 300 is controlled to light up to provide backlight LED. At this time, the liquid crystal capacitor Clc and the charging and discharging capacitor Cps are charged, and the charge is distributed according to the capacitance ratio. At this time, the two initial grayscale voltages with opposite polarities and equal voltage difference compared to the first common electrode voltage CFVCOM are input to the adjacent data lines. The coupling effect of the first common electrode voltage CFVCOM cancels each other out, reducing crosstalk and flicker of the display panel 100.

[0179] Then, the line scan moves to the next line, and sub-pixel 10 enters the second time period t2. The output of the line scan signal and data signal is cut off to the sub-pixel 10 of this line. At this time, the second voltage signal V2 is output to the signal coupling line to control the backlight module 300 to turn off, stop providing backlight LED, and reduce the influence of the signal coupling line on the common electrode crosstalk.

[0180] The charge stored in the charging and discharging capacitor Cps is released through capacitive coupling effect and charges or discharges the sub-pixel 10. For example, when a high-level signal is input, the charging and discharging capacitor Cps discharges and adds the charge to the liquid crystal capacitor Clc. The gray level voltage of the liquid crystal capacitor Clc rises to the target gray level voltage. Correspondingly, the two sub-pixels 10 in the pixel group 103 are transformed to the first target gray level voltage and the second target gray level voltage, respectively, thereby realizing the separation of high and low gray levels and improving the side-view brightness and contrast.

[0181] Then, in the third time period t3, the compensated target grayscale voltage is maintained, and the backlight module 300 is turned on to provide backlight. The display panel 100 turns on to display the image, and the second voltage signal V2 of the signal coupling line is maintained until the next cycle.

[0182] In order to improve the contrast, the third voltage difference between the first target gray level voltage and the second target gray level voltage obtained by the pixel group 103 must be greater than a preset value, for example, the third voltage difference is greater than 5V. Therefore, the initial gray level voltage of each pixel group 103 and the corresponding first voltage signal V1 and second voltage signal V2 must be set accordingly to meet the requirements of the target gray level voltage.

[0183] In an optional embodiment, after S10 and before S20, as Figure 18 As shown, the driving method for the display panel also includes:

[0184] S50. Obtain the two initial grayscale voltages corresponding to each pixel group 103 in the current row, and compare the first voltage difference between the two initial grayscale voltages of each pixel group 103.

[0185] S60. The pixel group 103 with the smallest first voltage difference is set as the target pixel group, and the second voltage difference between the first voltage signal V1 and the second voltage signal V2 is determined based on the first voltage difference of the target pixel group, so that the third voltage difference between the first target gray level voltage and the second target gray level voltage of each pixel group 103 in the current row is greater than a preset value.

[0186] The product of the second voltage difference and the first voltage difference of the target pixel group is proportional to a preset value.

[0187] In this embodiment, each pixel group 103 in each row determines the corresponding two initial gray level voltages based on the original gray level. For example, assuming that the gray level is divided into 256, 0~127 is the negative polarity gray level, and 128~255 is the positive polarity gray level.

[0188] Assuming the original grayscale of the first pixel group 103 in the current row is grayscale 130, the two initial grayscale levels that can be initially set are grayscale 132 and grayscale 123, with corresponding grayscale voltages of 9V and 7V respectively. The original grayscale of the second pixel group 103 in the current row is grayscale 140, and the two initial grayscale levels that can be initially set are grayscale 142 and grayscale 133, with corresponding grayscale voltages of 10V and 6V respectively.

[0189] If the fixed gain is set as described above, for example, 1.5 times, the voltage difference of the first pixel group 103 is 2V. The first target gray level voltage and the second target gray level voltage after gain amplification are 13.5V and 10.5V respectively. The third voltage difference between the first target gray level voltage and the second target gray level voltage after amplification is 3V, which is less than the preset value, resulting in low contrast.

[0190] The voltage difference of the second pixel group 103 is 4V. The first target gray level voltage and the second target gray level voltage of the gain amplification are 15V and 9V respectively. After amplification, the third voltage difference between the first initial gray level voltage and the second initial gray level voltage is 6V, which is greater than the preset value, resulting in high contrast.

[0191] The second voltage difference between the first voltage signal V1 and the second voltage signal V2 determines the voltage change of the two liquid crystal capacitors in the pixel group 103, which in turn determines the amplification gain of the two original grayscale voltages in the pixel group 103. The larger the second voltage difference between the first voltage signal V1 and the second voltage signal V2, the larger the amplification gain, and the larger the first target grayscale voltage and the second target grayscale voltage are, as well as the larger the third voltage difference.

[0192] Therefore, in order to improve the consistency of contrast of each pixel group 103 in the current row, after determining the initial gray level voltages symmetrical to the first common electrode voltage according to the original gray level, the first voltage difference between the two initial gray level voltages of each pixel group 103 is calculated, and the first voltage difference corresponding to each pixel group 103 is compared. The pixel group 103 with the smallest first voltage difference is selected as the target pixel group. The magnitude and voltage difference of the first voltage signal V1 and the second voltage signal V2 are determined based on the target pixel group and the preset value.

[0193] For example, in the current row, the two initial gray levels of the target pixel group with the smallest first voltage difference are gray levels 132 and 123, corresponding to two gray level voltages of 9V and 7V respectively, with a preset value of 5V. At this time, the amplification gain needs to be set to at least 2.5. When the second voltage difference between the original first voltage signal V1 and the second voltage signal V2 is 3V, the amplification gain of 1.2 does not meet the requirements. At this time, the second voltage difference between the first voltage signal V1 and the second voltage signal V2 is increased. According to the proportional relationship, the second voltage difference is at least 6.25V. At this time, the amplification gain of each pixel group 103 is 2.5V. The first voltage difference of the initial gray level voltage of other pixel groups 103 is greater than the first voltage difference of the target pixel group. That is, after the gain is amplified at the same time, the third voltage difference of the two target gray level voltages of other pixel groups 103 is greater than the preset value, and the target contrast is achieved, thus improving the contrast consistency.

[0194] Alternatively, in another optional embodiment, the amplification gain can be fixed, while the initial grayscale voltage of different pixel groups 103 can be selected and set, such as after S10 and before S20. Figure 19 As shown, the driving method for the display panel also includes:

[0195] S70. Obtain the first target gray level voltage and the second target gray level voltage corresponding to each pixel group 103 in the current row, and compare the third voltage difference between the first target gray level voltage and the second target gray level voltage of each pixel group 103.

[0196] S80. The pixel group 103 with the smallest third voltage difference is set as the target pixel group, and the magnitude of the second initial gray level voltage of the target pixel group is determined based on the ratio of the third voltage difference and the second voltage difference of the target pixel group. The second voltage difference is the voltage difference between the first voltage signal V1 and the second voltage signal V2.

[0197] In this embodiment, the amplification gain is fixed, and the two initial gray level voltages corresponding to each original gray level are selected and adjusted. For example, the original gray level of the first pixel group 103 in the current row is gray level 130, and the two initial gray levels are initially set to gray levels 132 and 123. The corresponding two gray level voltages are 9V and 7V, respectively. After the gain is amplified by, for example, 1.5 times, the first target gray level voltage and the second target gray level voltage are 13.5V and 10.5V, respectively. After amplification, the third voltage difference between the first target gray level voltage and the second target gray level voltage is 3V, which is less than the preset value, resulting in low contrast.

[0198] The original grayscale of the second pixel group 103 in the current row is grayscale 140. The two initial grayscale levels are set to grayscale 142 and grayscale 133, with corresponding grayscale voltages of 10V and 6V respectively. After gain amplification, for example by 1.5 times, the first target grayscale voltage and the second target grayscale voltage are 15V and 9V respectively. After amplification, the third voltage difference between the first target grayscale voltage and the second target grayscale voltage is 6V, which is greater than the preset value, resulting in high contrast.

[0199] To achieve contrast consistency, the first target grayscale voltage and the second target grayscale voltage corresponding to each pixel group 103 in the current row are also obtained. The third voltage difference between the first target grayscale voltage and the second target grayscale voltage of each pixel group 103 is compared, and the pixel group 103 with the smallest third voltage difference is set as the target pixel group. The second initial grayscale voltage of the target pixel group is determined based on the ratio of the preset value and the second voltage difference.

[0200] For example, in the current row, the two target grayscale voltages of the target pixel group with the smallest third voltage difference are 13.5V and 10.5V respectively. At this time, the preset value is determined, the second voltage ratio determines the amplification gain, and the two initial grayscale voltages of the target pixel are determined according to the preset value and the ratio of the second voltage difference.

[0201] For example, assuming the preset value is 6V, and the second voltage difference is 3V, the amplification gain is 1.5V. At this time, the preset value and the second voltage difference are proportional to the ratio of the preset value and the amplification gain. Thus, the voltage difference between the two initial grayscale voltages of the target pixel group is determined to be 4V. In this case, the two initial grayscale voltages of the target pixel group can be set to 10V and 6V respectively. The two updated initial grayscale levels are 142 grayscale and 133 grayscale. After amplification, the third voltage difference between the first initial grayscale voltage and the second initial grayscale voltage is 6V, which is greater than the preset value, resulting in high contrast.

[0202] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A display panel, characterized by, The display panel comprises a plurality of data lines arranged in parallel, a plurality of scan lines arranged in parallel, the plurality of data lines and the plurality of scan lines are arranged in a cross manner, a sub-pixel is arranged between adjacent two columns of the data lines and adjacent two rows of the scan lines, the sub-pixel is connected with adjacent one of the data lines and one of the scan lines, the display panel further comprises a plurality of signal coupling lines, one of the signal coupling lines is arranged between adjacent two rows of the scan lines, and the sub-pixel is further connected with adjacent one of the signal coupling lines; The sub-pixel comprises a thin film transistor, a liquid crystal capacitor and a charging and discharging capacitor, the upper plate of the liquid crystal capacitor and the upper plate of the charging and discharging capacitor are connected with the corresponding data line and scan line through the thin film transistor, the lower plate of the liquid crystal capacitor is used for inputting a first common electrode voltage, the lower plate of the charging and discharging capacitor is connected with the signal coupling line, and two sub-pixels in each adjacent two columns form a pixel group; Each of the sub-pixels works in a first period and a second period in turn, in the first period, the corresponding scan line and two data lines of the pixel group input a row scanning signal and two initial gray scale voltages with opposite polarities, the absolute value of the voltage difference between the two initial gray scale voltages and the first common electrode voltage is equal, and the corresponding signal coupling line of the pixel group inputs a first voltage signal; In the second period, the corresponding scan line and two data lines of the pixel group are cut off, the corresponding signal coupling line of the pixel group inputs a second voltage signal with a polarity opposite to that of the first voltage signal, and the gray scale voltages of the two liquid crystal capacitors in the pixel group are charged and discharged and transformed into first target gray scale voltages and second target gray scale voltages with opposite polarities respectively.

2. The display panel of claim 1, wherein, The pixel group comprises a first sub-pixel and a second sub-pixel, the gray scale voltage corresponding to the first sub-pixel is a first initial gray scale voltage in the first period and a first target gray scale voltage in the second period, and the gray scale voltage corresponding to the second sub-pixel is a second initial gray scale voltage in the first period and a second target gray scale voltage in the second period; When the first absolute value of the voltage difference between the first target gray scale voltage and the first common electrode voltage is greater than the second absolute value of the voltage difference between the first initial gray scale voltage and the first common electrode voltage, and the third absolute value of the voltage difference between the second target gray scale voltage and the first common electrode voltage is less than the fourth absolute value of the voltage difference between the second initial gray scale voltage and the first common electrode voltage, the first voltage signal is less than the second voltage signal; When the first absolute value of the voltage difference between the first target gray scale voltage and the first common electrode voltage is less than the second absolute value of the voltage difference between the first initial gray scale voltage and the first common electrode voltage, and the third absolute value of the voltage difference between the second target gray scale voltage and the first common electrode voltage is greater than the fourth absolute value of the voltage difference between the second initial gray scale voltage and the first common electrode voltage, the first voltage signal is greater than the second voltage signal.

3. The display panel of claim 2, wherein, The display panel comprises an array substrate, a liquid crystal layer and a color film substrate arranged in a stacking manner. The array substrate is provided with the data line, the scan line, the thin film transistor, a metal layer and a plurality of pixel electrodes, the pixel electrode is connected with the scan line and the data line through the thin film transistor, and the metal layer comprises a plurality of array-arranged metal lines, each metal line is arranged opposite to the pixel electrode. The upper plate of the liquid crystal capacitor and the upper plate of the charge-discharge capacitor are pixel electrodes, and the lower plate of the charge-discharge capacitor is the metal line. The color film substrate comprises a first common electrode layer and a color film layer arranged in layers, and the lower plate of the liquid crystal capacitor is the first common electrode layer.

4. The display panel of claim 3, wherein, The array substrate is provided with a gate layer, the gate layer is arranged opposite to the pixel electrode, the gate layer is used for arranging the scan line, and the metal line is arranged on the gate layer and is arranged in a spaced manner with the scan line.

5. A display device, characterized by comprising: The display panel comprises a driving circuit and a display panel as claimed in any one of claims 1-4, the driving circuit is connected with the display panel, and the driving circuit is used for outputting a corresponding row scan signal, a gray scale voltage, a first voltage signal and a second voltage signal to the display panel.

6. The display device of claim 5, wherein, The driving circuit is specifically used for: obtaining an original gray scale of a pixel group, and determining two initial gray scale voltages corresponding to the pixel group, a first target gray scale voltage and a second target gray scale voltage based on the original gray scale of the pixel group; in a first time period, outputting a row scan signal and two initial gray scale voltages with opposite polarities to the scan line and two data lines corresponding to the pixel group, and outputting the first voltage signal to the signal coupling line corresponding to the pixel group; in the second time period, outputting the second voltage signal to the signal coupling line to charge and discharge the gray scale voltages of two liquid crystal capacitors in the pixel group and transform the first target gray scale voltage and the second target gray scale voltage.

7. The display device of claim 6, wherein, The driving circuit is further used for: obtaining two initial gray scale voltages corresponding to each pixel group of the current row, and comparing a first voltage difference of the two initial gray scale voltages of each pixel group; setting the pixel group with the smallest first voltage difference as a target pixel group, and determining the second voltage difference of the first voltage signal and the second voltage signal based on the first voltage difference of the target pixel group, so that a third voltage difference of the first target gray scale voltage and the second target gray scale voltage of each pixel group of the current row is greater than a preset value; the product of the second voltage difference and the first voltage difference of the target pixel group is proportional to the preset value.

8. The display device of claim 6, wherein, The third voltage difference of the first target gray scale voltage and the second target gray scale voltage is greater than a preset value. The driving circuit is further used for: obtaining the first target gray scale voltage and the second target gray scale voltage corresponding to each pixel group of the current row, and comparing a third voltage difference of the first target gray scale voltage and the second target gray scale voltage of each pixel group; The pixel group with the minimum third voltage difference is set as a target pixel group, and a second initial gray scale voltage of the target pixel group is determined based on a ratio of the preset value and a second voltage difference, the second voltage difference being a voltage difference between the first voltage signal and the second voltage signal.

9. The display device of claim 6, wherein, The display device further comprises a backlight module, and the driving circuit is further connected with the backlight module. The driving circuit is further configured to: control the backlight module to emit light during the first time period; control the backlight module to be turned off during the second time period; and control the backlight module to emit light during a third time period after the second time period.

10. The display device of claim 9, wherein, The driving circuit comprises: a backlight driving circuit connected with the backlight module, the backlight driving circuit being configured to drive the backlight module to emit light or be turned off according to a first control signal; a display panel driving circuit connected with the display panel, the display panel driving circuit being configured to output corresponding row scanning signals, data signals, corresponding first voltage signals and second voltage signals according to a second control signal; a control circuit connected with the backlight driving circuit and the display panel driving circuit respectively, the control circuit being configured to output the corresponding first control signal and the second control signal according to a received original gray scale of a pixel group.

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