Gate driving circuit and display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel. The gate driving circuit comprises N driving units and at least one virtual unit in cascade. The virtual unit comprises: a pre-charging module, configured to charge a first driving control node through a gate driving signal of an N-i-th driving unit; an output module, configured to output a stage transmission signal acting on an N-j-th driving unit in response to a driving control signal on the first driving control node and a clock signal on a clock signal line in a normal mode; and a repairing module, configured to generate a repairing signal corresponding to an m-th driving unit in a repairing mode, and to repair driving capability and stage transmission capability of the m-th driving unit through the repairing signal. The application realizes a low-cost and high-efficiency repairing method for the gate driving circuit through multiplexing of the virtual unit, reduces layout area of the circuit, and improves panel yield and product competitiveness.

Description

Technical Field

[0001] This disclosure belongs to the field of display driving technology, specifically relating to a gate driving circuit and a display panel. Background Technology

[0002] In liquid crystal display panels, Gate-on-Array (GOA) technology integrates the row scan driving circuit directly onto the array substrate, which is crucial for achieving narrow bezels, low cost, and high reliability. The GOA circuit consists of multiple cascaded driving units. The gate output signal (Gn) of each stage not only activates the pixels in the current row, but its generated cascade signal (Fn) is also key to the pull-up and pull-down control of the preceding and following stages. This tight cascading dependency means that a failure in a single driving unit (such as output failure or waveform distortion) can propagate along the cascade path, causing not only display abnormalities in the corresponding row but also potentially leading to horizontal lines, flickering, or even area blackouts across the entire screen, severely restricting panel yield and reliability.

[0003] To address this issue, existing technologies typically employ the introduction of additional dedicated repair circuitry. For example, a separate repair unit is reserved outside the GOA circuit, or redundant drive stages are added to the panel design. However, these methods all have significant drawbacks: firstly, the additional transistors (TFTs) and wiring significantly increase the circuit layout area, contradicting the trend towards narrow bezel designs; secondly, they increase the complexity of the circuit design and wiring congestion; and thirdly, they increase additional manufacturing costs and power consumption.

[0004] Therefore, in the process of repairing the gate drive circuit, how to reduce the circuit layout area and cost is an urgent problem to be solved. Summary of the Invention

[0005] This application provides a gate driving circuit and a display panel, which solves the problems of large layout area and high cost in the repair process of gate driving circuit. By reusing virtual units, this application not only realizes a low-cost and high-efficiency repair method for gate driving circuit, but also reduces the layout area of ​​the circuit, improves panel yield and product competitiveness.

[0006] In a first aspect, this application provides a gate driving circuit, the gate driving circuit including N cascaded driving units and at least one virtual unit, the virtual unit including: a pre-charge module, the control terminal of the pre-charge module being connected to the stage output terminal of the Ni-th stage driving unit, the first terminal of the pre-charge module being connected to the drive output terminal of the Ni-th stage driving unit, and the output terminal of the pre-charge module being connected to a first drive control node, used to charge the first drive control node through the gate driving signal of the Ni-th stage driving unit; and an output module, the first terminal of the output module being connected to the first drive control node, the second terminal of the output module being connected to the clock signal line corresponding to the virtual unit, and the drive output terminal of the output module being connected to the pull-down control of the Nj-th stage driving unit. A terminal is connected to the first drive control node and the clock signal on the clock signal line in normal mode, and outputs the stage transmission signal acting on the Nj-th stage drive unit; where 0≤j<i; a repair module, the first terminal of which is connected to the stage transmission output terminal of the mi-th stage drive unit, the second terminal of which is connected to the clock signal line corresponding to the m-th stage drive unit, and the output terminal of which is connected to the stage transmission output terminal and the drive output terminal of the m-th stage drive unit respectively, and is used to generate a repair signal corresponding to the m-th stage drive unit in repair mode, and repair the drive capability and stage transmission capability of the m-th stage drive unit through the repair signal; wherein, the m-th stage drive unit is an abnormal drive unit.

[0007] Secondly, this application provides a display panel including a display area and a non-display area, wherein the display area includes multiple scan lines; the non-display area includes a gate driving circuit, and the drive output terminal of the drive unit in the gate driving circuit is electrically connected to at least one scan line.

[0008] The technical solution provided in this application has at least the following beneficial effects:

[0009] In normal mode, the virtual unit in this application achieves load matching and tail-stage pull-down through the pre-charge module and output module. In repair mode, the repair module repairs the driving capability and stage transmission capability of the abnormal stage. Therefore, by reusing the virtual unit, this application not only achieves a low-cost and high-efficiency repair method for the gate drive circuit, but also reduces the circuit layout area, making it suitable for narrow bezel and high-resolution display panels. In addition, the repair process of this application does not require external compensation circuitry, reducing signal delay and waveform mismatch risks, and improving panel yield and product competitiveness. Attached Figure Description

[0010] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0011] Figure 1 The diagram shown is a structural schematic of a repair unit in related technologies.

[0012] Figure 2 The diagram shown illustrates the repair techniques used in this invention.

[0013] Figure 3 The diagram shown is a schematic diagram of a gate driving circuit provided in an embodiment of this application.

[0014] Figure 4 The diagram shown is a circuit diagram of the first type of driving unit provided in an embodiment of this application.

[0015] Figure 5 The diagram shown is a circuit diagram of the first type of virtual unit provided in the embodiment of this application.

[0016] Figure 6 The diagram shown is a first type of repair provided in an embodiment of this application.

[0017] Figure 7 The diagram shown is a circuit diagram of the second type of driving unit provided in an embodiment of this application.

[0018] Figure 8 The diagram shown is a circuit diagram of the second type of virtual unit provided in the embodiment of this application.

[0019] Figure 9 The diagram shown is a schematic diagram of a panel partition provided in an embodiment of this application.

[0020] Figure 10 The diagram shown is a second type of repair provided in an embodiment of this application.

[0021] Explanation of reference numerals in the attached figures:

[0022] 100. Gate drive circuit; 110. Drive unit; 120. Virtual unit; 121. Precharge module; 122. Output module; 123. Repair module; 1231. Isolation submodule; T1. First transistor; T2. Second transistor; T3. Third transistor; T4. Fourth transistor; T5. Fifth transistor; T6. Sixth transistor; T7. Seventh transistor; T8. Eighth transistor; T9. Ninth transistor; T10. Tenth transistor; T5-1. First reserved transistor; T5-2. Second reserved transistor; C1. First capacitor; C2. Second capacitor; C2-1. First reserved capacitor; C2-2. Second reserved capacitor; Qa. First drive control node; Qb. Second drive control node; L1. First repair line; L2. Second repair line; L3. Third repair line. Detailed Implementation

[0023] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0024] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0025] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0026] In liquid crystal display (LCD) panels, the Gate Driver on Array (GDL) circuit, as the core row driver circuit, is responsible for outputting scan signals line by line to control the switching state of pixel units, thereby enabling normal image display. However, because GDL circuits are typically composed of a large number of cascaded transistor devices, distributed at the edge of the panel or directly integrated on the glass substrate, their reliability is particularly prominent. Once a stage of the GDL circuit fails, such as due to output waveform distortion, signal delay, or complete failure, the pixels in the corresponding row cannot be correctly selected, resulting in obvious horizontal lines or flickering defects in the displayed image, severely affecting the display quality and yield of the panel.

[0027] In existing technologies, if an anomaly occurs at a certain level of GDL, common responses include:

[0028] (1) Turn off the entire gate output: avoid abnormal diffusion by shielding or disabling the corresponding scan line, but this can only be used in small dual-drive systems and will weaken the driving force of the entire row of pixels, which may lead to display defects.

[0029] (2) External circuit compensation: The output signal of GDL is led out to the PCB, and then repaired by an additional circuit before being sent back to the panel. However, this method increases the wiring complexity and has problems with delay and waveform mismatch.

[0030] (3) Local circuit redundancy: Introduce additional GDL redundant units in the panel design, but such solutions occupy a large area, have high design complexity, and cannot flexibly cope with anomalies in different locations.

[0031] For example: Figure 1 As shown, this repair scheme reserves an additional repair unit outside the GOA circuit (assuming the number of gate stages is 1080). When the nth stage output in the GOA circuit is abnormal, the signal laser of the abnormal stage precharge unit is disconnected, and the signal of F(n-2) is led out to the repair unit through the reserved repair line. The gate of its first transistor T1 is connected to the corresponding F(n-2), and the source is connected to G(n-2). After the repair stage generates the repair signal G(n), it is sent back to the abnormal stage through the repair line. At the abnormal stage, G(n) and F(n) are connected by laser to serve as the precharge signal of the n+2 stage circuit. In addition, the signal of F(n+2) is sent into the repair unit for pull-down. Figure 1 and Figure 2As shown, the repair stage transmission scheme is to disconnect the laser signals G(n-2) and F(n-2) sent to the abnormal stage to avoid the abnormal stage affecting the signals of other stages. In addition, the F(n-2) and F(n+2) signals are introduced into the repair stage. The G(n) required by the repair stage is led out to the abnormal stage, and G(n) and F(n) are laser connected at the abnormal stage. The purpose is to ensure that the G(n+2) can be precharged normally.

[0032] However, this repair method uses additional circuitry for repair, requiring the same number of transistors as a normal GOA circuit. This increases the number of transistors, leading to problems such as design complexity, large footprint, and high cost.

[0033] To address the aforementioned problems, this application provides a gate driving circuit, specifically including the following embodiments:

[0034] Figure 3 The diagram shown is a structural schematic of a gate driving circuit 100 provided in an embodiment of this application; as follows: Figure 3 As shown, the gate drive circuit 100 includes N cascaded drive units 110 (i.e., GDL units) and at least one dummy unit 120 (i.e., DUMMY unit); each drive unit 110 is responsible for generating a gate drive signal G(n) and a cascading signal F(n) to control the switching of pixel rows and cascading transmission. The dummy unit 120 is typically located at the end of the circuit to improve signal integrity and provide pull-down functionality.

[0035] In this embodiment, the virtual unit 120 includes a pre-charge module 121. The control terminal of the pre-charge module 121 is connected to the stage output terminal of the Ni-th stage driving unit 110. The first terminal of the pre-charge module 121 is connected to the drive output terminal of the Ni-th stage driving unit 110. The output terminal of the pre-charge module 121 is connected to the first drive control node Qa, and is used to charge the first drive control node Qa through the gate drive signal of the Ni-th stage driving unit 110. In this application, N is a constant, and i is a variable, which can take any value such as 1, 2, 3, 4, etc. In this embodiment, N=1080 and i=2 are used as an example.

[0036] It should be noted that the precharge module 121 is part of the virtual unit 120 and is controlled by the stage transmission signal output from the stage transmission output terminal of the Ni-stage driving unit 110 and the gate drive signal output from the drive output terminal of the Ni-stage driving unit 110. In normal mode, the stage transmission signal F(Ni) and the gate drive signal G(Ni) of the Ni-stage driving unit 110 are input to the precharge module 121, so that the precharge module 121 charges the first drive control node Qa through the gate drive signal of the Ni-stage driving unit 110, providing a driving basis for the subsequent output module 122.

[0037] In this embodiment, the virtual unit 120 further includes an output module 122. The first end of the output module 122 is connected to the first drive control node Qa, and the second end of the output module 122 is connected to the clock signal line corresponding to the virtual unit 120. The drive output end of the output module 122 is connected to the pull-down control end of the Nj-th stage drive unit 110. It is used to respond to the drive control signal on the first drive control node Qa and the clock signal on the clock signal line in normal mode, and output the stage transmission signal acting on the Nj-th stage drive unit 110.

[0038] It should be noted that the parameters in this embodiment satisfy 0 ≤ j < i, for example, i = 2, j = 0, indicating that the output signal acts on the pull-down control of the Nth stage drive unit 110. After the pre-charge is completed in normal mode, the output module 122 is in the conducting state under the action of the first drive control node Qa. When the clock signal corresponding to the virtual unit 120 arrives, the output module 122 outputs the clock signal as a cascade signal F(Nj). This cascade signal is sent to the pull-down control terminal of the Njth stage drive unit 110 to maintain the normal pull-down operation of the cascade link; for example, the output signal may be used to control the pull-down circuit of the Nth stage drive unit 110 to ensure its normal reset. It should be noted that the output module 122 of the virtual unit 120 can normally output the gate drive signal, but this gate drive signal is not used for the drive of the scan line.

[0039] In this embodiment, the virtual unit 120 further includes a repair module 123. The first end of the repair module 123 is connected to the stage transmission output end of the mi-th driving unit 110, the second end of the repair module 123 is connected to the clock signal line corresponding to the m-th stage driving unit 110, and the output end of the repair module 123 is connected to the stage transmission output end and the drive output end of the m-th stage driving unit 110, respectively. It is used to generate a repair signal corresponding to the m-th stage driving unit 110 in the repair mode, and repair the driving capability and stage transmission capability of the m-th stage driving unit 110 through the repair signal.

[0040] It should be noted that in this embodiment, the m-th stage driving unit 110 is set as the abnormal driving unit 110. In the repair mode, the virtual unit 120 uses the stage transmission signal F(mi) output by the mi-th driving unit 110 and the clock signal line CK(m) corresponding to the m-th stage driving unit 110 to generate a repair signal G(m). The repair signal G(m) replaces the gate driving signal and stage transmission signal of the abnormal stage, thereby restoring the driving capability and stage transmission capability of the abnormal stage driving unit 110.

[0041] The specific working principle is as follows: When the m-th stage drive unit 110 malfunctions, the following operations are performed via laser:

[0042] (1) Disconnect the original precharge path and output path of the m-th stage drive unit 110;

[0043] (2) The transmission signal F(mi) of the mi-th stage drive unit 110 is introduced into the first terminal of the repair module 123.

[0044] (3) Connect the output of the repair module 123 to the stage transmission output and drive output of the m-th stage drive unit 110.

[0045] This embodiment achieves simultaneous repair of the transmission and driving capabilities of the abnormal drive unit 110 through the repair module 123, avoiding horizontal lines or flickering on the display screen. Through laser switching, this module provides a highly flexible repair solution applicable to faults in different locations. Simultaneously, the module design avoids signal crosstalk, ensuring the quality of the repaired waveform and improving the display consistency and reliability of the panel.

[0046] In summary, the virtual unit 120 of this application achieves load matching and tail stage pull-down in normal mode through the pre-charge module 121 and the output module 122, and repairs the driving capability and stage transmission capability of the abnormal stage through the repair module 123 in repair mode. Therefore, by reusing the virtual unit 120, this application not only achieves a low-cost and high-efficiency repair method for the gate drive circuit 100, but also reduces the circuit layout area, making it suitable for narrow bezel and high-resolution display panels. In addition, the repair process of this application does not require external compensation circuits, reducing signal delay and waveform mismatch risks, and improving panel yield and product competitiveness.

[0047] Figure 4 The diagram shown is a circuit schematic of the first type of driving unit 110 provided in an embodiment of this application. Figure 4 As shown, the driving unit 110 in this embodiment includes a precharge module 121, an output module 122, a reset module, a noise reduction module, and a pull-down module; Figure 5 The diagram shown is a circuit diagram of the first type of virtual unit provided in an embodiment of this application. Figure 5 As shown, in order to meet the load matching requirements, the virtual unit 120 and the drive unit 110 in this application have the same circuit structure in the precharge module 121, output module 122, reset module, noise reduction module and pull-down module. The difference is that the virtual unit 120 has an additional repair module 123 compared to the drive unit 110.

[0048] like Figure 4 and Figure 5 As shown, the precharge module 121 includes: a first transistor T1, the control terminal of the first transistor T1 serves as the control terminal of the precharge module 121, the first end of the first transistor T1 serves as the first end of the precharge module 121, and the second end of the first transistor T1 serves as the second end of the precharge module 121.

[0049] like Figure 4 and Figure 5 As shown, the output module 122 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a first capacitor C1, and a second capacitor C2. Specifically, the first terminal of the second transistor T2 serves as the first terminal of the output module 122, and the control terminal of the second transistor T2 serves as the second terminal of the output module 122. The control terminal of the third transistor T3 is connected to the second terminal of the second transistor T2, and the first terminal of the third transistor T3 is connected to the second terminal of the second transistor T2. The second terminal of the third transistor T3 serves as the stage output terminal of the output module 122. The control terminal of the fourth transistor T4 is connected to the control terminal of the third transistor T3 through the second drive control node Qb. The first terminal of the fourth transistor T4 is connected to the power supply terminal, and the second terminal of the fourth transistor T4 serves as the drive output terminal of the output module 122. The first terminal of the first capacitor C1 is connected to the second drive control node Qb, and the second terminal of the first capacitor C1 is connected to the second terminal of the fourth transistor T4. The first terminal of the second capacitor C2 is connected to the first drive control node Qa, and the second terminal of the second capacitor C2 is connected to the second terminal of the fourth transistor T4.

[0050] It should be noted that this embodiment uses N-type MOS transistors as an example to explain the working principle of the precharge module 121 and the output module 122 in detail:

[0051] (1) In normal mode, when the normal stage transmission signal F(ni) of the previous stage becomes high, the first transistor T1 is turned on; at the same time, the normal gate drive signal G(ni) of the previous stage is also a high-level pulse. The turned-on first transistor T1 transmits the high-level pulse G(ni) to the first drive control node Qa, thereby charging the second capacitor C2 connected to the first drive control node Qa, so that the potential of the first drive control node Qa is raised to a higher level; this process occurs before the arrival of the main clock CK(n) of the output module 122, and is a pre-charging operation to prepare the voltage for the subsequent output drive.

[0052] (2) When the corresponding clock signal CK(n) is high, the second transistor T2 is turned on. Since the first drive control node Qa is at a high potential at this time, the high potential of the first drive control node Qa directly acts on the control terminal of the third transistor T3 through the turned-on second transistor T2, causing the third transistor T3 to turn on, thereby outputting a high-level gate drive signal F(n). At the same time, the high potential of the first drive control node Qa charges the second drive control node Qb through the turned-on second transistor T2, causing the potential of the second drive control node Qb to rise. The rise in the potential of the second drive control node Qb causes the fourth transistor T4 to turn on, transmitting the high-level VDD signal to the output terminal, generating the gate drive signal G(n).

[0053] Furthermore, when the output signal of G(n) changes from low to high due to the conduction of the fourth transistor T4, since the voltage across the first capacitor C1 cannot change abruptly, the first capacitor C1 will bootstrap the potential of the second drive control node Qb to a value higher than the high-level voltage of CK(n). This ensures that the fourth transistor T4 can be fully and adequately turned on, resulting in a steep waveform and strong driving capability of the output G(n) signal, which is sufficient to drive the gate line load of the pixel row.

[0054] like Figure 5 As shown, the repair module 123 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an isolation submodule 1231. Specifically, the control terminal of the fifth transistor T5 serves as the second terminal of the repair module 123, the first terminal of the fifth transistor T5 is connected to the first drive control node Qa, and the second terminal of the fifth transistor T5 is connected to the second drive control node Qb. The first terminal of the sixth transistor T6 is connected to the first terminal of the fifth transistor T5, and the control terminal of the sixth transistor T6 is connected to the second terminal of the sixth transistor T6. The first terminal of the seventh transistor T7 serves as the first terminal of the repair module 123, and the control terminal of the seventh transistor T7 serves as the second terminal of the repair module 123. The first terminal of the seventh transistor T7 is connected to the second terminal of the sixth transistor T6; the first terminal of the isolation submodule 1231 is connected to the second terminal of the seventh transistor T7; the second terminal of the isolation submodule 1231 is connected to the first terminal of the fourth transistor T4; the third terminal of the isolation submodule 1231 is connected to the second terminal of the fourth transistor T4; the third terminal of the isolation submodule 1231 serves as the output terminal of the repair module 123, used to isolate the gate drive signal generated by the output module 122 in normal mode, and to repair the abnormal level by the gate drive signal generated by the output module 122 in repair mode.

[0055] In one embodiment, the isolation submodule 1231 includes an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10; the control terminal of the eighth transistor T8 serves as the first terminal of the isolation submodule 1231, and the first terminal of the eighth transistor T8 is connected to a low-level terminal; the control terminal of the ninth transistor T9 is connected to the second terminal of the eighth transistor T8, the first terminal of the ninth transistor T9 is connected to the first terminal of the eighth transistor T8, and the second terminal of the ninth transistor T9 serves as the third terminal of the isolation submodule 1231; the control terminal of the tenth transistor T10 serves as the second terminal of the isolation submodule 1231, the first terminal of the tenth transistor T10 is connected to the control terminal of the ninth transistor T9, and the second terminal of the tenth transistor T10 is connected to the control terminal of the tenth transistor T10.

[0056] It should be noted that this embodiment takes all the above transistors as N-type MOS transistors as an example, and the working principle of the repair module 123 will be explained in detail here:

[0057] (1) such as Figure 5 As shown, a reserved connection point A is formed between the first terminal of the fifth transistor T5 and the first drive control node Qa; a reserved connection point B is formed between the control terminal of the tenth transistor T10 and the first terminal of the fourth transistor T4; and a reserved connection point C is formed between the second terminal of the ninth transistor T9 and the second terminal of the fourth transistor T4. When repair is not required, the reserved connection points are not laser-connected, and the repair module 123 in the virtual unit 120 does not work, thus having no additional impact on the normal operation of the overall circuit. When repair is required, electrical connections are made through the laser-reserved connection points, causing the repair module 123 to work and generate the corresponding repair signal.

[0058] (2) The seventh transistor T7 serves as the pre-charge unit of the repair module 123. After the pre-charge signal F(mi) sequentially turns on the seventh transistor T7 and the sixth transistor T6, the second capacitor C2 is pre-charged through the first drive control node Qa. When the clock signal CK(m) corresponding to the abnormal level arrives, the fifth transistor T5 is turned on. At this time, the charge of the second capacitor C2 is charged into the first capacitor C1 through the first drive control node Qa, the fifth transistor T5, and the second drive control node Qb. The fourth transistor T4 is turned on and pushes the voltage on the second drive control node Qb to Vmax through the bootstrap effect of the first capacitor C1. The repair signal G(m) is output through the second terminal of the fourth transistor T4.

[0059] (3) The functions of the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 are: to isolate the gate drive signal generated by the output module 122 in normal mode, to prevent the G(dm) signal output by the output module 122 from being sent to the abnormal level, and to prevent signal crosstalk; in addition, to repair the abnormal level by the gate drive signal generated by the output module 122 in repair mode; the specific working mechanism is as follows: when the precharge signal F(mi) has not arrived, that is, the precharge signal required for the repair signal G(m) is not generated, the eighth transistor T8 is turned off, and the tenth transistor T10 and the ninth transistor T9 are turned on, thereby pulling down the second terminal of the fourth transistor T4 to a low level, thereby realizing the function of isolating the gate drive signal generated by the output module 122 in normal mode; when the precharge signal F(mi) arrives, the seventh transistor T7 and the eighth transistor T8 are turned on in sequence, and the ninth transistor T9 is turned off, and the repair signal G(m) is output normally, thereby realizing the function of repairing the abnormal level by the gate drive signal generated by the output module 122 in repair mode.

[0060] In this embodiment, the function of the sixth transistor T6 is to prevent the output G(Ni) from being output when the first transistor T1 is turned on, which in turn turns on the eighth transistor T8 and turns off the ninth transistor T9, thus avoiding signal crosstalk and improving the stability of the output signal. The function of the tenth transistor T10 in this embodiment is to reduce the driving force of the high-level signal acting on the gate of the ninth transistor T9, thereby reducing the driving force loss of VDD.

[0061] The repair diagram corresponding to this embodiment is as follows: Figure 6 As shown, this repair method is similar to Figure 2 The difference in the repair methods shown is that: replacement is done via virtual unit 120. Figure 2 The repair unit in the middle; in addition, Figure 6 The circuit structure of virtual unit 120 and Figure 2 Compared to the previous version, a repair module 123 has been added.

[0062] Figure 7 The diagram shown is a circuit diagram of the second type of driving unit 110 provided in an embodiment of this application. Figure 8 The diagram shown is a circuit schematic of the second type of virtual unit 120 provided in an embodiment of this application; as shown Figure 7 and Figure 8 As shown, the pre-charge module 121 of both the driving unit 110 and the virtual unit 120 includes a first transistor T1. The control terminal of the first transistor T1 serves as the control terminal of the pre-charge module 121, the first end of the first transistor T1 serves as the first end of the pre-charge module 121, and the second end of the first transistor T1 serves as the second end of the pre-charge module 121.

[0063] like Figure 7 and Figure 8As shown, the output module 122 of both the driving unit 110 and the virtual unit 120 includes a second transistor T2, a third transistor T3, and a first capacitor C1. Specifically, the control terminal of the second transistor T2 serves as the first terminal of the output module 122, the first terminal of the second transistor T2 serves as the second terminal of the output module 122, and the second terminal of the second transistor T2 serves as the stage transmission output terminal of the output module 122. The control terminal of the third transistor T3 is connected to the control terminal of the second transistor T2, the first terminal of the third transistor T3 is connected to the first terminal of the second transistor T2, and the second terminal of the third transistor T3 serves as the driving output terminal of the output module 122. The first terminal of the first capacitor C1 is connected to the first driving control node Qa, and the second terminal of the first capacitor C1 is connected to the second terminal of the third transistor T3.

[0064] It should be noted that this embodiment takes all transistors as N-type MOS transistors as an example, and the working principle of the pre-charge module 121 and the output module 122 of the drive unit 110 will be explained in detail here:

[0065] (1) In normal mode, when the normal stage transmission signal F(ni) of the previous stage becomes high, the first transistor T1 is turned on; at the same time, the normal gate drive signal G(ni) of the previous stage is also a high-level pulse. The turned-on first transistor T1 transmits the high-level pulse G(ni) to the first drive control node Qa, thereby charging the first capacitor C1 connected to the first drive control node Qa, so that the potential of the first drive control node Qa is raised to a higher level; this process occurs before the arrival of the main clock CK(n) of the output module 122, and is a pre-charging operation to prepare the voltage for the subsequent output drive.

[0066] (2) Since the high potential on the first drive control node Qa simultaneously turns on the second transistor T2 and the third transistor T3, when the corresponding clock signal CK(n) is high, the stage transmission signal F(n) is output through the second terminal of the second transistor T2, and the gate drive signal G(n) is output through the second terminal of the third transistor T3.

[0067] like Figure 8As shown, the repair module 123 of the virtual unit 120 in this embodiment includes an isolation submodule 1231, a fourth transistor T4, a fifth transistor T5, a second capacitor C2, and a third capacitor. Specifically, the isolation submodule 1231 is connected to the first drive control node Qa, the second drive control node Qb, the output terminal of the output module 122, and the output terminal of the repair module 123, respectively, to isolate the first drive control node Qa and the second drive control node Qb from each other, and to isolate the output terminal of the output module 122 from the output terminal of the repair module 123. The control terminal of the fourth transistor T4 serves as the first terminal of the repair module 123, and the first terminal of the fourth transistor T4 is connected to the control terminal of the fourth transistor T4. The second terminal of the fourth transistor T4 is connected to the second drive control node Qb. The first terminal of the second capacitor C2 is connected to the second drive control node Qb, and the second terminal of the second capacitor C2 serves as the output terminal of the repair module 123. The first terminal of the fifth transistor T5 serves as the second terminal of the repair module 123, and the control terminal of the fifth transistor T5 is connected to the second drive control node Qb. The second terminal of the fifth transistor T5 is connected to the second terminal of the second capacitor C2.

[0068] In one embodiment, the isolation submodule 1231 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9. Specifically, the control terminal of the sixth transistor T6 is connected to the first drive control node Qa, the first terminal of the sixth transistor T6 is connected to the control terminal of the sixth transistor T6, and the second terminal of the sixth transistor T6 is connected to the third drive control node; the control terminal of the seventh transistor T7 is connected to the second drive control node Qb, the first terminal of the seventh transistor T7 is connected to the third drive control node, and the second terminal of the seventh transistor T7 is connected to the control terminal of the seventh transistor T7; the control terminal of the eighth transistor T8 is connected to the output terminal of the output module 122, and the first terminal of the eighth transistor T8 is connected to the control terminal of the eighth transistor T8; the control terminal of the ninth transistor T9 is connected to the output terminal of the repair module 123, the first terminal of the ninth transistor T9 is connected to the second terminal of the eighth transistor T8, and the second terminal of the ninth transistor T9 is connected to the control terminal of the ninth transistor T9.

[0069] It should be noted that this embodiment takes all the above transistors as N-type MOS transistors as an example, and the working principle of the repair module 123 will be explained in detail here:

[0070] (1) In this embodiment, the output circuit of the virtual unit 120 is completely divided into two parts by the isolation submodule 1231. One part is the normal signal output part through the output module 122 and the repair signal output part composed of the fourth transistor T4 and the fifth transistor T5. The first drive control node Qa and the second drive control node Qb are isolated by the sixth transistor T6 and the seventh transistor T7 in the isolation submodule 1231. The gate drive signal G(dm) output by the output module 122 and the repair signal G(m) output by the repair module 123 are isolated by the eighth transistor T8 and the sixth transistor T6. In this way, signal crosstalk is avoided, and the same pull-down module, reset module and noise reduction module can be used to reset, pull down and noise reduce the corresponding nodes, thereby reducing the number of transistors in the circuit.

[0071] (2) The fourth transistor T4 serves as the pre-charge unit of the repair module 123. When the pre-charge signal F(mi) arrives, the fourth transistor T4 is turned on and the second capacitor C2 is pre-charged through the second drive control node Qb, while the fifth transistor T5 is turned on. When the clock signal CK(m) corresponding to the abnormal level arrives, the repair signal G(m) is output through the second terminal of the fifth transistor T5.

[0072] In one embodiment, the repair module 123 further includes: at least one reserved capacitor, the first end of the reserved capacitor forming a reserved connection point with the second drive control node Qb, and the second end of the reserved capacitor forming a reserved connection point with the second end of the second capacitor C2.

[0073] In one embodiment, the repair module 123 further includes: at least one reserved transistor, the control terminal of the reserved transistor being connected to the control terminal of the fifth transistor T5, the first terminal of the reserved transistor forming a reserved connection point with the first terminal of the fifth transistor T5, and the second terminal of the reserved transistor forming a reserved connection point with the second terminal of the second capacitor C2.

[0074] like Figure 8 As shown, the reserved capacitors include a first reserved capacitor C2-1 and a second reserved capacitor C2-2, and the reserved transistors include a first reserved transistor T5-1 and a second reserved transistor T5-2; the specific functions of the reserved capacitors and reserved transistors in this embodiment are as follows:

[0075] This embodiment divides the repair levels into three regions: far, middle, and inward. Figure 9Regions 1, 2, and 3 are shown. The reason is that the trace distance from the abnormal level to the virtual cell 120 is inconsistent, which leads to differences in the landing. Therefore, in this embodiment, three bootstrap capacitors are set, namely: the second capacitor C2, the first reserved capacitor, and the second reserved capacitor. Three output transistors are also set, namely: the fifth transistor T5, the first reserved transistor, and the second reserved transistor, to correspond to the landing for different trace distances. If the abnormal level is located in region 3, the first reserved capacitor, the second reserved capacitor, the first reserved transistor, and the second reserved transistor are all connected to the repair module 123 through laser reserved connection points. In this way, by increasing the remote output driving force, the difference between the repair signal G(m) and the normal gate driving signal corresponding to the abnormal level is reduced.

[0076] In addition, the transistors in the pull-down module of the virtual unit 120 in this embodiment adopt a dual-gate structure and increase the gate control signal of F(N+2) so that the repair stage can pull down normally and not interfere with the pull-down function of the virtual unit 120 (the virtual unit 120 adopts STV pull-down).

[0077] In one embodiment, the gate drive circuit 100 further includes a first repair line L1, a second repair line L2, and a third repair line L3; the first repair line L1 forms a reserved connection point with the stage transmission output terminal of each drive unit 110 and the first terminal of the repair module 123 respectively; the second repair line L2 forms a reserved connection point with the stage transmission output terminal of each drive unit 110 and the output terminal of the repair module 123 respectively; and the third repair line L3 forms a reserved connection point with the stage transmission output terminal of each drive unit 110 and the pull-down terminal of the repair module 123 respectively.

[0078] like Figure 8 As shown, the reserved capacitors include a first reserved capacitor C2-1 and a second reserved capacitor C2-2, and the reserved transistors include a first reserved transistor T5-1 and a second reserved transistor T5-2; the specific functions of the reserved capacitors and reserved transistors in this embodiment are as follows:

[0079] This embodiment divides the repair levels into three regions: far, middle, and inward. Figure 9Regions 1, 2, and 3 are shown. The reason is that the trace distance from the abnormal level to the virtual cell is inconsistent, which leads to differences in the landing. Therefore, in this embodiment, three bootstrap capacitors are set: the second capacitor, the first reserved capacitor, and the second reserved capacitor. Three output transistors are also set: the fifth transistor, the first reserved transistor, and the second reserved transistor, to correspond to the landing for different trace distances. If the abnormal level is located in region 3, the first reserved capacitor, the second reserved capacitor, the first reserved transistor, and the second reserved transistor are all connected to the repair module through laser reserved connection points. In this way, by increasing the remote output driving force, the difference between the repair signal G(m) and the normal gate driving signal corresponding to the abnormal level is reduced.

[0080] In addition, the transistors in the pull-down module of the virtual unit in this embodiment adopt a dual-gate structure and add F(N+2) gate control signal so that the repair stage can pull down normally and does not interfere with the pull-down function of the virtual unit (the virtual unit adopts STV pull-down).

[0081] In one embodiment, the gate drive circuit further includes a first repair line, a second repair line, and a third repair line; the first repair line forms a reserved connection point with the stage transmission output terminal of each drive unit and the first terminal of the repair module, respectively; the second repair line forms a reserved connection point with the stage transmission output terminal of each drive unit and the output terminal of the repair module, respectively; and the third repair line forms a reserved connection point with the stage transmission output terminal of each drive unit and the pull-down terminal of the repair module, respectively.

[0082] The repair diagram corresponding to this embodiment is as follows: Figure 10 As shown, this repair method is similar to Figure 6 The only difference between the repair methods shown is: Figure 10 The virtual unit in the middle reduces the VDD signal drive of the power line output; specifically: F(m) and G(m) originally generated at the abnormal level are laser disconnected at the abnormal level. After disconnection, F(m) and G(m) are lasered together again at a distance from the laser disconnection point as the precharge signal of the m+i level.

[0083] In summary, this application achieves automatic compensation for stage-by-stage anomalies or local transistor failures by involving virtual stage circuits in the gate drive circuit for repair. This not only reduces the need for additional repair stages in terms of transistor count and circuit area but also effectively reduces power consumption and wiring complexity. Under extreme conditions such as high and low temperatures, this structure enhances the charge retention capability of the drive control node, ensuring the integrity of the output waveform of the drive unit, thereby significantly improving the display uniformity and stability of the panel. Furthermore, this application fully utilizes existing circuit resources to improve the fault tolerance of the drive unit stage without increasing additional hardware costs, which helps to improve the yield and reliability of large-size, high-resolution panels, and has significant industrial application value and competitive advantages. Therefore, the gate drive circuit repair method in this application has the advantages of simple design improvement and reduced cost, and this improvement is applicable to the repair of single-stage drive unit anomalies, without limiting the type and number of abnormal transistors in a certain stage.

[0084] Thirdly, this application provides a display panel including a display area and a non-display area. The display area includes multiple scan lines; the non-display area includes the gate driving circuit described in the above embodiments, and the drive output terminal of the drive unit in the gate driving circuit is electrically connected to at least one scan line.

[0085] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0086] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0087] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate driving circuit, characterized in that, The gate drive circuit includes N cascaded drive units and at least one virtual unit, the virtual unit comprising: A pre-charge module, wherein the control terminal of the pre-charge module is connected to the stage output terminal of the Ni-level drive unit, the first terminal of the pre-charge module is connected to the drive output terminal of the Ni-level drive unit, and the output terminal of the pre-charge module is connected to the first drive control node, and is used to charge the first drive control node through the gate drive signal of the Ni-level drive unit. An output module, wherein the first end of the output module is connected to the first drive control node, the second end of the output module is connected to the clock signal line corresponding to the virtual unit, and the drive output end of the output module is connected to the pull-down control end of the Nj-th stage drive unit, for responding to the drive control signal on the first drive control node and the clock signal on the clock signal line in normal mode, and outputting the stage transmission signal acting on the Nj-th stage drive unit; wherein, 0≤j<i. A repair module is provided, wherein the first end of the repair module is connected to the stage transmission output of the mi-th driving unit, the second end of the repair module is connected to the clock signal line corresponding to the m-th driving unit, and the output end of the repair module is connected to the stage transmission output and the drive output of the m-th driving unit, respectively. This module is used to generate a repair signal corresponding to the m-th driving unit in repair mode, and to repair the driving capability and stage transmission capability of the m-th driving unit through the repair signal; wherein the m-th driving unit is an abnormal driving unit. The repair module includes: The fifth transistor, the control terminal of the fifth transistor serves as the second terminal of the repair module, the first terminal of the fifth transistor forms a reserved connection point with the first drive control node, and the second terminal of the fifth transistor is connected to the second drive control node; The sixth transistor has its first terminal connected to the first terminal of the fifth transistor, and its control terminal connected to its second terminal. The seventh transistor has a first terminal serving as the first terminal of the repair module, a control terminal connected to the first terminal of the seventh transistor, and a second terminal connected to the second terminal of the sixth transistor. An isolation submodule is provided, wherein the first end of the isolation submodule is connected to the second end of the seventh transistor, the second end of the isolation submodule forms a reserved connection point with the first end of the fourth transistor, and the third end of the isolation submodule forms a reserved connection point with the second end of the fourth transistor. The third end of the isolation submodule serves as the output end of the repair module, used to isolate the gate drive signal generated by the output module in normal mode, and to repair the abnormal level by the gate drive signal generated by the output module in repair mode.

2. The gate driving circuit according to claim 1, characterized in that, The pre-charge module includes: The first transistor has its control terminal serving as the control terminal of the precharge module, its first terminal serving as the first terminal of the precharge module, and its second terminal serving as the second terminal of the precharge module. Or / and, the output module includes: The second transistor has a first terminal serving as the first terminal of the output module and a control terminal serving as the second terminal of the output module. The third transistor has its control terminal connected to the second terminal of the second transistor, and its first terminal connected to the second terminal of the second transistor. The second terminal of the third transistor serves as the stage transmission output terminal of the output module. The fourth transistor has its control terminal connected to the control terminal of the third transistor via a second drive control node. The first terminal of the fourth transistor is connected to the power supply terminal, and the second terminal of the fourth transistor serves as the drive output terminal of the output module. A first capacitor, the first terminal of which is connected to the second drive control node, and the second terminal of which is connected to the second terminal of the fourth transistor; The second capacitor has its first terminal connected to the first drive control node and its second terminal connected to the second terminal of the fourth transistor.

3. The gate driving circuit according to claim 1, characterized in that, The isolation submodule includes: The eighth transistor, the control terminal of which serves as the first terminal of the isolation submodule, is connected to a low-level terminal; The ninth transistor has its control terminal connected to the second terminal of the eighth transistor, its first terminal connected to the first terminal of the eighth transistor, and its second terminal serving as the third terminal of the isolation submodule. The tenth transistor has its control terminal serving as the second terminal of the isolation submodule. The first terminal of the tenth transistor is connected to the control terminal of the ninth transistor, and the second terminal of the tenth transistor is also connected to the control terminal of the tenth transistor.

4. A gate driving circuit, characterized in that, The gate drive circuit includes N cascaded drive units and at least one virtual unit, the virtual unit comprising: A pre-charge module, wherein the control terminal of the pre-charge module is connected to the stage output terminal of the Ni-level drive unit, the first terminal of the pre-charge module is connected to the drive output terminal of the Ni-level drive unit, and the output terminal of the pre-charge module is connected to the first drive control node, and is used to charge the first drive control node through the gate drive signal of the Ni-level drive unit. An output module, wherein the first end of the output module is connected to the first drive control node, the second end of the output module is connected to the clock signal line corresponding to the virtual unit, and the drive output end of the output module is connected to the pull-down control end of the Nj-th stage drive unit, for responding to the drive control signal on the first drive control node and the clock signal on the clock signal line in normal mode, and outputting the stage transmission signal acting on the Nj-th stage drive unit; wherein, 0≤j<i. A repair module is provided, wherein the first end of the repair module is connected to the stage transmission output of the mi-th driving unit, the second end of the repair module is connected to the clock signal line corresponding to the m-th driving unit, and the output end of the repair module is connected to the stage transmission output and the drive output of the m-th driving unit, respectively. This module is used to generate a repair signal corresponding to the m-th driving unit in repair mode, and to repair the driving capability and stage transmission capability of the m-th driving unit through the repair signal; wherein the m-th driving unit is an abnormal driving unit. The repair module includes: An isolation submodule is connected to the first drive control node, the second drive control node, the output terminal of the output module, and the output terminal of the repair module, respectively, for isolating the first drive control node and the second drive control node from each other, and isolating the output terminal of the output module and the output terminal of the repair module from each other; The fourth transistor, wherein the control terminal of the fourth transistor serves as the first terminal of the repair module, the first terminal of the fourth transistor is connected to the control terminal of the fourth transistor, and the second terminal of the fourth transistor is connected to the second drive control node; The second capacitor has its first end connected to the second drive control node, and its second end serves as the output terminal of the repair module. The fifth transistor has its first terminal serving as the second terminal of the repair module, its control terminal connected to the second drive control node, and its second terminal connected to the second terminal of the second capacitor.

5. The gate driving circuit according to claim 4, characterized in that, The pre-charge module includes: The first transistor has its control terminal serving as the control terminal of the precharge module, its first terminal serving as the first terminal of the precharge module, and its second terminal serving as the second terminal of the precharge module. Or / and, the output module includes: The second transistor has its control terminal serving as the first terminal of the output module, its first terminal serving as the second terminal of the output module, and its second terminal serving as the stage transmission output terminal of the output module. The third transistor has its control terminal connected to the control terminal of the second transistor, its first terminal connected to the first terminal of the second transistor, and its second terminal serving as the drive output terminal of the output module. A first capacitor, the first terminal of which is connected to the first drive control node, and the second terminal of which is connected to the second terminal of the third transistor.

6. The gate driving circuit according to claim 4, characterized in that, The repair module also includes: At least one reserved capacitor, wherein the first end of the reserved capacitor forms a reserved connection point with the second drive control node, and the second end of the reserved capacitor forms a reserved connection point with the second end of the second capacitor; Or / and, at least one reserved transistor, the control terminal of the reserved transistor being connected to the control terminal of the fifth transistor, the first terminal of the reserved transistor forming a reserved connection point with the first terminal of the fifth transistor, and the second terminal of the reserved transistor forming a reserved connection point with the second terminal of the second capacitor.

7. The gate driving circuit according to claim 4, characterized in that, The isolation submodule includes: The sixth transistor has a control terminal connected to the first drive control node, a first terminal connected to the control terminal, and a second terminal connected to the third drive control node. A seventh transistor, wherein the control terminal of the seventh transistor is connected to the second drive control node, the first terminal of the seventh transistor is connected to the third drive control node, and the second terminal of the seventh transistor is connected to the control terminal of the seventh transistor; The eighth transistor has its control terminal connected to the output terminal of the output module, and its first terminal is connected to the control terminal of the eighth transistor. The ninth transistor has its control terminal connected to the output terminal of the repair module, its first terminal connected to the second terminal of the eighth transistor, and its second terminal connected to the control terminal of the ninth transistor.

8. The gate driving circuit according to any one of claims 1-7, characterized in that, The gate driving circuit further includes: The first repair line forms a reserved connection point with the stage transmission output end of each drive unit and the first end of the repair module; The second repair line forms a reserved connection point with the stage transmission output terminal of each drive unit and the output terminal of the repair module; The third repair line forms a reserved connection point with the stage transmission output terminal of each drive unit and the pull-down terminal of the repair module.

9. A display panel, comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines; characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1 to 8, wherein the driving output terminal of the driving unit in the gate driving circuit is electrically connected to at least one scan line.

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