Power supply starting and constant current logic circuit and control method

Abstract

The invention discloses a power supply starting and constant current logic circuit and a control method thereof. The circuit comprises a constant-current power supply management chip U1, a starting branch and a constant-current control branch. The starting branch comprises a triode Q1 and a clamping / biasing network thereof, and a preset level Vpre is provided for the FB in a power-on stage so as to meet the starting condition of the U1; and along with the rise of the OUT, when the VBE of the Q1 is reduced to a cut-off threshold VBEOFF, the starting branch automatically quits. The constant-current control branch is composed of an operational amplifier U2, a sampling resistor Rs and a reference source Vref, the U2 compares voltages at the two ends of the Rs with the Vref and applies the voltages to the FB through a one-way coupling network, and closed-loop constant-current control over the output current after starting is achieved. Furthermore, a conflict detection and power consumption suppression sub-circuit is provided, when external trigger inputs A and B are effective at the same time, VINDET is pulled down to be lower than an undervoltage locking threshold VUVLO of U1, a grid electrode of a power MOSFET M1 is pulled down, and the retention time Thold is larger than or equal to Trestartmin, so that repeated starting is suppressed. The power-on success rate is improved, the handover oscillation is suppressed, and the system power consumption is reduced.

Description

Technical Field

[0001] This invention relates to the field of power management and analog circuit control, specifically a power-on and constant current logic circuit and control method. Background Technology

[0002] Constant current power supplies are widely used in LED driving, battery formation / aging, sensor excitation, and power-on management of communication equipment. In traditional solutions, the handover between the soft-start branch and the constant current loop often presents the following problems: 1) The power-on boundary conditions are harsh, and the FB terminal has difficulty entering the effective area quickly during cold start, resulting in a cycle of "jitter-power failure-restart"; 2) The starting branch and the constant current loop restrain each other, and the FB potential jump at the moment of handover causes oscillation or overshoot; 3) In multi-source triggering or abnormal conditions, improper coupling between undervoltage lockout (UVLO) and external control logic can easily lead to high-frequency repeated startup, resulting in EMI and power consumption problems. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a power-on and constant-current logic circuit, including: a constant-current power management chip U1, a startup branch, and a constant-current control branch; The constant current power management chip U1 has a feedback pin FB and an output node OUT; The startup branch includes transistor Q1 and its clamping / biasing network. The collector of Q1 is connected to FB, the emitter is connected to OUT, and the base is controlled by the clamping / biasing network to provide a preset level Vpre to FB during the power-on phase, so that U1 meets the startup conditions. As OUT rises, when the base-emitter voltage VBE of Q1 drops to the cutoff threshold VBE_OFF, the startup branch automatically cuts off and stops affecting FB. The constant current control branch includes an operational amplifier U2, a sampling resistor Rs, and a reference source Vref. U2 is used to compare the voltage across Rs with Vref and apply the comparison result to FB via a coupling network to perform closed-loop constant current control on the output current after the start-up branch exits.

[0004] Furthermore, the clamping / biasing network is set with OUT as a reference, so that the base potential of Q1 increases as OUT rises, and VBE_OFF is limited by the base resistor Rb and the clamping device. Q1 is turned off when OUT reaches a predetermined threshold VOUT_TH; wherein, the clamping device is a diode.

[0005] Furthermore, the preset level Vpre is provided by a preset level generator, which is a voltage divider network consisting of series voltage divider resistors R1 and R2 and a parallel time constant capacitor C1, or a constant current limiting network consisting of a constant current source Ipre, a current limiting resistor Rlim, and a limiting diode Dlim; and the exit mechanism of the start-up branch is not achieved by setting a conduction path between FB and ground / power supply node consisting of a unidirectional device and a capacitor connected in series / parallel, which is cut off in reverse to allow the capacitor to be quickly released or decoupled.

[0006] Furthermore, the coupling network includes a unidirectional isolation diode D2 and a series resistor Rf. D2 and Rf are connected in series between the output terminal of U2 and FB. The anode of D2 is connected to the output terminal of U2, and the cathode is connected to FB via Rf, so as to reduce the mutual interference between the constant current control branch and the start-up branch and suppress the switching transient oscillation.

[0007] Furthermore, Rs is positioned between the load circuit and ground. The inverting input of U2 is connected to the load side of Rs, and the non-inverting input is connected to Vref. The output of U2 is adjusted by FB through the coupling network to maintain the voltage on Rs near Vref so as to set the constant current Iout≈Vref / Rs.

[0008] Furthermore, it also includes a collision detection and power consumption suppression sub-circuit, which has a first external trigger input A and a second external trigger input B; when A and B are both active: Pull the input detection node VIN_DET below the undervoltage lockout threshold VUVLO of U1 to put U1 into the undervoltage judgment state; and pull down the gate of the power MOSFET M1 used for startup to keep the startup branch off to suppress repeated startup.

[0009] Furthermore, the conflict detection and power consumption suppression sub-circuit includes a logic determination circuit and a holding circuit. The logic determination circuit is used to determine the validity of the combination of A and B and simultaneously drive VIN_DET and the gate of M1 to the off level. The holding circuit sets a holding time Thold, so that the duration for which VIN_DET and the gate of M1 are simultaneously kept off is not less than the minimum automatic restart period of U1, Trestart_min, thereby suppressing repeated startups for a short period of time after the conflict is resolved.

[0010] Furthermore, the logic decision circuit is any one of AND gate logic, window comparator or its analog equivalent gating network; the holding circuit is a monostable multivibrator or an integrated RC timer.

[0011] A control method for power-on and constant-current logic, applied to a power-on and constant-current logic circuit, characterized in that it includes: S1: During the power-on phase, Vpre is provided to FB through the startup branch containing Q1, so that U1 meets the startup conditions and drives OUT to rise; S2: As OUT increases, when VBE(Q1)≤VBE_OFF, the starting branch will automatically stop and exit the influence on FB based on the VBE threshold. S3: After the start-up branch exits, the constant current control branch compares the voltage across Rs with Vref, and adjusts FB through a unidirectional coupling network to maintain the output current at the target constant current.

[0012] Preferably, it further includes: when external trigger inputs A and B are both valid, simultaneously pull VIN_DET low to below VUVLO and pull down the gate of M1, and keep at least Thold ≥ Trestart_min, so as to suppress rapid repeated startup at the moment the conflict is resolved; then restore VIN_DET and M1 to normal state, and then execute S1 to S3 in sequence. Where A is the first external trigger input; B is the second external trigger input; VIN_DET is the input detection node; VUVLO is the undervoltage lockout threshold; Thold is the hold time; and Trestart_min is the minimum automatic restart cycle.

[0013] The beneficial effects of this invention are: 1) High startup success rate: Vpre ensures that FB enters the valid area during the initial power-on phase; 2) Disturbance-free handover: Natural exit based on VBE threshold avoids memory / residual charge effects caused by the "reverse cutoff decoupling path"; 3) Loop stability: The unidirectional coupling of D2+Rf suppresses mutual interference and transient ringing; 4) Controllable power consumption: The conflict detection and hold strategy curbs repeated startups at the system level, reducing thermal stress and EMI. Attached Figure Description

[0014] Figure 1 A flowchart illustrating a control method for power-on startup and constant current logic; Figure 2 This is a schematic diagram of the processing flow when external trigger inputs A and B are both valid. Detailed Implementation

[0015] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings, but the scope of protection of the present invention is not limited to the following description.

[0016] The features and performance of the present invention will be further described in detail below with reference to embodiments.

[0017] A power-on and constant-current logic circuit includes: a constant-current power management chip U1, a startup branch, and a constant-current control branch; The constant current power management chip U1 has a feedback pin FB and an output node OUT; The startup branch includes transistor Q1 and its clamping / biasing network. The collector of Q1 is connected to FB, the emitter is connected to OUT, and the base is controlled by the clamping / biasing network to provide a preset level Vpre to FB during the startup phase, so that U1 meets the startup conditions. As OUT rises, when the base-emitter voltage VBE of Q1 drops to its cutoff threshold VBE_OFF, the startup branch automatically cuts off and stops affecting FB. The constant current control branch includes an operational amplifier U2, a sampling resistor Rs, and a reference source Vref. U2 is used to compare the voltage across Rs with Vref and apply the comparison result to FB via a coupling network to perform closed-loop constant current control on the output current after the start-up branch exits.

[0018] The clamping / biasing network is set with OUT as a reference, so that the base potential of Q1 increases as OUT rises. The base resistor Rb and the clamping device are used to set the VBE of Q1 to drop to its cutoff threshold VBE_OFF when OUT reaches a predetermined threshold VOUT_TH, thereby turning off Q1. The clamping device is a diode.

[0019] The preset level Vpre is provided by a preset level generator, which is a voltage divider network consisting of series voltage divider resistors R1 and R2 and a parallel time constant capacitor C1, or a constant current limiting network consisting of a constant current source Ipre, a current limiting resistor Rlim, and a limiting diode Dlim. The exit mechanism of the startup branch is not achieved by setting a soft-start / decoupling network consisting of a unidirectional device and a capacitor connected in series or in parallel between FB and ground and / or power supply nodes, and relying on the unidirectional device to conduct in one direction and cut off in the opposite direction to enable the capacitor to charge and discharge quickly or decouple from FB.

[0020] The coupling network includes a unidirectional isolation diode D2 and a series resistor Rf. D2 and Rf are connected in series between the output terminal of U2 and FB. The anode of D2 is connected to the output terminal of U2, and the cathode is connected to FB via Rf, so as to reduce the mutual interference between the constant current control branch and the start-up branch and suppress the switching transient oscillation.

[0021] Rs is positioned between the load circuit and ground. The inverting input of U2 is connected to the load side of Rs, and the non-inverting input is connected to Vref. The output of U2 is adjusted by the coupling network FB so that the voltage on Rs is maintained near Vref to set the constant current Iout≈Vref / Rs.

[0022] It also includes a conflict detection and power consumption suppression sub-circuit, which has a first external trigger input A and a second external trigger input B; wherein, the power MOSFET M1 used for startup is connected in series in the input power supply path or output power supply path of U1, and together with the startup branch, forms a startup loop; when A and B are both active: Pull the input detection node VIN_DET below the undervoltage lockout threshold VUVLO of U1 to put U1 into the undervoltage determination state; and pull down the gate of the power MOSFET M1 used for startup to keep the startup circuit off to suppress repeated startup.

[0023] The input detection node VIN_DET is connected to the undervoltage detection comparator inside U1, and its potential is compared with the undervoltage lockout threshold VUVLO to determine whether U1 has entered an undervoltage state. The conflict detection and power consumption suppression sub-circuit includes a logic determination circuit and a holding circuit. The logic determination circuit is used to determine the validity of the combination of A and B and simultaneously drive VIN_DET and the gate of M1 to the off level. The holding circuit sets a holding time Thold, so that the duration for which VIN_DET and the gate of M1 are simultaneously kept off is not less than the minimum automatic restart period of U1 Trestart_min, thereby suppressing repeated startups for a short period of time after the conflict is resolved.

[0024] The logic decision circuit is any one of AND gate logic, window comparator or its analog equivalent gating network; the holding circuit is a monostable trigger or RC timing network / integrated timer.

[0025] like Figure 1 As shown, a control method for power-on and constant-current logic is applied to the aforementioned power-on and constant-current logic circuit, comprising: S1: During the startup phase, a preset level Vpre is generated by the preset level generator and applied to FB through the startup branch containing Q1, so that U1 meets the startup conditions and drives OUT to start rising. S2: As OUT increases, when VBE(Q1)≤VBE_OFF, the starting branch will automatically stop and exit the influence on FB based on the VBE threshold. S3: After the start-up branch exits, the constant current control branch compares the voltage across Rs with Vref, and adjusts FB through a unidirectional coupling network to maintain the output current at the target constant current.

[0026] like Figure 2As shown, it also includes: when external trigger inputs A and B are valid at the same time, VIN_DET is pulled low to below VUVLO and the gate of M1 is pulled down, and Thold is kept at least ≥ Trestart_min, so as to suppress rapid repeated startup at the moment the conflict is resolved; then VIN_DET and M1 are restored to normal state, and S1 to S3 are executed in sequence. Where A is the first external trigger input; B is the second external trigger input; VIN_DET is the input detection node connected to the U1 undervoltage detection comparator; VUVLO is the undervoltage lockout threshold; Thold is the hold time; and Trestart_min is the minimum automatic restart cycle.

[0027] Example 1: Voltage divider preset + diode clamping + basic constant current control The constant current power management chip U1 has a feedback pin FB and an output node OUT, and an undervoltage lockout threshold VUVLO. The startup branch includes: an NPN Q1 (e.g., in an SOT-23 package), a base resistor Rb, a clamping diode Dclamp (a common silicon diode), and a preset level generator, which is an R1 / R2 / C1 voltage divider network: R1 and R2 are connected in series between OUT and ground, FB is connected through a limiting resistor from the voltage divider point of R1 and R2, and C1 is connected in parallel with R2.

[0028] The constant current control branch includes: operational amplifier U2 (rail-to-rail or its input common-mode range covers the Rs voltage), sampling resistor Rs connected to the load circuit to ground; reference voltage source Vref (e.g., 1.00 V); the inverting input terminal of U2 is connected to the Rs load side, and the non-inverting input terminal is connected to Vref; the output of U2 is coupled to FB via unidirectional isolation diode D2 and damping resistor Rf.

[0029] This embodiment does not employ a "reverse cutoff decoupling path": that is, a soft-start network consisting of diodes and capacitors is not set between the FB and ground and / or power supply nodes, and the network is not used to conduct in one direction and cut off in the opposite direction to achieve rapid charging and discharging of the soft-start capacitor or decoupling from the FB.

[0030] The working process is as follows: During the process of U1 powering on and attempting to drive OUT to gradually rise, the R1 / R2 / C1 voltage divider network divides the voltage of OUT, and the resulting preset level Vpre is applied to FB through the startup branch, making it easier for U1 to meet the startup conditions and drive OUT to continue rising. At the same time, the collector of Q1 is connected to FB, the emitter is connected to OUT, and the base is controlled by Rb and Dclamp. As OUT rises, the base potential of Q1 rises with OUT, and its VBE gradually decreases; when VBE≤VBE_OFF (typically 0.55–0.65 V), Q1 is cut off, and the startup branch automatically exits. At this time, the constant current loop is closed: U2 adjusts its output to pull FB through D2 and Rf, so that the Rs voltage is maintained at approximately Vref, thus Iout≈Vref / Rs. D2 provides unidirectional isolation, and Rf is used for phase compensation / damping to suppress the oscillation at the moment of startup branch exit and constant current take-off.

[0031] Typical parameters include: Vref=1.00 V, Iout=500 mA ⇒ Rs≈1.00 V / 0.5 A=2.0 Ω (select ≥1 W metal film or shunt, such as 2.0 Ω / 2 W); R1=240 kΩ, R2=100 kΩ, C1=100 nF (Vpre rise time constant ≈ R2·C1). Rb=47 kΩ, Dclamp=1N4148; D2 is a Schottky diode (such as BAT54), Rf = 1–4.7 kΩ; Optionally, a compensation capacitor Cf (e.g., 10–100 pF) can be connected in parallel between the output of U2 and its inverting input to optimize the phase margin.

[0032] VOUT_TH is preferably set so that Q1 exits when OUT reaches 30–60% of the steady-state output voltage, in order to avoid competing for control with the constant current closed loop.

[0033] Example 2: Constant current source preset + Zener diode clamping + collision detection (AND gate + RC monostable multivibrator) Compared with Example 1, the main difference in this example is: The preset level generator uses a constant current source Ipre (e.g., 2–10 μA) and a current limiting resistor Rlim, along with a limiting diode Dlim, to form a constant current limiting network to generate Vpre and limit the injection of power-on spikes into FB. The clamping device uses a Zener diode Dclamp (such as a 2.4–3.3 V low-power Zener) to stabilize the base rise trajectory of Q1 and more accurately set VOUT_TH corresponding to VBE_OFF; A collision detection and power consumption suppression sub-circuit is introduced: the logic decision uses an AND gate, and the holding circuit uses an RC monostable network.

[0034] In the collision detection and power consumption suppression sub-circuit: A and B are external trigger inputs (e.g., A is the external adapter insertion detection signal; B is the battery present and voltage valid signal). When both A and B are valid, the AND gate outputs a high level: (i) Pull VIN_DET below VUVLO of U1, so that U1 enters the undervoltage judgment state; (ii) At the same time, the gate of the power MOSFET M1 related to startup is pulled low via NMOS or pull-down network to disable the startup circuit; The holding circuit consists of an RC monostable network composed of Rhold / Chold, providing a holding time Thold, ensuring that the duration for which VIN_DET and the gate of M1 remain off is not less than the minimum auto-restart period of U1, Trestart_min.

[0035] Typical values ​​are as follows: Trestart_min=50 ms, then the design Thold=70–100 ms; Ipre=5 μA, Rlim=200 kΩ, Dlim is a Schottky diode, which limits Vpre to a safe window of 0.3–0.4 V; Dclamp uses a 2.7 V Zener diode with Rb=56 kΩ; Rhold=560 kΩ, Chold=150 nF (Thold≈Rhold·Chold≈84 ms); Other parameters are the same as in Example 1 or scaled appropriately according to the target Iout.

[0036] Example 3: Window comparator decision + monostable multivibrator hold + disturbance rejection optimization In this embodiment, the logic determination circuit uses a window comparator: when the combination of A and B is in a pre-set "conflict window" (for example, A is high and B is high, or the A / B levels are within a defined voltage window), the window comparator outputs a valid control signal; The holding circuit uses a monostable multivibrator, which can be implemented by a low-power timer or an on-chip monostable module. The monostable multivibrator outputs a fixed-width pulse after being triggered by the valid edge of the window comparator. This pulse synchronously pulls VIN_DET and the M1 gate low, maintaining the off state for the duration of the pulse width.

[0037] To enhance disturbance rejection and stability, this embodiment can be further optimized as follows: U2 loop compensation: A small capacitor Cf (e.g., 22–82 pF) is placed between the inverting input terminal and the output of U2, which together with Rf forms an appropriate zero-pole point to ensure sufficient phase margin; Impedance shaping on the FB side: A small capacitor Cfb (e.g., 47–220 pF) is connected in parallel between the FB and ground to reduce high-frequency noise injection into the FB node, while controlling the steady-state error within the allowable range; For high-current applications, it is preferable to use a sampling resistor Rs with low parasitic inductance (such as a four-terminal shunt) and optimize the current return path to reduce the disturbance of the ground bounce voltage caused by dI / dt on the common-mode input of U2.

[0038] Relevant parameters are as follows: Window comparator thresholds: VTH_L=0.8 V, VTH_H=2.0 V (can be set according to A / B interface standard); Monostable trigger pulse width Tw = 100 ms (Tw ≥ Trestart_min); Cf is set to 47 pF, and Cfb is set to 100 pF; For other parameters, please refer to Examples 1 and 2.

[0039] The control method implementation steps, applicable to any of the above embodiments, include: S1: During the startup phase, a preset level Vpre is generated by the preset level generator and applied to FB through the startup branch containing Q1, so that U1 meets the startup conditions and drives OUT to start rising. S2: As OUT increases, VBE of Q1 gradually decreases. When VBE(Q1)≤VBE_OFF, Q1 is cut off, and the starting branch automatically exits its influence on FB. S3: After the start-up branch exits, the constant current control branch closes. U2 compares the voltage across Rs with Vref. FB is adjusted via D2 and Rf unidirectional coupling to make Iout≈Vref / Rs stable output. Optionally, S4: When A and B are both valid, the logic determination circuit outputs a valid signal, pulls VIN_DET low to below VUVLO and pulls down the gate of M1, and keeps Thold ≥ Trestart_min; after the holding time ends and the conflict is resolved, VIN_DET and the gate of M1 are restored to normal state, and then S1 to S3 are executed.

[0040] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A power-on and constant-current logic circuit, characterized in that, include: Constant current power management chip U1, startup branch, constant current control branch; The constant current power management chip U1 has a feedback pin FB and an output node OUT; The startup branch includes transistor Q1 and its clamping / biasing network, wherein the collector of Q1 is connected to FB, the emitter is connected to OUT, and the base is controlled by the clamping / biasing network to provide a preset level Vpre to FB during the power-on phase, so that U1 meets the startup conditions. As OUT increases, when the base-emitter voltage VBE of Q1 drops to the cutoff threshold VBE_OFF, the start-up branch automatically shuts off and stops affecting FB. The constant current control branch includes an operational amplifier U2, a sampling resistor Rs, and a reference source Vref. U2 is used to compare the voltage across Rs with Vref and apply the comparison result to FB via a coupling network to perform closed-loop constant current control on the output current after the start-up branch exits.

2. The power-on and constant-current logic circuit according to claim 1, characterized in that, The clamping / biasing network is set with OUT as a reference, so that the base potential of Q1 increases as OUT rises, and VBE_OFF is limited by the base resistor Rb and the clamping device. Q1 is turned off when OUT reaches a predetermined threshold VOUT_TH; wherein, the clamping device is a diode.

3. The power-on and constant-current logic circuit according to claim 1, characterized in that, The preset level Vpre is provided by a preset level generator, which is a voltage divider network consisting of series voltage divider resistors R1 and R2 and a parallel time constant capacitor C1, or a constant current limiting network consisting of a constant current source Ipre, a current limiting resistor Rlim, and a limiting diode Dlim. Furthermore, the exit mechanism of the start-up branch is not achieved by setting a conduction path between FB and the ground / power supply node, which consists of a unidirectional device and a capacitor connected in series / parallel and is cut off in reverse to allow the capacitor to be quickly released or decoupled.

4. The power-on and constant-current logic circuit according to claim 1, characterized in that, The coupling network includes a unidirectional isolation diode D2 and a series resistor Rf. D2 and Rf are connected in series between the output terminal of U2 and FB. The anode of D2 is connected to the output terminal of U2, and the cathode is connected to FB via Rf, so as to reduce the mutual interference between the constant current control branch and the start-up branch and suppress the switching transient oscillation.

5. The power-on and constant-current logic circuit according to claim 1, characterized in that, Rs is positioned between the load circuit and ground. The inverting input of U2 is connected to the load side of Rs, and the non-inverting input is connected to Vref. The output of U2 is adjusted by the coupling network FB so that the voltage on Rs is maintained near Vref to set the constant current Iout≈Vref / Rs.

6. The power-on and constant-current logic circuit according to claim 1, characterized in that, It also includes a collision detection and power consumption suppression sub-circuit, which has a first external trigger input A and a second external trigger input B; when A and B are both active: Pull the input detection node VIN_DET below the undervoltage lockout threshold VUVLO of U1 to put U1 into the undervoltage judgment state; and pull down the gate of the power MOSFET M1 used for startup to keep the startup branch off to suppress repeated startup.

7. The power-on and constant-current logic circuit according to claim 6, characterized in that, The conflict detection and power consumption suppression sub-circuit includes a logic determination circuit and a holding circuit. The logic determination circuit is used to determine the validity of the combination of A and B and simultaneously drive VIN_DET and the gate of M1 to the off level. The holding circuit sets a holding time Thold, so that the duration for which VIN_DET and the gate of M1 are simultaneously kept off is not less than the minimum automatic restart period of U1 Trestart_min, thereby suppressing repeated startups for a short period of time after the conflict is resolved.

8. The power-on and constant-current logic circuit according to claim 7, characterized in that, The logic decision circuit is any one of AND gate logic, window comparator or its analog equivalent gating network; the holding circuit is a monostable multivibrator or an integrated RC timer.

9. A control method for power-on startup and constant current logic, applied to a power-on startup and constant current logic circuit as described in any one of claims 1-8, characterized in that, include: S1: During the power-on phase, Vpre is provided to FB through the startup branch containing Q1, so that U1 meets the startup conditions and drives OUT to rise; S2: As OUT increases, when VBE(Q1)≤VBE_OFF, the starting branch will automatically stop and exit the influence on FB based on the VBE threshold. S3: After the start-up branch exits, the constant current control branch compares the voltage across Rs with Vref, and adjusts FB through a unidirectional coupling network to maintain the output current at the target constant current.

10. The control method for power-on and constant current logic according to claim 9, characterized in that, Also includes: When external trigger inputs A and B are both valid, VIN_DET is pulled low to below VUVLO and the gate of M1 is pulled down, and Thold is kept at least ≥ Trestart_min to suppress rapid repeated startup at the moment the conflict is resolved; then VIN_DET and M1 are restored to normal state, and S1 to S3 are executed in sequence. Where A is the first external trigger input; B is the second external trigger input; VIN_DET is the input detection node; VUVLO is the undervoltage lockout threshold; Thold is the hold time; and Trestart_min is the minimum automatic restart cycle.

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