Stacked image sensor

Abstract

The stacked image sensor includes a first pixel array including a plurality of photoelectric conversion elements sharing a floating diffusion node, and a second pixel array configured to convert optical signals from the plurality of photoelectric conversion elements into electrical signals and output the electrical signals, the second pixel array includes a first conversion gain control transistor connected to the floating diffusion node, and a second conversion gain control transistor connected in series to the first conversion gain control transistor, and the first pixel array further includes a capacitor connected between the first conversion gain control transistor and the second conversion gain control transistor.

Description

[0001] Cross Reference to Related Applications

[0002] Related Applications This application is based on and claims priority to Korean Patent Application No. 10-2024-0081373, filed on June 21, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. TECHNICAL FIELD

[0003] The inventive concept relates to a stacked image sensor. More particularly, the inventive concept relates to a stacked image sensor operable in a multiple conversion gain mode. BACKGROUND

[0004] An image sensor can be a device that converts an optical image into an electrical signal, and can be used in a camera of a portable electronic device such as a smart phone or a tablet personal computer (PC). A stacked image sensor has been developed to reduce the size of a portable electronic device and improve camera performance. The stacked image sensor can achieve a reduction in the planar area of an image sensor, an increase in the resolution of an image sensor, and an increase in the signal processing speed of an image sensor. SUMMARY

[0005] The inventive concept provides an image sensor capable of securing capacitance in a floating diffusion region by using a capacitor formed on a top plate.

[0006] According to some aspects of the inventive concept, a stacked image sensor is provided.

[0007] According to some aspects of the inventive concept, a stacked image sensor is provided, including a first pixel array including a plurality of photoelectric conversion elements sharing a floating diffusion node, and a second pixel array configured to convert an optical signal from the plurality of photoelectric conversion elements into an electrical signal and output the electrical signal, the second pixel array including a first conversion gain control transistor connected to the floating diffusion node, and a second conversion gain control transistor connected in series to the first conversion gain control transistor, and the first pixel array further including a capacitor connected between the first conversion gain control transistor and the second conversion gain control transistor.

[0008] According to some aspects of the inventive concept, a stacked image sensor is provided.

[0009] According to some aspects of the inventive concept, there is provided a stacked image sensor including a first semiconductor chip including at least one photoelectric conversion region, at least one floating diffusion region, at least one transfer transistor configured to transfer a charge in the at least one photoelectric conversion region to the at least one floating diffusion region, and a deep trench isolation structure configured to isolate each of the at least one photoelectric conversion region, and a second semiconductor chip including a pixel circuit configured to convert a light signal from the at least one photoelectric conversion region into an electrical signal and output the electrical signal, the first semiconductor chip including a capacitor formed on the deep trench isolation structure and configured to adjust a conversion gain in the at least one floating diffusion region.

[0010] According to some aspects of the inventive concept, there is provided a stacked image sensor.

[0011] According to some aspects of the inventive concept, there is provided a stacked image sensor including a first unit pixel and a second unit pixel, the first unit pixel including a first pixel array and a second pixel array, the first pixel array including a plurality of photoelectric conversion elements sharing a floating diffusion node, and the second pixel array configured to convert a light signal from the plurality of photoelectric conversion elements into an electrical signal and output the electrical signal, the second unit pixel including a first pixel array and a second pixel array, the first pixel array of the second unit pixel including a plurality of photoelectric conversion elements sharing a floating diffusion node, and the second pixel array of the second unit pixel configured to convert a light signal from the plurality of photoelectric conversion elements into an electrical signal and output the electrical signal, the first pixel array of the first unit pixel and the first pixel array of the second unit pixel being in a first semiconductor chip, and the second pixel array of the first unit pixel and the second pixel array of the second unit pixel being in a second semiconductor chip, the second pixel array of the first unit pixel and the second pixel array of the second unit pixel each including a first conversion gain control transistor connected to the floating diffusion node and a second conversion gain control transistor connected in series to the first conversion gain control transistor, and the first pixel array of the first unit pixel and the first pixel array of the second unit pixel each further including a capacitor configured to adjust a conversion gain of the floating diffusion node, respectively. BRIEF DESCRIPTION OF DRAWINGS

[0012] Example embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, and by comparison with the claims, in which:

[0013] Figure 1 is a block diagram of an image sensor according to some example embodiments;

[0014] Figure 2 is a diagram illustrating Figure 1a block diagram of a first pixel array, a second pixel array, a logic circuit, and an analog-to-digital converter (ADC) of

[0015] Figure 3 is a three-dimensional view illustrating Figure 1 a perspective view of a first pixel array, a second pixel array, a logic circuit, and an ADC of

[0016] Figure 4 is a circuit diagram illustrating a unit pixel including Figure 1 a first pixel array and a second pixel array of

[0017] Figures 5A-5C is a timing diagram illustrating timing of a signal applied to adjust a multiple conversion gain in Figure 4

[0018] Figure 6A and Figure 6B is a circuit diagram of a unit pixel according to some example embodiments;

[0019] Figure 7A is a plan view illustrating an arrangement of components of a first pixel array on a first semiconductor chip in Figure 4

[0020] Figure 7B is a sectional view of a plan view of Figure 7A Figure 7A

[0021] Figure 8A is a plan view of a unit pixel in a first semiconductor chip according to some example embodiments;

[0022] Figure 8B is a plan view of a unit pixel in a second semiconductor chip according to some example embodiments;

[0023] Figure 9A and Figure 9B is a sectional view of an example of a plan view of Figure 8A Figure 8A

[0024] Figures 10A-10F is a sectional view for explaining generation of a capacitor in a first semiconductor chip according to some example embodiments. DETAILED DESCRIPTION

[0025] Hereinafter, one or more embodiments are described with reference to the accompanying drawings.

[0026] Figure 1 is a block diagram of an image sensor according to some example embodiments.

[0027] Referring to​​​​​​Figure 1 The image sensor 1 can include a first semiconductor chip 100, a second semiconductor chip 200, and a third semiconductor chip 300. The first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300 can overlap each other in a plan view. The first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300 can be sequentially stacked in a vertical direction. The first semiconductor chip 100 can be referred to as an upper plate, the second semiconductor chip 200 can be referred to as a middle plate, and the third semiconductor chip 300 can be referred to as a lower plate.

[0028] The first semiconductor chip 100 can include a first pixel array 10. The second semiconductor chip 200 can include a second pixel array 20. The third semiconductor chip 300 can include a logic circuit 30 and an analog-to-digital converter (ADC) 35. The first pixel array 10 can generate a charge in proportion to an amount of light entering the first pixel array 10. Although not shown, light can be concentrated through a microlens disposed on the first pixel array 10. The second pixel array 20 can convert an optical signal into an electrical signal, i.e., an analog signal, according to a control of the logic circuit 30. The second pixel array 20 can output the analog signal to the ADC 35. The ADC 35 can convert the analog signal into a digital signal. The ADC 35 can provide data based on the digital signal.

[0029] Although not shown, the image sensor according to some example embodiments can further include a memory cell array. The memory cell array can store data based on the digital signal.

[0030] The data can be image data generated in units of frames. A number of bits in the data can be determined based on a resolution of the ADC 35. The number of bits in the data can be determined based on a high dynamic range (HDR) supported by the image sensor. In addition, the bits in the data can further include at least one extension bit representing a location where the data is generated, data information, etc.

[0031] The image sensor 1 is described as a 3-stack image sensor including a first pixel array 10 and a second pixel array 20, both of which are formed on different chips. The image sensor 1 can perform a multi-conversion gain operation using a structure including a capacitor in the first pixel array 10 of the first semiconductor chip 100, which will be described below with reference to Figure 4 Detailed Description.

[0032] Figure 2 is a block diagram illustrating Figure 1 the first pixel array 10, the second pixel array 20, the logic circuit 30, and the ADC 35 of

[0033] Referring to Figure 2The first pixel array 10 can be implemented in a first semiconductor chip 100. The second pixel array 20 can be implemented in a second semiconductor chip 200. The logic circuit 30 and the ADC 35 can be implemented in a third semiconductor chip 300.

[0034] The first pixel array 10 can convert incident light and generate an electrical signal. The second pixel array 20 can include unit pixels arranged in a matrix form along a row direction and a column direction. The second pixel array 20 can operate according to a control of the logic circuit 30. In detail, the logic circuit 30 can control a plurality of transistors included in the second pixel array 20. The plurality of transistors in the second pixel array 20 can control the electrical signal from the first pixel array 10 based on a signal received from the logic circuit 30.

[0035] The logic circuit 30 can include a row driver 31 and a timing controller 32, and can be connected to the ADC 35. According to some example embodiments, the logic circuit 30 can generate a readout signal using a global shutter method that simultaneously (e.g., at the same or approximately the same time) detects all unit pixels, a rolling shutter method that adjusts an exposure time during which all unit pixels are simultaneously (e.g., at the same or approximately the same time) detected, a rolling shutter method that controls unit pixels on a row basis, an encoded rolling shutter method, etc.

[0036] The row driver 31 can control the second pixel array 20 in units of rows according to a control of the timing controller 32. The row driver 31 can select at least one of rows of the second pixel array 20 based on a row address. The row driver 31 can decode the row address, and can be connected to a selection transistor SEL, a reset transistor RG, and a source follower transistor SF included in the second pixel array 20. The second pixel array 20 can be driven by a plurality of driving signals such as a pixel selection signal, a reset signal, and a charge transfer signal received from the row driver 31.

[0037] The ADC 35 can be connected to the second pixel array 20 through a column line COL. The ADC 35 can convert an analog signal received from the second pixel array 20 through the column line COL into a digital signal. The number of the ADC 35 can be determined based on the number of unit pixels arranged in a row and the number of column lines COL. There can be at least one ADC 35.

[0038] For example, the ADC 35 can include a reference signal generator REF, a comparator CMP, a counter CNT, and a buffer BUF. The reference signal generator REF can generate a ramp signal having a certain gradient, and provide the ramp signal as a reference signal of the comparator CMP. The comparator CMP can compare the analog signal with the ramp signal from the reference signal generator REF, and output comparison signals each having a transition point according to the effective signal component. The counter CNT can generate a count signal by performing a counting operation, and provide the count signal to the buffer BUF. The buffer BUF can include a latch circuit connected to the column line COL, respectively, and can latch the count signal from the counter CNT to each column in response to a transition of the comparison signal, thereby outputting the latched count signal as data.

[0039] In some embodiments, the ADC 35 can further include a correlated double sampling (CDS) circuit configured to perform CDS by calculating a difference between a reference voltage indicating a reset state of each unit pixel and an output voltage indicating a signal component corresponding to incident light, and further configured to output an analog sampling signal corresponding to the effective signal component. The CDS circuit can be connected with the column line COL.

[0040] The timing controller 32 can control the operation timing of the row driver 31 and the ADC 35. The timing controller 32 can provide timing signals and control signals to the row driver 31 and the ADC 35. In more detail, the timing controller 32 can control the ADC 35, and the ADC 35 can provide data to the logic circuit 30 according to the control of the timing controller 32. Further, the timing controller 32 can further include a circuit that provides a request, a command, or an address to the logic circuit 30 to enable data of the ADC 35 to be stored in the memory cell array.

[0041] Figure 3 is a perspective view of the first pixel array 10, the second pixel array 20, the logic circuit 30, and the ADC 35, which are illustrated in three dimensions. Figure 1

[0042] Referring to Figure 3 In the image sensor 1, the first to third semiconductor chips 100 to 300 can be sequentially stacked. Figure 3 ​The sizes of the first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300 are shown to be the same as each other for convenience, but one or more embodiments are not limited thereto. The sizes of the first semiconductor chip 100, the second semiconductor chip 200, and the third semiconductor chip 300 can vary. As described above, the first pixel array 10 can be disposed on the first semiconductor chip 100, and the second pixel array 20 can be disposed on the second semiconductor chip 200. The logic circuit 30 and the ADC 35 can be disposed on the third semiconductor chip 300.

[0043] In the first semiconductor chip 100 and the second semiconductor chip 200, a plurality of unit pixels can be disposed in a two-dimensional array on a two-dimensional plane. Although not shown, the first pixel array 10 can include a sensor array region and a pad region. The sensor array region can be located at, for example, the center of the first semiconductor chip 100, and the pad region can be located at, for example, the edge of the first semiconductor chip 100, but one or more embodiments are not limited thereto. In the sensor array region, an active pixel configured to generate an active signal by receiving light can be disposed. The second pixel array 20 can be configured to transmit a control signal to the sensor array region of the first pixel array 10. The second pixel array 20 can be configured to transmit an output signal of a unit pixel to the logic circuit 30 of the third semiconductor chip 300. The pad region can be configured so that the image sensor according to some embodiments can exchange electrical signals with an external device.

[0044] The logic circuit 30 can include a circuit configured to process a pixel signal from a unit pixel. The logic circuit 30 can receive an image signal from the ADC 35 and process it.

[0045] When a multi-conversion gain operation is performed in a 3-stack image sensor, the image sensor 1 according to some example embodiments can adjust capacitance in a floating diffusion region through a capacitor in a pixel array. Hereinafter, structural features are described in detail.

[0046] Figure 4 is a circuit diagram showing a unit pixel included in the first pixel array 10 and the second pixel array 20. Figure 1

[0047] Figure 4 is a circuit diagram showing a connection relationship between components included in a unit pixel PXa. The components in the unit pixel PXa can be divided into the first pixel array 10 and the second pixel array 20, and the components in the first pixel array 10 can be disposed on a different chip from the components in the second pixel array 20.

[0048] ​The first pixel array 10 can include a plurality of photoelectric conversion elements PD, a plurality of transfer transistors TG, a floating diffusion node FD, and a capacitor cap. The second pixel array 20 can include a reset transistor RG, a first conversion gain control transistor LRG, a second conversion gain control transistor HRG, a source follower transistor SF, and a selection transistor SEL. According to some example embodiments, the second pixel array 20 can be a pixel circuit configured to convert a light signal from the plurality of photoelectric conversion elements PD into an electrical signal and output the electrical signal.

[0049] The first pixel array 10 can include a plurality of photoelectric conversion elements PD and a plurality of transfer transistors TG. According to some example embodiments, the number of photoelectric conversion elements PD can be the same as the number of transfer transistors TG. The photoelectric conversion elements PD can share a floating diffusion node FD. According to some example embodiments, the first pixel array 10 included in the unit pixel PXa can include eight photoelectric conversion elements PD. According to some example embodiments, the photoelectric conversion elements PD sharing the floating diffusion node FD can be arranged in a 2X4 array. The unit pixel PXa according to some example embodiments can be a pixel including eight photoelectric conversion elements PD arranged in a 2X4 array.

[0050] The photoelectric conversion element PD can generate an electric charge in proportion to an amount of an external incident light. The photoelectric conversion element PD can be coupled to the transfer transistor TG configured to transmit the generated and accumulated electric charge to the floating diffusion node FD. The floating diffusion node FD can be a region in which the electric charge is converted into a voltage, and can store the electric charge cumulatively due to its parasitic capacitance. The electric charge accumulated in the floating diffusion node FD can be converted into a voltage. In this case, a ratio at which the electric charge accumulated in the floating diffusion node FD is converted into a voltage can be referred to as a conversion gain. The conversion gain can vary depending on the capacitance of the floating diffusion node FD. When the capacitance of the floating diffusion node FD increases, the conversion gain decreases, and when the capacitance of the floating diffusion node FD decreases, the conversion gain can increase.

[0051] One end of the transfer transistor TG can be connected to the photoelectric conversion element PD, and the other end thereof can be connected to the floating diffusion node FD. The transfer transistor TG can be formed as a transistor driven according to a specific bias (e.g., a transfer signal TX). That is, the transfer transistor TG can be configured to transmit the electric charge generated by the photoelectric conversion element PD to the floating diffusion node FD according to the transfer signal TX. According to some example embodiments, the transfer transistor TG can have a vertical transfer gate (VTG) structure that can increase a transfer efficiency of photocharge, but one or more embodiments are not limited thereto.

[0052] The source follower transistor SF can amplify a change in potential of the floating diffusion node FD that receives electric charges from the photoelectric conversion element PD, and can output the amplified change to the output line VOUT. When the source follower transistor SF is turned on, a certain potential (e.g., a power supply voltage VDD) provided to the drain of the source follower transistor SF can be transmitted to the drain region of the selection transistor SEL.

[0053] The selection transistor SEL can select a unit pixel to be read on a line-by-line basis. The selection transistor SEL can be a transistor driven by a selection line configured to apply a certain bias (e.g., a row selection signal SX).

[0054] The reset transistor RG can periodically reset the floating diffusion node FD. The reset transistor RG can be a transistor driven by a reset line configured to apply a certain bias (e.g., a reset signal). When the reset transistor RG is turned on according to the reset signal RX, a certain potential (e.g., a power supply voltage VDD) provided to the drain of the reset transistor RG can be transmitted to the floating diffusion node FD.

[0055] The first conversion gain control transistor LRG and the second conversion gain control transistor HRG can be connected in series to the floating diffusion node FD. Depending on whether the first conversion gain control transistor LRG and the second conversion gain control transistor HRG are turned on or off, the capacitance of the floating diffusion node FD can change, and the conversion gain can be variously changed accordingly. According to some example embodiments, multi-conversion gain mode operation by the first conversion gain control transistor LRG and the second conversion gain control transistor HRG is possible. The multi-conversion gain mode operation can refer to an operation of controlling the conversion gain in multiple stages.

[0056] According to some example embodiments, the first pixel array 10 of the unit pixel PXa can include a capacitor cap connected between the first conversion gain control transistor LRG and the second conversion gain control transistor HRG. According to some example embodiments, the first conversion gain control transistor LRG and the second conversion gain control transistor HRG can be arranged in the second pixel array 20, and the capacitor cap can be arranged in the first pixel array 10. That is, the first conversion gain control transistor LRG and the second conversion gain control transistor HRG can be formed on a different semiconductor chip from the capacitor cap.

[0057] According to some example embodiments, the capacitor cap can be a poly-insulator-poly (PIP) capacitor. According to another embodiment, the capacitor cap can be a MIM capacitor. The capacitor cap can be connected between the first conversion gain control transistor LRG and the second conversion gain control transistor HRG, and can provide additional capacitance. According to some example embodiments, the capacitance of the capacitor cap can be in a range from about 10 fF or exactly 10 fF to about 20 fF or exactly 20 fF.

[0058] According to some example embodiments, as the area of the unit pixel is reduced, the photoelectric conversion element PD, the transfer transistor TG, and the capacitor cap can be formed on a first semiconductor chip (100), and the first conversion gain control transistor LRG, the second conversion gain control transistor HRG, the reset transistor RG, the source follower transistor SF, and the selection transistor SEL can be formed on a second semiconductor chip (200). Figure 1 Figure 1

[0059] Figures 5A-5C is a timing chart illustrating the timing of signals applied to adjust the multiple conversion gains in the circuit of Figure 4 .

[0060] Figures 5A-5C is a timing chart of signals respectively applied to the selection transistor SEL, the reset transistor RG, the second conversion gain control transistor HRG, the first conversion gain control transistor LRG, and the transfer transistor TG. When the signal applied to the corresponding transistor is at a high level H, it can indicate that the corresponding transistor is turned on, and when the signal applied to the corresponding transistor is at a low level L, it can indicate that the corresponding transistor is turned off. When the signal applied to the selection transistor SEL is at a high level H, the unit pixel including the selection transistor SEL can be selected, and thus, a pixel signal can be output.

[0061] Figure 5A is a timing chart explaining the timing of signals in a low capacitance mode (i.e., a high conversion gain mode).

[0062] Referring to Figure 5A , when the signal applied to the selection transistor SEL is at a high level H, the first conversion gain control transistor LRG can be at a low level L, and the second conversion gain control transistor HRG and the reset transistor RG can each be at a high level H. In this case, because the first conversion gain control transistor LRG connected to the floating diffusion node FD is turned off, the transistors connected to the floating diffusion node FD can also be turned off, resulting in a low capacitance of the floating diffusion node FD, thereby obtaining a high conversion gain.

[0063] Figure 5B ​​is a timing chart explaining timing of signals in the high-capacitance mode (i.e., the low conversion gain mode).

[0064] Referring to Figure 5B When the signal applied to the selection transistor SEL is at the high level H, the first conversion gain control transistor LRG can be at the high level H, the second conversion gain control transistor HRG can be at the low level L, and the reset transistor RG can be at the high level H. In this case, because the first conversion gain control transistor LRG connected to the floating diffusion node FD is on, and the second conversion gain control transistor HRG is off, the capacitance of the floating diffusion node FD can increase due to the capacitance of the first conversion gain control transistor LRG and the capacitor cap located between the first conversion gain control transistor LRG and the second conversion gain control transistor HRG, resulting in a low conversion gain. Figure 5A

[0065] Figure 5C is a timing chart explaining timing of signals in the high-capacitance mode (i.e., the low conversion gain mode).

[0066] Referring to Figure 5C When the signal applied to the selection transistor SEL is at the high level H, the first conversion gain control transistor LRG and the second conversion gain control transistor HRG can each be at the high level H, and the reset transistor RG can be at the low level L. In this case, because the first conversion gain control transistor LRG and the second conversion gain control transistor HRG connected to the floating diffusion node FD are on, and the reset transistor RG is off, the capacitance of the floating diffusion node FD can increase due to the capacitance of the first conversion gain control transistor LRG, the second conversion gain control transistor HRG, and the capacitor cap located between the first conversion gain control transistor LRG and the second conversion gain control transistor HRG, resulting in a low conversion gain. Figure 5A Figure 5B

[0067] ​​​That is, by adjusting the control signals applied to the first conversion gain control transistor LRG and the second conversion gain control transistor HRG, the conversion gain can be controlled in three stages so that the first conversion gain control transistor LRG and the second conversion gain control transistor HRG can operate in a multi-conversion gain mode. In addition, by using the capacitor cap connected between the first conversion gain control transistor LRG and the second conversion gain control transistor HRG, capacitance can be additionally obtained in both the medium-capacitance mode and the high-capacitance mode. For example, according to some example embodiments, based on the above-described methods, there can be an increase in speed, accuracy, resource efficiency, and / or power efficiency of the device. Thus, the improved device and method overcome the drawbacks of conventional devices and methods, while reducing resource consumption, and / or improving data accuracy and resource allocation (e.g., latency).

[0068] Figure 6A and Figure 6B is a circuit diagram of a unit pixel according to some example embodiments. In describing Figure 6A and Figure 6B circuit diagrams, components already described with reference to Figure 4 will not be described again.

[0069] Referring to Figure 6A , components included in the unit pixel PXb can be divided into a first pixel array 10b and a second pixel array 20b, and components included in the first pixel array 10b can be formed on a different chip from components included in the second pixel array 20b.

[0070] In comparison with the second pixel array 20 of the unit pixel PXa of Figure 4 , the second pixel array 20b of the unit pixel PXb of Figure 6A may not include a reset transistor RG. According to some example embodiments, a floating diffusion node FD can be connected to the first conversion gain control transistor LRG and the second conversion gain control transistor HRG, and a capacitor cap can be connected between the first conversion gain control transistor LRG and the second conversion gain control transistor HRG. Referring to Figure 6A , the second conversion gain control transistor HRG can perform the function of the reset transistor RG, and can obtain capacitance by using the capacitor cap connected between the first conversion gain control transistor LRG and the second conversion gain control transistor HRG, thereby adjusting the capacitance of the floating diffusion node FD.

[0071] Components included in the unit pixel PXc of Figure 6B may be divided into a first pixel array 10c and a second pixel array 20c, and components included in the first pixel array 10c can be formed on a different chip from components included in the second pixel array 20c.

[0072] Referring to Figure 6B , the second pixel array 20c can include a reset transistor RG connected in series to a floating diffusion node FD, a first conversion gain control transistor LRG, and a second conversion gain control transistor HRG. According to some example embodiments, the position at which the reset transistor RG is connected can be different from the position of the unit pixel PXa in the second pixel array 20 of Figure 4 . Referring to Figure 6B , the reset transistor RG can be connected between the first conversion gain control transistor LRG and the floating diffusion node FD. The first conversion gain control transistor LRG can be connected in series to the second conversion gain control transistor HRG, and a capacitor cap can be connected between the first conversion gain control transistor LRG and the second conversion gain control transistor HRG.

[0073] Figure 6A and Figure 6B is a circuit diagram of a unit pixel according to some example embodiments, and shows two conversion gain control transistors and a capacitor connected therebetween, but one or more embodiments are not limited thereto. According to some example embodiments, the second pixel array can include three or more conversion gain control transistors, and in this case, the multi-conversion gain can be controlled in more stages than the three-stage control of the multi-conversion gain shown in Figure 5A and Figure 5B . In addition, when the second pixel array includes three or more conversion gain control transistors, a capacitor cap can be connected between two adjacent conversion gain control transistors among the three or more conversion gain control transistors, and in this case, the capacitor cap can be formed in the first pixel array. According to another embodiment, when the second pixel array includes three or more conversion gain control transistors, two or more capacitors cap can be connected between the three or more conversion gain control transistors. In this case, the two or more capacitors cap can also be formed in the first pixel array.

[0074] Figure 7A is a plan view showing the arrangement of components of the first pixel array on the first semiconductor chip in the circuit diagram of Figure 4 . Figure 7B is a cross-sectional view of the plan view of Figure 7A taken along line A-A' of Figure 7A .

[0075] Figure 7A and Figure 7B are a plan view and a cross-sectional view of the first semiconductor chip 100a, respectively, illustrating the components included in Figure 4the arrangement of components included in the circuit diagram of the unit pixel PXa. Figure 7A is a plan view of the first semiconductor chip 100a for explaining Figure 4 the arrangement of the four photoelectric conversion elements PD, the four transfer transistors TG, the floating diffusion node FD, and the capacitor cap included in the first pixel array 10 of the unit pixel PXa. Although Figure 4 the first pixel array 10 of the unit pixel PXa includes eight photoelectric conversion elements PD and eight transfer transistors TG, for ease of explanation, Figure 7A only four photoelectric conversion elements PD and four transfer transistors TG are shown. That is, Figure 7A the plan view is a plan view showing the arrangement of some components of the first pixel array 10 of the unit pixel PXa.

[0076] Referring to Figure 7A and Figure 7B , the first semiconductor chip 100a of the unit pixel according to some example embodiments can include a semiconductor substrate 110, a photoelectric conversion region 120 formed on the semiconductor chip 110, a floating diffusion region 130, a VTG 140, a deep trench isolation (DTI) structure 150, and a capacitor 160. According to some example embodiments, the first semiconductor chip 100a of the unit pixel can further include a color filter 170 and a microlens 180.

[0077] The semiconductor substrate 110 can have a first surface SUF1 and a second surface SUF2 opposite the first surface SUF1. In some example embodiments, the image sensor including the pixel can be a backside illumination (BSI) image sensor. In some example embodiments, the semiconductor substrate 110 can include a semiconductor layer formed by an epitaxial process. In some example embodiments, the semiconductor substrate 110 can be doped with impurities of a first conductivity type (e.g., p-type).

[0078] The photoelectric conversion region 120 can be formed in the semiconductor substrate 110 and generate electric charges (e.g., photocharges) based on incident light. For example, electron-hole pairs can be generated in response to the incident light, and the photoelectric conversion region 120 can collect such electrons and holes. According to some example embodiments, the photoelectric conversion region 120 can include a photodiode, a pinned photodiode (PPD), a phototransistor, a photogate, or a combination thereof.

[0079] The floating diffusion region 130 can be spaced apart from the photoelectric conversion region 120 in the semiconductor substrate 110. In the floating diffusion region 130, the electric charge generated in the photoelectric conversion region 120 can be transferred and stored by the VTG 140. In some example embodiments, the floating diffusion region 130 can be doped with impurities of a second conductive type (e.g., n-type).

[0080] The VTG 140 or other transistor can be formed on a first surface SUF1 (e.g., front surface) of the semiconductor substrate 110, and the incident light can reach the photoelectric conversion region 120 through a second surface SUF2 (e.g., back surface). The VTG 140 can be configured to form a transfer channel between the photoelectric conversion region 120 and the floating diffusion region 130 in response to a transfer signal, to enable the electric charge generated in the photoelectric conversion region 120 to be transferred to the floating diffusion region 130.

[0081] The first semiconductor chip 100a of the unit pixel can further include a DTI structure 150 formed to surround the photoelectric conversion region 120 to separate each photoelectric conversion region 120 from an adjacent photoelectric conversion region 120. The DTI structure 150 can extend from the first surface SUF1 of the semiconductor substrate 110 to a certain depth, or can be formed by penetrating the semiconductor substrate 110 completely from the first surface SUF1 to the second surface SUF2 thereof. Further, in another embodiment, the DTI structure 150 can be formed by penetrating the semiconductor substrate 110 completely or reaching a certain depth from the second surface SUF2 of the semiconductor substrate 110. For example, the DTI structure 150 can include any insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), and / or hafnium oxide (HfOx).

[0082] According to some example embodiments, the first semiconductor chip 100a of the unit pixel can include a capacitor 160 formed on the DTI structure 150. The capacitor 160 can include a first polysilicon member 161, a second polysilicon member 162, and an insulator member 163. Referring to Figure 7B , the capacitor 160 can be a PIP capacitor. Referring to Figure 7A and Figure 7B The second polysilicon member 162 of the capacitor 160 can be formed on the DTI structure 150, and the insulator member 163 and the first polysilicon member 161 can be stacked on the second polysilicon member 162, thus forming the capacitor 160. As described above, when the capacitor 160 is arranged at the upper portion of the DTI structure 150, additional capacitance can be achieved by utilizing the remaining portion on the upper plate of the stacked image sensor.

[0083] A color filter 170 can be formed on the second surface SUF2 of the semiconductor substrate 110 to correspond to the photoelectric conversion regions 120. The color filter 170 can be included in a color filter array arranged in a matrix form. In some example embodiments, the color filter array can have a Bayer pattern including a red color filter, a green color filter, and a blue color filter. In another embodiment, the color filter array can include a yellow color filter, a magenta color filter, and a cyan color filter. In addition, the color filter array can additionally include a white color filter. According to some example embodiments, an anti-reflection layer, at least one insulating layer, etc. can be formed between the color filter 170 and the second surface SUF2 of the semiconductor substrate 110.

[0084] A microlens 180 can be formed to correspond to the color filter 170 and the photoelectric conversion regions 120. The microlens 180 can adjust a path of incident light to concentrate the incident light entering the microlens 180 into the photoelectric conversion regions 120. In addition, the microlens 180 can be included in a microlens array arranged in a matrix form.

[0085] Figure 8A is a plan view of a unit pixel in a first semiconductor chip according to some example embodiments.

[0086] Figure 8A is a plan view of a first semiconductor chip 100b corresponding to a first pixel array of first unit pixels PXd and second unit pixels PXe. According to some example embodiments, in the first semiconductor chip 100b, components included in the first pixel array of the first unit pixels PXd and the second unit pixels PXe can be arranged. The first unit pixels PXd can have the same or similar structure as the second unit pixels PXe. The first pixel array of the first unit pixels PXd and the second unit pixels PXe can each include eight photoelectric conversion regions, and each of the eight photoelectric conversion regions can be arranged in a 2x4 array. Because the first unit pixels PXd have the same or similar structure as the second unit pixels PXe, the description regarding the first unit pixels PXd can equally apply to the second unit pixels PXe. According to some example embodiments, the components included in the first pixel array of the first unit pixels PXd and the second unit pixels PXe arranged in the first semiconductor chip 100b can correspond to the structures included in the first pixel array 10 of Figure 4 .

[0087] In the first semiconductor chip 100b of the first unit pixel PXd, a photoelectric conversion region (not shown), a floating diffusion region 130b, a VTG 140b, a DTI structure 150b, an upper polysilicon member 161b, and a lower polysilicon member 162b can be arranged. Further, a silicon region 191 can be formed in some portions of the first semiconductor chip 100b. According to some example embodiments, the silicon region 191 can be an active region.

[0088] Because the photoelectric conversion region, the floating diffusion region 130b, the VTG 140b, and the DTI structure 150b arranged in the first semiconductor chip 100b correspond to the photoelectric conversion region 120, the floating diffusion region 130, the VTG 140, and the DTI structure 150 described with reference to Figure 7A and Figure 7B The photoelectric conversion region 120, the floating diffusion region 130, the VTG 140, and the DTI structure 150 described, the repeated description is omitted.

[0089] With reference to Figure 8A , the lower polysilicon member 162b and the upper polysilicon member 161b can be arranged on the DTI structure 150b. Although not shown due to the characteristics of the plan view, an insulator member can be arranged between the lower polysilicon member 162b and the upper polysilicon member 161b. As the lower polysilicon member 162b, the upper polysilicon member 161b, and the insulator member therebetween can be combined, the first capacitor 160_1, the second capacitor 160_2, and the third capacitor 160_3 can be formed in the first semiconductor chip 100b.

[0090] For example, in some example embodiments of Figure 7A and Figure 7B , the areas of the upper polysilicon member 161b and the lower polysilicon member 162b of the first capacitor 160_1, the second capacitor 160_2, and the third capacitor 160_3 can be different from those shown in some example embodiments of Figure 8A According to some example embodiments, the area of the lower polysilicon member 162b can be about the same as or greater than the area of the upper polysilicon member 161b. In Figure 8A , a lower polysilicon member 162b having an area corresponding to that of the area where the upper polysilicon member 161b is located can be formed below the area. This will be described in more detail below with reference to Figure 9A .

[0091] With reference to Figure 8AThe upper polysilicon member 161b and the lower polysilicon member 162b can be combined, and the first capacitor 160_1, the second capacitor 160_2, and the third capacitor 160_3 can be formed. According to some example embodiments, the capacitor connected to correspond to the first unit pixel PXd can be the second capacitor 160_2, and the capacitor connected to correspond to the second unit pixel PXe can be the third capacitor 160_3. The first capacitor 160_1 can be a capacitor connected to correspond to a unit pixel disposed on a side surface of the first unit pixel PXd.

[0092] Referring to Figure 8A , each unit pixel can include one capacitor, and in a plan view, each capacitor can be disposed not only in an upper portion of a corresponding unit pixel but also in an upper portion of an adjacent unit pixel. According to some example embodiments, the second capacitor 160_2 can be a capacitor corresponding to the first unit pixel PXd, but can be disposed to overlap with an upper portion of the second unit pixel PXe.

[0093] Referring to Figure 8A , the first capacitor 160_1, the second capacitor 160_2, and the third capacitor 160_3 can be connected to vertical contacts C0, C1, and C2, respectively. According to some example embodiments, the first capacitor 160_1 can be connected to the vertical contact C0, the second capacitor 160_2 can be connected to the vertical contact C1, and the third capacitor 160_3 can be connected to the vertical contact C2. The vertical contacts C0, C1, and C2 can extend in a Z-axis direction, and can electrically connect the first semiconductor chip 100b to the second semiconductor chip 200b.

[0094] Figure 8B is a plan view of a unit pixel in a second semiconductor chip according to some example embodiments.

[0095] Figure 8B is a plan view of a second semiconductor chip 200b corresponding to a first unit pixel PXd and a second unit pixel PXe. According to some example embodiments, in the second semiconductor chip 200b, components included in a second pixel array of the first unit pixel PXd and the second unit pixel PXe can be disposed. The first unit pixel PXd can have the same or similar structure as the second unit pixel PXe. Because the first unit pixel PXd and the second unit pixel PXe have the same or similar structure, descriptions regarding the first unit pixel PXd can be equally applied to the second unit pixel PXe. According to some example embodiments, components included in the second pixel array of the first unit pixel PXd and the second unit pixel PXe disposed in the second semiconductor chip 200b can correspond to Figure 4 the structure of the second pixel array 20 of FIG. 1.

[0096] In the second semiconductor chip 200b of the first unit pixel PXd, a source follower transistor SF, a selection transistor SEL, a first conversion gain control transistor LRG, a second conversion gain control transistor HRG, and a reset transistor RG can be arranged. Figure 8B The source follower transistor SF, the selection transistor SEL, the first conversion gain control transistor LRG, the second conversion gain control transistor HRG, and the reset transistor RG of the second semiconductor chip 200b can refer to gates of the respective transistors.

[0097] Referring to Figure 8B , the first conversion gain control transistor LRG, the second conversion gain control transistor HRG, and the reset transistor RG can be connected in series, the first conversion gain control transistor LRG and the second conversion gain control transistor HRG can share the active regions 191a and 191c, and the second conversion gain control transistor HRG and the reset transistor RG can share the active regions 191b and 191d. According to some example embodiments, the vertical contacts C1 and C2 can be connected between the first conversion gain control transistor LRG and the second conversion gain control transistor HRG and can correspond to the vertical contacts C1 and C2 of the first semiconductor chip 100b.

[0098] Accordingly, the regions between the first conversion gain control transistor LRG and the second conversion gain control transistor HRG and the second capacitor 160_2 and the third capacitor 160_3 of the first semiconductor chip 100b can be electrically connected through the vertical contacts C1 and C2 formed between the first conversion gain control transistor LRG and the second conversion gain control transistor HRG.

[0099] Figure 9A is a cross-sectional view of a plan view of Figure 8A taken along the line B-B'. According to some example embodiments, Figure 8A the plan view ofshows the first semiconductor chip 100b, but for the sake of clear understanding, Figure 9A and are cross-sectional views of the first semiconductor chip and the second semiconductor chip and the third semiconductor chip stacked on the first semiconductor chip, respectively. Figure 9B

[0100] Figure 9Ais a cross-sectional view of an image sensor 2 in which a first semiconductor chip 101, a second semiconductor chip 201, and a third semiconductor chip 301 are stacked in this order. According to some example embodiments, the first semiconductor chip 101 can be an upper plate, the second semiconductor chip 201 can be a middle plate, and the third semiconductor chip 301 can be a lower plate. In the drawing, it is shown that the first semiconductor chip 101 is formed at the lowermost portion, but this is only for ease of explanation. The upper plate of the stacked image sensor 2 can be the first semiconductor chip 101. That is, the actual stacked image sensor 2 can be formed by stacking the third semiconductor chip 301, the second semiconductor chip 201, and the first semiconductor chip 101 in this order. According to some example embodiments, Figure 9A the first semiconductor chip 101 can correspond to Figure 3 the first semiconductor chip 100, Figure 9A the second semiconductor chip 201 can correspond to Figure 3 the second semiconductor chip 200, and Figure 9A the third semiconductor chip 301 can correspond to Figure 3 the third semiconductor chip 300.

[0101] The first semiconductor chip 101 can include a first semiconductor substrate 110b_1 and a first insulating layer 110b_2 arranged on the first semiconductor substrate 110b_1. The second semiconductor chip 201 can include a second semiconductor substrate 210b_1 and a second insulating layer 210b_2 arranged below the second semiconductor substrate 210b_1. The third semiconductor chip 301 can include a third semiconductor substrate 310b_1 and a third insulating layer 310b_2 arranged below the third semiconductor substrate 310b_1. In this specification, the first semiconductor substrate 110b_1, the second semiconductor substrate 210b_1, and the third semiconductor substrate 310b_1 can each be a substrate including a semiconductor such as silicon. According to some example embodiments, the first semiconductor substrate 110b_1, the second semiconductor substrate 210b_1, and the third semiconductor substrate 310b_1 can each be a silicon single-crystal substrate or a silicon-on-insulator (SOI) substrate. In this specification, the first insulating layer 110b_2, the second insulating layer 210b_2, and the third insulating layer 310b_2 can have, for example, a single-layer structure or a multi-layer structure including at least one of a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, and a porous insulating layer.

[0102] Although in Figure 9AThe color filter and the microlens can be disposed under the first semiconductor substrate 110b_1, although not shown. The first semiconductor substrate 110b_1 can include a photoelectric conversion region 120b corresponding to a photodiode. The first semiconductor substrate 110b_1 can include a DTI structure 150b separable from another pixel region. According to some example embodiments, the DTI structure 150b can be a structure formed such that a DTI region 150b_1 is connected to an STI region 150b_2. The STI region 150b_2 can be a region forming electrical isolation between elements on a surface for the first semiconductor substrate 110b_1 to contact the first insulating layer 110b_2, and the DTI region 150b_1 can be a region penetrating the first semiconductor substrate 110b_1. According to some example embodiments, the DTI region 150b_1 can be a region in contact with a second surface SUF2 of the first semiconductor substrate 110b_1 and separate from a first surface SUF1 thereof.

[0103] The floating diffusion regions 130b_1 and 130b_2 can be formed in the first semiconductor substrate 110b_1, and the VTG 140b can be formed in a recess region penetrating the first semiconductor substrate 110b_1. According to some example embodiments, a floating connection region 130b_3 connecting the floating diffusion regions 130b_1 and 130b_2 corresponding to adjacent photoelectric conversion regions 120b can be formed on the first insulating layer 110b_2. The floating connection region 130b_3 can be a material including polysilicon, and can electrically connect the floating diffusion regions 130b_1 and 130b_2. According to some example embodiments, in the first semiconductor chip 101, the floating connection region 130b_3, the second capacitor 160_2, and the third capacitor 160_3 can be disposed. According to some example embodiments, the floating connection region 130b_3, the first and second polysilicon members 161b_2 and 162b_2 of the second capacitor 160_2, and the first and second polysilicon members 161b_1 and 162b_1 of the third capacitor 160_3 can include the same or similar materials. As described below, the floating connection region 130b_3, the second capacitor 160_2, and the third capacitor 160_3 can be formed simultaneously (e.g., at the same or approximately the same time) by a single process.

[0104] Referring to Figure 9A The second capacitor 160_2 and the third capacitor 160_3 can be disposed on the DTI structure 150b. The second capacitor 160_2 can include a first polysilicon member 161b_2, a second polysilicon member 162b_2, and an insulator member 163b_2, and the third capacitor 160_3 can include a first polysilicon member 161b_1, a second polysilicon member 162b_1, and an insulator member 163b_1. As described above with reference toFigure 8A The second capacitor 160_2 and the third capacitor 160_3 can be disposed on the upper portion of the DTI structure 150b, but in the plan view, a region of the second polysilicon members 162b_1 and 162b_2 can be formed within a range shared by adjacent unit pixels. In other words, a region in which the second polysilicon members 162b_1 and 162b_2 contact the upper portion of the DTI structure 150b is not limited to the cross-sectional area of the DTI structure 150b, and can extend to the surface of the adjacent unit pixel within a range in which the second polysilicon members 162b_1 and 162b_2 do not interfere with the peripheral transistor.

[0105] Referring to Figure 9A The area of the first polysilicon member 161b_2 of the second capacitor 160_2 can be different from the area of the second polysilicon member 162b_2 of the second capacitor 160_2, and the area of the first polysilicon member 161b_1 of the third capacitor 160_3 can be the same as or similar to the area of the second polysilicon member 162b_1 of the third capacitor 160_3. According to some example embodiments, the first and second polysilicon members can be a material including polysilicon, and the insulator member can be a material including SiO2 and / or HfO2. According to some example embodiments, the insulator member can include an oxide, a high-k (HfO2), etc.

[0106] The second capacitor 160_2 and the third capacitor 160_3 can be formed on the first insulating layer 110b_2 formed on the upper portion of the first semiconductor substrate 110b_1, and since a region in which the second capacitor 160_2 and the third capacitor 160_3 are formed is located above the upper portion of the DTI structure 150b, the remaining portion of the first insulating layer 110b_2 can be effectively utilized, and the complexity of the wiring can be reduced.

[0107] The active region 191c shared by the first conversion gain control transistor LRG and the second conversion gain control transistor HRG formed on the second semiconductor chip 201 can be electrically connected to the third capacitor 160_3 through the vertical contact C2 penetrating the second insulating layer 210b_2 of the second semiconductor chip 201.

[0108] The second insulating layer 210b_2 of the second semiconductor chip 201 can include a plurality of metal pads and additional vertical contacts, and the vertically formed vertical contacts at different positions can be connected vertically through the metal pads. According to some example embodiments, the second insulating layer 210b_2 of the second semiconductor chip 201 can include gates of source follower transistors, selection transistors, first conversion gain control transistors, second conversion gain control transistors, and reset transistors, and active regions of the aforementioned transistors can be included in the second semiconductor substrate 210b_1. For ease of illustration, other transistors except for the first conversion gain control transistors and the second conversion gain control transistors are omitted in the drawings.

[0109] The third semiconductor chip 301 can include a third semiconductor substrate 310b_1 and a third insulating layer 310b_2, and the third insulating layer 310b_2 can include a plurality of metal pads and vertical contacts and gates of transistors. According to some example embodiments, Figure 1 The logic circuit 30 and the ADC 35 of the

[0110] Figure 9B is a cross-sectional view taken along the plane of line B-B’ Figure 8A of the plan view.

[0111] In describing Figure 9B some example embodiments of the Figure 9A components described with reference to Figure 9B The first semiconductor chip 102, the second semiconductor chip 202, and the third semiconductor chip 302 are sequentially stacked.

[0112] Referring to Figure 9B , the image sensor 2000 can further include a deep contact C2’ for connecting the active region 191c located on different layers to the third capacitor 160_3. According to some example embodiments, the deep contact C2’ can be a vertical contact vertically extending from the first polysilicon member 161b_1 of the third capacitor 160_3 in the third direction (i.e., the Z-axis direction). The deep contact C2’ can penetrate the first insulating layer 110b_2 and the second insulating layer 210b_2.

[0113] According to Figure 9A and Figure 9BIn some example embodiments, the second capacitor 160_2 and the third capacitor 160_3 can be arranged to obtain capacitances of the floating diffusion regions in the first and second semiconductor chips 101 and 102, and can be formed at an upper portion of the DTI structure 150b. In addition, the second capacitor 160_2 and the third capacitor 160_3 can be electrically connected between the first and second transimpedance control transistors LRG and HRG formed on different layers, through a vertical contact C2 or a deep contact C2’ extending in the Z-axis direction.

[0114] Figures 10A-10F is a cross-sectional view for explaining generation of a capacitor in a first semiconductor chip according to some example embodiments.

[0115] Referring to Figure 10A , the floating diffusion region 130c and the STI region 150c can be formed in the first substrate 110c, and an insulating layer 151c covering the floating diffusion region 130c and the STI region 150c can be formed on a surface of the first substrate 110c. Polysilicon members 160c_1 and 160c_2 can be formed on the insulating layer 151c. According to some example embodiments, gate spacers 160c_3 can be formed on both sides of each of the polysilicon members 160c_1 and 160c_2.

[0116] Referring to Figure 10B , an oxide layer 165c covering the polysilicon members 160c_1 and 160c_2 and the gate spacers 160c_3 can be deposited.

[0117] Referring to Figure 10C , in order to form a floating connection region for connecting the floating diffusion region 130c, photoresists PR_1 and PR_2 can be applied on the polysilicon members 160c_1 and 160c_2 and the gate spacers 160c_3, and then etched accordingly. According to some example embodiments, the etching can be performed by a wet etching process or a dry etching process.

[0118] Referring to Figure 10D , the photoresists PR_1 and PR_2 can be removed, and polysilicon poly can be additionally deposited. Through this process, it can be identified that the deposition is performed in the order of polysilicon-insulator-polysilicon.

[0119] Referring to Figure 10E , photoresists PR_3, PR_4, and PR_5 can be applied to remove unnecessary polysilicon, and then etched accordingly. According to some example embodiments, the etching can be performed by a wet etching process or a dry etching process.

[0120] Reference Figure 10F The photoresists PR_3, PR_4 and PR_5 can be removed, and the contact w and the interlayer insulating layer ILD can be formed. Through the above process, the PIP capacitor cap and the floating connection region SLC for connecting the floating diffusion region 130c can be formed. According to the process stated above, the capacitor cap can be generated next to the floating connection region SLC for connecting the floating diffusion region 130c, resulting in cost efficiency in the process.

[0121] According to a comparative example, it is desirable to connect adjacent unit pixels to obtain the capacitance of the floating diffusion region, and as the connection increases, the image quality can be degraded due to defects. According to some example embodiments disclosed herein, by forming a capacitor on the upper plate in a 2-layer pixel structure, the capacitor on the upper plate can be used to adjust the capacitance of the floating diffusion region for increasing the dynamic range within the unit pixel, thereby enabling to reduce the wiring complexity.

[0122] Any or all of the elements described with reference to the figures can be in communication with any or all of the other elements described with reference to the figures. For example, any element can be in one-way and / or two-way and / or broadcast communication with any or all of the other elements in the figures to transfer and / or exchange and / or receive information such as but not limited to data and / or commands via a bus such as a wireless and / or wired bus (not shown) in a manner such as a serial and / or parallel manner. The information can be in various formats such as analog and / or digital formats.

[0123] When the term "about" or "substantially" is used in this specification in connection with a numerical value, it is intended that the associated numerical value include manufacturing or operational tolerances (e.g., ±10%) around the stated numerical value. Additionally, when the words "generally" and "substantially" are used in connection with a geometric shape, it is intended that precision of the geometric shape is not required, but rather a tolerance in the shape is within the scope of the present disclosure. Furthermore, whether or not a numerical value or shape is modified as "about" or "substantially", it should be understood that these values and shapes should be interpreted to include manufacturing or operational tolerances (e.g., ±10%) around the stated numerical value or shape.

[0124] As described herein, any electronic device and / or portions thereof according to any example embodiment can comprise, can be included in, and / or can be implemented by one or more instances of processing circuitry, such as hardware comprising logic circuitry; a hardware / software combination, such as a processor executing software; or any combination thereof. For example, processing circuitry can more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA), and a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), a neural processing unit (NPU), an electronic control unit (ECU), an image signal processor (ISP), and the like. In some example embodiments, processing circuitry can include a non-transitory computer-readable storage device (e.g., a memory device, such as a DRAM device) storing a program of instructions and a processor (e.g., a CPU) configured to execute the program of instructions to implement the functions and / or methods performed by some or all of any device, system, module, unit, controller, circuit, architecture, and / or portions thereof according to any example embodiment and / or any portions thereof.

[0125] While the present inventive concept has been particularly shown and described with reference to certain example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A stacked image sensor, comprising: The first pixel array includes multiple photoelectric conversion elements sharing a floating diffusion node; and The second pixel array is configured to convert optical signals from the plurality of photoelectric conversion elements into electrical signals and output the electrical signals. The second pixel array includes A first conversion gain control transistor is connected to the floating diffusion node; and The second conversion gain control transistor is connected in series with the first conversion gain control transistor, and The first pixel array further includes a capacitor connected between the first conversion gain control transistor and the second conversion gain control transistor.

2. The stacked image sensor according to claim 1, wherein, The capacitor includes a polycrystalline silicon-insulator-polycrystalline silicon capacitor.

3. The stacked image sensor according to claim 1, wherein, The number of the plurality of photoelectric conversion elements is eight.

4. The stacked image sensor according to claim 1 further includes a reset transistor connected in series with the second conversion gain control transistor.

5. The stacked image sensor of claim 1 further includes a reset transistor connected between the first conversion gain control transistor and the floating diffusion node.

6. The stacked image sensor according to claim 1, wherein, The first pixel array and the second pixel array are located on different semiconductor chips.

7. A stacked image sensor, comprising: A first semiconductor chip includes at least one photoelectric conversion region, at least one floating diffusion region, at least one transfer transistor configured to send charge in the at least one photoelectric conversion region to the at least one floating diffusion region, and a deep trench isolation structure configured to separate each of the at least one photoelectric conversion region. and A second semiconductor chip includes a pixel circuit configured to convert an optical signal from the at least one photoelectric conversion region into an electrical signal and output the electrical signal. The first semiconductor chip includes a capacitor formed on the deep trench isolation structure, and the capacitor is configured to adjust the conversion gain in the at least one floating diffusion region.

8. The stacked image sensor according to claim 7, wherein, The capacitor includes a polycrystalline silicon-insulator-polycrystalline silicon capacitor.

9. The stacked image sensor according to claim 7, wherein, The second semiconductor chip includes a first conversion gain control transistor and a second conversion gain control transistor, which are configured to adjust the capacitance of the at least one floating diffusion region.

10. The stacked image sensor according to claim 9, wherein, The capacitor is electrically connected to an active region shared by the first conversion gain control transistor and the second conversion gain control transistor.

11. The stacked image sensor according to claim 7, wherein, The capacitor includes First polycrystalline silicon component; Second polycrystalline silicon component; and An insulating component is located between the first polysilicon component and the second polysilicon component, and The area of ​​the first polycrystalline silicon component is different from the area of ​​the second polycrystalline silicon component.

12. The stacked image sensor according to claim 11, wherein, The first semiconductor chip includes a floating connection region configured to connect the at least one floating diffusion region, and The floating connection region, the first polysilicon component, and the second polysilicon component are made of the same material.

13. A stacked image sensor, comprising: The first unit pixel includes a first pixel array and a second pixel array. The first pixel array includes multiple photoelectric conversion elements sharing a floating diffusion node, and the second pixel array is configured to convert optical signals from the multiple photoelectric conversion elements into electrical signals and output the electrical signals. and The second unit pixel includes a first pixel array and a second pixel array. The first pixel array of the second unit pixel includes multiple photoelectric conversion elements sharing a floating diffusion node, and the second pixel array of the second unit pixel is configured to convert optical signals from the multiple photoelectric conversion elements into electrical signals and output the electrical signals. The first pixel array of the first unit pixel and the first pixel array of the second unit pixel are located in a first semiconductor chip, and the second pixel array of the first unit pixel and the second pixel array of the second unit pixel are located in a second semiconductor chip. The second pixel array of the first unit pixel and the second pixel array of the second unit pixel each include a first conversion gain control transistor connected to the floating diffusion node and a second conversion gain control transistor connected in series with the first conversion gain control transistor. The first pixel array of the first unit pixel and the first pixel array of the second unit pixel each further include a capacitor, which is configured to adjust the conversion gain of the floating diffusion node, respectively.

14. The stacked image sensor according to claim 13, wherein, The capacitor includes a polycrystalline silicon-insulator-polycrystalline silicon capacitor.

15. The stacked image sensor according to claim 13, wherein, The capacitor is electrically connected to an active region shared by the first conversion gain control transistor and the second conversion gain control transistor.

16. The stacked image sensor according to claim 15, wherein, The active region is electrically connected to the capacitor via deep contacts.

17. The stacked image sensor according to claim 13, wherein, The capacitor includes First polycrystalline silicon component; Second polycrystalline silicon component; and An insulating component, located between the first polysilicon component and the second polysilicon component, and The area of ​​the first polycrystalline silicon component is different from the area of ​​the second polycrystalline silicon component.

18. The stacked image sensor according to claim 17, wherein, The capacitor includes a deep trench isolation structure, the upper part of which includes the second polysilicon component, and the deep trench isolation structure is configured to isolate the plurality of photoelectric conversion elements.

19. The stacked image sensor according to claim 17, wherein, The capacitor includes the second polysilicon component in a region shared by the first unit pixel and the second unit pixel in two dimensions.

20. The stacked image sensor according to claim 13, wherein, The number of the plurality of photoelectric conversion elements is eight.

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