Three-dimensional compact co-packaged switch fabric
By using a three-dimensional compact co-packaged switch structure, employing flip-chip bonding technology and an interposer layer to integrate metal wiring circuits, the problem of excessive distance between the switching chip and the transceiver chip is solved, achieving more efficient signal transmission and a smaller package size.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
- Filing Date
- 2025-10-09
- Publication Date
- 2026-05-12
AI Technical Summary
In existing co-packaged optics, there is a long distance between the switching chip and the transceiver chip, which affects signal transmission, and the switch has a large area.
The switch adopts a three-dimensional compact co-package structure, which uses flip-chip bonding to bond electrical chips and optical chips, and integrates metal wiring circuits in the interposer layer. It uses through silicon vias to achieve vertical stacking and horizontal interconnection, shortening the signal transmission path.
Significantly reduces signal transmission loss and power consumption, enhances anti-interference capabilities, reduces package size, and supports higher-speed signal transmission.
Smart Images
Figure CN121194091B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the fields of optoelectronic integration and optical communication, specifically to a three-dimensional compact co-packaged switch structure. Background Technology
[0002] Optoelectronic integration technology, by incorporating the advantages of low power consumption, high-speed transmission, and high integration of photonic devices, has become a key path to overcome the limitations of Moore's Law in electrical systems. In currently used switching systems, hot-swappable optical modules face significant challenges within their existing form factors, including increasing requirements for electrical and optical connector density and continuously rising power consumption. Co-packaged optics overcomes these limitations through optoelectronic co-design, integrating silicon photonic engines and ASIC switching chips onto the same package substrate. This replaces traditional board-level links with micron-level interconnects, shortening electrical signal transmission distance by more than 90%, reducing impedance mismatch losses, and significantly lowering power consumption. However, current co-packaged optics still have problems. Most research focuses on improving the packaging of optical and electrical chips, but rarely considers the switching chip. In co-packaged optics, a certain distance still exists between the switching chip and the transceiver chip, which affects the transmission of switch signals. Summary of the Invention
[0003] (a) Technical problems to be solved
[0004] In view of the above problems, this disclosure provides a three-dimensional compact co-packaged switch structure to at least partially solve the technical problems existing in current co-packaged optics, such as the long distance between the switching chip and the transceiver chip, and the large area of the switch.
[0005] (II) Technical Solution
[0006] The first aspect of this disclosure provides a three-dimensional compact co-packaged switch structure, including: a switching chip; an optical chip disposed below the switching chip; an electrical chip disposed between the optical chip and the switching chip, and bonded to the optical chip by a flip-chip bonding process; wherein the electrical chip and the optical chip together constitute a transceiver chip; and an intermediary layer disposed below the transceiver chip and connected to the transceiver chip, wherein the intermediary layer integrates metal wiring circuitry.
[0007] According to embodiments of this disclosure, it further includes: a molding compound, which fills the top and sides of the transceiver chip and covers the upper surface of the interposer layer, so that the transceiver chip is embedded in the molding compound.
[0008] According to embodiments of this disclosure, it further includes: a substrate bonded to the lower surface of the switching chip and interconnected with the switching chip by wire bonding.
[0009] According to embodiments of this disclosure, after the metal wiring circuit is rewired in the interposer layer, the signals in the metal wiring circuit are interconnected with the switching chip through microbumps.
[0010] According to embodiments of this disclosure, the transmitting chip in the transceiver chip is one or more of an electroabsorption modulated laser chip, a distributed feedback laser chip, or a Fabry-Perot laser chip.
[0011] According to embodiments of this disclosure, the receiving chip in the transceiver chip is one or more of a PIN photodiode chip, an avalanche photodiode chip, or a monolithic integrated chip.
[0012] According to embodiments of this disclosure, the materials of the interlayer include silicon, organic materials, glass, and composite materials.
[0013] According to embodiments of this disclosure, through-silicon vias are integrated within the interposer, and the through-silicon vias are configured to achieve vertical stacking.
[0014] According to embodiments of this disclosure, the metal wiring circuitry integrated within the interposer layer forms a rewiring layer, which is configured to implement horizontal interconnections.
[0015] According to embodiments of this disclosure, the transceiver chip is provided with an optical structure for edge coupling or grating coupling, the optical structure being configured to realize the input and output of optical signals.
[0016] (III) Beneficial Effects
[0017] This disclosure overcomes the shortcomings of the prior art and provides a three-dimensional compact co-packaged switch structure, which has at least the following technical effects:
[0018] (1) This disclosure significantly reduces signal loss during transmission by integrating optoelectronic transceiver chips and switching chips in three dimensions (3D), while effectively suppressing the attenuation of high-frequency signals. In addition, it avoids the high-frequency loss and electromagnetic crosstalk problems introduced by long traces in traditional designs, and eliminates the reflection noise generated by traditional printed circuit board traces, thereby significantly improving the chip's anti-interference capability.
[0019] (2) This disclosure adopts an integrated design, realizing short-distance driving of the chip, thereby reducing voltage and power consumption. At the same time, the application of low-loss materials further significantly reduces I / O power consumption. In addition, the socket area of the traditional optical engine is eliminated, thereby effectively reducing the package size. Attached Figure Description
[0020] To gain a more complete understanding of this disclosure and its advantages, reference will now be made to the following description taken in conjunction with the accompanying drawings, in which:
[0021] Figure 1 The illustration shows a cross-sectional view of a three-dimensional compact co-packaged switch structure provided in an embodiment of the present disclosure;
[0022] Figure 2 The illustration shows a top view of a three-dimensional compact co-packaged switch structure provided in an embodiment of the present disclosure.
[0023] Explanation of reference numerals in the attached figures:
[0024] 1- Switching chip;
[0025] 2-Substrate;
[0026] 3-Electrical chip;
[0027] 4-Optical chip;
[0028] 5-molding plastic;
[0029] 6-Intermediary layer. Detailed Implementation
[0030] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.
[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.
[0032] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.
[0033] Research has revealed that with the explosive growth of internet traffic, traditional electrical interconnect integration architectures are increasingly showing technical bottlenecks in terms of speed, power consumption, and integration, failing to meet the increasingly stringent performance requirements of 5G applications, the internet, the Internet of Things (IoT), and artificial intelligence (AI). In contrast, optoelectronic integration technology exhibits significant advantages: photons propagate at the speed of light, possessing natural resistance to electromagnetic interference, and different wavelengths of light signals can be transmitted in parallel within the same channel, significantly improving bandwidth capacity and transmission efficiency; the energy consumption of optical interconnects is far lower than that of electrical interconnects, especially in long-distance communication, where energy loss is almost independent of distance, drastically reducing system-level power consumption. In the communications field, high-speed optical modules and photonic integrated circuits provide strong support for high-speed interconnection between 5G base stations and data centers; three-dimensional optoelectronic hybrid integration architectures effectively solve the low-latency, high-bandwidth data exchange requirements between graphics processor / tensor processor clusters; in the IoT and autonomous driving fields, integrated optical sensors and optical communication modules enable efficient environmental perception and vehicle-to-everything (V2X) communication. However, in existing co-packaged optical technologies, a certain distance still exists between the switching chip and the transceiver chip, which can adversely affect the signal transmission of the switch.
[0034] In view of this, embodiments of the present disclosure provide a three-dimensional compact co-packaged switch structure.
[0035] Figure 1 The illustration shows a cross-sectional view of a three-dimensional compact co-packaged switch structure provided in an embodiment of the present disclosure.
[0036] Figure 2 The illustration shows a top view of a three-dimensional compact co-packaged switch structure provided in an embodiment of the present disclosure.
[0037] like Figure 1 and Figure 2 As shown, the switch structure includes: a switching chip 1, a substrate 2, an electrical chip 3, an optical chip 4, a molding compound 5, and an interposer 6.
[0038] Switching chip 1 is located at the top of the system and is used to process data signals.
[0039] The substrate 2 is bonded to the lower surface of the switching chip 1 and interconnected with the switching chip 1 by wire bonding.
[0040] The switching chip 1 can be electrically interconnected with the substrate 2 via gold wire bonding, and can be connected to the lower transceiver chip via through-silicon vias (TSVs).
[0041] For example, the switching chip is electrically interconnected with the packaging substrate 2 using wire bonding. The specific process can be as follows: using gold or aluminum wires, bonding points are formed through metal plastic deformation and atomic solid-phase diffusion under ultrasonic, thermo-press, or thermo-ultrasonic energy. The first bonding point is connected to the chip pad in a ball-on manner, and the second bonding point is connected to the substrate pad in a wedge-on manner. The electrical chip 3 and the optical chip 4 are interconnected and packaged using a flip-chip method. The core of the process lies in the fabrication of the chip-substrate connection structure, which can be achieved by constructing a bump structure on the chip pads: first, a metallization layer under the bumps is deposited on the surface of the aluminum chip pads to enhance adhesion; after the metallization layer deposition is completed, electroplating or printing processes are used to form solder balls or copper pillar bumps at specific locations; subsequently, the chip with the completed bumps is flipped to precisely align the bumps with the corresponding pads on the substrate; finally, a stable and reliable electrical and mechanical connection between the chip and the substrate is achieved through reflow soldering or thermo-press bonding technology.
[0042] During signal transmission, rewiring can be performed in interposer layer 6. Specifically, multiple layers of organic dielectric material can be deposited on interposer layer 6, and the copper metal layer can be patterned to redistribute the signals from the original pads on the chip to the microbump array area. Finally, the signals are vertically interconnected with the switching chip through a structure with a diameter smaller than the microbumps. This structure utilizes solder caps on top of the copper pillars to achieve low-resistance connections, providing support for high-density 3D integration.
[0043] The electrical chip 3 is positioned between the optical chip 4 and the switching chip 1, and is bonded to the optical chip 4 through a flip-chip bonding process. That is, the optical chip 4 and the electrical chip 3 are interconnected and packaged in a flip-chip manner.
[0044] The electrical chip 3 and the optical chip 4 together constitute the transceiver chip. The transceiver chip is equipped with an optical structure for edge coupling or grating coupling. The optical structure is configured to realize the input and output of optical signals, that is, to couple light into the transceiver chip or output optical signals from the transceiver chip.
[0045] Optionally, in the three-dimensional compact co-packaged switch structure, micro-bump vertical integration technology can be used to integrate 16 transceiver chips under the switching chip 1. The transceiver chips can be evenly distributed around the switching chip, specifically located on the four sides of the switching chip, with 4 transceiver chips arranged on each side.
[0046] The transmitting chip in the transceiver chip can be one or more of an electro-absorption modulated laser chip (EML chip), a distributed feedback laser chip (DFB chip), or a Fabry-Perot laser chip (FP chip).
[0047] The receiving chip in a transceiver chip can be one or more of a PIN photodiode chip, an avalanche photodiode chip (APD chip), or a monolithic integrated chip. Among these, a monolithic integrated chip can further reduce the chip area.
[0048] Optical chip 4 is located below the switching chip.
[0049] Molding compound 5 fills the top and sides of the transceiver chip and covers the upper surface of the interposer layer 6, so that the transceiver chip is embedded in the molding compound 5, forming a structural support and physical protection layer.
[0050] For example, molding compound 5 is selected as epoxy molding compound (EMC), which achieves chip encapsulation through a thermosetting cross-linking reaction. Specifically, in the transfer molding process, the epoxy molding compound melt is first preheated, and then injected into the mold cavity under high temperature of 150-180°C and pressure of 10-20 MPa, allowing it to fill the cavity through the gating system and completely encapsulate the chip. After 80% initial solidification, demolding is performed. In the compression molding process, EMC particles can be directly placed into the cavity, heated to 150-180°C to melt them, and then pressure of 5-10 MPa is applied to ensure uniform material filling, ultimately forming a dense protective shell that provides reliable protection for the chip.
[0051] Intermediate layer 6 is located below the transceiver chip and is connected to the transceiver chip. Intermediate layer 6 has integrated metal wiring circuitry, which means that the circuit can be rewired in intermediate layer 6.
[0052] The metal wiring circuitry integrated within the interposer layer 6 forms a redistribution layer (RDL), which is configured to achieve high-density horizontal interconnects.
[0053] After the metal wiring circuit is rewired in the intermediate layer 6, the signals in the metal wiring circuit are interconnected with the switching chip 1 through microbumps.
[0054] Intermediate layer 6 integrates through-silicon vias (TSVs) that are configured to enable efficient vertical stacking.
[0055] The materials of the interposer 6 include silicon, organic materials, glass and composite materials, that is, the interposer 6 includes, but is not limited to, silicon interposers, organic interposers, glass interposers and hybrid interposers.
[0056] For example, the interposer layer 6 utilizes a redistribution layer to achieve high-density horizontal interconnections. This involves fabricating micron-level metal wiring on the interposer layer 6 through processes such as photolithography, copper plating, and etching, thereby redistributing the chip I / O pad positions and optimizing signal transmission paths. Simultaneously, efficient vertical stacking is achieved through through-silicon vias (TSVs). This involves forming conductive channels within the silicon substrate using deep silicon etching, followed by filling with conductive materials such as copper or tungsten, ultimately achieving low-resistance electrical connections between multiple layers of chips.
[0057] Understandably, by integrating the optoelectronic transceiver chip onto the bottom of the switching chip 1, a three-dimensional stacking of the switching chip 1 and the transceiver chip is achieved. This significantly shortens the distance between the switching chip 1 and the transceiver chip, reduces the electrical signal transmission path, decreases signal transmission loss and power consumption, and enhances anti-interference capabilities. Simultaneously, the vertical interconnect structure effectively avoids signal jitter, electromagnetic crosstalk, and timing deviations caused by long traces, suppresses high-frequency signal distortion and attenuation, and supports higher-speed signal transmission. Furthermore, this design reduces the switch's area, achieving a more compact package and higher-density interconnects. Under the integrated architecture, the chip drive voltage decreases due to the shortened transmission distance, and combined with the low-loss dielectric material of the interposer layer 6, I / O power consumption is significantly reduced. This technology provides an effective solution for next-generation high-speed switches and has broad prospects for mass production.
[0058] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.
[0059] Although this disclosure has been shown and described with reference to specific exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made to this disclosure without departing from the spirit and scope of the disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the above embodiments, but should be defined not only by the appended claims, but also by their equivalents.
Claims
1. A three-dimensional co-encapsulated switch, characterized in that, include: Switching chip; An optical chip is disposed below the switching chip; An electrical chip is disposed between the optical chip and the switching chip, and is bonded to the optical chip by a flip-chip bonding process; wherein, the electrical chip and the optical chip together constitute a transceiver chip; An intermediate layer is disposed below the transceiver chip and connected to the transceiver chip. The intermediate layer integrates metal wiring circuitry.
2. The switch according to claim 1, characterized in that, Also includes: A molding compound is filled into the top and sides of the transceiver chip and covers the upper surface of the interposer layer, so that the transceiver chip is embedded in the molding compound.
3. The switch according to claim 1, characterized in that, Also includes: The substrate is bonded to the lower surface of the switching chip and interconnected with the switching chip by wire bonding.
4. The switch according to claim 1, characterized in that, After the metal wiring circuit is rewired in the interposer layer, the signals in the metal wiring circuit are interconnected with the switching chip through microbumps.
5. The switch according to claim 1, characterized in that, The transmitting chip in the transceiver chip is one or more of an electroabsorption modulated laser chip, a distributed feedback laser chip, or a Fabry-Perot laser chip.
6. The switch according to claim 1, characterized in that, The receiving chip in the transceiver chip is one or more of a PIN photodiode chip, an avalanche photodiode chip, or a monolithic integrated chip.
7. The switch according to claim 1, characterized in that, The materials of the interlayer include silicon, organic materials, glass, and composite materials.
8. The switch according to claim 1, characterized in that, The interposer layer has integrated through-silicon vias (TSVs) configured to achieve vertical stacking.
9. The switch according to claim 1, characterized in that, The metal wiring circuitry integrated within the interposer layer forms a redistribution layer, which is configured to enable horizontal interconnections.
10. The switch according to claim 1, characterized in that, The transceiver chip is provided with an optical structure for edge coupling or grating coupling, and the optical structure is configured to realize the input and output of optical signals.