Preparation method of low-leakage III-group nitride selective epitaxial PN junction

Abstract

The invention discloses a preparation method of a low-leakage III-group nitride selective epitaxial PN junction, and belongs to the technical field of semiconductors. The method comprises the following steps of: performing graphical etching on a group III nitride template to form a trapezoidal groove, performing secondary epitaxy on group III nitride containing a p-type layer in the groove, and performing annealing to drive an acceptor to diffuse and push a junction so as to obtain the low-electric-leakage group III nitride selective region epitaxy PN junction. Wherein a trapezoidal groove structure is realized through two rounds of photoetching, so that lateral growth of a p-type material during secondary epitaxy is reduced, preferential growth in the vertical direction is promoted, and the crystal quality and acceptor concentration of a p-type layer are improved. The method has excellent process compatibility, can be widely applied to preparation of various III-group nitride devices (such as super junction structures and junction barrier Schottky diodes) based on the selected area PN junctions, can give full play to the electric field modulation effect of the selected area PN junctions, effectively improves the performance of the devices, and further promotes the development process of III-group nitride medium-high voltage power electronic devices.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a method for preparing a low-leakage group III nitride selective epitaxial PN junction. Background Technology

[0002] Group III nitrides, with their wide bandgap, high critical breakdown field strength, high electron saturation drift velocity, and excellent resistance to high temperature, high pressure, and radiation, have become key semiconductor materials for applications such as next-generation general-purpose power supplies, mobile communications, and semiconductor lighting. For example, in the field of power electronics, GaN-based high electron mobility transistors (HEMTs) have been widely used in fast charging adapters and data center power supplies, significantly improving system efficiency and reducing size.

[0003] However, currently commercially available GaN-based power electronic devices are limited to the low-voltage (<650V) market. To expand into medium- and high-voltage applications, their performance still needs significant improvement. Drawing on the development experience of silicon (Si) and silicon carbide (SiC) power devices, GaN-based devices require more complex structural designs (such as junction field-effect transistors, superjunction structures, and junction barrier Schottky diodes) to overcome the theoretical limits of materials. Among these, the selected PN junction is a key element in realizing these complex structures, crucial for controlling the internal electric field distribution, increasing breakdown voltage, and reducing on-resistance. However, achieving high-quality selected PN junctions on GaN materials still faces significant challenges.

[0004] In Si and SiC devices, selected-area PN junctions are generally achieved through ion implantation. However, Mg ion implantation of GaN suffers from problems such as difficulty in eliminating implantation defects and stringent annealing activation conditions requiring extremely high pressure, hindering the commercial application of this approach. In contrast, another approach—selective epitaxy, which involves selectively etching a nitride drift layer and then epitaxially growing p-type nitride within the etched groove—offers good process compatibility and achieves stable p-type activation rates, making it the preferred solution for obtaining high-performance selected-area PN junctions.

[0005] However, recent studies have revealed two major bottlenecks in selected epitaxial growth schemes: p-GaN grown laterally within the groove suffers from low Mg incorporation efficiency, which is easily compensated for by unintentionally doped O and Si impurities, forming an n-type structure and creating a tunneling barrier; the secondary epitaxial interface, after etching and other processes, has a high defect density that overlaps with the peak electric field region of the PN junction. Under the combined effect of high electric field and high defect state, carriers are highly prone to tunneling, leading to a significant increase in device leakage current and premature breakdown, contradicting the goal of improving breakdown voltage. Therefore, to achieve high-performance selected PN junctions in group III nitride materials and promote the development of high-voltage power devices based on GaN, it is urgent to develop new methods to reduce leakage current in group III nitride selected epitaxial PN junctions. Summary of the Invention

[0006] To achieve high-performance group III nitride selected PN junctions, eliminate leakage current channels at the secondary epitaxial interface, fully utilize the electric field modulation effect of the selected PN junction, and improve the performance of group III nitride devices, this invention provides a method for reducing reverse leakage current in group III nitride selected epitaxial PN junctions.

[0007] This invention is achieved through the following technical solution: A method for preparing a low-leakage group III nitride selective region epitaxial PN junction includes the following steps: (1) Select a group III nitride material template, which includes n + Transport layer and n above it - Drift layer; (2) Pattern the etching of the group III nitride material template, define the p-type region in the device structure as the target p-type region, and etch the n-type region of the target p-type region. - The drift layer forms a trapezoidal groove that is narrower at the top and wider at the bottom; (3) Secondary epitaxy includes single-layer or multilayer materials including p-type III nitrides; (4) Remove secondary epitaxial material outside the target p-type region; (5) Annealing drives the acceptor-to-n axis in p-type III nitrides - Diffusion within the drift layer.

[0008] Finally, the III-nitride device is fabricated using semiconductor processes, including using etching techniques to expose the source / drain / gate of the device and depositing metal electrodes.

[0009] The material type of the group III nitride material template selected in step (1) above can be gallium nitride, aluminum nitride, indium nitride and their ternary alloys or quaternary alloys.

[0010] The group III nitride material template mentioned in step (1) above may include a substrate layer and a stress buffer layer thereon, n + Transport layer and n - The drift layer, wherein the substrate layer can be silicon, sapphire, silicon carbide, or a group III nitride substrate or a bonded substrate. The stress buffer layer can be gallium nitride, aluminum nitride, aluminum gallium nitride, or combinations thereof, used to improve the quality of the nitride crystal and reduce the stress of the epitaxial layer.

[0011] The n of the group III nitride material template mentioned in step (1) above + The transport layer is typically doped at a concentration of 10. 17 ~10 20 cm -3 , used for subsequent electrode contact.

[0012] The functional layer of the group III nitride material template mentioned in step (1) above generally refers to n - Drift layer, doping concentration 10 15 ~10 16 cm -3 It can also be n - A combination of drift layers and group III nitride heterostructures such as AlGaN / GaN.

[0013] The etching in step (2) above can combine dry etching and wet etching. It needs to be etched into a trapezoidal groove structure that is narrow at the top and wide at the bottom to reduce the deposition of sidewall sources and lateral growth in secondary epitaxy, promote preferential growth in the vertical direction, and improve the crystal quality and acceptor concentration of p-type III nitrides.

[0014] The method for preparing the trapezoidal groove in step (2) above can be referred to Figure 2 In the first round of photolithography etching, a groove structure with a tilt angle of 90° is etched by adjusting the etching parameters or combining with wet etching. In the second photolithography etching, the key is in the exposure stage. The angle of the ultraviolet beam is adjusted so that it is incident into the groove once from the right and once from the left at the same tilt angle. This ensures that the photoresist adhering to the inner sidewall of the groove is thicker at the top and thinner at the bottom after development. In the subsequent etching stage, the lower sidewall is etched first, and finally a trapezoidal groove structure that is narrower at the top and wider at the bottom can be formed.

[0015] The tilt angle of the bottom of the groove in step (2) above can be controlled by the incident angle of the ultraviolet beam during the second exposure. The optimal tilt angle can be determined by combining the device simulation software, for example, 30°~70°.

[0016] In step (3) above, the secondary epitaxial material can be a p-type group III nitride; or a stack of unintentionally doped group III nitride and p-type group III nitride to avoid problems such as premature breakdown caused by the overlap of the regrowth interface and the PN junction interface; or a stack of C-doped group III nitride and p-type group III nitride to compensate for the high concentration of donors at the secondary epitaxial interface with the C-doped layer, thereby improving the crystal quality of the p-type nitride; or a stack of C-doped group III nitride, unintentionally doped group III nitride, and p-type group III nitride to achieve a comprehensive optimization effect.

[0017] The epitaxial method in step (3) above can be MOVPE (metal-organic vapor phase epitaxy) or MBE (molecular beam epitaxy). During the epitaxy process, before introducing the organic or metal source, the surface of the material template can be cleaned under a certain temperature and gas atmosphere. The gas can be one or more of the following: ammonia, hydrogen, nitrogen, and etching gases containing chlorine or fluorine, in order to reduce the accumulation of impurities at the secondary epitaxial interface and reduce the surface roughness.

[0018] In the epitaxial process of step (3) above, the full migration of atoms can be promoted by adjusting other parameters such as reducing the growth rate and increasing the temperature, so as to avoid the generation of sidewall edge holes.

[0019] The epitaxy described in step (3) above can be performed with a mask, which can be silicon dioxide, aluminum nitride, silicon nitride, etc.

[0020] In step (4) above, if epitaxy is performed with a mask in step (3), the mask and the secondary epitaxial material attached thereto can be removed simultaneously by etching with acidic or alkaline solutions. Otherwise, the secondary epitaxial material outside the target p-type region needs to be removed by photolithography etching process.

[0021] The diffusion in step (5) above can be achieved by thermal annealing, laser annealing, or irradiation annealing.

[0022] The diffusion in step (5) above can be carried out with a mask to prevent the decomposition or damage of the group III nitride surface during the diffusion process. The mask can be silicon dioxide, aluminum nitride, silicon nitride, etc., and can be obtained by in-situ growth in epitaxial equipment or by physical vapor deposition.

[0023] The method for fabricating a low-leakage group III nitride selective epitaxial PN junction provided by this invention is not only applicable to the fabrication of vertical structure devices, such as junction field-effect transistors, superjunction power devices, and junction barrier Schottky diodes, but also applicable to the fabrication of lateral structure devices, wherein the vertical structure device can be a quasi-vertical or fully vertical structure.

[0024] The beneficial effects of this invention are: This invention provides a method for fabricating a low-leakage group III nitride selected-area epitaxial PN junction, which effectively eliminates leakage channels related to impurity defect states at the secondary epitaxial interface, thereby fully leveraging the selective PN junction's control over electric field and current, and promoting the development of high-voltage power devices in group III nitrides. The trapezoidal groove structure proposed in this invention effectively avoids the problem of low acceptor concentration in laterally grown p-type group III nitrides, promotes preferential growth in the vertical direction, and improves the crystal quality and acceptor concentration of p-type group III nitrides. Spatial decoupling between the active region and interface defects is achieved through a secondary epitaxial C-doped / unintentionally doped / p-type group III nitride stack. This invention proposes a diffusion-pull junction method to shift the electric field peak from the original secondary epitaxial region to the drift layer, further effectively decoupling the active region from interface defects, ultimately significantly reducing tunneling leakage current related to impurity defects at the secondary epitaxial interface, and is expected to achieve high-performance selected-area PN junctions. In addition, this method has excellent process compatibility and can be widely used in the fabrication of various group III nitride devices based on selected PN junctions (such as superjunction structures, junction barrier Schottky diodes, etc.). Attached Figure Description

[0025] Figure 1 This is a flowchart of the method for preparing a low-leakage group III nitride selective epitaxial PN junction according to the present invention.

[0026] Figure 2 This is a flowchart of the method for preparing the trapezoidal groove of the present invention.

[0027] Figure 3 This is a schematic diagram illustrating the steps of a method for fabricating a low-leakage GaN junction barrier Schottky diode according to Embodiment 1 of the present invention.

[0028] Figure 4 In Embodiment 1 of the present invention, TCAD software is used to simulate and analyze the influence of the main diffusion push junction on the electric field distribution in the c direction. "With diffusion" means performing step (e) high-temperature annealing, and "without diffusion" means omitting step (e).

[0029] Figure 5 This is a schematic diagram of the steps in the fabrication method of a low-leakage GaN junction field-effect transistor according to Embodiment 2 of the present invention. Detailed Implementation

[0030] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments, but the implementation of the present invention is not limited thereto.

[0031] Example 1 Please see Figure 3 The fabrication method of the low leakage current GaN junction barrier Schottky diode (JBS) in this embodiment includes the following steps: Step (a): Select a Group III nitride drift layer template. Specifically, use MOCVD to sequentially epitaxially grow a stress buffer layer and an n-nitride drift layer on a 2-inch sapphire substrate. + Transport layer and n - Drift layer, wherein the stress buffer layer is GaN; n + The transport layer is n + -GaN, with a thickness of 1 μm and a Si doping concentration of 5e18 cm⁻¹. -3 ;n - The drift layer is GaN with a thickness of 2 μm and a Si doping concentration of 1e16cm. -3 .

[0032] Step (b) involves photolithographic etching of the drift layer template to form a trapezoidal groove structure that is narrower at the top and wider at the bottom. For details, see [link to relevant documentation]. Figure 2The first photolithography etching process was performed using AZ6130 photoresist. A spin coater was used at 4000 rpm to obtain a photoresist mask with a thickness of approximately 3 μm. The mask was then baked on a hot plate at 90°C for 90 s, followed by exposure using an MJB4 lithography machine with perpendicular UV beam incidence. After development, the mask was baked on a hot plate at 125°C for 120 s, and then etched using ICP with Cl2 / BCl3 / Ar etching gases to remove 0.5 μm of n-type precipitates beforehand. - The drift layer was cleaned of residual photoresist using concentrated H2SO4 and H2O2, and then immersed in a TMAH solution at 85°C for 1 hour to form a vertical groove structure. A second photolithography etching was then performed using AZ6130 photoresist, and a spin coater was used at 4000 rpm to obtain a photoresist mask with a thickness of approximately 3 μm. The mask was then baked on a hot plate at 90°C for 90 s, followed by exposure using an MJB4 lithography machine. The UV beam was incident at 45° angles from both the right and left sides once. After development, a thicker top and thinner bottom photoresist layer was formed on the sidewalls of the grooves. The mask was then baked in an oven at 80°C for 10 minutes to prevent photoresist collapse, followed by ICP etching using Cl2 / BCl3 / Ar etching gases to form a trapezoidal groove structure with a depth of 1.5 μm, a top width of 1 μm, and a bottom width of 3 μm. Finally, the epitaxial wafer was thoroughly cleaned using concentrated H2SO4 and H2O2.

[0033] Step (c), secondary epitaxy of p-GaN and p + -GaN. Specifically, p-GaN layers were grown via MOCVD epitaxy, heated to 930°C in an N2 and NH3 atmosphere, followed by thermal cleaning of the epitaxial wafer for 10 minutes. Then, TMGa and CP2Mg were introduced to grow the p-GaN layer. The TMGa flow rate was 6 sccm to achieve a lower growth rate, which facilitated trench filling and planarization. The p-GaN thickness was 2 μm, and the Mg doping concentration was 3e19 cm⁻¹. -3 ;p + The GaN thickness is 20 nm, and the Mg doping concentration is 1e20 cm⁻¹. -3 .

[0034] Step (d) involves removing the secondary epitaxial p-type GaN outside the target p-type region through photolithography and ICP etching. Specifically, photolithography exposes the window outside the target p-type region, followed by ICP etching using Cl2 / BCl3 / Ar etching gases to remove the n-type region outside the groove. - The secondary epitaxial p-type GaN above the drift layer retains only the secondary epitaxial p-type GaN in the groove region.

[0035] Step (e) promotes the diffusion of Mg acceptor impurities from the recessed p-type GaN to the surrounding drift layer through high-temperature annealing. Specifically, AlN is deposited on the epitaxial wafer using an ALD device as a mask, and the high-temperature annealing equipment is MOCVD. The annealing atmosphere includes ammonia and nitrogen, and the annealing temperature is 1000℃. Finally, annealing is performed at 800℃ for 10 minutes under a nitrogen atmosphere to activate the p-type dopant.

[0036] Step (f) involves fabricating a junction barrier Schottky diode using semiconductor technology. Specifically, the AlN mask is first removed, followed by photolithography to form the mask pattern, and then ICP etching to expose the n-type diode. + -GaN layer. Then, the mask pattern was obtained by overlay etching, and Ti / Al / Ni / Au cathode metal was deposited by electron beam evaporation. After the metal was stripped, it was annealed in a nitrogen atmosphere at 850°C for 35 s in a rapid annealing furnace. Next, the mask pattern was obtained by overlay etching, and Ni / Au anode metal was deposited by electron beam evaporation with thicknesses of 10 nm and 50 nm, respectively. After the metal was stripped, it was annealed in an oxygen atmosphere at 550°C for 300 s in a rapid annealing furnace.

[0037] The above scheme has excellent process compatibility. Among them, the diffusion push-junction step (e) can effectively suppress the electric field spikes caused by impurity aggregation at the secondary epitaxial interface (see...). Figure 3 (Device simulation results) significantly reduce tunneling leakage current. The junction barrier Schottky diode prepared according to this process has the advantages of both low forward conduction resistance and high reverse withstand voltage, and is suitable for power electronics fields such as photovoltaic inverters and smart grids.

[0038] Example 2 Please see Figure 4 The fabrication method of the low-leakage GaN junction field-effect transistor (JFET) in this embodiment includes the following steps: Step (a): Select a Group III nitride drift layer template. Specifically, use the MOCVD method on n + - Epitaxial growth on GaN homogeneous substrate n - Drift layer, n - The drift layer is GaN with a thickness of 10 μm and a Si doping concentration of 1e16 cm⁻¹. -3 .

[0039] Step (b) involves photolithography etching of the drift layer template to form a trapezoidal groove structure that is narrower at the top and wider at the bottom. First, 100 nm AlN is deposited using PECVD as a mask, followed by the first photolithography etching. AZ5214 photoresist is selected, and a spin coater is used at 4000 rpm to obtain a photoresist mask with a thickness of approximately 1.7 μm. The mask is then baked on a hot plate at 90°C for 90 s, followed by exposure using an MJB4 lithography machine with perpendicular UV beam incidence. After development, the mask is baked on a hot plate at 125°C for 120 s. Finally, ICP etching is used to remove the AlN mask and the 0.5 μm thick n-type substrate. - A drift layer was used with an RF power of 15 W and an ICP power of 100 W. The etching gas was Cl2 / BCl3 / Ar, resulting in a nearly vertical groove structure. Residual photoresist was then removed using concentrated H2SO4 and H2O2, retaining the AlN mask. A second photolithography etching was performed using AZ6130 photoresist at 4000 rpm to obtain a photoresist mask with a thickness of approximately 3 μm. The mask was then baked on a hot plate at 90°C for 90 s, followed by exposure using an MJB4 lithography machine. The UV beam was incident at 60° angles from both the right and left sides once. After development, a thicker top and thinner bottom photoresist layer was formed on the groove sidewalls. The mask was then baked in an oven at 80°C for 10 minutes to prevent photoresist collapse. ICP etching was then used to form a trapezoidal groove structure with a depth of 1 μm, a top width of 1 μm, and a bottom width of 2 μm. The epitaxial wafer was then thoroughly cleaned using concentrated H2SO4 and H2O2.

[0040] Step (c), secondary epitaxy of C-doped GaN, p-GaN and p-GaN + -GaN layer. Specifically, MOCVD epitaxy was used, with the temperature raised to 930°C in an H2 and NH3 atmosphere. The epitaxial wafer was thermally cleaned for 5 minutes, and then a TMGa epitaxial growth of a C-doped GaN layer was achieved using a TMGa flow rate of 30 sccm to obtain 5e18 cm⁻¹. -3 The C doping concentration was adjusted, and then the TMGa flow rate was reduced to 6 sccm. CP2Mg was then introduced to epitaxially grow a p-GaN layer with a thickness of 1 μm and a Mg doping concentration of 3e19 cm⁻¹. -3 ;p + The GaN thickness is 20 nm, and the Mg doping concentration is 1e20 cm⁻¹. -3 .

[0041] Step (d) involves removing the mask and any secondary epitaxial material attached to it. Specifically, the epitaxial wafer is cleaned with acetone, ethanol, and water, followed by the removal of the AlN mask and any secondary epitaxial material attached to it using a TMAH solution.

[0042] Step (e) promotes the diffusion of Mg acceptors to the drift region in p-type GaN by pulsed laser annealing. Specifically, a 20 nm AlN mask is first deposited using an atomic layer deposition (ALD) apparatus. Then, it is placed in an annealing apparatus for annealing.

[0043] Step (f) involves fabricating a junction field-effect transistor (JFET) using semiconductor processes. Specifically, the epitaxial wafer is cleaned, and a mask pattern is formed by photolithography. Ni / Au gate metal is deposited by electron beam evaporation, and after metal stripping, it is annealed in a rapid annealing furnace. Then, a mask pattern is obtained by overlay etching, and Ti / Al / Ni / Au source metal is deposited by electron beam evaporation. After metal stripping, it is annealed. Drain metal is deposited on the back side of the substrate. Finally, device isolation is achieved by ion implantation.

[0044] The GaN junction field-effect transistor fabricated in this embodiment benefits from the narrow top and wide bottom groove structure and C-doped insertion layer, which effectively improves the crystal quality and acceptor concentration of the secondary epitaxial p-type GaN. Therefore, when a reverse bias voltage is applied between the gate and the source, the depletion region of the PN junction inside it is fully expanded, thereby adjusting the width of the n-type channel and controlling the current between the source and drain. It is suitable for low-noise applications such as electronic switches and buffer amplifiers.

[0045] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the spirit and principles of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A method for preparing a low-leakage group III nitride selective epitaxial PN junction, comprising the following steps: 1) Select a group III nitride material template, which includes n + Transport layer and n above it - Drift layer; 2) Patterned etching of group III nitride material templates, defining the p-type region in the device structure as the target p-type region, and etching the n-type region of the target p-type region. - The drift layer forms a trapezoidal groove that is narrower at the top and wider at the bottom; 3) Secondary epitaxy includes single-layer or multilayer materials containing p-type group III nitrides; 4) Remove secondary epitaxial material outside the target p-type region; 5) Annealing drives the acceptor-to-n axis in p-type III nitrides. - Diffusion within the drift layer.

2. The preparation method according to claim 1, characterized in that, Step 1) The types of materials selected for the group III nitride material template include gallium nitride, aluminum nitride, indium nitride, and their ternary or quaternary alloys.

3. The preparation method according to claim 1, characterized in that, The group III nitride material template mentioned in step 1) includes a substrate layer and a stress buffer layer thereon, n + Transport layer and n - Drift layer.

4. The preparation method according to claim 1, characterized in that, The n of the group III nitride material template mentioned in step 1) + Transport layer doping concentration 10 17 ~10 20 cm -3 The n - Drift layer doping concentration 10 15 ~10 16 cm -3 .

5. The preparation method according to claim 1, characterized in that, In step 2), two rounds of photolithography etching are used to etch n - The drift layer forms a trapezoidal groove that is narrower at the top and wider at the bottom: In the first round of photolithography etching, a groove structure with an inclination angle of 90° is etched; in the second photolithography etching, the angle of the ultraviolet beam is adjusted during the exposure stage, and the ultraviolet beam is incident into the groove once from the right and left sides at the same inclination angle, respectively, to ensure that the photoresist adhering to the inner sidewall of the groove is thicker at the top and thinner at the bottom after development. In the subsequent etching stage, the lower sidewall is etched first, and finally a trapezoidal groove that is narrower at the top and wider at the bottom is formed.

6. The preparation method according to claim 5, characterized in that, The bottom tilt angle of the trapezoidal groove described in step 2) is controlled by the incident angle of the ultraviolet beam during the second exposure, and the optimal tilt angle is determined by combining the device simulation software.

7. The preparation method according to claim 1, characterized in that, In step 3), the material for secondary epitaxy is a p-type group III nitride, or a stack of unintentionally doped group III nitride and p-type group III nitride, or a stack of C-doped group III nitride and p-type group III nitride, or a stack of C-doped group III nitride, unintentionally doped group III nitride, and p-type group III nitride.

8. The preparation method according to claim 1, characterized in that, Step 3) uses MOVPE and / or MBE as the epitaxial method, promoting full atomic migration by reducing the growth rate and / or increasing the temperature; when step 3) uses epitaxy with a mask, step 4) removes the mask and the secondary epitaxial material attached thereto by etching with an acidic or alkaline solution; when step 3) does not use an epitaxial mask, step 4) removes the secondary epitaxial material outside the target p-type region by photolithography etching process; step 5) uses thermal annealing, laser annealing or irradiation annealing, with or without a mask during the annealing process.

9. A low-leakage group III nitride selective epitaxial PN junction obtained by the preparation method according to any one of claims 1 to 8.

10. A semiconductor device comprising the low-leakage group III nitride selective epitaxial PN junction of claim 9.

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