LED structure and photoelectric detection structure integrated device and preparation method thereof

Abstract

The invention belongs to the technical field of semiconductors, and discloses an LED structure and photoelectric detection structure integrated device and a preparation method thereof. The device comprises a silicon substrate and a bottom silicon electrode layer, wherein a photoelectric detection structure and an LED structure are arranged on the bottom silicon electrode layer; the photoelectric detection structure comprises an intrinsic silicon absorption layer and a top silicon electrode layer; the LED structure comprises an N-type aluminum gallium arsenic lower cladding layer, an active light-emitting region, a P-type aluminum gallium arsenic upper cladding layer and a P-type heavily-doped gallium arsenide electrode layer. The groove is distributed between the photoelectric detection structure and the LED structure, and the bottom silicon electrode layer is exposed at the bottom of the groove; the passivation layer uniformly covers the surfaces of the photoelectric detection structure and the LED structure and the inner wall of each groove; and a first electrode and a second electrode. According to the integrated chip, an LED and a photoelectric detection structure are integrated on the same substrate, the light propagation path is shortened, and the optical coupling loss is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to an LED structure and photoelectric detection structure integrated device and a preparation method thereof. BACKGROUND

[0002] With the rapid development of optoelectronic integrated chip technology and the continuous maturity of heterogeneous integration platform, efficient integration of high-performance light sources and photoelectric detectors on a single silicon substrate has become a key technical challenge to promote on-chip optical interconnection, miniature spectral analysis, biomedical sensing and other frontier applications. The current mainstream optoelectronic integration technology path mainly transfers the light source or detector module based on III-V material prefabrication to the silicon substrate through direct bonding or auxiliary bonding, etc., to build a heterogeneous functional chip.

[0003] The above integration method has realized the integration of light sources and photoelectric detectors to some extent, but still has some problems: it is difficult to stably control the bonding interface quality, defects such as voids, cracks, and interface state density are prone to occur on the bonding interface, affecting the electrical and optical performance of the device; the manufacturing process requires extremely high precision matching of surface roughness, cleanliness, flatness and thermal expansion coefficient, resulting in complex process and low final product yield; the physical positions of the light source and the detector are dispersed, the optical path is long, and the near-field coupling efficiency is low, which is difficult to meet the requirements of system-level optoelectronic closed-loop integration. SUMMARY

[0004] Therefore, embodiments of the present application provide an LED structure and photoelectric detection structure integrated device and a preparation method thereof. The integrated chip integrates LED and photoelectric detection structure on the same substrate, shortens the light propagation path, and reduces the light coupling loss.

[0005] In a first aspect, the present application provides an LED structure and photoelectric detection structure integrated device.

[0006] The present application is realized by the following technical solutions:

[0007] An LED structure and photoelectric detection structure integrated device comprises:

[0008] A silicon substrate, wherein a bottom silicon electrode layer is arranged on the silicon substrate, and the bottom silicon electrode layer is a shared electrode layer of the photoelectric detection structure and the LED structure;

[0009] The photoelectric detection structure and the LED structure are spaced apart and arranged on the bottom silicon electrode layer;

[0010] The photoelectric detection structure comprises, from bottom to top, an intrinsic silicon absorption layer and a top silicon electrode layer, and the top silicon electrode layer and the bottom silicon electrode layer adopt different doping types;

[0011] The LED structure consists of an N-type aluminum gallium arsenide lower cladding layer, an active light-emitting region, a P-type aluminum gallium arsenide upper cladding layer, and a P-type heavily doped gallium arsenide electrode layer, stacked sequentially from bottom to top.

[0012] And multiple grooves distributed between the photodetector structure and the LED structure, the bottom of the grooves exposing the bottom silicon electrode layer;

[0013] And a passivation layer, which uniformly covers the surface of the photodetector structure, the surface of the LED structure and the inner wall of each of the grooves;

[0014] The first electrode is disposed at the bottom of the groove;

[0015] The second electrode is disposed on the top silicon electrode layer of the photodetector structure and on the P-type heavily doped gallium arsenide electrode layer of the LED structure.

[0016] In a preferred embodiment of this application, the bottom silicon electrode layer can be further configured as an N-type heavily doped silicon electrode layer, and the top silicon electrode layer of the LED structure is a P-type heavily doped silicon electrode layer.

[0017] Alternatively, the bottom silicon electrode layer may be a P-type heavily doped silicon electrode layer, and the top silicon electrode layer of the LED structure may be an N-type heavily doped silicon electrode layer.

[0018] In a preferred embodiment of this application, the doping element of the N-type heavily doped silicon electrode layer may be selected from phosphorus or arsenic, and the doping concentration may be set to 10. 18 ~10 20 cm -3 ;

[0019] The doping element of the P-type heavily doped silicon electrode layer is selected from boron or aluminum, and the doping concentration is set to 10. 18 ~10 20 cm -3 .

[0020] In a preferred embodiment of this application, the thickness of the intrinsic silicon absorption layer of the photodetector structure can be further set to 0.3 μm to 3.0 μm.

[0021] In a preferred embodiment of this application, the active light-emitting region of the LED structure can be further configured as GaAs / Al. 0.2 Ga 0.8 As multiple quantum well structure.

[0022] In a preferred embodiment of this application, the total thickness of the N-type aluminum gallium arsenide lower cladding, the active light-emitting region, the P-type aluminum gallium arsenide upper cladding, and the P-type heavily doped gallium arsenide electrode layer of the LED structure is the same as the total thickness of the intrinsic silicon absorption layer and the top silicon electrode layer of the photodetector structure.

[0023] In a preferred embodiment of this application, the thickness of the active light-emitting region and the N-type aluminum gallium arsenide lower cladding of the LED structure is the same as the thickness of the intrinsic silicon absorption layer of the photodetector structure.

[0024] In a preferred embodiment of this application, the total thickness of the P-type aluminum gallium arsenide cladding layer and the P-type heavily doped gallium arsenide electrode layer of the LED structure is the same as the thickness of the top silicon electrode layer of the photodetector structure.

[0025] Secondly, this application provides a method for fabricating an integrated device of an LED structure and a photoelectric detection structure.

[0026] This application is achieved through the following technical solution:

[0027] A method for fabricating an integrated LED structure and photodetector structure device, used to fabricate the integrated LED structure and photodetector structure device described in the first aspect above, comprising:

[0028] Provide a silicon substrate;

[0029] A bottom silicon electrode layer, an intrinsic silicon absorber layer, and a top silicon electrode layer are sequentially and globally epitaxially grown on a silicon substrate, with the bottom and top silicon electrode layers employing different doping types.

[0030] Etch the pre-defined LED area until the bottom silicon electrode layer is exposed;

[0031] An N-type aluminum gallium arsenide lower cladding layer, an active light-emitting region, a P-type aluminum gallium arsenide upper cladding layer, and a P-type heavily doped gallium arsenide electrode layer are epitaxially grown on the exposed bottom silicon electrode layer in the LED region.

[0032] A mesa structure forming a photoelectric detection structure and an LED structure is provided, wherein the mesa structure is isolated by a groove, and the bottom of the groove is connected to the bottom silicon electrode layer.

[0033] A surface passivation layer is uniformly covered on the photoelectric detection structure, the LED structure, and the inner wall of each groove;

[0034] A first electrode is deposited at the bottom of the groove;

[0035] A second electrode is deposited on top of the silicon electrode layer of the photodetector structure and on top of the P-type heavily doped gallium arsenide electrode layer of the LED structure.

[0036] In a preferred embodiment of this application, the total thickness of the N-type aluminum gallium arsenide lower cladding layer, the active light-emitting region, the P-type aluminum gallium arsenide upper cladding layer, and the P-type heavily doped gallium arsenide electrode layer of the LED structure is the same as the total thickness of the intrinsic silicon absorption layer and the top silicon electrode layer of the photodetector structure.

[0037] In summary, compared with the prior art, the beneficial effects of the technical solution provided in this application include at least the following:

[0038] The integrated device proposed in this application includes a silicon substrate; a bottom silicon electrode layer disposed on the silicon substrate, the bottom silicon electrode layer being a shared electrode layer for a photodetector structure and an LED structure; a photodetector structure and an LED structure spaced apart on the bottom silicon electrode layer; the photodetector structure having an intrinsic silicon absorption layer and a top silicon electrode layer stacked sequentially from bottom to top, the top silicon electrode layer and the bottom silicon electrode layer employing different doping types; the LED structure having an N-type aluminum gallium arsenide lower cladding layer, an active light-emitting region, a P-type aluminum gallium arsenide upper cladding layer, and a P-type heavily doped gallium arsenide electrode layer stacked sequentially from bottom to top; a plurality of grooves distributed between the photodetector structure and the LED structure, the bottom of the grooves exposing the bottom silicon electrode layer; a passivation layer uniformly covering the surface of the photodetector structure, the surface of the LED structure, and the inner wall of each groove; a first electrode disposed at the bottom of the grooves; and a second electrode disposed above the top silicon electrode layer of the photodetector structure and above the P-type heavily doped gallium arsenide electrode layer of the LED structure. This integrated device integrates a photodetector structure and an LED structure on the same silicon substrate, achieving tight coupling between the light source and the detector. Compared with the traditional physical separation layout of heterogeneous devices, the integrated device proposed in this application significantly shortens the light propagation path, reduces optical coupling loss, and improves photoelectric conversion efficiency and system response speed. In addition, the coplanar integration of heterogeneous materials in this application achieves a compact layout of high-density, multifunctional optoelectronic devices, improving chip space utilization. This design is conducive to building low-power, small-size optoelectronic integrated systems, meeting the high requirements of system integration and portability for applications such as optical communication, biometrics, and environmental monitoring. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of the integrated LED structure and photoelectric detection structure device provided in one embodiment of this application;

[0040] Figure 2 This is a schematic diagram of the various stages in the fabrication process of an integrated LED structure and photoelectric detection structure device provided in an embodiment of this application;

[0041] Figure 3This is a schematic flowchart illustrating a method for fabricating an integrated LED structure and photodetector structure device according to an embodiment of this application; Explanation of reference numerals:

[0042] 1. Silicon substrate, 2. Bottom silicon electrode layer, 3. Photodetector structure, 4. LED structure, 301. Intrinsic silicon absorber layer, 302. Top silicon electrode layer, 401. N-type aluminum gallium arsenide lower cladding layer, 402. Active light-emitting region, 403. P-type aluminum gallium arsenide upper cladding layer, 404. P-type heavily doped gallium arsenide electrode layer, 5. Groove, 6. Passivation layer, 7. First electrode, 8. Second electrode. Detailed Implementation

[0043] This specific embodiment is merely an explanation of this application and is not intended to limit it. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but such modifications are protected by patent law as long as they fall within the scope of the claims of this application.

[0044] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0045] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this application, unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship.

[0046] In this application, the terms "first," "second," etc., are used to distinguish identical or similar items with essentially the same function. It should be understood that there is no logical or temporal dependency between "first," "second," and "nth," nor are there any restrictions on quantity or execution order.

[0047] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0048] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0049] See Figure 1 The image shown is a first exemplary embodiment of this application providing an integrated device for an LED structure and a photodetector structure, comprising:

[0050] Silicon substrate 1. Specifically, the silicon substrate is selected as single-crystal silicon, preferably intrinsic silicon material with crystal orientation (100), low dislocation density, and surface roughness less than 1 nm. The size of the silicon wafer can be 100 nm, 150 nm, 200 nm or 300 nm, and the thickness can be 525 μm, 675 μm, 725 μm and 775 μm.

[0051] The bottom silicon electrode layer 2 is located on the silicon substrate 1. The bottom silicon electrode layer 2 is the shared electrode layer of the photodetector structure 3 and the LED structure 4.

[0052] The photodetector structure 3 and the LED structure 4 are distributed at intervals on the bottom silicon electrode layer 2; the photodetector structure 3 and the LED structure 4 are arranged in a mesa structure on the bottom silicon electrode layer 2.

[0053] In this structure, the photodetector 3 consists of an intrinsic silicon absorption layer 301 and a top silicon electrode layer 302 stacked sequentially from bottom to top. The top silicon electrode layer 302 and the bottom silicon electrode layer 2 employ different doping types. In practical applications, the intrinsic silicon absorption layer 301 and the top silicon electrode layer 302, together with the shared electrode layer (bottom silicon electrode layer 2), constitute the complete functional layer of the light-emitting structure.

[0054] The LED structure 4 consists of, from bottom to top, an N-type aluminum gallium arsenide (AGaAs) lower cladding layer 401, an active light-emitting region 402, a P-type AGaAs upper cladding layer 403, and a P-type heavily doped gallium arsenide electrode layer 404. In practical applications, the N-type AGaAs lower cladding layer 401, the active light-emitting region 402, the P-type AGaAs upper cladding layer 403, the P-type heavily doped gallium arsenide electrode layer 404, and the shared electrode layer (bottom silicon electrode layer 2) together constitute the complete functional layer of the detection structure.

[0055] Among them, the N-type aluminum gallium arsenide underlayer 401 is an N-type Al 0.4 Ga 0.6 As the cladding layer, the thickness of this layer is typically set to 50nm–200nm. Setting the thickness within this range is a design based on a comprehensive trade-off between optical waveguide mode constraints, carrier constraints, and production costs and efficiency. This design can reduce material growth time and costs while ensuring and guiding the optical field.

[0056] The active light-emitting region 402 uses GaAs / Al 0.2 Ga 0.8In GaAs multi-quantum-well structures, the thickness of this layer is typically set to 100 nm to 500 nm. The active light-emitting region 402, as the core region for light emission in the GaAs LED structure, adjusts the emission wavelength and efficiency through the quantum confinement effect. Setting the thickness within the aforementioned range allows for a good balance between luminescent performance and crystal quality. When the thickness is too low, the device may not produce a significant quantum confinement effect due to insufficient quantum well periods; when the thickness is too high, the device may develop defects due to excessive accumulated strain, affecting crystal quality.

[0057] And multiple grooves 5, wherein the grooves 5 are distributed between the photoelectric detection structure 3 and the LED structure 4, and the bottom of the grooves 5 exposes the bottom silicon electrode layer 2.

[0058] And passivation layer 6, which uniformly covers the surface of photoelectric detection structure 3, the surface of LED structure 4 and the inner wall of each groove 5.

[0059] The first electrode 7 is located at the bottom of the recess. The first electrode 7 serves as the shared bottom electrode for both the photodetector structure and the LED structure. Furthermore, this shared bottom electrode enhances vertical integration, facilitating the construction of compact, regular photoelectric arrays, reducing package size, and supporting miniaturized integrated system applications. The common bottom electrode design naturally supports a common ground structure, allowing the LED driving circuit and detector readout circuit to be designed within a unified potential reference framework. This effectively suppresses circuit coupling noise, is beneficial for high-speed / low-power interface design, and is suitable for systems with high signal synchronization requirements, such as time-resolved fluorescence detection and time-of-flight (ToF) ranging photoelectric integration applications. Thermally, the shared electrode forms a continuous heat conduction path, helping to dissipate LED heat promptly, alleviating localized heat buildup, and improving device lifespan and stability.

[0060] The second electrode 8 is disposed on the top silicon electrode layer 302 of the photodetector structure 3 and on the P-type heavily doped gallium arsenide electrode layer 404 of the LED structure 4.

[0061] The proposed coplanar monolithic integrated architecture of the photodetector and LED structures significantly shortens the light propagation path between them. Through meticulous design of the optical interface structure, it effectively reduces optical coupling loss and improves overall photoelectric conversion efficiency. Furthermore, the coplanar integration of heterogeneous materials significantly enhances device integration and space utilization, achieving efficient coupling between the light source and detector. This structure can be used to construct low-power, compact optoelectronic integrated systems, suitable for modern optical communication, biometrics, environmental monitoring, and micro-spectral analysis, among other fields.

[0062] In one embodiment, the bottom silicon electrode layer of the photodetector structure is an N-type heavily doped silicon electrode layer, and the top silicon electrode layer is a P-type heavily doped silicon electrode layer. When the electrode layer in contact with the silicon substrate is an N-type heavily doped silicon electrode layer, a PIN photodetector with an NIP structure is formed.

[0063] In another embodiment, the bottom silicon electrode layer of the photodetector structure is a heavily p-type doped silicon electrode layer, and the top silicon electrode layer is an heavily n-type doped silicon electrode layer. When the electrode layer in contact with the silicon substrate is a heavily p-type doped silicon electrode layer, a PIN photodetector with a PIN structure is formed.

[0064] While the NIP structure and the PIN structure are physically equivalent, differences in the transport of charge carriers, electric field distribution, and response to light arise due to the differences in hole and electron mobility and the distribution characteristics of photogenerated charge carriers.

[0065] In this process, the doping element of the N-type heavily doped silicon electrode layer is selected from phosphorus (P) or arsenic (As), and the doping concentration is set to 10. 18 ~10 20 cm -3 ;

[0066] The doping element of the P-type heavily doped silicon electrode layer is selected from boron (B) or aluminum (Al), and the doping concentration is set to 10. 18 ~10 20 cm -3 .

[0067] The thickness of the N-type heavily doped silicon electrode layer is set to 50 nm to 500 nm. For example, the thickness of the N-type heavily doped silicon electrode layer can be 50 nm, 100 nm, 150 nm, 200 nm, 300 nm or 500 nm.

[0068] The thickness of the heavily doped p-type silicon electrode layer is set to 50 nm to 500 nm. For example, the thickness of the heavily doped p-type silicon electrode layer can be 50 nm, 100 nm, 150 nm, 200 nm, 300 nm or 500 nm.

[0069] Preferably, the thickness of the intrinsic silicon absorption layer of the photodetector structure is set to 0.3 μm to 3.0 μm.

[0070] Preferably, the active light-emitting region of the LED structure is a GaAs / Al0.2Ga0.8As multi-quantum-well structure.

[0071] In a preferred embodiment, the total thickness of the N-type aluminum gallium arsenide lower cladding layer 401, the active light-emitting region 402, the P-type aluminum gallium arsenide upper cladding layer 403, and the P-type heavily doped gallium arsenide electrode layer 404 of the LED structure 4 is the same as the total thickness of the intrinsic silicon absorber layer 301 and the top silicon electrode layer 302 of the photodetector structure 3. Through coplanar integration of heterogeneous materials, the device integration density and space utilization are significantly improved, achieving efficient coupling of the light source and detector functions on a single chip. This feature supports the construction of low-power, compact optoelectronic integrated systems, meeting the urgent needs for integration and portability in modern optical communication, biometrics, environmental monitoring, and micro-spectral analysis.

[0072] The thickness of the active light-emitting region 402 and the N-type aluminum gallium arsenide underlayer 401 in the LED structure is the same as the thickness of the intrinsic silicon absorption layer 301 in the photodetector structure.

[0073] The total thickness of the P-type aluminum gallium arsenide cladding layer 403 and the P-type heavily doped gallium arsenide electrode layer 404 in the LED structure is the same as the thickness of the top silicon electrode layer 302 in the photodetector structure.

[0074] It should be noted that the N-type aluminum gallium arsenide (AlGaAs) cladding and active light-emitting region of the LED structure have the same thickness as the intrinsic silicon absorber layer of the photodetector structure. This ensures the structural symmetry of the integrated chip in the vertical direction and the matching of its electrical and optical performance, allowing for better physical compatibility between the LED and photodetector structures. The complete alignment of the GaAs light-emitting region and the silicon detector region ensures a highly flat surface (coplanar structure) for the entire integrated device, significantly simplifying subsequent key processes such as photolithography, metal interconnection, and passivation packaging. It avoids the difficulties in pattern alignment, thin-film stress concentration, and process defects caused by stepped structures, improving manufacturing yield and repeatability. For large-scale optoelectronic array systems, the coplanar structure significantly enhances scalability and CMOS compatibility, meeting the requirements of high-density integration and wafer-level packaging.

[0075] The P-type aluminum gallium arsenide cladding and N-type heavily doped gallium arsenide electrode layer of the LED structure are aligned with the top silicon electrode layer of the photodetector structure. This helps to achieve precise electrode contact and uniform current distribution, while ensuring the vertical positioning of electrode layers in different areas within the integrated structure.

[0076] Consistent thickness ensures that the optical axes of GaAs LEDs and silicon PIN detectors are collinear in a coplanar layout, significantly improving the stability and alignment accuracy of the light propagation path; it facilitates the integrated fabrication and efficient coupling of micro-optical structures (such as microlens arrays and waveguide arrays), reduces light transmission loss, and improves the system signal-to-noise ratio and response speed; it also reduces adverse effects such as scattering and shading caused by differences in device height, thereby improving the overall photoelectric conversion efficiency.

[0077] Preferably, the thickness of the active light-emitting region of the LED structure and the N-type aluminum gallium arsenide lower cladding layer is the same as that of the intrinsic silicon absorption layer of the photodetector structure.

[0078] Reference Figure 2 (including 2a to 2h) and Figure 3 As shown, another embodiment of this application provides a method for fabricating an integrated device of an LED structure and a photodetector structure, the method comprising:

[0079] S1: Provide a silicon substrate.

[0080] Specifically, see Figure 2 As shown in Figure a, a single-crystal silicon substrate is selected, preferably an intrinsic silicon material with a crystal orientation of (100), low dislocation density, and surface roughness of less than 1 nm. First, organic residues and metallic impurities on the surface of the single-crystal silicon substrate are removed using a cleaning process conforming to RCA standards.

[0081] Furthermore, the surface chemical stability of the single-crystal silicon substrate and the lattice matching quality of the initial interface of heteroepitaxial growth can be improved by removing the oxide layer after thin-layer thermal oxidation of the single-crystal silicon substrate, thus laying the foundation for subsequent homo-silicon epitaxy and selective III-V group material epitaxy.

[0082] S2: A bottom silicon electrode layer, an intrinsic silicon absorber layer, and a top silicon electrode layer are sequentially grown globally on a silicon substrate, with the bottom and top silicon electrode layers using different doping types.

[0083] For details, see Figure 2 As shown in Figure b, a three-layer vertical structure is formed from bottom to top through homoepitaxial growth over the entire area of ​​the silicon substrate: a bottom silicon electrode layer 2, an intrinsic silicon absorption layer 301, and a top silicon electrode layer 302. The bottom silicon electrode layer is a first-doped silicon layer, serving as the bottom electrode shared by the entire device. An intrinsic silicon layer is formed on the surface of the bottom silicon electrode layer, serving as the absorption region of the photodetector structure to absorb the visible light signal emitted by the LED structure. The top silicon electrode layer is a second-doped silicon layer, which subsequently serves as the contact layer for the top electrode of the photodetector structure. This three-layer vertical structure design takes into account the electrical and optical performance requirements of the photodetector while ensuring the process compatibility of the GaAs LED heteroepitaxial region and the matching of the interlayer thicknesses of the device.

[0084] When the first doped silicon layer is an N-type heavily doped silicon layer, the second doped silicon layer is a P-type heavily doped silicon layer; when the first doped silicon layer is a P-type heavily doped silicon layer, the second doped silicon layer is an N-type heavily doped silicon layer.

[0085] In practice, a three-layer vertical structure can be formed on a silicon substrate by homoepitaxial growth over the entire area using molecular beam epitaxy (MBE) or plasma-enhanced chemical vapor deposition (PECVD) techniques.

[0086] S3: Etch in the preset light source area until the bottom silicon electrode layer is exposed.

[0087] Specifically, see Figure 2 As shown in Figure c, a combination of photolithography and dry etching is used to selectively remove the top silicon electrode layer and intrinsic silicon absorber layer in the area where the GaAs LED is to be integrated, until the bottom silicon electrode layer is exposed. The exposed bottom silicon electrode layer serves as the substrate for the GaAs LED epitaxial region. Simultaneously, the bottom silicon electrode layer also serves as the shared bottom electrode for connecting the silicon PIN detector and the GaAs LED, achieving an integrated point-contact design. Traditional methods require fabricating two separate devices to integrate a GaAs LED and a silicon detector, then bonding them together with metal wires. This approach, through selective etching, integrates the PIN detector and GaAs LED on a single silicon substrate, greatly simplifying the process. Furthermore, the two devices share space in the vertical direction, resulting in a more compact device structure.

[0088] Dry etching employs inductively coupled plasma etching (ICP) or reactive-ion etching (RIE).

[0089] S4: An N-type aluminum gallium arsenide lower cladding layer, an active light-emitting region, a P-type aluminum gallium arsenide upper cladding layer, and a P-type heavily doped gallium arsenide electrode layer are epitaxially grown on the exposed bottom silicon electrode layer in the LED region.

[0090] See Figure 2 As shown in Figure d, in the reserved LED region, an N-type aluminum gallium arsenide (AGaAs) lower cladding layer 401, an active light-emitting region 402, a P-type AGaAs upper cladding layer 403, and a P-type heavily doped gallium arsenide electrode layer 404 are epitaxially formed layer by layer using metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). The N-type AGaAs lower cladding layer 401 is an N-type Al… 0.4 Ga 0.6 The As cladding layer, with the active light-emitting region 402 made of GaAs / Al, is used. 0.2 Ga 0.8 As a multi-quantum-well structure, the p-type aluminum gallium arsenide cladding 403 adopts a p-type Al... 0.4 Ga 0.6 The As cladding layer and the P-type heavily doped gallium arsenide electrode layer 404 adopt an N-type heavily doped GaAs electrode layer.

[0091] Specifically, N-type Al 0.4 Ga 0.6 As is used as the lower cladding layer to achieve electron injection and photon guidance, GaAs / Al 0.2 Ga0.8 As a multi-quantum-well structure is used as the active light-emitting region to enhance radiative recombination efficiency, P-type Al 0.4 Ga 0.6 As the top cladding layer can optimize hole injection efficiency and suppress carrier overflow, while the heavily doped N-type GaAs electrode layer enables low-resistance ohmic contacts. The N-type Al formed in the LED region... 0.4 Ga 0.6 As undercoat, GaAs / Al 0.2 Ga 0.8 As multi-quantum-well structure (active light-emitting region), P-type Al 0.4 Ga 0.6 The total thickness of the As cladding and the N-type heavily doped GaAs electrode layer is equal to the total thickness of the intrinsic silicon absorber layer and the top silicon electrode layer of the photodetector structure, ensuring that the requirements for subsequent mesa structure alignment, coplanar layout and process flatness are met.

[0092] S5: A mesa structure forming a photoelectric detection structure and an LED structure, the mesa structure being isolated by a groove, the bottom of which is connected to the bottom silicon electrode layer.

[0093] First, using photoresist and other masking materials, the patterns of the LED structure and photodetector structure areas to be retained are defined on the chip surface. For areas not protected by the mask, dry etching technology is used to remove a portion of the material vertically downwards. Taking the photodetector structure as a reference, the top silicon electrode layer and intrinsic silicon absorber layer are etched away, exposing the bottom silicon electrode layer below. After etching, the masked areas are retained, forming a raised mesa structure. The LED structure and photodetector structure are physically isolated by grooves 5. (See [reference]). Figure 2 As shown in e.

[0094] A well-defined mesa structure can prevent subsequent metal short circuits and improve the sidewalls' ability to suppress optical reflections and electron dark currents. Precise control of the mesa structure plays a crucial role in the consistency of the device's electro-optic performance.

[0095] It should be noted that, when forming the mesa structure, considering the dimensional control deviations during micro-nano fabrication processes such as photolithography and etching, and to provide tolerance for alignment deviations in the device pattern, avoiding unnecessary physical or electrical connections between the GaAs LED structure and the silicon PIN optoelectronic structure due to overlay errors, and ensuring precise isolation between the two device structures, a very small portion of the silicon PIN optoelectronic structure can be reserved around the GaAs LED structure. This reserved silicon PIN optoelectronic structure can also alleviate the interface stress generated during heterogeneous integration, reduce the diffusion of crystal defects (such as dislocations) caused by stress concentration into the active region, and ensure the crystal quality of the core area of ​​the device. Furthermore, subsequent high-resistivity treatment of the reserved area (such as ion implantation to form an isolation wall) can further enhance the lateral electrical isolation between the GaAs region and the silicon PIN region, reduce leakage current, and improve the operational stability of the device.

[0096] S6: A surface passivation layer is uniformly covered on the photoelectric detection structure, the LED structure, and the inner wall of each groove.

[0097] A high-quality passivation dielectric film was deposited over the entire surface of the prepared mesa structure using atomic layer deposition (ALD) or chemical vapor deposition (CVD) techniques as passivation layer 6. (See [reference]) Figure 2 As shown in f, this thin film covers all exposed surfaces, including the bottom silicon electrode layer, the N-type heavily doped GaAs electrode layer, and the inner walls of each isolation groove. It effectively passivates defect states on the mesa sidewalls and surfaces, suppressing leakage current and non-radiative recombination processes caused by interface states, thereby significantly improving device reliability and lifespan. Furthermore, this passivation layer also provides electrical isolation and physical protection, offering a pattern window for subsequent electrode patterning.

[0098] S7: The first electrode is deposited at the bottom of the groove.

[0099] See Figure 2 As shown in g, a metal layer (such as Ti / Al or Ni / Au composite metal) is deposited at the bottom of the groove by sputtering or evaporation, and a stable low-resistance ohmic contact is formed by annealing, serving as the first electrode 7. This metal layer serves as the bottom electrode for both the photodetector structure and the LED structure, avoiding the need for separate electrodes for each device, significantly reducing the number of metal layers and wiring density. The shared electrode structure simplifies process steps such as metal evaporation and pattern etching, shortening the process flow and improving process yield, making it particularly suitable for mass integration and wafer-level manufacturing. Furthermore, the shared bottom electrode allows the photodetector structure and LED structure to be naturally aligned with the bottom electrode layer during processing, avoiding misalignment or obstruction. In a coplanar integration architecture, bottom alignment also facilitates the construction of vertically coupled structures (such as a through-emission-through-detection structure), improving system coupling efficiency.

[0100] S8: A second electrode is deposited on top of the silicon electrode layer in the photodetector region and on top of the N-type heavily doped gallium arsenide electrode layer in the LED structure.

[0101] See Figure 2 As shown in Figure h, metal electrodes are deposited on the top silicon electrode layer of the photodetector region and the N-type heavily doped gallium arsenide electrode layer of the LED structure using photolithography and metal sputtering processes, respectively, serving as the second electrode 8 to ensure that the photodetector structure and the LED structure can be driven and read out independently. The second electrode 8 is the top electrode.

[0102] Preferably, the total thickness of the N-type aluminum gallium arsenide lower cladding, the active light-emitting region, the P-type aluminum gallium arsenide upper cladding, and the P-type heavily doped gallium arsenide electrode layer of the LED structure is the same as the total thickness of the intrinsic silicon absorption layer and the top silicon electrode layer of the photodetector structure.

[0103] In practical implementation, to enhance the efficiency of light flux utilization, transparent conductive electrodes (such as ITO) or windowed structures can be designed in the light incident region to improve the absorption efficiency of the photodetector structure for the LED structure. Ultimately, this allows the light signal emitted by the integrated light source to be directly captured by the adjacent detector, achieving a closed-loop on-chip transmit-receive function.

[0104] This application utilizes selective epitaxy (SEEP) technology to achieve directional growth of GaAs LED structures in the open area of ​​a silicon substrate. This effectively alleviates the high defect density problem caused by lattice mismatch and differences in thermal expansion coefficients between traditional III-V semiconductors and silicon substrates, significantly optimizes the crystal structure of the GaAs light-emitting layer, improves photoelectric conversion efficiency and long-term device stability, and lays a solid material foundation for the integration of high-performance heterogeneous optoelectronic devices. The SEEP process eliminates the wafer bonding step between the III-V semiconductor and the silicon wafer in traditional methods, reducing process difficulty and fabrication costs, while improving the heterogeneous interface quality and device consistency.

[0105] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, structural embodiments are basically similar to method embodiments, so they are described more simply; relevant parts can be referred to the descriptions in the method embodiments. Those skilled in the art can understand and implement these embodiments without any creative effort.

[0106] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A device integrating an LED structure and a photoelectric detection structure, characterized in that, include: silicon substrate; A bottom silicon electrode layer is disposed on a silicon substrate, and the bottom silicon electrode layer is a shared electrode layer for the photoelectric detection structure and the LED structure. The photoelectric detection structure and LED structure are spaced apart at the bottom silicon electrode layer; The photoelectric detection structure consists of an intrinsic silicon absorption layer and a top silicon electrode layer stacked from bottom to top, wherein the top silicon electrode layer and the bottom silicon electrode layer use different doping types. The LED structure consists of an N-type aluminum gallium arsenide lower cladding layer, an active light-emitting region, a P-type aluminum gallium arsenide upper cladding layer, and a P-type heavily doped gallium arsenide electrode layer, stacked sequentially from bottom to top. And multiple grooves distributed between the photodetector structure and the LED structure, the bottom of the grooves exposing the bottom silicon electrode layer; And a passivation layer, which uniformly covers the surface of the photodetector structure, the surface of the LED structure and the inner wall of each of the grooves; The first electrode is disposed at the bottom of the groove; The second electrode is disposed on the top silicon electrode layer of the photodetector structure and on the P-type heavily doped gallium arsenide electrode layer of the LED structure.

2. The integrated device of LED structure and photoelectric detection structure according to claim 1, characterized in that, The bottom silicon electrode layer is an N-type heavily doped silicon electrode layer, and the top silicon electrode layer of the LED structure is a P-type heavily doped silicon electrode layer; Alternatively, the bottom silicon electrode layer may be a P-type heavily doped silicon electrode layer, and the top silicon electrode layer of the LED structure may be an N-type heavily doped silicon electrode layer.

3. The integrated LED structure and photoelectric detection structure device according to claim 2, characterized in that, The doping element of the N-type heavily doped silicon electrode layer is selected from phosphorus or arsenic, and the doping concentration is set to 10. 18 ~10 20 cm -3 ; The doping element of the P-type heavily doped silicon electrode layer is selected from boron or aluminum, and the doping concentration is set to 10. 18 ~10 20 cm -3 .

4. The integrated device of LED structure and photoelectric detection structure according to claim 1, characterized in that, The thickness of the intrinsic silicon absorption layer of the photodetector structure is set to be 0.3 μm to 3.0 μm.

5. The integrated device of LED structure and photoelectric detection structure according to claim 1, characterized in that, The active light-emitting region of the LED structure is GaAs / Al. 0.2 Ga 0.8 As multiple quantum well structure.

6. The integrated device of LED structure and photoelectric detection structure according to claim 1, characterized in that, The total thickness of the N-type aluminum gallium arsenide lower cladding, active light-emitting region, P-type aluminum gallium arsenide upper cladding, and P-type heavily doped gallium arsenide electrode layer of the LED structure is the same as the total thickness of the intrinsic silicon absorption layer and the top silicon electrode layer of the photodetector structure.

7. The integrated LED structure and photoelectric detection structure device according to claim 6, characterized in that, The thickness of the active light-emitting region and the N-type aluminum gallium arsenide lower cladding layer of the LED structure is the same as the thickness of the intrinsic silicon absorption layer of the photodetector structure.

8. The integrated device of LED structure and photoelectric detection structure according to claim 6, characterized in that, The total thickness of the P-type aluminum gallium arsenide top cladding and the P-type heavily doped gallium arsenide electrode layer of the LED structure is the same as the thickness of the top silicon electrode layer of the photodetector structure.

9. A method for fabricating an integrated device of an LED structure and a photoelectric detection structure, characterized in that, The preparation method includes: Provide a silicon substrate; A bottom silicon electrode layer, an intrinsic silicon absorber layer, and a top silicon electrode layer are sequentially and globally epitaxially grown on a silicon substrate, with the bottom and top silicon electrode layers employing different doping types. Etch the pre-defined LED area until the bottom silicon electrode layer is exposed; An N-type aluminum gallium arsenide lower cladding layer, an active light-emitting region, a P-type aluminum gallium arsenide upper cladding layer, and a P-type heavily doped gallium arsenide electrode layer are epitaxially grown on the exposed bottom silicon electrode layer in the LED region. A mesa structure forming a photoelectric detection structure and an LED structure is provided, wherein the mesa structure is isolated by a groove, and the bottom of the groove is connected to the bottom silicon electrode layer. A surface passivation layer is uniformly covered on the photoelectric detection structure, the LED structure, and the inner wall of each groove; A first electrode is deposited at the bottom of the groove; A second electrode is deposited on top of the silicon electrode layer of the photodetector structure and on top of the P-type heavily doped gallium arsenide electrode layer of the LED structure.

10. The method for fabricating the integrated LED structure and photoelectric detection structure device according to claim 9, characterized in that, The total thickness of the N-type aluminum gallium arsenide lower cladding, active light-emitting region, P-type aluminum gallium arsenide upper cladding, and P-type heavily doped gallium arsenide electrode layer in the LED structure is the same as the total thickness of the intrinsic silicon absorber layer and the top silicon electrode layer in the photodetector structure.

Images