Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. According to the display panel, the fan-out lines are arranged in the display area, the area of the fan-out area is reduced, the frame is reduced, at least one initialization bus is connected with the initialization signal lines through the fan-out lines, and the initialization signal lines located at the lower R corner can be connected to the initialization buses through the fan-out lines; according to the display panel, the initialized bus does not need to extend into the non-display area to be connected with the initialized bus, and the corresponding initialized bus does not need to be arranged at the lower R corner, so that the frame at the lower R corner is reduced, and the frame of the display panel is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the display technical field, and particularly relates to a display panel and a display device. BACKGROUND

[0002] With the development of display technology, the requirement for narrow frame is higher and higher. Compared with a small-size display device, a medium-size display device has a larger display area, and accordingly, the uniformity requirement for an initialization signal in the display area is higher. Generally, a plurality of groups of initialization connection lines exist, which cross the barrier wall and converge to a bus line at the bottom of the display area, and are connected with an initialization signal line of the display area to realize the input of the initialization signal line. In the process of designing the initialization bus line, in order to ensure that each initialization signal line can be connected to the initialization bus line, a section of the initialization bus line is arranged at the lower R corner of the display device, so that the initialization signal line located above the R corner is connected with the initialization bus line, and the uniformity of the initialization signal is improved. However, this leads to a larger frame at the lower R corner of the display device, which is not conducive to realizing the narrow frame.

[0003] Therefore, the existing display device has the technical problem that the initialization bus line needs to be arranged at the lower R corner, which leads to a larger frame. SUMMARY

[0004] Embodiments of the present application provide a display panel and a display device, which are used to solve the technical problem that the existing display device has a larger frame due to the need to arrange an initialization bus line at the lower R corner.

[0005] In order to achieve the above-mentioned purpose, according to a first aspect of the present application, a display panel is provided, which comprises a display area and a non-display area, the display area is provided with a pixel driving circuit and an initialization signal line connected with the pixel driving circuit, and the display area is further provided with a fan-out line, and the non-display area is provided with a plurality of initialization bus lines. At least one of the initialization bus lines is connected with the initialization signal line through the fan-out line.

[0006] According to a second aspect of the present application, a display device is provided, which comprises the display panel according to any one of the above-mentioned embodiments.

[0007] Embodiments of the present application provide a display panel and a display device; the display panel reduces the area of the fan-out area by arranging the fan-out line in the display area, reduces the frame, and makes at least one initialization bus line connect with the initialization signal line through the fan-out line, so that the initialization signal line located at the lower R corner can be connected to the initialization bus line through the fan-out line, without the need to extend into the non-display area to be connected with the initialization bus line. Accordingly, the initialization bus line can also not be arranged at the lower R corner, thereby reducing the frame at the lower R corner and reducing the frame of the display panel.

[0008] Other features and advantages of the present application will be described in the following detailed description. BRIEF DESCRIPTION OF DRAWINGS In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments description will be briefly introduced. Obviously, the drawings in the following description only represent some of the embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0009] In order to more completely understand the present application and its advantages, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0010] Figure 1 The schematic diagram of a comparative display device provided by the embodiments of the present application.

[0011] Figure 2 The planar schematic diagram of a display panel provided by the embodiments of the present application.

[0012] Figure 3 The enlarged view of the area A of the display panel in Figure 2

[0013] Figure 4 The wiring arrangement diagram of the display area of the display panel provided by the embodiments of the present application.

[0014] Figure 5 The circuit diagram of the pixel driving circuit of the display panel provided by the embodiments of the present application.

[0015] Figure 6 The cross-sectional view of the display panel provided by the embodiments of the present application. DETAILED DESCRIPTION

[0016] The technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments only represent some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort belong to the protection scope of the present application.

[0017] In order to illustrate the principle of the technical problems in the embodiments of the present application, some comparative display devices are provided. It can be understood that these comparative display devices cannot be used as prior art of the present application. For example, Figure 1 ​As shown, the comparison display device includes a display area 101 and a non-display area 102. Multiple sub-pixels 111 are provided in the display area 101, and a GOA unit 114 is provided in the non-display area 102. The pixel circuit in each sub-pixel 111 is connected to the initialization signal line 112, and the pixel circuit in each sub-pixel 111 is connected to the output terminal of the GOA unit. Figure 1 As can be seen, in order to input a signal to the initialization signal trace 112, a bus 113 needs to be set on the lower bezel of the comparison display device. The initialization signal trace 112 is connected through the bus 113 to realize the signal input of the initialization signal trace 112. From Figure 1 As can be seen, in order to improve display uniformity and ensure that each initialization signal trace 112 can be connected to the bus, a bus 113 is set at the lower R-corner of the comparison display device. This connects the initialization signal trace 112 located above the R-corner to the bus 113, improving the uniformity of the initialization signal. However, this results in a larger bezel at the lower R-corner of the display device, which is not conducive to achieving a narrow bezel. Therefore, existing display devices have the technical problem of needing to set an initialization bus at the lower R-corner, resulting in a larger bezel.

[0018] This application provides a display panel and a display device to address the aforementioned technical problems.

[0019] Figure 2 This is a plan view of the display panel provided in an embodiment of this application. Figure 3 for Figure 2 An enlarged view of area A of the display panel. Figure 4 This is a wiring layout diagram of the display area of ​​the display panel provided in an embodiment of this application. Figure 5 A circuit diagram of the pixel driving circuit of the display panel provided in an embodiment of this application.

[0020] like Figure 2 As shown, this application embodiment provides a display panel 2, which includes a display area 201 and a non-display area 202. The non-display area 202 includes a lower border area 202a, a first sub-border area 202b, a second sub-border area 202c, and a top border area 202d. The lower border area 202a may include a fan-out area 2021, a binding area, and a bending area.

[0021] Specifically, such as Figure 2 As shown, the display area 201 is provided with a pixel unit 21, which includes a first sub-pixel unit 211, a second sub-pixel unit 212 and a third sub-pixel unit 213. Each sub-pixel unit is driven by a corresponding pixel driving circuit.

[0022] Specifically, a gate driving circuit 34 can be provided in at least one of the first sub-border area 202b and the second sub-border area 202c. The gate driving circuit outputs control signals to the transistors in the pixel driving circuit to control the operation of the pixel driving circuit.

[0023] like Figures 2 to 5 As shown, this application embodiment provides a display panel 2, which includes a display area 201 and a non-display area 202. The display area 201 is provided with a pixel driving circuit 22 and an initialization signal line 33 connected to the pixel driving circuit 22. The display area 201 is also provided with a fan-out line 32. The non-display area 202 is provided with multiple initialization buses 31. At least one of the initialization buses 31 is connected to the initialization signal line 33 via the fan-out line 32.

[0024] This application provides a display panel; the display panel 2 reduces the area of ​​the fan-out area and the bezel by setting a fan-out line 32 in the display area 201, and allows at least one initialization bus 31 to be connected to the initialization signal line 33 through the fan-out line 32. This allows the initialization signal line 33 located at the lower R-corner to be connected to the initialization bus 31 through the fan-out line 32 without having to extend into the non-display area 202 to connect with the initialization bus 31. The corresponding initialization bus 31 can also be omitted from the lower R-corner, thereby reducing the bezel at the lower R-corner and reducing the bezel of the display panel.

[0025] Specifically, it is understandable that, without considering the influence of factors such as voltage drop, the initialization bus 31, the initialization signal line 33, and the fan-out line 32 connecting the initialization bus and the initialization signal line 33 transmit the same signal, and in essence, they can all use the same name. The reason for naming the traces in different areas here is to explain their design.

[0026] Specifically, it is understood that the embodiments of this application... Figure 3 The design of the first corner area 201a will be used as an example for explanation. For the design of the second corner area 201b, please refer to the design of the first corner area 201a. It will not be described again here.

[0027] Specifically, such as Figure 3 As shown, Figure 3 (a) shows the arrangement of some traces in the display panel, because Figure 3 The traces in (a) are relatively dense. To facilitate viewing the trace design in the display panel, a portion of the traces was cut off, resulting in... Figure 3 (b) in the middle.

[0028] Specifically, in some display devices, fan-out lines are set within the display area, with some fan-out lines connected to data lines, thereby reducing the number of traces in the fan-out area, reducing the space of the fan-out area, and reducing the bezel. Since not every fan-out line is connected to a data line, some fan-out lines become invalid traces. In some display devices, to prevent these invalid traces from being suspended and affecting other traces, these invalid traces are connected to the power line. Based on the above findings, this application embodiment connects some fan-out lines 32 in the display area to the initialization signal line 33 and the initialization bus 31, which can reduce the bezel at the lower R-corner and reduce the bezel of the display panel.

[0029] Specifically, it is understood that when some fan-out lines 32 in the display area are used to connect the initialization signal line 33 and the initialization bus 31 in this embodiment of the application, invalid traces can be used to connect the initialization signal line 33 and the initialization bus 31. The data line can still be connected to the fan-out line without affecting the connection of the data line. Furthermore, using some traces to connect the initialization signal line 33 and the initialization bus 31 reduces the number of fan-out lines connected to the power line. The reduction of some fan-out lines connected to the power line has little or no impact on its signal. Therefore, this embodiment of the application can further reduce the lower R-corner border without affecting other signals and reducing the border of the fan-out area.

[0030] In some embodiments, such as Figures 2 to 5 As shown, the non-display area 202 includes a fan-out area 2021, a first sub-border area 202b, and a second sub-border area 202c. The first sub-border area 202b and the second sub-border area 202c are arranged adjacent to the fan-out area 2021, and are arranged opposite to each other on both sides of the display area 201. The display area 201 includes a first corner area 201a arranged adjacent to the first sub-border area 202b and the fan-out area 2021, and a second corner area 201b arranged adjacent to the second sub-border area 202c and the fan-out area 2021. The initialization bus 31 is connected to the fan-out line 32 located in at least one of the first corner area 201a and the second corner area 201b. By connecting the initialization bus 31 to the fan-out line 32 located in at least one of the first corner area 201a and the second corner area 201b, the width of the lower R-corner on one side of at least one of the first corner area 201a and the second corner area 201b can be reduced, thereby reducing the bezel of the display panel.

[0031] Specifically, such as Figure 3As shown, within the first corner region 201a, the initialization bus 31 is connected to the initialization signal line 33 via a fan-out line 32. This eliminates the need for the initialization bus 31 to extend into the bezel area below the first corner region 201a, reducing the space in the bezel area below the first corner region 201a and thus reducing the bezel size of the display panel. Similarly, within the second corner region 201b, the initialization bus 31 can be connected to the initialization signal line 33 via a fan-out line 32, eliminating the need for the initialization bus 31 to extend into the bezel area below the second corner region 201b, further reducing the space in the bezel area below the second corner region 201b and thus reducing the bezel size of the display panel.

[0032] In some embodiments, the connection point between the initialization bus 31 and the fan-out line 32 is located on one side of the first corner area 201a and / or the second corner area 201b near the middle area of ​​the display area 201.

[0033] Specifically, within the first corner area 201a, the connection point between the initialization bus 31 and the fan-out line 32 can be located on the side of the first corner area 201a near the middle area of ​​the display area 201; or within the second corner area 201b, the connection point between the initialization bus 31 and the fan-out line 32 can be located on the side of the second corner area 201b near the middle area of ​​the display area 201; or within the first corner area 201a, the connection point between the initialization bus 31 and the fan-out line 32 can be located on the side of the first corner area 201a near the middle area of ​​the display area 201, and within the second corner area 201b, the connection point between the initialization bus 31 and the fan-out line 32 can be located on the side of the second corner area 201b near the middle area of ​​the display area 201.

[0034] Specifically, such as Figure 3 As shown, by placing the connection point of the initialization bus 31 and the fan-out line 32 on one side of the first corner area 201a near the middle area of ​​the display area 201, the initialization bus 31 does not need to extend to the bottom of the first corner area 201a, thereby reducing the bezel below the first corner area 201a, reducing the space of the lower R corner, and reducing the bezel of the display panel.

[0035] Specifically, by placing the connection point of the initialization bus 31 and the fan-out line 32 on one side of the second corner area 201b near the middle area of ​​the display area 201, the initialization bus 31 does not need to extend to the bottom of the second corner area 201b, thereby reducing the bezel below the second corner area 201b, reducing the space of the lower R corner, and reducing the bezel of the display panel.

[0036] In some embodiments, such as Figures 3 to 5As shown, the display panel 2 also includes a light-emitting device (LED), which is connected to the pixel driving circuit 22. The initialization signal line 33 includes a first type initialization signal line VI-G and a second type initialization signal line VI-ANO. The initialization bus 31 includes a first type initialization bus 311 and a second type initialization bus 312. The first type initialization bus 311 is connected to the first type initialization signal line VI-G, and the second type initialization bus 312 is connected to the second type initialization signal line VI-ANO. The pixel driving circuit 22 includes a driving transistor T1, a first initialization transistor T4, and a second initialization transistor T7. One electrode of the first initialization transistor T4 is connected to the first type initialization signal line VI-G, and the other electrode of the first initialization transistor T4 is connected to the gate of the driving transistor T1. One electrode of the second initialization transistor T7 is connected to the second type initialization signal line VI-ANO, and the other electrode of the second initialization transistor T7 is connected to the light-emitting device (LED). In this configuration, at least one of the first type of initialization bus 311 and the second type of initialization bus 312 is connected to the fan-out line 32. By connecting at least one of the first type of initialization bus 311 and the second type of initialization bus 312 to the fan-out line 32, the space occupied by the first type of initialization bus 311 and the second type of initialization bus 312 in the lower R-corner can be reduced, thereby reducing the bezel of the display panel.

[0037] Specifically, the first type initialization bus 311 can be connected to the first type initialization signal line VI-G through the fan-out line 32, and the second type initialization bus 312 can be connected to the second type initialization signal line VI-ANO through the fan-out line 32. Alternatively, the first type initialization bus 311 can be connected to the first type initialization signal line VI-G through the fan-out line 32, and the second type initialization bus 312 can be connected to the second type initialization signal line VI-ANO through the fan-out line 32.

[0038] Specifically, such as Figure 3 , Figure 5 As shown in this embodiment, in the circuit diagram of the pixel driving circuit 22, the first type of initialization signal line is labeled VI-G and the second type of initialization signal line is labeled VI-ANO. In the plan view of the display panel, the first type of initialization signal line is labeled 331 and the second type of initialization signal line is labeled 332. It can be understood that this is based on the fact that the first type of initialization signal line and the second type of initialization signal line are labeled differently in different types of drawings, but they actually identify the same structure. Similarly, other structures represented by different labels in different types of drawings can be identified.

[0039] Specifically, in some display devices, a first type initialization signal line VI-G and a second type initialization signal line VI-ANO are respectively connected to a first initialization transistor T4 and a second initialization transistor T7. In this embodiment, the first type initialization bus 311 can be connected to the first type initialization signal line through a fan-out line, and the second type initialization bus 312 can be connected to the second type initialization signal line through a fan-out line, thereby reducing the space occupied by the first type initialization bus 311 and the second type initialization bus 312 in the lower R-corner and reducing the bezel of the display panel.

[0040] In some embodiments, such as Figure 2 , Figure 3 As shown, the display panel 2 includes a first sub-pixel unit 211, a second sub-pixel unit 212, and a third sub-pixel unit 213 with different luminous colors. The second type of initialization signal line 332 includes a first sub-signal line 332a and a second sub-signal line 332b. The second type of initialization bus 312 includes a first sub-bus 312a and a second sub-bus 312b. The first sub-signal line 332a is connected to the first sub-bus 312a, and the second sub-signal line 332b is connected to the second sub-bus 312b. In the first sub-pixel unit 211 and the third sub-pixel unit 213, one electrode of the second initialization transistor T7 is connected to the first sub-signal line 332a; in the second sub-pixel unit 212, one electrode of the second initialization transistor T7 is connected to the second sub-signal line 332b. At least one of the first type of initialization bus 311, the first sub-bus 312a, and the second sub-bus 312b is connected to the fan-out line 32.

[0041] Specifically, the first type initialization bus 311 can be connected to the first type initialization signal line 331 via the fan-out line 32, or the first sub-bus 312a can be connected to the first sub-signal line 332a via the fan-out line 32, or the second sub-bus 312b can be connected to the second sub-signal line 332b via the fan-out line 32; or two of the first type initialization bus 311, the first sub-bus 312a, and the second sub-bus 312b can be connected to the fan-out line 32, or the first type initialization bus 311, the first sub-bus 312a, and the second sub-bus 312b can be respectively connected to the first type initialization signal line 331, the first sub-signal line 332a, and the second sub-signal line 332b via fan-out lines.

[0042] Specifically, in some display panels, different signal lines are used to input different signals for the pixel driving circuits 22 in the first sub-pixel unit 211, the second sub-pixel unit 212, and the third sub-pixel unit 213 with different emission colors. For example, one electrode of the second initialization transistor T7 in the pixel driving circuit 22 of the first sub-pixel unit 211 and the third sub-pixel unit 213 is connected to the first sub-signal line 332a, and one electrode of the second initialization transistor T7 in the pixel driving circuit 22 of the second sub-pixel unit 212 is connected to the second sub-signal line 332b. Accordingly, the first sub-bus 312a and the second sub-bus 312b are set to transmit signals to the first sub-signal line 332a and the second sub-signal line 332b, respectively. This application embodiment reduces the space occupied by at least one of the first type initialization bus 311, the first sub-bus 312a, and the second sub-bus 312b in the lower R-corner by connecting it to the fan-out line 32, thereby reducing the bezel of the display panel.

[0043] In some embodiments, such as Figure 3 As shown, the fan-out line 32 includes a first sub-fan-out line 321, a second sub-fan-out line 322, and a third sub-fan-out line 323. The first sub-fan-out line 321 is connected to the first sub-bus 312a, the second sub-fan-out line 322 is connected to the second sub-bus 312b, and the third sub-fan-out line 323 is connected to the first type initialization bus 311.

[0044] Specifically, such as Figure 3 As shown, by connecting the first sub-bus 312a to the first sub-signal line 332a through the first sub-fan-out line 321, the space occupied by the first sub-bus 312a in the lower R-corner can be reduced, the bezel of the lower R-corner of the display panel can be reduced, and the bezel of the display panel can be reduced.

[0045] Specifically, such as Figure 3 As shown, by connecting the second sub-bus 312b to the second sub-signal line 332b via the second sub-fan-out line 322, the space occupied by the second sub-bus 312b in the lower R-corner can be reduced, thereby reducing the bezel of the lower R-corner of the display panel and the bezel of the display panel.

[0046] Specifically, such as Figure 3 As shown, by connecting the first type initialization bus 311 to the first type initialization bus through the third sub-fan-out line 323, the space occupied by the first type initialization bus 311 in the lower R corner can be reduced, the bezel of the lower R corner of the display panel can be reduced, and the bezel of the display panel can be reduced.

[0047] In some embodiments, such as Figure 4As shown, the display area 201 is also provided with a data line 35 and a power signal line 36 connected to the pixel driving circuit 22. The fan-out lines 32 include a first type fan-out line 32a, a second type fan-out line 32b, and a third type fan-out line 32c. The first type fan-out line 32a is connected to the data line 35, the second type fan-out line 32b is connected to the power signal line 36, and the third type fan-out line 32c is connected to the initialization signal line 33. By setting fan-out lines in the display area 201, connecting the first type fan-out line 32a to the data line 35 reduces the space occupied by the fan-out line connected to the data line 35 in the lower bezel, thus reducing the bezel of the display panel. Connecting the third type fan-out line 32c to the initialization signal line 33 reduces the space occupied by the lower corner of the initialization bus, further reducing the bezel of the display panel. Connecting the second type fan-out line 32b to the power signal line 36 prevents the fan-out lines from being suspended and affecting other signal lines.

[0048] In some embodiments, in the first direction Y, the projections of the second type of fan-out line 32b and the third type of fan-out line 32c on one side of the display panel 2 overlap, and the second type of fan-out line 32b and the third type of fan-out line 32c are insulated from each other.

[0049] Specifically, such as Figure 4 As shown, the second type fan-out line 32b and the third type fan-out line 32c can be two parts of a single fan-out line 32. The part of this fan-out line 32 that is close to the initialization bus serves as the third type fan-out line 32c to connect to the initialization bus 31. The part of this fan-out line 32 that is not connected to the initialization bus 31 and the data line 35 can be connected to the power signal line 36 to serve as the third type fan-out line 32c, thus avoiding the fan-out line 32 from being left floating and affecting other signal lines.

[0050] Specifically, and understandably, this is for ease of viewing. Figure 4 Only one initialization signal line 33 and one power signal line 36 are shown in the figure. In practice, multiple initialization signal lines 33 and power signal lines 36 will be set.

[0051] Specifically, the power signal line 36 can be one or both of a high-potential power line and a low-potential power line.

[0052] Specifically, such as Figure 4 As shown, Figure 4 The illustration shows that the fan-out line 32 is only provided in a portion of the display area, but the embodiments of this application are not limited to this. In order to improve electrical uniformity and display uniformity, the fan-out line 32 can be provided across the entire display area and divided into multiple segments, with each segment connected to different signal lines to avoid it being suspended and affecting other signal lines. For example, in Figure 4In some embodiments, a first-type fan-out line 32a extends only to the position where it connects to the data line. However, in some embodiments, fan-out lines can also be provided on both sides of the horizontal trace of this first-type fan-out line 32a, and a fan-out line can also be provided on the upper side of the vertical trace of this first-type fan-out line 32a. This improves electrical uniformity and display uniformity. Furthermore, the fan-out lines on both sides and the fan-out line on the upper side are connected to other signal lines, preventing the fan-out lines from being suspended and affecting other signal lines. Similarly, fan-out lines can be formed in a crisscross pattern in various areas of the display panel to improve the uniformity of the display area.

[0053] Specifically, it is understandable that when forming crisscrossing fan-out lines in a display panel, a horizontal trace may be divided into multiple segments, one connected to a data line and the other connected to other signal lines (such as power signal lines). In this case, it is necessary to disconnect and insulate the multiple segments of a horizontal trace to avoid signal crosstalk.

[0054] In some embodiments, such as Figure 3 As shown, the fan-out line 32 includes a horizontal portion 3201 and a vertical portion 3202. The horizontal portion 3201 is connected to the vertical portion 3202. The initialization signal line 33 is connected to the horizontal portion 3201 and / or the vertical portion 3202, and the initialization signal line 33 connecting the fan-out line 32 extends to the boundary between the display area 201 and the non-display area 202. By connecting the initialization signal line 33 to the horizontal portion 3201 and / or the vertical portion 3202, the initialization signal line 33 can be connected to the initialization bus 31, and the initialization signal line 33 extends to the boundary between the display area 201 and the non-display area 202, avoiding the initialization signal line 33 extending into the non-display area 202 and occupying space, thereby reducing the lower R-corner bezel and the bezel of the display panel.

[0055] Specifically, when the fan-out line 32 is set in the display area, it will have a vertical portion 3202 set along the first direction Y and a horizontal portion 3201 set along the second direction X. When the initialization signal line 33 is connected to the fan-out line 32, the initialization signal line 33 can be connected in the area where it intersects with the fan-out line 32 without changing the routing and setting position of the initialization signal line 33.

[0056] Specifically, the angle between the first direction Y and the second direction X is greater than 0 and less than or equal to 90 degrees.

[0057] like Figure 5 As shown, the pixel driving circuit 22 includes: a driving transistor T1, a switching transistor T2, a compensation transistor T3, a first initialization transistor T4, a first light-emitting transistor T5, a second light-emitting transistor T6, and a second initialization transistor T7.

[0058] Specifically, such asFigure 5 As shown, the gate of switching transistor T2 is connected to the first scan line Scan1, the first electrode of switching transistor T2 is connected to the data line Data, the second electrode of switching transistor T2 is connected to the first electrode of driving transistor T1 at the first node A, the gate of compensation transistor T3 is connected to the first scan line Scan1, the second electrode of compensation transistor T3 is connected to the second electrode of first initialization transistor T4 at the second node Q, the first electrode of compensation transistor T3 is connected to the second electrode of driving transistor T1 at the third node B, the gate of first initialization transistor T4 is connected to the second scan line Scan2, the first electrode of first initialization transistor T4 is connected to the first type of initialization signal line VI-G, and the first light-emitting crystal... The gate of transistor T5 is connected to the light-emitting control line EM. The first electrode of the first light-emitting transistor T5 is connected to the high-potential power supply line VDD. The second electrode of the first light-emitting transistor T5 is connected to the first electrode of the driving transistor T1. The gate of the second light-emitting transistor T6 is connected to the light-emitting control line EM. The first electrode of the second light-emitting transistor T6 is connected to the second electrode of the driving transistor T1. The second electrode of the second light-emitting transistor T6 is connected to the light-emitting device LED. The gate of the second initialization transistor T7 is connected to the second scan line Scan2. The first electrode of the second initialization transistor T7 is connected to the second type initialization signal line VI-ANO. The second electrode of the second initialization transistor T7 is connected to the light-emitting device LED at the fourth node C.

[0059] Specifically, such as Figure 3 As shown, the light-emitting device LED is connected to the low-potential power line VSS. The pixel driving circuit also includes a storage capacitor Cst. One end of the storage capacitor Cst is connected to the high-potential power line VDD, and the other end of the storage capacitor Cst is connected to the gate of the driving transistor T1.

[0060] Specifically, Figure 5 The specific structure of the pixel driving circuit is illustrated using a 7T1C circuit as an example, but the embodiments of this application are not limited to this. For example, the pixel driving circuit also includes a boost capacitor, one end of which is connected to the gate of the switching transistor T2, and the other end of which is connected to the gate of the driving transistor T1.

[0061] Specifically, the pixel driving circuit may also include a third initialization transistor, the gate of which may be connected to the second scan line Scan2, the first electrode of which is connected to the third type of initialization signal line, and the second electrode of which is connected to the first electrode of the driving transistor T1.

[0062] Accordingly, when the pixel driving circuit includes a third type of initialization signal line, a third type of initialization bus will be set up, so that at least one of the first type of initialization bus, the second type of initialization bus and the third type of initialization bus can be connected to the corresponding initialization signal line through the fan-out line.

[0063] Specifically, such as Figure 5 As shown, Figure 5 The example described uses P-type transistors as an example, where the driving transistor T1, switching transistor T2, compensation transistor T3, first initialization transistor T4, first light-emitting transistor T5, second light-emitting transistor T6, and second initialization transistor T7 are all P-type transistors. However, the embodiments of this application are not limited to this. For example, the compensation transistor T3 and the first initialization transistor T4 can be N-type transistors, and the other transistors can be P-type transistors.

[0064] Specifically, such as Figure 5 As shown, Figure 5 The example described uses compensation transistor T3 and first initialization transistor T4 as dual-gate transistors, but the embodiments of this application are not limited to this. For example, compensation transistor T3 and first initialization transistor T4 can be single-gate transistors, or compensation transistor T3 and first initialization transistor T4 can be top-bottom dual-gate transistors; or one or more of other transistors can be dual-gate transistors.

[0065] like Figure 6 As shown, the display panel 2 includes a substrate 41, a buffer layer 421, an active layer 422, a first gate insulating layer 423, a first gate layer 424, a second gate insulating layer 425, a second gate layer 426, an interlayer insulating layer 427, a first source-drain layer 428, a planarization layer 429, and a second source-drain layer 431.

[0066] Specifically, the active layer 422 can be made of silicon semiconductor or oxide semiconductor, specifically low-temperature polycrystalline silicon or metal oxide, such as indium gallium zinc oxide.

[0067] Specifically, Figure 6 The present invention uses a display panel 2 with only one active layer 422 as an example for illustration, but the embodiments of this application are not limited to this. The display panel may include two active layers, one of which is made of silicon semiconductor and the other of which is made of oxide semiconductor. A gate layer and an insulating layer are set accordingly to realize their functions. At the same time, each transistor may be set accordingly, so that the active layer of each transistor is made of different materials, which will not be elaborated here.

[0068] Specifically, Figure 6 The present invention uses a display panel 2 comprising two source-drain layers as an example for illustration, but the embodiments of this application are not limited thereto. The display panel 2 may comprise three source-drain layers, and an insulating layer or a planarization layer may be provided accordingly.

[0069] Specifically, the horizontal portion 3201 of the fan-out line 32 can be disposed in one of the first source-drain layer 428 and the second source-drain layer 431, and the vertical portion 3202 of the fan-out line 32 can be disposed in the other of the first source-drain layer 428 and the second source-drain layer 431, with the two connected by vias. However, the embodiments of this application are not limited to this. The horizontal portion 3201 and the vertical portion 3202 of the fan-out line 32 can be disposed in the same layer. Alternatively, when the display panel includes a third source-drain layer, the horizontal portion 3201 of the fan-out line 32 can be disposed in one of the first source-drain layer 428, the second source-drain layer 431, and the third source-drain layer, and the vertical portion 3202 of the fan-out line 32 can be disposed in the other of the first source-drain layer 428, the second source-drain layer 431, and the third source-drain layer.

[0070] Specifically, such as Figure 3 As shown, the initialization signal line 33 may include a horizontal initial portion and a vertical initial portion. The horizontal initial portion of the initialization signal line 33 may be disposed in one of the first source-drain layer 428 and the second source-drain layer 431, and the vertical initial portion of the initialization signal line 33 may be disposed in the other of the first source-drain layer 428 and the second source-drain layer 431. However, the embodiments of this application are not limited to this. When the display panel includes a third source-drain layer, the horizontal initial portion of the initialization signal line 33 may be disposed in one of the first source-drain layer 428, the second source-drain layer 431 and the third source-drain layer, and the vertical initial portion of the initialization signal line 33 may be disposed in the other of the first source-drain layer 428, the second source-drain layer 431 and the third source-drain layer.

[0071] Specifically, it can be understood that at the connection point between the initialization signal line 33 and the fan-out line 32, they can be directly connected when they are on the same layer, and connected through vias when they are on different layers. For example, the horizontal portion 3201 of the fan-out line 32 is disposed on the first source-drain layer 428, and the vertical portion 3202 of the fan-out line 32 is disposed on the second source-drain layer 431. Similarly, the horizontal initial portion of the initialization signal line 33 is disposed on the first source-drain layer 428, and the vertical initial portion of the initialization signal line 33 is disposed on the second source-drain layer 431. When the initialization signal line 32 is connected to the initialization signal line 33, the longitudinal initial portion of the initialization signal line 33 is connected to the transverse portion 3201 of the fan-out line 32. This allows the longitudinal initial portion of the initialization signal line 33 to pass through the via and connect to the transverse portion 3201 of the fan-out line 32. When the fan-out line 32 is connected to the initialization signal line 33, the transverse initial portion of the initialization signal line 33 is connected to the transverse portion 3201 of the fan-out line 32. This allows the transverse initial portion of the initialization signal line 33 to be directly connected to the transverse portion 3201 of the fan-out line 32.

[0072] Specifically, the data line can be formed using one of the first source-drain layer 428 and the second source-drain layer 431. However, the embodiments of this application are not limited to this. When the display panel includes a third source-drain layer, one or more of the first source-drain layer 428, the second source-drain layer 431 and the third source-drain layer can be used to form the data line.

[0073] Specifically, the power signal line can be formed using one or both of the first source-drain layer 428 and the second source-drain layer 431. However, the embodiments of this application are not limited to this. When the display panel includes a third source-drain layer, one or more of the first source-drain layer 428, the second source-drain layer 431 and the third source-drain layer can be used to form the power signal line.

[0074] Specifically, the initialization bus can be formed using one or both of the first source-drain layer 428 and the second source-drain layer 431. For example, in the part connecting the fan-out line or the initialization signal line, the initialization bus can include two parts located in the first source-drain layer 428 and the second source-drain layer 431. When connecting to a flexible circuit board in the bonding area, the initialization bus can be formed using the first source-drain layer 428. However, the embodiments of this application are not limited to this. When the display panel includes a third source-drain layer, the initialization bus can be formed using one or more of the first source-drain layer 428, the second source-drain layer 431, and the third source-drain layer.

[0075] Specifically, in the above embodiments, the first electrode of the transistor is the source and the second electrode is the drain; or in the above embodiments, the first electrode of the transistor is the drain and the second electrode is the source.

[0076] Specifically, the above embodiments have described the display panel in detail from the perspectives of the pixel driving circuit of the display panel, the wiring arrangement of the display panel, and their combination. It is understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the initialization bus is connected to the fan-out line located in at least one of the first corner area and the second corner area, and at least one of the first type of initialization bus and the second type of initialization bus is connected to the fan-out line.

[0077] Meanwhile, this application provides a display device, which includes a display panel as described in any of the above embodiments.

[0078] Specifically, the display device may also include a power supply, a housing, and other structures.

[0079] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0080] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0081] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0082] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, It includes a display area and a non-display area. The display area is provided with a pixel driving circuit and an initialization signal line connected to the pixel driving circuit. The display area is also provided with a fan-out line. The non-display area is provided with multiple initialization buses. At least one of the initialization buses is connected to the initialization signal line via the fan-out line.

2. The display panel according to claim 1, characterized in that, The non-display area includes a fan-out area, a first sub-border area, and a second sub-border area. The first sub-border area and the second sub-border area are adjacent to the fan-out area and are positioned opposite each other on both sides of the display area. The display area includes a first corner area adjacent to the first sub-border area and the fan-out area, and a second corner area adjacent to the second sub-border area and the fan-out area. The initialization bus is connected to the fan-out line located in at least one of the first corner region and the second corner region.

3. The display panel according to claim 2, characterized in that, The connection point between the initialization bus and the fan-out line is located on one side of the middle area of ​​the first corner area and / or the second corner area, near the display area.

4. The display panel according to claim 1, characterized in that, The display panel further includes a light-emitting device connected to the pixel driving circuit. The initialization signal lines include a first type of initialization signal line and a second type of initialization signal line. The initialization bus includes a first type of initialization bus and a second type of initialization bus. The first type of initialization bus is connected to the first type of initialization signal line, and the second type of initialization bus is connected to the second type of initialization signal line. The pixel driving circuit includes: Drive transistors; A first initialization transistor, one electrode of which is connected to the first type of initialization signal line, and the other electrode of which is connected to the gate of the driving transistor; A second initialization transistor, one electrode of which is connected to the second type of initialization signal line, and the other electrode of which is connected to the light-emitting device; Wherein, at least one of the first type of initialization bus and the second type of initialization bus is connected to the fan-out line.

5. The display panel according to claim 4, characterized in that, The display panel includes a first sub-pixel unit, a second sub-pixel unit, and a third sub-pixel unit with different luminous colors. The second type of initialization signal line includes a first sub-signal line and a second sub-signal line. The second type of initialization bus includes a first sub-bus and a second sub-bus. The first sub-signal line is connected to the first sub-bus, and the second sub-signal line is connected to the second sub-bus. In the first sub-pixel unit and the third sub-pixel unit, one electrode of the second initialization transistor is connected to the first sub-signal line; in the second sub-pixel unit, one electrode of the second initialization transistor is connected to the second sub-signal line. At least one of the first type of initialization bus, the first sub-bus, and the second sub-bus is connected to the fan-out line.

6. The display panel according to claim 5, characterized in that, The fan-out line includes a first sub-fan-out line, a second sub-fan-out line, and a third sub-fan-out line. The first sub-fan-out line is connected to the first sub-bus, the second sub-fan-out line is connected to the second sub-bus, and the third sub-fan-out line is connected to the first type of initialization bus.

7. The display panel according to any one of claims 1 to 6, characterized in that, The display area is also provided with data lines and power signal lines connected to the pixel driving circuit. The fan-out lines include a first type of fan-out line, a second type of fan-out line, and a third type of fan-out line. The first type of fan-out line is connected to the data line, the second type of fan-out line is connected to the power signal line, and the third type of fan-out line is connected to the initialization bus.

8. The display panel according to claim 7, characterized in that, In the first direction, the projections of the second type of fan-out line and the third type of fan-out line on one side of the display panel overlap, and the second type of fan-out line and the third type of fan-out line are insulated from each other.

9. The display panel according to any one of claims 1 to 6, characterized in that, The fan-out line includes a horizontal portion and a vertical portion, the horizontal portion is connected to the vertical portion, the initialization signal line is connected to the horizontal portion and / or the vertical portion, and the initialization signal line connecting the fan-out line extends to the boundary between the display area and the non-display area.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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