Superconducting quantum chip flip-chip bonding process, quantum chip, storage medium and electronic equipment

Abstract

The invention discloses a superconducting quantum chip flip-chip bonding process, a quantum chip, a storage medium and electronic equipment. The process comprises the following steps: providing a first substrate containing a Josephson junction and a first welding spot array in a non-junction region, a corresponding second substrate and a second welding spot array; the two substrates are in inverted butt joint, so that the welding spots are matched and aligned; and carrying out local annealing and pressure welding on the aligned welding spots. According to the method, local heating is carried out on the indium column through the laser micro-area annealing technology, and the problem that a Josephson junction is heated and damaged due to the fact that traditional flip-chip bonding whole-face heating is carried out is effectively solved. And meanwhile, the shortest heating time can be shortened to 40ms, thermal stress and deformation are greatly reduced, and due to the non-contact and repeatable characteristics of laser annealing, the method is suitable for large-scale efficient production of the superconducting quantum chip, the stable performance of the device is ensured, and the manufacturing yield is improved.

Description

Technical Field

[0001] This invention belongs to the field of chip fabrication technology, specifically relating to a flip-chip bonding process for superconducting quantum chips, quantum chips, storage media, and electronic devices. Background Technology

[0002] Superconducting qubits are key components of quantum circuits and a major part of quantum computers. In superconducting quantum devices, when the number of qubits is small, planar fabrication is used. However, when the number of qubits is large, the planar circuit size increases due to wiring issues. Flip-chip bonding allows the main components and wiring to be distributed on two planes, reducing the planar size and making it suitable for three-dimensional integration. In flip-chip bonding, simple bonding alone cannot achieve full conductivity in the indium pillars; heating is required to melt and conduct the indium pillars. During heating, since the entire substrate is heated, the entire chip is heated, and the Josephson junction, a crucial component within the chip, is also heated, affecting its performance.

[0003] To effectively address this issue, related technologies utilize high-energy electron beams to bombard localized areas of the sample, converting kinetic energy into heat energy to achieve localized annealing of specific components in quantum chips. However, this process requires a vacuum environment and can cause some damage to the sample, impacting chip performance. Another technology uses thermal probes to directly contact the sample for heat transfer, allowing for precise control of temperature and position. However, this relies on the quality and contact stability of the probe and can also damage the sample, negatively affecting the performance of the final flip-chip. Summary of the Invention

[0004] The purpose of this invention is to propose a flip-chip bonding process for superconducting quantum chips, quantum chips, storage media, and electronic devices to solve the problems in the prior art.

[0005] Therefore, the present invention provides a flip-chip bonding process for superconducting quantum chips, the steps of which include:

[0006] A first substrate is provided, wherein a Josephson junction is formed on the first substrate, and a first solder joint array is formed on the first substrate at locations other than the Josephson junction;

[0007] A second substrate is provided, wherein a corresponding second solder array is generated on the second substrate at the position of the first solder array on the first substrate;

[0008] The first substrate and the second substrate are flip-chip mated together so that the solder joints in the first solder joint array are matched and aligned with the solder joints in the second solder joint array;

[0009] The aligned solder joints are subjected to local annealing and pressure welding to form a weld between the first substrate and the second substrate.

[0010] In one embodiment, the local annealing of the aligned solder joints is performed using a laser annealing process, which is a dual-pulse laser annealing process. The dual pulses include a first laser pulse and a second laser pulse. The first laser pulse is first used to melt the top of the solder joint, and then the process is switched to the second laser pulse. The second laser pulse is used to melt the bottom of the solder joint into a liquid state while maintaining the liquid state at the top of the solder joint.

[0011] In one embodiment, the power of the first pulsed laser is 1.5-2.0W, the power of the second pulsed laser is 0.5-1.0W, the spot diameter of the first pulsed laser is 12-15μm, and the spot diameter of the second pulsed laser is 18-20μm.

[0012] In one embodiment, the local annealing treatment of the aligned solder joints is performed using a laser annealing process, the steps of which include:

[0013] Set the laser annealing parameters;

[0014] An optical system generates a laser beam, which is focused on the solder joint array region;

[0015] Annealing is performed on the solder joint array area.

[0016] In one embodiment, the annealing parameters include:

[0017] The laser beam wavelength range is 200-560nm, the laser beam power range is 0-2.5W, the laser beam spot diameter is 10μm-20μm, and the annealing temperature is 100-150℃.

[0018] In one embodiment, the shortest time for annealing the solder joint array region is no more than 40ms.

[0019] In one embodiment, the solder joint is a superconducting metal pillar with a height of 5-15 μm.

[0020] In one embodiment, the distance between adjacent solder joints in the first solder joint array and the second solder joint array is not less than 100 μm.

[0021] In one embodiment, the distance between the first substrate and the second substrate after pressure bonding is 8-15 μm.

[0022] In one embodiment, the step of forming a first solder joint array on the first substrate at a location other than the Josephson junction, or forming a corresponding second solder joint array on the second substrate at a location corresponding to the first solder joint array on the first substrate, includes:

[0023] Photoresist is coated on the surface of the first substrate or the second substrate, and photolithography is performed to form an array of opening regions;

[0024] A first solder joint or a second solder joint is grown in the opening region to form a first solder joint array and a corresponding second solder joint array.

[0025] On the other hand, a superconducting quantum chip is also provided, which is fabricated by the aforementioned flip-chip bonding process.

[0026] On the other hand, a computer-readable storage medium is also provided, which stores a computer program for a flip-chip bonding process, wherein the computer program causes a computer to perform the flip-chip bonding process.

[0027] On the other hand, an electronic device is also provided, comprising:

[0028] One or more processors; memory; and

[0029] One or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs including methods for performing the flip-chip bonding process.

[0030] Beneficial effects:

[0031] This invention provides a flip-chip bonding process for superconducting quantum chips, a quantum chip, a storage medium, and electronic devices. By using laser micro-area annealing technology to locally heat the indium pillar, it effectively solves the problem of heat damage to the Josephson junction caused by the full-area heating in traditional flip-chip bonding. This method allows for precise control of the heating area, enabling the indium pillar to soften rapidly at a preset temperature for easy bonding, while confining the heat-affected zone to the laser spot area, ensuring that surrounding sensitive components are not affected. Simultaneously, the minimum heating time can be shortened to 40ms, significantly reducing thermal stress and deformation. Combined with the non-contact and repeatable characteristics of laser annealing, it is suitable for the large-scale, high-efficiency production of superconducting quantum chips, ensuring stable device performance and improving manufacturing yield. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 A flowchart of the flip-chip bonding process for superconducting quantum chips provided by this invention.

[0034] Figure 2 This is a schematic diagram of each step in the flip-chip bonding process for superconducting quantum chips provided by the present invention.

[0035] Figure 3 This is a schematic diagram showing the distribution of the indium pillar array and Josephson junction on a chip, as provided by the present invention.

[0036] In the figure: 100, first substrate; 200, second substrate; 300, photoresist; 400, opening region; 500, first solder joint array; 600, second solder joint array; 700, Josephson junction. Detailed Implementation

[0037] The invention will be more readily understood by referring to the following detailed description of preferred embodiments and included examples. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. In case of conflict, the definitions in this specification shall prevail.

[0038] This invention provides a flip-chip bonding process for superconducting quantum chips, a quantum chip, a storage medium, and an electronic device. It solves the problem that existing technologies require heating to melt the indium pillars and make them conductive. However, using the heating function heats the entire substrate of the chip, leading to overall chip heating and, consequently, heating of the Josephson junction within the chip, causing performance degradation. To address this, related technologies have provided two localized heating methods for the indium pillars: electron beam heating or thermal probe heating. However, these still have some drawbacks, such as damage to the indium pillar sample.

[0039] The technical concept of this invention lies in using laser annealing technology to achieve localized softening and conduction of indium pillars without affecting the performance of the Josephson junction. Compared to existing technologies that involve heating the entire chip, this effectively avoids thermal decay of the Josephson junction. Furthermore, compared to existing local annealing techniques, this invention allows for precise focusing of the laser beam through non-contact local annealing, while simultaneously controlling the spacing between indium pillars. Heating a single indium pillar does not affect surrounding areas such as the Josephson junction or other unheated indium pillars, achieving a precise annealing process. Simultaneously, laser annealing provides rapid heating, quickly raising the indium pillars to the required temperature, helping to reduce thermal stress and deformation. This avoids damage to the indium pillars during annealing, preserving their original performance and material properties, and preventing adverse effects on chip integration caused by excessive spacing between indium pillars.

[0040] like Figure 1-3 As shown, this invention provides a flip-chip bonding process for superconducting quantum chips, the steps of which include:

[0041] A first substrate 100 is provided, on which a Josephson junction 700 is formed. A first solder joint array 500 is formed on the first substrate 100 at locations other than the Josephson junction 700. Photoresist 300 is coated onto the surface of the first substrate 100, and photolithography is performed to form an array of opening regions, which avoids the Josephson junction 700. In one embodiment, the substrate may be sapphire material. A negative photoresist 300 is coated on the sapphire substrate, and columnar openings, i.e., opening regions 400, are formed by exposure and development, thereby defining the position and shape of subsequent solder joints. The opening region array includes multiple opening regions 400, which are distributed in an array on the surface of the first substrate 100. The opening region array avoids the Josephson junction 700. It should be understood that "avoiding" means that no opening regions 400 are provided in the Josephson junction 700 region, which effectively avoids affecting the Josephson junction 700 during local heating of the solder joints.

[0042] After an array of solder joints is grown in the opening region to form a solder joint array, the photoresist 300 is removed. In one embodiment, superconducting metal is deposited on the pattern formed by the photoresist 300, covering the entire surface of the substrate. That is, superconducting metal pillars, i.e., solder joints, are deposited inside the opening region 400, and a superconducting metal film is also deposited on the surface of the photoresist 300. The photoresist 300 is dissolved by a solvent such as acetone, and the superconducting metal film is peeled off together with the photoresist 300 layer, leaving only the solder joints in the opening region 400. This forms multiple isolated solder joints on the substrate surface, with smooth surfaces and clear boundaries, facilitating subsequent laser local heating and pressure bonding.

[0043] In one embodiment, the Josephson junction 700 is located at the center of the first substrate 100.

[0044] A second substrate 200 is provided, and a corresponding second solder array 600 is generated on the second substrate 200 at the position of the first solder array 500 of the first substrate 100. The formation method of the second solder array 600 on the surface of the second substrate 200 is the same as the formation method of the first solder array 500 in the first substrate 100.

[0045] The first substrate 100 and the second substrate 200 are flip-chip bonded together, so that the solder points in the first solder point array 500 are matched and aligned with the solder points in the second solder point array 600. Specifically, the first substrate 100 with solder points is flipped over and placed on the second substrate 200, and the solder points at corresponding positions on the two substrates are aligned with each other. In one embodiment, the two substrates have identical structures and their solder point positions correspond to each other. One substrate is flipped over and placed on the other substrate for pressure bonding alignment. The solder point growth steps of the two substrates can be performed simultaneously. The alignment accuracy of the pressure bonding is better than 3μm. Specifically, it means that the lateral alignment error of the indium pillars at corresponding positions on the upper and lower substrates is ≤3μm during pressure bonding. The offset of the central axis of the upper and lower indium pillars in the horizontal plane (XY axis) is ≤3μm, ensuring that the contact area of ​​the indium pillars after pressure bonding is ≥90% of the theoretical value, avoiding poor contact due to tilting, which would affect the conductivity of the superconducting circuit.

[0046] The aligned solder joints are subjected to local annealing and pressure welding to form a weld between the first substrate 100 and the second substrate 200.

[0047] The solder joints undergo localized annealing to reduce their hardness, followed by pressure bonding to complete the flip-chip bonding. In one embodiment, a focused laser beam irradiates the solder joints; the light energy is absorbed and converted into heat energy, rapidly heating the solder joints to a certain temperature, melting them, thus facilitating interconnection between the solder joints of the upper and lower chip layers during subsequent pressure bonding. Simultaneously, laser annealing confines the heat-affected zone to the solder joint area, avoiding heating of surrounding sensitive components such as the Josephson junction 700. Furthermore, laser annealing is a non-contact heating method, preventing direct damage to the solder joints.

[0048] In one embodiment, the localized annealing of the aligned solder joints is performed using a laser annealing process. This laser annealing process is a dual-pulse laser annealing, where the dual pulses include a first laser pulse and a second laser pulse. The first laser pulse is used to melt the top of the solder joint, and then the process switches to the second laser pulse. The second laser pulse is used to melt the bottom of the solder joint into a liquid state while maintaining the liquid state at the top. The power of the first laser pulse is 1.5-2.0W, the power of the second laser pulse is 0.5-1.0W, the spot diameter of the first laser pulse is 12-15μm, and the spot diameter of the second laser pulse is 18-20μm.

[0049] Specifically, a high-power (1.5W) short-duration (10ms) first pulse laser is used to bring the top 5-8μm of the indium pillar to its melting point (156.6℃) within 10ms, forming a liquid indium layer. At this time, the bottom remains solid to prevent overall collapse. Then, while the pressure welding head is performing the pressure welding, the first pulse laser is turned off and a low-power (0.8W) second pulse laser is simultaneously turned on to irradiate the bottom of the weld joint, stabilizing the liquid indium layer at the top at 140-150℃ to maintain the low viscosity of the indium liquid. At the same time, the second pulse laser is expanded to 20μm to cover the pressure welding deformation area, ensuring a uniform thermal field. This lasts for 15ms, allowing the indium liquid to fully fill the micro-gap and preventing voids in the weld joint.

[0050] In summary, the dual-pulse laser annealing process effectively reduces the thermal impact on the Josephson junction by rapidly and precisely melting the top of the indium pillar with the first pulse and simultaneously maintaining the low-temperature liquid state and performing pressure welding with the second pulse. At the same time, it can effectively improve the gap filling rate of the solder joint, i.e., the indium pillar, after the final pressure welding is formed.

[0051] In one embodiment, the step of performing local annealing on the solder joint includes:

[0052] Set the parameters for laser annealing:

[0053] The laser beam wavelength range is 200-560nm. The laser beam power ranges from 0-2.5W, and can be adjusted according to actual needs in practical applications. The laser beam spot diameter is 10μm-20μm. By controlling the laser beam spot diameter, the laser beam can be focused only on the surface of the indium pillar. Simultaneously, setting the annealing temperature to 100-150℃ avoids overheating of the Josephson junction 700, thus preventing any impact on its performance.

[0054] The optical system generates a laser beam and precisely focuses it onto the indium pillar region. The diameter of the laser beam spot is controlled within 10-20 μm to ensure that the heat-affected zone is confined within the spot area. During annealing, two laser beams can be used simultaneously to anneal the first substrate 100 and the second substrate 200. The first substrate 100 and the second substrate 200 are made of sapphire because the laser beam can penetrate the sapphire to directly anneal the indium pillar.

[0055] By activating the laser beam, the solder joints are locally annealed, and the annealing of the corresponding indium pillars can be completed in a very short time. This avoids the expansion of the heat-affected zone caused by excessively long annealing time, which could damage the Josephson junction 700. At the same time, it can also avoid the problem of uncontrolled solder joint morphology, which would affect the welding quality.

[0056] In one embodiment:

[0057] The solder joint is a superconducting metal pillar, specifically an indium pillar. Indium has a melting point of approximately 156.6℃, a specific heat capacity (assuming it is the solid-state specific heat capacity, since the initial heating is primarily solid-state heating) of approximately 0.081 cal / (g·℃), and a density of approximately 7.31 g / cm³. 3 .

[0058] For an indium pillar with a diameter of 20 μm and a height of 10 μm, its volume is 10⁻¹⁵π m³. 3 The mass is 7.31 × 10⁻¹² π kg.

[0059] The initial temperature is set to room temperature 25℃ (298.15K). To heat it to the melting point 156.6℃ (429.75K), the temperature change ΔT = 156.6 - 25 = 131.6℃.

[0060] The energy required for heating is Q = mcΔT = 3.17 × 10⁻¹⁰π J.

[0061] Once the melting point is reached, further heating requires additional heat of fusion to melt it. The heat of fusion of indium is approximately 28.5 cal / g (empirical value), which translates to 28.5 × 4.184 J / g = 119.2 J / g in SI units. Therefore, the energy Q required for melting is... melt =m×L=7.31×10-12πkg×119.2×103J / kg≈8.74×10-7πJ.

[0062] Total energy Q total =Q+Q melt ≈3.17×10-10π+8.74×10-7π≈8.74×10-7πJ (because the energy corresponding to the heat of fusion is much greater than the energy required to raise the temperature).

[0063] Laser energy Q total =P×t. Typically, the absorption efficiency of metals to lasers is not 100%. Assuming an absorption efficiency of 50%, the actual laser energy required is 0.5×8.74×10⁻⁷πJ≈1.75×10⁻⁶πJ.

[0064] The laser power is set to 1W, and according to the energy calculation formula Q... total =P×t, so the annealing time can be estimated to be approximately 100ms.

[0065] In summary, annealing of indium pillars can be achieved in a very short time. On the one hand, this can effectively improve the efficiency of annealing heating, making it suitable for large-scale application. On the other hand, the fact that the annealing process can be completed in such a short time can further reduce the impact on components such as Josephson junctions 700 and capacitors.

[0066] In one embodiment, the solder joint is a superconducting metal pillar, i.e., an indium pillar, with a height of 5-15 μm. The indium pillar undergoes plastic deformation during the pressure welding process. If the indium pillar is too high, greater pressure needs to be applied during pressure welding, which may lead to excessive deformation or even cracking of the indium pillar. If the indium pillar is too low, a tight contact cannot be formed, resulting in increased contact resistance or even connection failure.

[0067] Meanwhile, the three-dimensional integration of superconducting quantum chips requires extremely small spacing between the upper and lower layers of chips. In one embodiment, the spacing is 8-15μm. The height of the indium pillars within this range can ensure compact wiring space and avoid excessive height leading to chip volume expansion, which would affect the high-density integration of qubits.

[0068] In addition, regarding the energy efficiency and thermal impact control of laser annealing, the laser beam spot diameter is 10-20μm. When the height of the indium pillar is 15μm, the laser beam spot diameter can be adjusted to 15μm to ensure that the laser energy is concentrated on the indium pillar and to prevent energy from being dissipated to the surrounding area. If the indium pillar is too high, such as >15μm, the laser needs to penetrate deeper materials, which may cause the thermal impact zone to extend into the chip. If it is too low, such as <5μm, the indium pillar is easily overheated or even completely melted, and the heat conduction with the substrate is accelerated, which will cause thermal impact on the Josephson junction 700.

[0069] In one embodiment, such as Figure 3 As shown, the spacing between solder joints in a solder joint array composed of multiple solder joints in an open region array is not less than 100 μm. This avoids short circuits caused by pressure bonding deformation or annealing diffusion, and prevents damage to the Josephson junction 700 by thermal conduction from adjacent indium pillars during laser annealing. It also provides sufficient area to avoid compression and impact, achieving low crosstalk and high reliability connections for flip-chip bonding of superconducting quantum chips. Furthermore, this application controls the spacing between adjacent solder joints in the solder joint array to be not less than 100 μm, but not more than 120 μm. This effectively avoids the problem that excessive spacing would lead to increased chip area and reduced integration density as the number of qubits increases.

[0070] On the other hand, a superconducting quantum chip is also provided, which is fabricated by the flip-chip bonding process described above.

[0071] On the other hand, a computer-readable storage medium is also provided, which stores a computer program for running a flip-chip bonding process for a superconducting quantum chip, wherein the computer program causes a computer to perform the following steps:

[0072] A first substrate 100 is provided, wherein a Josephson junction 700 is formed on the first substrate 100, and a first solder joint array 500 is formed on the first substrate 100 at a location other than the Josephson junction 700.

[0073] A second substrate 200 is provided, and a corresponding second solder array 600 is generated on the second substrate 200 at the position of the first solder array 500 of the first substrate 100.

[0074] The first substrate 100 and the second substrate 200 are flip-chip connected to match and align the solder points in the first solder point array 500 with the solder points in the second solder point array 600.

[0075] The aligned solder joints are subjected to local annealing and pressure welding to form a weld between the first substrate 100 and the second substrate 200.

[0076] The computer-readable storage medium can be a computer storage medium or a communication medium. A communication medium includes any medium that facilitates the transfer of a computer program from one location to another. A computer storage medium can be any available medium accessible to a general-purpose or special-purpose computer. For example, a computer-readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the computer-readable storage medium. Of course, the computer-readable storage medium can also be a component of the processor. The processor and the computer-readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the ASIC can reside in a user equipment. Of course, the processor and the computer-readable storage medium can also exist as discrete components in a communication device.

[0077] Specifically, the computer-readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random-Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The storage medium can be any available medium accessible to general-purpose or special-purpose computers.

[0078] An electronic device is also provided, comprising:

[0079] One or more processors; memory; and

[0080] One or more programs, wherein the programs are stored in memory and configured to be executed by one or more processors, the programs including steps for performing the following:

[0081] A first substrate 100 is provided, wherein a Josephson junction 700 is formed on the first substrate 100, and a first solder joint array 500 is formed on the first substrate 100 at a location other than the Josephson junction 700.

[0082] A second substrate 200 is provided, and a corresponding second solder array 600 is generated on the second substrate 200 at the position of the first solder array 500 of the first substrate 100.

[0083] The first substrate 100 and the second substrate 200 are flip-chip connected to match and align the solder points in the first solder point array 500 with the solder points in the second solder point array 600.

[0084] The aligned solder joints are subjected to local annealing and pressure welding to form a weld between the first substrate 100 and the second substrate 200.

[0085] A memory is used to store computer programs. This memory may include high-speed random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device, and may also be a USB flash drive, external hard drive, read-only memory, disk or optical disc, etc.

[0086] Specifically, the aforementioned memory is internal memory, which can be used to store computer-pointable program code, including instructions. Internal memory may include a program storage area and a data storage area. The program storage area may store the operating system, at least one application program required for a given function, etc. The data storage area may store data created during the use of the electronic device, etc. Furthermore, internal memory may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, universal flash storage (UFS), etc. The processor executes various functional applications and data processing of the electronic device by running instructions stored in the internal memory and / or instructions stored in memory located within the processor.

[0087] A processor is used to execute a computer program stored in memory to implement the vehicle system operation protection method in the above embodiments. The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0088] Optionally, the memory can be either standalone or integrated with the processor. The processor may include one or more processing units, such as an application processor (AP), modem processor, graphics processing unit (GPU), image signal processor (ISP), controller, video codec, digital signal processor (DSP), baseband processor, and / or neural network processing unit (NPU). Different processing units can be independent devices or integrated into one or more processors. The controller can generate operation control signals based on the instruction opcode and timing signals to control instruction fetching and execution.

[0089] When memory is a device independent of the processor, electronic devices may also include a bus. This bus is used to connect the memory and the processor. This bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc.

[0090] It should be noted that, through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the prior art, can be embodied in the form of software products. These computer software products can be stored in computer-readable storage media, such as ROM / RAM, magnetic disks, optical disks, etc., and include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods of various embodiments or certain portions of embodiments. In this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. In the absence of further restrictions, an element defined by the phrase "includes a..." does not preclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

Claims

1. A flip-chip bonding process for superconducting quantum chips, characterized by the following steps: include: A first substrate is provided, wherein a Josephson junction is formed on the first substrate, and a first solder joint array is formed on the first substrate at locations other than the Josephson junction; A second substrate is provided, wherein a corresponding second solder array is generated on the second substrate at the position of the first solder array on the first substrate; The first substrate and the second substrate are flip-chip mated together so that the solder joints in the first solder joint array are matched and aligned with the solder joints in the second solder joint array; The aligned solder joints are subjected to local annealing and pressure welding to form a weld between the first substrate and the second substrate.

2. The flip-chip bonding process according to claim 1, characterized in that, The local annealing of the aligned solder joints is performed using a laser annealing process, which is a dual-pulse laser annealing process. The dual pulses include a first laser pulse and a second laser pulse. The first laser pulse is first used to melt the top of the solder joint, and then the process is switched to the second laser pulse. The second laser pulse is used to melt the bottom of the solder joint into a liquid state while maintaining the liquid state at the top of the solder joint.

3. The flip-chip bonding process according to claim 1, characterized in that, The power of the first pulsed laser is 1.5-2.0W, the power of the second pulsed laser is 0.5-1.0W, the spot diameter of the first pulsed laser is 12-15μm, and the spot diameter of the second pulsed laser is 18-20μm.

4. The flip-chip bonding process according to claim 1, characterized in that, The localized annealing of the aligned solder joints is performed using laser annealing technology, and the steps include: Set the laser annealing parameters; An optical system generates a laser beam, which is focused on the solder joint array region; Annealing is performed on the solder joint array area.

5. The flip-chip bonding process according to claim 4, characterized in that, The annealing parameters include: The laser beam wavelength range is 200-560nm, the laser beam power range is 0-2.5W, the laser beam spot diameter is 10μm-20μm, and the annealing temperature is 100-150℃.

6. The flip-chip bonding process according to claim 4, characterized in that, The minimum time for annealing the solder joint array area is no more than 40ms.

7. The flip-chip bonding process according to claim 1, characterized in that, The solder joint is a superconducting metal pillar with a height of 5-15 μm.

8. The flip-chip bonding process according to claim 1, characterized in that, The distance between adjacent solder joints in the first solder joint array and the second solder joint array is not less than 100 μm.

9. The flip-chip bonding process according to claim 1, characterized in that, The distance between the first substrate and the second substrate after pressure bonding is 8-15 μm.

10. The flip-chip bonding process according to claim 1, characterized in that, The steps of forming a first solder joint array on the first substrate at a location other than the Josephson junction, or forming a corresponding second solder joint array on the second substrate at a location corresponding to the first solder joint array on the first substrate, include: Photoresist is coated on the surface of the first substrate or the second substrate, and photolithography is performed to form an array of opening regions; A first solder joint or a second solder joint is grown in the opening region to form a first solder joint array and a corresponding second solder joint array.

11. A superconducting quantum chip, characterized in that, The superconducting quantum chip is fabricated using the flip-chip bonding process described in any one of claims 1-10.

12. A computer-readable storage medium, characterized in that, It stores a computer program for flip-chip bonding, wherein the computer program causes a computer to perform the flip-chip bonding process as described in any one of claims 1-10.

13. An electronic device, characterized in that, include: One or more processors; Memory; as well as One or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs including methods for performing the flip-chip bonding process as described in any one of claims 1-10.

Images