Current generating circuit

Abstract

The invention provides a current generating circuit capable of improving the precision of a current value. The current generation circuit includes: a first current mirror circuit that generates a second current obtained by subtracting a first current from an input current; a second current mirror circuit that generates a third current obtained by subtracting the second current from the input current; and the output end outputs the third current.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a current generating circuit. BACKGROUND

[0002] A current generating circuit that generates a current even at a low power supply voltage is known (for example, Patent Literature 1).

[0003] In the current generating circuit of Patent Literature 1, a current having a negative temperature characteristic can be generated at a power supply voltage of 0.9 V. However, the precision of the current value is low due to the influence of the manufacturing variation of elements and the temperature characteristic of elements.

[0004] Patent Literature 1: Japanese Patent Application Laid-Open No. H11-506860 SUMMARY

[0005] The present disclosure provides a current generating circuit that can improve the precision of a current value.

[0006] An embodiment of the present disclosure is a current generating circuit including: a first current mirror circuit that generates a second current obtained by subtracting a first current from an input current inputted; a second current mirror circuit that generates a third current obtained by subtracting the second current from the input current; and an output terminal that outputs the third current.

[0007] According to the present disclosure, the precision of a current value can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is an example of a circuit diagram of a comparative current generating circuit.

[0009] Figure 2 is an example of a circuit diagram of a current generating circuit of the first embodiment.

[0010] Figure 3 is an example of a circuit diagram of a current generating circuit of variation 1 of the first embodiment.

[0011] Figure 4 is an example of a circuit diagram of a current generating circuit of variation 2 of the first embodiment.

[0012] Figure 5 is an example of a circuit diagram of a current generating circuit of variation 3 of the first embodiment.

[0013] Figure 6 is an example of a circuit diagram that shows a current source and a current generating circuit of variation 3 of the first embodiment.

[0014] Figure 7 is a graph that is an example of a temperature characteristic of a current in variation 3 of the first embodiment. DETAILED DESCRIPTION

[0015] Hereinafter, a mode for carrying out the present disclosure will be explained in detail with reference to the drawings. The following embodiments are examples for embodying the technical idea of the present application, and are not limited to the structure or value described in the present disclosure. In addition, the same reference numerals are assigned to the same structural parts in each drawing, and sometimes repeated explanation is appropriately omitted.

[0016] In the current generating circuit of Patent Literature 1, the current value of the generated current is deviated due to the deviation of the elements, and the precision of the current value is low. As the current generating circuit in which the precision of the current value is low, a comparative mode will be explained.

[0017] (Comparative Mode)

[0018] Figure 1 is an example of a circuit diagram of the current generating circuit of the comparative mode. As shown in Figure 1 the comparative mode current generating circuit 110 includes bipolar transistors N10, N11, resistance elements R10, R11, and a current mirror circuit 12F. The bipolar transistors N10 and N11 are NPN bipolar transistors. The current mirror circuit 12F has FETs (Field Effect Transistors) M10 and M11. The FETs M10 and M11 are P-channel FETs.

[0019] The bipolar transistor N10 has an emitter electrically connected to a ground line 21, a base electrically connected to a node N10A, and a collector electrically connected to a node N10B. The bipolar transistor N11 has an emitter electrically connected to the node N10A, a base electrically connected to the node N10B, and a collector electrically connected to a power supply line 20 via the FET M10. The resistance element R10 has one end electrically connected to the node N10A and the other end electrically connected to the ground line 21. The resistance element R11 has one end electrically connected to the node N10B and the other end electrically connected to the power supply line 20. The node N10A is a node between the bipolar transistor N11 and the resistance element R10. The node N10B is a node between the resistance element R11 and the bipolar transistor N10.

[0020] The FET M10 has a source electrically connected to the power supply line 20, a gate electrically connected to a drain, and a drain electrically connected to the collector of the bipolar transistor N11. The drain and the gate are commonly electrically connected. The FET M11 has a source electrically connected to the power supply line 20, a gate electrically connected to the gate of the FET M10, and a drain electrically connected to an output terminal OUT.

[0021] The current I10 flowing through the resistance element R10 is Vbe / R10. Vbe is the base-emitter voltage of the bipolar transistor N10, and R10 is the resistance value of the resistance element R10. The collector current of the bipolar transistor N11 and the drain current of the FET M10 are I10. The current I11 as the drain current of the FET M11 becomes the same current value as the current I10 through the current mirror circuit 12F. Thus, the current I10 is output from the output terminal OUT.

[0022] However, the bipolar transistor N11 is provided in the current generating circuit 110. The bipolar transistor N11 functions as an impedance conversion element. In the case where the bipolar transistor N11 is not provided, since the current I10 varies depending on the relationship of the impedances of the FET M10, the resistance element R10, and the bipolar transistor N10, constant current operation cannot be performed.

[0023] In addition, in the current generating circuit 110, the resistance element R10, the bipolar transistor N11, and the FET M10 are electrically connected in series between the power supply line 20 and the ground line 21. The voltage between the power supply line 20 and the ground line 21 is divided into the base-emitter voltage Vbe of the bipolar transistor N10, the collector-emitter voltage Vce of the bipolar transistor N11, and the gate-source voltage Vgs of the FET M10. In order to cause the current generating circuit 110 to generate a constant current, it is required that the bipolar transistors N10 and N11 operate in the active region, and it is required that the FET M10 operate in the saturation region. Therefore, Vbe + Vce + Vgs is about 1.5 V.

[0024] Therefore, in order to cause the current generating circuit 110 to operate, the power supply voltage VCC is 1.5 V or more. In the case where the power supply voltage VCC is less than 1.5 V, the current I10 becomes small, and a desired constant current cannot be generated. In the following embodiments, a current generating circuit which operates with a low power supply voltage of about 1.0 V and which is capable of generating a current with a small variation in current value with respect to the manufacturing variation and temperature characteristics of elements and the variation in the power supply voltage VCC is described.

[0025] (First Embodiment)

[0026] Figure 2 is an example of a circuit diagram of the current generating circuit of the first embodiment. As shown in Figure 2 The current generating circuit 100 of the first embodiment has current mirror circuits 12A and 12B, and current sources 14A and 14B.

[0027] The current mirror circuit 12A has bipolar transistors N3 and N4 and a resistive element Rl. The bipolar transistors N3 and N4 are NPN bipolar transistors. The bipolar transistor N3 has an emitter electrically connected to the ground line 21, a base electrically connected to a node NIA, and a collector electrically connected to a node NIB. The nodes NIA and NIB are at the same potential, and the collector and the base are commonly electrically connected. The bipolar transistor N4 has an emitter electrically connected to the ground line 21, a base electrically connected to the node NIA, and a collector electrically connected to a node N2B. The resistive element Rl has one end electrically connected to the node NIA and the other end electrically connected to the ground line 21. The other end of the resistive element Rl is electrically connected to the emitter of the bipolar transistor N3 via the ground line 21.

[0028] The current mirror circuit 12B has FETs M7 and M8. The FETs M7 and M8 are N-channel FETs. The FET M7 has a source electrically connected to the ground line 21, a gate electrically connected to a node N2A, and a drain electrically connected to a node N2B. The nodes N2A and N2B are at the same potential, and the drain and the gate are commonly electrically connected. The FET M8 has a source electrically connected to the ground line 21, a gate electrically connected to the node N2A, and a drain electrically connected to the output terminal OUT. The current source 14A is electrically connected between the power supply line 20 and the node NIB. The current source 14B is electrically connected between the power supply line 20 and the node N2B. The current sources 14A and 14B generate currents I0 having the same value.

[0029] Since one end of the resistive element Rl is electrically connected to the base of the bipolar transistor N3, the current I1 flowing through the resistive element Rl is Vbe / Rl. Vbe is the base-emitter voltage of the bipolar transistor N3, and Rl is the resistance value of the resistive element Rl. The current I0 generated by the current source 14A is branched into a current flowing from the collector to the emitter of the bipolar transistor N3 and the current I1 flowing through the resistive element Rl. Thus, the current flowing from the collector to the emitter of the bipolar transistor N3 becomes I0-I1. Since the current flowing through the bipolar transistor N4 is a replica current of the current I0-I1 flowing through the bipolar transistor N3, the current I2 flowing from the collector to the emitter of the bipolar transistor N4 becomes I0-I1.

[0030] The current I0 generated by the current source 14B is branched into a current I2 flowing from the collector to the emitter of the bipolar transistor N4 and a current flowing from the drain to the source of the FET M7. Thereby, the current flowing from the drain to the source of the FET M7 becomes I0-I2. Since the current flowing through the FET M8 is obtained by copying the current I0-I2 flowing through the FET M7, the current I3 flowing from the drain to the source of the FET M8 becomes I0-I2. Since I2=I0-I1, I3=I0-(I0-I1)=I1. Therefore, the current flowing through the output terminal OUT is I3=I1. As described above, the current I3 of the output terminal OUT becomes the current value of the current I1, and is independent of the current values of the current sources 14A and 14B.

[0031] According to the first embodiment, the current mirror circuit 12A (first current mirror circuit) generates a current I2 (second current) obtained by subtracting a current I1 (first current) from an input current I0 (input current). The current mirror circuit 12B (second current mirror circuit) generates a current I3 (third current) obtained by subtracting the current I2 from the current I0. The output terminal OUT outputs the current I3. Thereby, even if the current I0 varies due to the manufacturing variation of the elements of the current sources 14A and 14B, the temperature characteristics, and the variation of the power supply voltage VCC, the current I3 is not easily affected by the current I0. Therefore, if the current I1 is designed to have a desired current value and temperature characteristics, the current I3 can be designed to have a desired current value and temperature characteristics without being affected by the current I0.

[0032] In the current mirror circuit 12A, the current I0 is input to the collector of the bipolar transistor N3 (first bipolar transistor). One end of the resistive element R1 (first resistive element) is electrically connected to the base of the bipolar transistor N3, and the other end is connected to the emitter of the bipolar transistor N3. Thereby, the base-emitter voltage Vbe of the bipolar transistor N3 and the resistance value of the resistive element R1 can be determined. The current value of the current I1 becomes Vbe / R1.

[0033] The base of the bipolar transistor N4 (second bipolar transistor) is electrically connected to the base of the bipolar transistor N3. Thereby, the current I2=I0-I1 flows between the collector and the emitter of the bipolar transistor N4.

[0034] The drain of the FET M7 (first transistor) inputs a current I0, and is electrically connected to the collector of the bipolar transistor N4. Thus, a current I0-I2 flows through the FET M7. The current I0-I2 is copied, and a current I3 = I0-I2 flows between the drain and the source of the FET M8 (second transistor). Therefore, the current I3 flowing through the output terminal OUT is I1 = Vbe / R1. Thus, the current I3 can be made to be Vbe / R independently of the current I0. That is, in order to improve the accuracy of the current I1, it is only necessary to suppress the element deviation of the bipolar transistor N3 and the resistive element R1. As a result, the accuracy of the current I1 flowing through the output terminal OUT can be improved.

[0035] As the first transistor and the second transistor of the current mirror circuit 12B, FETs are described as an example, but the first transistor and the second transistor can be bipolar transistors. In the case where the transistors are FETs, the source, the drain, and the gate correspond to the input terminal, the output terminal, and the control terminal, respectively. In the case where the transistors are bipolar transistors, the emitter, the collector, and the base correspond to the input terminal, the output terminal, and the control terminal, respectively. In addition, the input terminal and the output terminal are not limited to the case where currents having positive current values are input and output, respectively, but can input and output currents having negative current values, respectively.

[0036] (Modified example 1 of the first embodiment)

[0037] Figure 3 is an example of a circuit diagram of the current generating circuit of the modified example 1 of the first embodiment. As shown in Figure 3 , the current generating circuit 102 of the modified example 1 of the first embodiment has the current mirror circuits 12A, 12B, 12C, the current sources 14A and 14B. The subsequent stage circuit 16 is connected to the output terminal OUT.

[0038] The structures of the current mirror circuits 12A, 12B, the current sources 14A and 14B are the same as those of the current generating circuit 100 of the first embodiment except that the drain of the FET M8 is electrically connected to the node N3B, and the description is omitted.

[0039] The current mirror circuit 12C has FETs M5 and M6. The FETs M5 and M6 are P-channel FETs. The FET M5 has a source electrically connected to the power supply line 20, a gate electrically connected to the node N3A, and a drain electrically connected to the node N3B. The nodes N3A and N3B are at the same potential, and the drain and the gate are electrically connected in common. The FET M6 has a source electrically connected to the power supply line 20, a gate electrically connected to the node N2A, and a drain electrically connected to the output terminal OUT.

[0040] The subsequent stage circuit 16 is, for example, a reference voltage generating circuit, and has a bipolar transistor N5 (third bipolar transistor) and a resistive element R3 (second resistive element) as a starting circuit. The bipolar transistor N5 is an NPN bipolar transistor, and has an emitter electrically connected to a ground line 21, a base electrically connected to an output terminal OUT, and a collector electrically connected to the subsequent stage circuit. The resistive element R3 has one end electrically connected to the output terminal OUT and the other end electrically connected to the ground line 21. The other end of the resistive element R3 is electrically connected to the emitter of the bipolar transistor N5 via the ground line 21. Note that a circuit element can be provided between the resistive element R3 and the ground line 21. Note that a circuit element can be provided between the bipolar transistor N5 and the ground line 21.

[0041] In the modification 1 of the first embodiment, the current mirror circuit 12C (third current mirror circuit) inputs the current I3 generated by the current mirror circuit 12B, and outputs the current I3 to the output terminal OUT. Thus, the direction of the current I3 at the output terminal OUT in the first embodiment (in which the current I3 is introduced into the output terminal OUT) can be made opposite to the direction of the current I3 at the output terminal OUT of the modification 1 of the first embodiment (in which the current I3 is output from the output terminal OUT). Figure 2 In the modification 1 of the first embodiment, the current mirror circuit 12C (third current mirror circuit) inputs the current I3 generated by the current mirror circuit 12B, and outputs the current I3 to the output terminal OUT. Thus, the direction of the current I3 at the output terminal OUT in the first embodiment (in which the current I3 is introduced into the output terminal OUT) can be made opposite to the direction of the current I3 at the output terminal OUT of the modification 1 of the first embodiment (in which the current I3 is output from the output terminal OUT). Figure 3 In the modification 1 of the first embodiment, the current mirror circuit 12C (third current mirror circuit) inputs the current I3 generated by the current mirror circuit 12B, and outputs the current I3 to the output terminal OUT. Thus, the direction of the current I3 at the output terminal OUT in the first embodiment (in which the current I3 is introduced into the output terminal OUT) can be made opposite to the direction of the current I3 at the output terminal OUT of the modification 1 of the first embodiment (in which the current I3 is output from the output terminal OUT).

[0042] In the current mirror circuit 12C, the source and the gate of the FET M5 (third transistor) are commonly electrically connected. The gate of the FET M6 (fourth transistor) is electrically connected to the gate of the FET M5. The source of the FET M6 is electrically connected to the output terminal OUT. Thus, the current I3 generated by the current mirror circuit 12A flows between the source and the drain of the FET M5. The current I3, which is a copy of the current I3 flowing between the source and the drain of the FET M5, flows between the source and the drain of the FET M6.

[0043] The third transistor and the fourth transistor of the current mirror circuit 12C are described by way of example using FETs, but the third transistor and the fourth transistor can be bipolar transistors.

[0044] The subsequent stage circuit 16 is started when the base-emitter voltage Vbe of the bipolar transistor N5 is greater than the product of the current I3 and the resistance value of the resistive element R3. In the case where the starting voltage of the subsequent stage circuit 16 is about 1 V, if a current generating circuit having a power supply voltage of 1.5 V is used as in the comparative example, the subsequent stage circuit does not operate.

[0045] In the current generating circuit 102, the sum of the drain-source voltage Vds of the FET M8 and the gate-source voltage Vgs of the FET M5 becomes the power supply voltage VCC. If the FETs M5 and M8 operate in the saturation region, the current flows in the positive direction through the gate-source of the FET M5. For example, Vds = 0.8 V and Vgs = 0.2 V, and the power supply voltage VCC can be set to about 1 V. In this way, the power supply voltage VCC is preferably less than 1.5 V, and more preferably 1.2 V or less.

[0046] In the case where the current I3 and the start condition of the subsequent stage circuit 16 are different, the subsequent stage circuit 16 does not start or the start time is different. As in the modification example 1 of the first embodiment, when the bipolar transistors N3, N4, and N5 are NPN bipolar transistors, even if manufacturing variations occur, the Vbe of the bipolar transistors N3, N4, and N5 are almost the same. In addition, the temperature characteristics of the Vbe of the bipolar transistors N3, N4, and N5 are substantially the same. For example, when the Vbe of the bipolar transistor N5 increases due to manufacturing variations or temperature changes, the current I3 also increases. Thus, it is possible to suppress the start failure of the subsequent stage circuit 16 and the variation in the start time. Furthermore, by setting the resistance elements Rl and R3 to resistance elements of the same configuration, such as diffusion resistance or polysilicon resistance, it is possible to make the manufacturing variations and the temperature changes of the resistance elements Rl and R2 also substantially the same. From the viewpoint of suppressing manufacturing variations, the current generating circuit 102 and the subsequent stage circuit 16 are preferably provided on the same semiconductor substrate.

[0047] (Modification example 2 of the first embodiment)

[0048] Figure 4 is an example of a circuit diagram of the current generating circuit of the modification example 2 of the first embodiment. As shown in Figure 4 In the current generating circuit 104 of the modification example 2 of the first embodiment, the bipolar transistors N3, N4, and N5 are PNP bipolar transistors. The FETs M5 and M6 are N-channel FETs, and the FETs M7 and M8 are P-channel FETs.

[0049] The emitter of the bipolar transistors N3, N4, and N5, the source of the FETs M7 and M8, and the other end of the resistance elements Rl and R3 are electrically connected to the power supply line 20. The sources of the FETs M5 and M6 are electrically connected to the ground line 21. The current source 14A is connected between the node NIB and the ground line 21, and the current source 14B is connected between the node N2B and the ground line 21. The other connection relationships are the same as those of the modification example 1 of the first embodiment.

[0050] The current I1 flowing through the resistance element R1 is Vbe / R1. Vbe is the base-emitter voltage of the bipolar transistor N3, and R1 is the resistance value of the resistance element R1. The current flowing through the bipolar transistor N3 is I0-I1. The current I2 flowing through the bipolar transistor N4 is I0-I1. The current flowing through the FET M7 is I0-I2, and the current I3 flowing through the FET M8 is I0-I2=I1. Thus, the output terminal OUT outputs the current I3=I1. The power supply voltage VCC is determined by Vds of the FET M8 and Vgs of the FET M3, and thus the power supply voltage VCC can be made smaller than 1.5 V.

[0051] As the modification example 2 of the first embodiment, when the bipolar transistor N5 of the later-stage circuit 16 is a PNP bipolar transistor, the bipolar transistors N3 and N4 are preferably PNP bipolar transistors. Thus, Vbe of the bipolar transistors N3, N4, and N5 is almost the same, and the temperature characteristics of Vbe are also almost the same.

[0052] (Modification example 3 of the first embodiment)

[0053] Figure 5 is an example of a circuit diagram of the current generation circuit of the modification example 3 of the first embodiment. As shown in Figure 5 In the current generation circuit 106 of the modification example 3 of the first embodiment, the current source 18 and the current generation circuit 19 are provided. The current source 18 has the bipolar transistors N1 and N2 and the resistance element R2. The bipolar transistors N1 and N2 are NPN bipolar transistors. The current generation circuit 19 has the FETs M1, M2, M3, and M4. The FETs M1 to M4 are P-channel FETs.

[0054] Figure 6 is an example of a circuit diagram of the current source and the current generation circuit of the modification example 3 of the first embodiment. "X1", "X2", "XN" shown near each transistor indicate the size of the transistor. For example, the transistor of "XN" indicates that the size is N times as large as that of the transistor of "X1", which corresponds to connecting N number of transistors of the same size in parallel.

[0055] As shown in Figure 6 In the current source 18, the bipolar transistor N1 has an emitter electrically connected to the ground line 21, a base electrically connected to the node N4A, and a collector electrically connected to the node N4B. The nodes N4A and N4B are at the same potential, and the collector and the base are commonly electrically connected. The bipolar transistor N2 has an emitter electrically connected to the ground line 21 via the resistance element R2, a base electrically connected to the node N4A, and a collector electrically connected to the power supply line 20 via the FET M2. The resistance element R2 has one end electrically connected to the emitter of the bipolar transistor N2 and the other end electrically connected to the ground line 21.

[0056] If the base-emitter voltages of bipolar transistors N1 and N2 are set to Vbe(N1) and Vbe(N2) respectively, and the resistance of resistor R2 is set to R2, then the current flowing through resistor R2 is IG = [Vbe(N1) - Vbe(N2)] / R2. For example, when the size of bipolar transistor N2 is twice the size of bipolar transistor N1, IG = [Vbe(N1) - Vbe(N2)] / R2 = VT × ln2 / R2. VT is the thermal voltage, and ln is the natural logarithm. The circuit that generates the current IG can be any circuit other than those described above.

[0057] In the current generation circuit 19, FET M1 has a source electrically connected to power line 20, a gate electrically connected to node N5A, and a drain electrically connected to node N4B. FET M2 has a source electrically connected to power line 20, a gate electrically connected to node N5A, and a drain electrically connected to the collector of bipolar transistor N4. FET M3 has a source electrically connected to power line 20, a gate electrically connected to node N5B, and a drain electrically connected to node N1B. FET M4 has a source electrically connected to power line 20, a gate electrically connected to node N5B, and a drain electrically connected to node N2B. Nodes N5A and N5B are at the same potential, and the gates of FETs M1 to M4 are connected to a common ground.

[0058] Current IG flows through FETs M1 and M2. When the sizes of FETs M3 and M4 are N times those of FETs M1 and M2, the current I0 flowing through FETs M3 and M4 is I0 = N × IG. As an example, N = 3. It is possible to make the current I0 of current sources 14A and 14B in the first embodiment and its variations 1 and 2 the same as each other.

[0059] exist Figures 2 to 5 If the current I0 is less than the current I1, the current I1 cannot be generated. Therefore, the current I0 should be greater than the current I1. The current I0 is preferably 1.5 times or more than the current I1, and more preferably 2 times or more.

[0060] In order to increase the current I0, in the variation 3 of the first embodiment, the current source 18 generates a current IG (reference current). The current generation circuit 19 generates a current I0 that is larger than the current IG based on the current IG. Thus, a large current I0 can be generated.

[0061] More specifically, the current IG flows between the source and the drain of the FETs Ml and M2 (fifth transistor). The gate of the FET M3 (sixth transistor) is electrically connected to the gates of the FETs Ml and M2. Thereby, the current IO that is N times the current IG flows between the source and the drain of the FET M3. The gate of the FET M4 (seventh transistor) is electrically connected to the gates of the FETs Ml and M2. Thereby, the current IO that is N times the current IG flows between the source and the drain of the FET M4. Thereby, it is possible to set the current IO input to the current mirror circuits 12A and 12B to be N times the current IG. Therefore, it is possible to make the current IO larger than the current II.

[0062] As the fifth transistor, the sixth transistor, and the seventh transistor, FETs are exemplified, but the fifth transistor, the sixth transistor, and the seventh transistor can be bipolar transistors. In the case where the transistors are FETs, the source, the drain, and the gate correspond to the input terminal, the output terminal, and the control terminal, respectively. In the case where the transistors are bipolar transistors, the emitter, the collector, and the base correspond to the input terminal, the output terminal, and the control terminal, respectively.

[0063] Figure 7 is a graph showing an example of the temperature characteristic of the current in Modification 3 of the first embodiment. The horizontal axis shows the temperature of the surroundings of the current generating circuit 104, and the vertical axis shows the current I3 output from the output terminal OUT. As shown in Figure 7 the current I3 has a negative temperature coefficient with respect to the temperature. The temperature coefficient is about -2800 ppm / °C. The temperature coefficient of Vbe of a bipolar transistor is generally about -2 mV / °C, and according to the temperature coefficient of Vbe, it is considered that the output current also has a negative temperature coefficient. In addition, since the resistance element Rl is used as a resistance element whose temperature coefficient of resistance is positive, the temperature coefficient of the output current becomes negative and large. The temperature coefficient of the current I3 is mainly determined by the temperature coefficient of Vbe of the bipolar transistor N3 and the temperature coefficient of the resistance element Rl, and is not easily affected by other elements. Therefore, it is possible to make the temperature characteristic of the current I3 a desired temperature characteristic.

[0064] As in Modification 2 of the first embodiment, a P-channel FET can be used as the FETs Ml to M4, and a PNP bipolar transistor can be used as the bipolar transistors Nl and N2. In this case, the sources of the FETs Ml to M4 are connected to the ground line 21, and the emitters of the bipolar transistors Nl and N2 are connected to the power supply line 20. As described above, the sources of the FETs Ml to M4 can be electrically connected to either one of the power supply line 20 and the ground line 21, and the emitters of the bipolar transistors Nl and N2 can be electrically connected to the other one of the power supply line 20 and the ground line 21.

[0065] As in Modification Examples 1 and 2 of the first embodiment, the types (NPN or PNP) of the bipolar transistor N3 and the bipolar transistor N5 of the subsequent stage circuit are made the same as the structures (diffusion resistance or polysilicon resistance) of the resistive elements Rl and R3. Thereby, it is possible to make the temperature coefficients of the current generating circuit and the subsequent stage circuit 16 the same.

[0066] As described above, the embodiments have been described, but the above-described embodiments are presented as examples, and the present application is not limited to the above-described embodiments. The above-described embodiments can be implemented in other various ways, and various combinations, omissions, substitutions, changes, and the like can be made within the scope of the gist of the present application. These embodiments, modifications thereof, are included in the scope and gist of the present application, and in the scope of the invention recited in the claims and the equivalent thereof.

[0067] Explanation of Reference Signs

[0068] 12A, 12B, 12C, 12F current mirror circuit

[0069] 14A, 14B, 18 current source

[0070] 16 subsequent stage circuit

[0071] 19 current generating circuit

[0072] 20 power supply line

[0073] 21 ground line

Claims

1. A current generating circuit characterized by comprising: a first current mirror circuit that generates a second current obtained by subtracting a first current from an input current inputted; a second current mirror circuit that generates a third current obtained by subtracting the second current from the input current; and an output terminal that outputs the third current.

2. The current generating circuit according to claim 1, characterized in that the first current mirror circuit has: a first bipolar transistor that has a collector that inputs the input current and a base that is electrically connected to the collector; a first resistive element that has one end electrically connected to the base of the first bipolar transistor; and a second bipolar transistor that has a base electrically connected to the base of the first bipolar transistor, the first current is determined by a base-emitter voltage of the first bipolar transistor and a resistance value of the first resistive element.

3. The current generating circuit according to claim 2, characterized in that the second current flows between an emitter and a collector of the second bipolar transistor.

4. The current generating circuit according to claim 3, characterized in that the second current mirror circuit has: a first transistor that has an output terminal that inputs the input current and is electrically connected to a collector of the second bipolar transistor, and a control terminal that is electrically connected to the output terminal; and a second transistor that has a control terminal that is electrically connected to the control terminal of the first transistor, the third current flows between an input terminal and an output terminal of the second transistor.

5. The current generating circuit according to claim 4, characterized in that the current generating circuit comprises a third current mirror circuit that inputs the third current generated by the second current mirror circuit and outputs the third current to the output terminal.

6. The current generating circuit according to claim 5, characterized in that the third current mirror circuit has: a third transistor that has an input terminal that inputs the third current generated by the second current mirror circuit and a control terminal that is connected to the input terminal; and a fourth transistor that has an input terminal that is electrically connected to the output terminal and a control terminal that is electrically connected to the control terminal of the third transistor, the third current generated by the second current mirror circuit flows between the input terminal and the output terminal of the third transistor, a current that is a replica of the third current flowing between the input terminal and the output terminal of the third transistor flows between the input terminal and the output terminal of the fourth transistor.

7. The current generating circuit according to claim 1, characterized in that the input current is larger than the first current.

8. The current generating circuit according to claim 7, characterized in that the current generating circuit comprises: a current source that generates a reference current; and a current generating circuit that generates the input current that is larger than the reference current based on the reference current.

9. The current generating circuit according to claim 2, characterized in that ​ ​ ​ The current generating circuit includes a post-stage circuit electrically connected to the output terminal, and having a third bipolar transistor and a second resistance element.

10. The current generating circuit according to claim 9, wherein the third bipolar transistor has a base electrically connected to the output terminal, the second resistance element has one end electrically connected to the base of the third bipolar transistor, the post-stage circuit is activated when a base-emitter voltage of the third bipolar transistor is greater than a product of the third current and a resistance value of the second resistance element.

11. The current generating circuit according to claim 6, wherein the second transistor and the third transistor operate in a saturation region, a sum of a voltage between an input terminal and an output terminal of the second transistor and a voltage between the control terminal and the output terminal of the third transistor is less than 1.5 V.

12. The current generating circuit according to claim 9, wherein the first bipolar transistor, the second bipolar transistor, and the third bipolar transistor are NPN bipolar transistors, or, the first bipolar transistor, the second bipolar transistor, and the third bipolar transistor are PNP bipolar transistors.

13. The current generating circuit according to claim 8, wherein the current generating circuit includes: a power supply line; and a ground line, the current generating circuit includes: a fifth transistor having an input terminal electrically connected to either of the power supply line and the ground line, through which the reference current flows between the input terminal and an output terminal, a sixth transistor having an input terminal electrically connected to the either line, an output terminal electrically connected to the first current mirror circuit, and a control terminal electrically connected to a control terminal of the fifth transistor, through which the input current flows between the input terminal and the output terminal, and a seventh transistor having an input terminal electrically connected to the either line, an output terminal electrically connected to the second current mirror circuit, and a control terminal electrically connected to the control terminal of the fifth transistor, through which the input current flows between the input terminal and the output terminal. ​

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