Processor and method for dynamically adjusting cache size

Abstract

The invention provides a processor and a method for dynamically adjusting the cache size of the processor. The processor includes a cache, a workload monitor, and a microcontroller unit. The microcontroller unit operates the cache and the workload monitor, and dynamically adjusts the size of the cache according to the workload information monitored by the workload monitor.

Description

Technical Field

[0001] This invention relates to processor cache management. Background Technology

[0002] Processors are typically configured with cache. As technology advances, processor caches are becoming larger and consume more power.

[0003] In traditional technology, the processor cache is considered an integral part of the processor, operating at the same frequency as the processor core. When the processor core operates at a high frequency, the processor cache's frequency also increases accordingly to reduce latency and maximize processor performance. When the processor core operates at a low frequency, the processor cache also reduces its frequency, and the processor enters a power-saving mode.

[0004] However, in practical applications, processor resource allocation is quite complex. Simply reducing the clock speed is not the optimal solution. How to optimize system performance is a major challenge in this technical field. Summary of the Invention

[0005] This application proposes a processor that collects workload information, analyzes the utilization rate of the processor cache, estimates the cache size requirement under the current processor workload, dynamically closes unnecessary cache space, and saves power consumption of the processor cache.

[0006] A processor implemented according to one embodiment of this application includes a cache, a workload monitor, and a microcontroller unit. The microcontroller unit operates the cache and the workload monitor, and dynamically adjusts the size of the cache according to the workload information monitored by the workload monitor.

[0007] In one implementation, the microcontroller unit dynamically adjusts the size of the cache by setting the number of cache paths to run. By reducing the number of cache paths to run, the microcontroller unit can increase the core frequency of the processor.

[0008] In one embodiment, the firmware of the microcontroller unit includes running a cache size prediction model. This cache size prediction model is constructed using machine learning and outputs cache size setting parameters based on workload information collected by the workload monitor, thereby enabling dynamic adjustment of the cache size.

[0009] In addition to offline training, in one implementation, the cache size prediction model also learns in real time. The workload information collected in real time by the workload monitor, as well as the real-time size setting parameters of the cache, will be used as training data for the real-time learning of the cache size prediction model.

[0010] The aforementioned technology is further used to implement a method for dynamically adjusting the processor's cache size. One embodiment further proposes a software product comprising program code for executing the aforementioned method, which, when loaded into the processor and executed, implements the method.

[0011] The present invention will be described in detail below with reference to specific embodiments and accompanying drawings. Attached Figure Description

[0012] Figure 1 According to one embodiment of this application, a processor 100 is illustrated;

[0013] Figure 2 The diagram illustrates the input and output architecture of the cache size prediction model 118;

[0014] Figure 3 This is a flowchart illustrating the offline training methods in the laboratory;

[0015] Figure 4 The flowchart illustrates the dynamic adjustment of cache size 106 implemented by the cache size prediction model 118; and

[0016] Figure 5 The flowchart illustrates the real-time training of the cache size prediction model 118 after productization.

[0017] [Symbol Explanation]

[0018] 100: Processor

[0019] 102: Microcontroller Unit

[0020] 104: Workload Monitor

[0021] 106: Cache

[0022] 108: Core

[0023] 110: Counter

[0024] 112: Instruction Prefetch Engine

[0025] 114: System Memory

[0026] 116: Input / output devices

[0027] 118: Cache Size Prediction Model

[0028] S302…S306, S402…S408, S502…S506: Steps Detailed Implementation

[0029] The following description illustrates various embodiments of the present invention. The following description introduces the basic concepts of the invention and is not intended to limit the scope of the invention. The actual scope of the invention should be defined according to the claims. The various functional blocks (machine learning models, or functional modules, units, logic) mentioned below can be implemented by a combination of hardware, software, and firmware, and may also include special circuits. The various functional blocks are not limited to separate implementations, but can also be combined to share certain functions.

[0030] This application monitors the processor workload in real time and predicts the processor's cache size requirements accordingly, dynamically disables redundant caches, saves cache power consumption, and even uses the saved power consumption to improve the processor core speed.

[0031] Figure 1 A processor 100 is illustrated according to one embodiment of this application. A microcontroller unit (MCU) 102 on the processor 100 operates a workload monitor 104 to monitor workload information of the processor 100. Based on the workload information monitored by the workload monitor 104, the microcontroller unit (MCU) 102 dynamically adjusts the size of a cache 106.

[0032] In one embodiment, the cache 106 is a multiplexed structure. The microcontroller unit (MCU) 102 dynamically adjusts the size of the cache 106 by setting the number of paths that the cache 106 operates on. Based on low cache demand represented by workload information, the cache 106 can be partially shut down to handle the operation of the processor 100 with fewer paths.

[0033] In one implementation, by reducing the number of paths that the cache 106 operates on, the microcontroller unit (MCU) 102 can further increase the operating frequency of the processor 100's core 108, making better use of the power saved by the cache 106. The cache 106 can also be increased in frequency, significantly improving the performance of the processor 100. In contrast, traditional techniques save cache power by downclocking, resulting in decreased processor performance.

[0034] In one embodiment, the workload monitor 104 uses a counter 110 to monitor the number of cache load hits, cache misses, or cache evictions of the cache 106, and uses the counting results as workload information.

[0035] Workload information can also take other forms. The illustrated processor 100 also includes an instruction prefetcher 112, and is connected to a system memory (such as DRAM) 114 and an input / output device (I / O device) 116. The workload monitor 104 can further monitor the operating status of these modules as workload information.

[0036] In one implementation, the workload monitor 104 uses a counter 110 to monitor the number of times the instruction prefetch engine 112 initiates a prefetch, the number of prefetch hits, or the number of prefetch misses, and uses the count results as workload information.

[0037] In one embodiment, the workload monitor 104 uses a counter 110 to monitor the number of memory reads or memory writes of the system memory 114, and uses the count results as workload information.

[0038] In one embodiment, the workload monitor 104 uses a counter 110 to monitor the number of I / O reads or I / O writes of the input / output device 116, and uses the counting results as workload information.

[0039] After analysis, the workload monitored by the processor can be of various types.

[0040] As mentioned above, the real-time monitoring of workload is achieved using counter 110.

[0041] The items counted can be cache hits, cache misses, cache replacements, prefetches initiated by the prefetch engine, prefetch hits, prefetch misses, system memory reads, system memory writes, I / O reads, and / or I / O writes. Any combination of these counts can be used as workload information to dynamically adjust the cache size (bandwidth).

[0042] The concept of dynamically adjusting cache size can also be applied to the management of in-core cache size within core 108.

[0043] In addition to the tabular preset workload information for matching cache size, this application uses machine learning to construct a cache size prediction model 118, which is implemented by the firmware of the microcontroller unit (MCU) 102.

[0044] Figure 2The diagram illustrates the input and output architecture of the cache size prediction model 118. Based on the workload information collected by the workload monitor 104, the cache size prediction model 118 outputs the size setting parameters for the cache 106. Based on these size setting parameters, the microcontroller unit (MCU) 102 adjusts the size of the cache 106. In one embodiment, the cache size prediction model 118 first predicts the size requirement of the cache 106 and then converts it into the size setting parameters for the cache 106.

[0045] In one implementation, the cache size prediction model 118 is run with laboratory training parameters.

[0046] Figure 3 The flowchart illustrates the offline training method in the laboratory. Step S302: The processor 100 is run under various working scenarios. Step S304: Workload information and cache 106 occupancy size are collected for various working scenarios as training data for offline training. Step S306: A series of training data sets are used to train the cache size prediction model 118, stabilizing the parameters of the cache size prediction model 118, thus completing the offline training.

[0047] Figure 4 The flowchart illustrates the dynamic adjustment of the cache 106 size implemented by the cache size prediction model 118. Step S402: The counter 110 of the workload monitor 104 collects workload information of the processor 100. Step S404: The workload information is input into the cache size prediction model 118. Step S406: The cache size prediction model 118 predicts the size setting parameters of the cache 106. Step S408: The microcontroller unit (MCU) 102 adjusts the size of the cache 106 according to these size setting parameters; for example, the MCU 102 can adjust the size of the cache 106 in the next clock cycle to conform to the predicted size and match the collected workload information.

[0048] In one implementation, the cache size prediction model 118 is further trained online after productization to meet the customer's operating scenarios. Figure 5 The flowchart illustrates the real-time training of the cache size prediction model 118 after productization. Step S502: The workload monitor 104 collects workload information in real time. Step S504: The microcontroller unit (MCU) 102 collects the real-time size setting parameters of the cache 106 accordingly. Step S506: Using the real-time collected workload information and size setting parameters as training data for real-time learning, the cache size prediction model 118 is corrected.

[0049] According to the technology of this application, the cache size 106 of the processor 100 can be adjusted according to different computing needs, which greatly reduces power consumption and improves the performance of the processor 100.

[0050] The dynamic cache bandwidth implemented according to this application can feed back the power consumption budget saved by cache 106 to processor core 108, thereby improving the overall performance of processor 100. In computationally intensive scenarios, the cache power consumption saved by dynamically adjusting the size of cache 106 will significantly improve the battery life of electronic devices.

[0051] The aforementioned technology is further used to implement a method for dynamically adjusting the cache size of a processor, including the steps of: monitoring the workload information of the processor 100; and dynamically adjusting the size of the cache 106 based on the workload information. The method may further include running the cache size prediction model 118.

[0052] One embodiment further proposes a software product comprising program code for performing the aforementioned method, which, when loaded into and executed by the processor 100, implements the method.

[0053] Any processor 100 that reduces cache bandwidth but operates at a higher frequency may be subject to the technical content of this application.

[0054] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the appended claims.

Claims

1. A processor that dynamically adjusts cache size, comprising: cache; Workload monitor; as well as The microcontroller unit operates the cache and the workload monitor, and dynamically adjusts the size of the cache in accordance with the workload information monitored by the workload monitor.

2. The processor with dynamically adjustable cache size as described in claim 1, wherein: The microcontroller unit dynamically adjusts the size of the cache by setting the number of paths the cache can run.

3. The processor with dynamically adjustable cache size as described in claim 2, wherein: By reducing the number of paths the cache runs on, the microcontroller unit causes the processor core to operate at a higher frequency.

4. The processor with dynamically adjustable cache size as described in claim 1, wherein: The workload monitor includes a counter to monitor the number of cache hits, misses, or replacements.

5. The processor with dynamically adjustable cache size as described in claim 1, wherein: The workload monitor includes a counter that monitors the number of times the instruction prefetch engine initiates a prefetch, the number of prefetch hits, or the number of prefetch misses.

6. The processor with dynamically adjustable cache size as described in claim 1, wherein: The workload monitor includes a counter to monitor the number of reads or writes to the system memory.

7. The processor with dynamically adjustable cache size as described in claim 1, wherein: The workload monitor includes a counter to monitor the number of reads or writes to input and output devices.

8. The processor with dynamically adjustable cache size as described in claim 1, wherein: The firmware of the microcontroller unit includes a cache size prediction model that is built using machine learning. Based on the workload information collected by the workload monitor, the model outputs the cache size setting parameters to achieve dynamic adjustment of the cache size.

9. The processor with dynamically adjustable cache size as described in claim 8, wherein: The cache size prediction model also learns in real time, using the workload information collected in real time by the workload monitor and the real-time size setting parameters of the cache as training data for real-time learning.

10. A method for dynamically adjusting the cache size of a processor, comprising: Monitor processor workload information; and The cache size is dynamically adjusted based on the workload information.

11. The method for dynamically adjusting the cache size of a processor as described in claim 10, wherein the cache size is dynamically adjusted by setting the number of paths the cache runs.

12. The method for dynamically adjusting the processor cache size as described in claim 11, further comprising: The reduced number of cached paths allows the processor's cores to operate at higher frequencies.

13. The method for dynamically adjusting the processor cache size as described in claim 10, further comprising: Count the number of cache hits, misses, or replacements as information for the workload.

14. The method for dynamically adjusting the processor cache size as described in claim 10, further comprising: The count instruction prefetch engine initiates a prefetch, the number of prefetch hits, or the number of prefetch misses.

15. The method for dynamically adjusting the processor cache size as described in claim 10, further comprising: The number of reads or writes to the system memory.

16. The method for dynamically adjusting the cache size of a processor as described in claim 10, further comprising: Count the number of reads or writes to the input and output devices.

17. The method for dynamically adjusting the processor cache size as described in claim 10, further comprising: Run the cache size prediction model, The cache size prediction model is constructed using machine learning. Based on the workload information, it outputs the cache size setting parameters to achieve dynamic adjustment of the cache size.

18. The method for dynamically adjusting the processor cache size as described in claim 17, wherein: The cache size prediction model also learns in real time. The training data for real-time learning includes workload information collected in real time, as well as the real-time size setting parameters of the cache.

19. A software product comprising program code for performing the method of claim 17, which, when loaded into a processor and executed, implements the method.

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