Interrupt processing method, apparatus, device, storage medium, and program

Abstract

The application provides an interrupt processing method, device, equipment, storage medium and program, the method comprises the following steps: if an SMI interrupt storm is detected, the interrupt source generating the SMI interrupt storm is shielded; a timer with a default time period is started, so that a timer SMI interrupt is generated after the timer counts to the time period; in response to the timer SMI interrupt, if the SMI interrupt storm still exists, an error corresponding to the SMI interrupt storm is processed; the time period of the timer is recalculated based on a setting factor; after the recalculated time period of the timer is taken as the time period of the timer, the timer is restarted, so that a new timer SMI interrupt is generated after the timer counts to the time period, and the step of responding to the timer SMI interrupt is jumped to. The technical scheme of the application can process the interrupt storm while reducing the influence of the interrupt storm on the system performance.

Description

Technical Field

[0001] This application belongs to the field of operating system technology, and specifically relates to an interrupt handling method, apparatus, device, storage medium, and program. Background Technology

[0002] An SMI (System Management Interrupt) is a hardware-level failure, typically associated with firmware (BIOS / UEFI) design flaws or hardware errors. An SMI storm refers to a phenomenon where SMI interrupts are triggered abnormally frequently within a short period, leading to excessive processor resource consumption, severe system performance degradation, and even system freezes or crashes.

[0003] Systems experiencing an SMI outage storm are prone to the following phenomena:

[0004] 1. System lag: CPU usage is abnormally high (but Task Manager or performance monitoring tools may show it as "idle" because SMI is not visible in the operating system).

[0005] 2. Increased latency: Slower mouse and keyboard input response, and stuttering audio / video playback.

[0006] 3. Abnormal temperature: SMI interruption storm may cause the equipment fan control to fail, leading to overheating.

[0007] 4. Log recording: Some system logs may record a large number of ACPI (Advanced Configuration and Power Interface) or hardware error events. Summary of the Invention

[0008] The purpose of this application is to provide an interrupt handling method, apparatus, device, storage medium, and program, which aims to solve the technical problem in the related art of not being able to dynamically adjust the processing cycle according to system performance when handling SMI interrupt storms.

[0009] According to a first aspect of this application, an interruption handling method is provided, comprising:

[0010] If an SMI interrupt storm is detected, the interrupt source that caused the SMI interrupt storm is blocked.

[0011] Start a timer with a default timing period to generate a timer SIM interrupt after the timer reaches its timing period;

[0012] In response to a timer SIM interrupt, if the SMI interrupt storm still exists, the error corresponding to the SMI interrupt storm is handled.

[0013] The timer's timing period is recalculated based on set factors, including system load, the priority of the SMI interrupt storm, and / or the number of storm triggers of the corresponding interrupt source of the SMI interrupt storm.

[0014] After recalculating the timer's timing period as the timer's timing period, the timer is restarted. Once the timer's timing period is reached, a new timer SIM interrupt is generated, and the process jumps to the steps corresponding to the timer SIM interrupt. If the SMI interrupt storm still exists, the steps for handling the error corresponding to the SMI interrupt storm are executed.

[0015] In an optional implementation, if an SMI interruption storm is detected, the interruption source that generated the SMI interruption storm is blocked, including:

[0016] In response to an SMI outage event, check if an SMI outage storm has occurred;

[0017] If an SMI interruption storm occurs, the interruption source that caused the SMI interruption storm will be blocked.

[0018] Handle the error corresponding to the SMI interrupt event.

[0019] In an optional implementation, the method further includes:

[0020] In response to an SMI interruption event, the storm trigger count corresponding to the interruption source that caused the SMI interruption event is incremented by 1.

[0021] In an optional implementation, the method further includes:

[0022] In response to a timer SIM interrupt event, if the SMI interrupt storm does not exist, the interrupt source is restored and the current process ends.

[0023] In an optional implementation, the method further includes:

[0024] In response to a timer SIM interrupt event, if the SMI interrupt storm still exists, the storm trigger count corresponding to the interrupt source of the SMI interrupt storm will be incremented by 1.

[0025] In an optional implementation, the method includes, prior to detecting an SMI interruption storm:

[0026] The number of interrupt triggers corresponding to the same interrupt source is used to determine whether an SMI interrupt storm has occurred.

[0027] In an optional implementation, before starting a timer with a default timing period, the method further includes:

[0028] Handle the errors corresponding to the SIM interrupt storm.

[0029] In an optional implementation, the setting factor is the system operating load, and the timing period of the recalculated timer is proportional to the system operating load.

[0030] In an optional implementation, the setting factor is the priority of the SMI interrupt storm, and the timing period of the recalculated timer is inversely proportional to the priority of the SMI interrupt storm.

[0031] In an optional implementation, the setting factor is the number of times the interrupt source corresponding to the SMI interrupt storm is triggered, and the timing period of the recalculated timer is proportional to the number of times the interrupt source corresponding to the SMI interrupt storm is triggered.

[0032] In an optional implementation, the setting factors include system operating load, the priority of the SMI interrupt storm, and the number of storm triggers of the interrupt source corresponding to the SMI interrupt storm. The recalculated timing period is calculated as follows:

[0033] Timing period = Base period × (Priority coefficient × System load coefficient × Storm trigger coefficient) n )

[0034] Wherein, the base period is a preset default value, the priority coefficient is the coefficient corresponding to the priority of the SMI interrupt storm, the system load coefficient is the coefficient corresponding to the system operating load, the storm trigger coefficient is a preset default value greater than 1, and n is the number of storm triggers.

[0035] According to a second aspect of this application, an interrupt handling apparatus is provided, comprising:

[0036] The shielding module is configured to shield the interrupt source that generates the SMI interrupt storm if an SMI interrupt storm is detected.

[0037] The startup module is configured to start a timer with a default timing period to generate a timer SIM interrupt after the timer reaches its timing period.

[0038] The processing module is configured to respond to a timer SIM interrupt and, if the SMI interrupt storm still exists, process the error corresponding to the SMI interrupt storm.

[0039] The calculation module is configured to recalculate the timer's timing period based on set factors, including system operating load, the priority of the SMI interrupt storm, and / or the number of storm triggers of the interrupt source corresponding to the SMI interrupt storm.

[0040] The restart module is configured to restart the timer after using the recalculated timer period as the timer period, so as to generate a new timer SIM interrupt after the timer reaches its period and jump to the processing module.

[0041] The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above function.

[0042] In one possible design, the above-described device includes a memory and a processor. The memory stores one or more computer instructions that support the device in performing the corresponding methods described above, and the processor is configured to execute the computer instructions stored in the memory. The device may also include a communication interface for communicating with other devices or communication networks.

[0043] A third aspect of this application provides an electronic device including a processor and a memory, the memory storing a plurality of instructions, and the processor being configured to read the instructions and execute the method of the first aspect described above.

[0044] A fourth aspect of this application provides a computer-readable storage medium storing a plurality of instructions that can be read by a processor and used to execute the method described in the first aspect.

[0045] The fifth aspect of this application provides a computer program product comprising computer instructions which, when executed by a processor, are used to implement the methods described in any of the preceding aspects.

[0046] Compared with related technologies, the technical solution of this application has at least the following advantages:

[0047] The proposed solution continuously handles interrupt errors caused by SMI interrupt storms within the timer processing task. Since the timer's timing period is recalculated based on set factors and is no longer fixed, the timing period can be influenced by these factors, thereby accelerating or delaying the detection of SMI interrupt storms and the handling of interrupt errors causing them. Specifically, the timer's timing period can be reduced when the system is idle to expedite the detection and handling of SMI interrupt storms and their associated interrupt errors, while the timing period can be increased when the system is busy to delay the detection and handling of SMI interrupt storms and their associated interrupt errors. This approach reduces the impact of interrupt storms on system performance while simultaneously handling them.

[0048] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures and processes shown in the description and the accompanying drawings. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is a flowchart illustrating an interrupt handling method according to an exemplary embodiment of this application.

[0051] Figure 2 This is a schematic diagram of the processing flow after detecting an SMI interruption according to an exemplary embodiment of this application.

[0052] Figure 3 This is a schematic diagram of the processing flow after detecting a timer SIM interrupt according to an exemplary embodiment of this application.

[0053] Figures 4A-4C These are schematic diagrams illustrating the interruption handling effects in different scenarios according to exemplary embodiments of this application. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0055] The method provided in this application can be implemented in a terminal environment that may include one or more of the following components: a processor, a memory, and a display screen. The memory stores at least one instruction, which is loaded and executed by the processor to implement the method described in the following embodiments.

[0056] A processor may include one or more processing cores. The processor uses various interfaces and lines to connect various parts of the terminal, and performs various functions and processes data by running or executing instructions, programs, code sets or instruction sets stored in memory, and by calling data stored in memory.

[0057] Memory can include random access memory (RAM) or read-only memory (ROM). Memory can be used to store instructions, programs, code, code sets, or instructions.

[0058] The display screen is used to show the user interface of each application.

[0059] In addition, those skilled in the art will understand that the structure of the terminal described above does not constitute a limitation on the terminal. The terminal may include more or fewer components, or combine certain components, or have different component arrangements. For example, the terminal may also include radio frequency circuits, input units, sensors, audio circuits, power supplies, and other components, which will not be described in detail here.

[0060] To address the problems described in the background technology, related technologies provide a module for detecting SMI interrupt storms. When the module detects an SMI interrupt storm in the system, it disables the hardware interrupt source that caused the SMI interrupt storm and simultaneously starts a periodic timer SIM interrupt to handle hardware events. The timer SIM interrupt handler periodically checks whether the SMI interrupt storm has stopped. If the SMI interrupt storm has stopped, it disables the timer SIM interrupt and re-enables the previously disabled hardware interrupt source that caused the SMI interrupt. However, in the above-mentioned related technologies, the timer period lacks flexibility and cannot be dynamically adjusted according to system load.

[0061] Based on the above analysis, see Figure 1 As shown in the figure, an embodiment of this application proposes an interruption handling method, including:

[0062] In step S101, if an SMI interruption storm is detected, the interruption source that generates the SMI interruption storm is blocked.

[0063] In step S102, a timer with a default timing period is started so that a timer SIM interrupt is generated after the timer reaches its timing period.

[0064] In step S103, in response to a timer SIM interrupt, if the SMI interrupt storm still exists, the error corresponding to the SMI interrupt storm is processed.

[0065] In step S104, the timing period of the timer is recalculated based on set factors; the set factors include system operating load, the priority of SMI interrupt storm and / or the number of storm triggers of the interrupt source corresponding to the SMI interrupt storm;

[0066] In step S105, after using the recalculated timer period as the timer period, the timer is restarted so that a new timer SIM interrupt is generated after the timer reaches its period, and the process jumps to step S103.

[0067] In this embodiment, if the number of times the same interrupt source triggers an SMI interrupt exceeds a set value within a set time period, an SMI interrupt storm is considered to have been detected. After detecting an SMI interrupt storm, to prevent continuous SMI interrupts from being triggered in a short period, this embodiment first masks the interrupt source of the detected SMI interrupt storm, that is, disables the function of the interrupt source to generate SMI interrupts. Thus, even if the interrupt source generates an interrupt error again, it cannot trigger an SMI interrupt. In other words, although the function of the interrupt source to generate SMI interrupts is disabled, the interrupt source may still continuously generate interrupt errors. For example, if the interrupt source is memory, after disabling the function of memory to generate SMI interrupts, the memory can still generate memory errors until the problem causing the interrupt is resolved.

[0068] In some embodiments, this application also starts a timer, the timing period of which can be a preset default value, which can be a relatively short time. The purpose of starting the timer is to trigger a timer SIM interrupt after the timer count overflows, i.e., after one timing period is reached, thereby triggering a timer processing task by the timer SIM interrupt. In the timer processing task, it is checked again whether the SMI interrupt storm still exists. If it does, the error corresponding to the SMI interrupt storm is handled, the timer timing period is recalculated, and then the timer is restarted. The process from detecting an SMI interrupt to starting the timer is described in [link to documentation]. Figure 2 As shown, the processing flow in the timer processing task is as follows: Figure 3 As shown.

[0069] In some embodiments, whether an SMI interrupt storm still exists can be determined by checking if an interrupt error corresponding to a masked interrupt source has reappeared. In step S101, after detecting an SMI interrupt storm and masking the interrupt source, the interrupt error generated by that interrupt source can be cleared first. It should be noted that although the interrupt source is masked, it can still generate corresponding interrupt errors. Therefore, if an interrupt error corresponding to that interrupt source is found to reappear in the timer processing task, it means that the interrupt error of that interrupt source is still continuing. At this time, the error corresponding to the SMI interrupt storm can be processed first, that is, the interrupt error generated by the masked interrupt source can be processed. Then, the timing period is recalculated, and the timer is started with the recalculated timing period. After the restarted timer count reaches the recalculated timing period, the timer SIM interrupt will be triggered again, thereby triggering the timer processing task and re-executing the process in the timer processing task. That is, if the SMI interrupt storm still exists, the timing period will be recalculated, the timer will be restarted, and the process in the timer processing task will be re-executed, and so on.

[0070] In some embodiments, the setting factors for recalculating the timing cycle can be set according to actual needs. For example, the setting factors may be factors reflecting the current system performance, factors reflecting the importance of the interrupt source, and / or factors reflecting whether the interrupt error of the interrupt source needs to be delayed in processing. For example, the setting factors may include system operating load, the priority of the SMI interrupt storm, and / or the number of storm triggers of the interrupt source corresponding to the SMI interrupt storm.

[0071] In this way, interrupt errors caused by SMI interrupt storms can be continuously processed during timer processing tasks. Since the timer's timing period is recalculated based on set factors and is no longer fixed, the timing period can be affected by setting factors, thereby speeding up or delaying the detection of SMI interrupt storms and the processing of interrupt errors that cause SMI interrupt storms. It is possible to reduce the timer's timing period when the system is idle to speed up the detection of SMI interrupt storms and the processing of interrupt errors caused by SMI interrupt storms, and increase the timer's timing period when the system is busy to delay the detection of SMI interrupt storms and the processing of interrupt errors caused by SMI interrupt storms. In this way, the impact of interrupt storms on system performance can be reduced while processing interrupt storms.

[0072] In some optional implementations, if an SMI interrupt storm is detected, the interrupt source that caused the SMI interrupt storm is masked, including:

[0073] In response to an SMI outage event, check if an SMI outage storm has occurred;

[0074] If an SMI interruption storm occurs, the interruption source that caused the SMI interruption storm will be blocked.

[0075] Handle the error corresponding to the SMI interrupt event.

[0076] In this optional implementation, such as Figure 2 As shown, after any interrupt source triggers an SMI interrupt event, the interrupt storm detection module checks whether an SMI interrupt storm has occurred. This interrupt storm detection module can be implemented in hardware or software, depending on the specific requirements; this application does not impose any specific restrictions. The interrupt storm detection module can determine whether an SMI interrupt storm has occurred by counting whether the number of SMI interrupts triggered by the same interrupt source within a set time exceeds a set value. If an SMI interrupt storm is determined to have occurred, the interrupt storm detection module will mask the interrupt source that caused the SMI interrupt storm, preventing that interrupt source from reporting interrupt events. Simultaneously, it will also handle the interrupt error corresponding to the SMI interrupt event. The handling process varies depending on the interrupt source and the interrupt error; this application also does not impose any specific restrictions on this.

[0077] In some alternative implementations, the method further includes:

[0078] In response to an SMI interruption event, the storm trigger count corresponding to the interruption source that caused the SMI interruption event is incremented by 1.

[0079] In this optional implementation, as described above, whenever an interrupt source triggers an SMI interrupt event, the interrupt storm detection module will detect whether an SMI interrupt storm has occurred. To this end, after each detected SMI interrupt event, the interrupt storm detection module can increment the storm trigger count of the interrupt source corresponding to that SMI interrupt event by 1, thereby determining whether an interrupt source has experienced an SMI interrupt storm based on this storm trigger count. It should be noted that since an SMI interrupt storm refers to whether the number of SMI interrupt events generated within a set time period exceeds a set value, the interrupt storm detection module also records the detection time of each SMI interrupt event, and the storm trigger count of the interrupt source is the storm trigger count within that set time period.

[0080] In some alternative implementations, the method further includes:

[0081] In response to a timer SIM interrupt event, if the SMI interrupt storm does not exist, the interrupt source is restored and the current process ends.

[0082] In this optional implementation, a Timer SIM interrupt event is generated after the timer overflows. Upon detecting this Timer SIM interrupt event, if it is determined that the SMI interrupt storm does not exist (i.e., there is no interrupt error corresponding to the masked interrupt source), then it is assumed that the interrupt source will no longer generate new errors. Therefore, no further processing is needed for the SMI interrupt storm generated by this interrupt source. Instead, the function of generating SMI interrupts by this interrupt source is restored, and the current process is terminated directly. That is, the error corresponding to the SMI interrupt storm is no longer processed, the timing period is no longer recalculated, and the timer is no longer restarted.

[0083] In some alternative implementations, the method further includes:

[0084] If the SMI interruption storm still exists, the storm trigger count corresponding to the interruption source that caused the SMI interruption storm will be incremented by 1.

[0085] For this optional implementation, see [link / reference]. Figure 3 As shown, in the timer processing task, if an SMI interrupt storm is detected to still exist, the storm trigger count corresponding to the interrupt source of the SMI interrupt storm is incremented by 1. Here, the storm trigger count still refers to the number of times the interrupt source triggers an SMI interrupt event within the set time period. In this way, although the interrupt source that caused the SMI interrupt storm is masked and cannot trigger an SMI interrupt event, the timer processing task can still correctly count the number of storm triggers of the interrupt source within the set time period by detecting whether the interrupt source has generated an interrupt error.

[0086] In some alternative implementations, the method further includes, prior to detecting an SMI interruption storm:

[0087] The number of interrupt triggers corresponding to the same interrupt source is used to determine whether an SMI interrupt storm has occurred.

[0088] In this optional implementation, before step S101, it can be determined whether an interrupt source has generated an SMI interrupt storm by detecting whether the number of interrupt triggers corresponding to the same interrupt source exceeds a set value. The number of interrupt triggers is the number of SMI interrupt events triggered by the interrupt source within a set time period. As mentioned above, after each SMI interrupt event is detected, the number of interrupt triggers for each interrupt source is counted, thereby determining whether the interrupt source has generated an SMI interrupt storm based on the number of interrupt triggers.

[0089] In some alternative implementations, the method further includes, before starting a timer with a default timing period:

[0090] Handle the errors corresponding to the SIM interrupt storm.

[0091] In this optional implementation, after detecting an SMI interrupt storm and masking the interrupt source, the interrupt error generated by that interrupt source can be cleared first to prevent the interrupt error from having a subsequent impact on system operation. The interrupt error handling process varies depending on the interrupt source and the interrupt error, and this application does not impose specific restrictions on it.

[0092] In some alternative implementations, the setting factor is the system operating load, and the timing period of the recalculated timer is proportional to the system operating load.

[0093] The setting factor for recalculating the timer's timing period can be the system load; the higher the system load, the longer the recalculated timing period. This can delay the handling of interrupt errors caused by interrupt sources corresponding to SMI interrupt storms when the system load is high, thereby reducing the system burden. In some embodiments, the system load can be determined by statistically analyzing the system processor's operating frequency; the higher the operating frequency, the higher the system load, and vice versa. The processor's operating frequency can be obtained by statistically analyzing the operating frequencies of all threads running on that processor. In other embodiments, the system load can also be determined by statistically analyzing the system processor's sleep state, voltage state, etc. The specific settings can be determined according to actual conditions and are not specifically limited here.

[0094] In some alternative implementations, the setting factor is the priority of the SMI interrupt storm, and the timing period of the recalculated timer is inversely proportional to the priority of the SMI interrupt storm.

[0095] In this optional implementation, the setting factor can also be the priority of the SMI interrupt storm. The higher the priority, the shorter the recalculation timer cycle, which allows for timely handling of interrupt errors generated by interrupt sources corresponding to higher-priority SMI interrupt storms. In some embodiments, a corresponding priority can be pre-set for each interrupt source, with the priority of the SMI interrupt storm being the priority of the corresponding interrupt source.

[0096] In some optional implementations, the setting factor is the number of times the interrupt source corresponding to the SMI interrupt storm is triggered, and the timing period of the recalculated timer is proportional to the number of times the interrupt source corresponding to the SMI interrupt storm is triggered.

[0097] In this optional implementation, the setting factor can also be the number of storm triggers for the interrupt source. The greater the number of storm triggers, the longer the recalculated timing period; the smaller the number of storm triggers, the shorter the recalculated timing period. In this way, for interrupt sources that trigger more SMI interrupt events, the processing of interrupt errors can be delayed, that is, the impact of multiple SMI interrupts triggered by the same event on system operation can be weakened.

[0098] In some alternative implementations, the timer's timing period can be recalculated by combining the above three setting factors. That is, the setting factors include system operating load, the priority of the SMI interrupt storm, and the number of storm triggers of the interrupt source corresponding to the SMI interrupt storm. The recalculated timing period is calculated as follows:

[0099] Timing period = Base period × (Priority coefficient × System load coefficient × Storm trigger coefficient) n )

[0100] Among them, the base period is a preset default value, the priority coefficient is the coefficient corresponding to the priority of the SMI interrupt storm, different priorities of different interrupt sources can correspond to different coefficients, the higher the priority, the smaller the priority coefficient; the system load coefficient is the coefficient corresponding to the system operating load, different system operating loads can correspond to different coefficients, the larger the system operating load, the larger the system load coefficient; the storm trigger coefficient is a preset default value greater than 1, and n is the number of storm triggers.

[0101] The above settings are explained below with examples. The base period of the timer is a preset default value, such as 100 milliseconds.

[0102] Priority coefficient: System objects that can trigger SMI interrupt events can be called SMI interrupt sources, such as memory and I / O devices. In this application, different priorities are pre-set for different SMI interrupt sources, and different priority coefficients are assigned to each priority. For example, memory error priority is P0 with a corresponding priority coefficient of 10, I / O error priority is P1 with a corresponding priority coefficient of 100, and other error priority is P2 with a corresponding priority coefficient of 500.

[0103] System load factor: After entering the Timer SIM interrupt handling task, the operating frequency of the processor core can be obtained and divided by the processor core's maximum frequency to obtain the system load factor of that processor core. For example, if the processor core's maximum operating frequency is 2.0GHz, and it is operating at 1.2GHz when the interrupt occurs, then the system load factor of that processor core is 1.2 / 2.0 = 0.6; if it is operating at its maximum frequency of 2.0GHz when the interrupt occurs, then the system load factor of that processor core is 2.0 / 2.0 = 1.0. If there are multiple processor cores in the system, the system load of all processor cores in the system can be weighted and summed. The larger the system load factor, the busier the system; the smaller the system load factor, the less busy the system.

[0104] Storm Trigger Coefficient: After each consecutive trigger of the same error, the timer period is multiplied by a base factor, i.e., the storm trigger coefficient. This storm trigger coefficient is a pre-set default value greater than 1, for example, 1.1. After n triggers, the consecutive trigger coefficient is updated to (storm trigger coefficient). n ).

[0105] The following is through Figures 4A-4C This explains the actual effect of recalculating the timing period using the above-mentioned settings.

[0106] Example 1: If the same SMI interrupt source repeatedly triggers an SMI interrupt event, thus satisfying the conditions for an SMI interrupt storm, then how do the solutions in related technologies compare with the actual effects of this application? Figure 4A As shown, this application will gradually postpone the processing time of the same event, thereby gradually reducing the impact of the interrupt storm caused by the same interrupt event on the system.

[0107] Example 2: Comparing two hardware errors with different priorities that continuously trigger SMI interrupt storms, the P0 error has a higher priority than the P1 error. The effectiveness of this application in handling faults of different priorities is as follows: Figure 4B As shown, high-priority errors can be processed faster, while low-priority errors are processed relatively slowly. This ensures that high-priority errors receive timely responses and reduces the impact of low-priority errors on the system.

[0108] Example 3: Two hardware errors of the same priority that continuously trigger SMI interrupt storms exhibit the following response effects under different system loads: Figure 4C As shown, errors can be processed faster when the system is under light load, and slower when the system is under heavy load.

[0109] Accordingly, this application provides a second aspect of an SMI interrupt handling apparatus, comprising:

[0110] The shielding module is configured to shield the interrupt source that generates the SMI interrupt storm if an SMI interrupt storm is detected.

[0111] The startup module is configured to start a timer with a default timing period to generate a timer SIM interrupt after the timer reaches its timing period.

[0112] The processing module is configured to respond to a timer SIM interrupt and, if the SMI interrupt storm still exists, process the error corresponding to the SMI interrupt storm.

[0113] The calculation module is configured to recalculate the timer's timing period based on set factors, including system operating load, the priority of the SMI interrupt storm, and / or the number of storm triggers of the interrupt source corresponding to the SMI interrupt storm.

[0114] The restart module is configured to restart the timer after using the recalculated timer period as the timer period, so as to generate a new timer SIM interrupt after the timer reaches its period and jump to the processing module.

[0115] In some alternative implementations, the shielding module includes:

[0116] The inspection submodule, configured to respond to SMI interrupt events, checks whether an SMI interrupt storm has occurred.

[0117] The masking submodule is configured to mask the interrupt source that caused the SMI interrupt storm if an SMI interrupt storm occurs.

[0118] The processing submodule is configured to handle the error corresponding to the SMI interrupt event.

[0119] In some alternative implementations, the apparatus further includes:

[0120] The first accumulation module is configured to increment the storm trigger count corresponding to the interrupt source of the SMI interrupt event by 1 in response to the SMI interrupt event.

[0121] In some alternative implementations, the apparatus further includes:

[0122] The recovery module is configured to respond to a timer SIM interrupt event, and if the SMI interrupt storm does not exist, restore the interrupt source and terminate the current process.

[0123] In some alternative implementations, the apparatus further includes:

[0124] The second accumulation module is configured to, in response to a timer SIM interrupt event, increment the storm trigger count corresponding to the interrupt source of the SMI interrupt storm by 1 if the SMI interrupt storm still exists.

[0125] In some alternative implementations, the device includes, prior to the shielding module:

[0126] The determination module is configured to determine whether an SMI interrupt storm has occurred by counting the number of interrupts triggered for the same interrupt source.

[0127] In some alternative implementations, the device further includes the following prior to the startup module:

[0128] An error handling module is configured to handle errors corresponding to the SIM interrupt storm.

[0129] In some alternative implementations, the setting factor is the system operating load, and the timing period of the recalculated timer is proportional to the system operating load.

[0130] In some alternative implementations, the setting factor is the priority of the SMI interrupt storm, and the timing period of the recalculated timer is inversely proportional to the priority of the SMI interrupt storm.

[0131] In some optional implementations, the setting factor is the number of times the interrupt source corresponding to the SMI interrupt storm is triggered, and the timing period of the recalculated timer is proportional to the number of times the interrupt source corresponding to the SMI interrupt storm is triggered.

[0132] In some optional implementations, the setting factors include system operating load, the priority of the SMI interrupt storm, and the number of storm triggers of the interrupt source corresponding to the SMI interrupt storm. The recalculated timing period is calculated as follows:

[0133] Timing period = Base period × (Priority coefficient × System load coefficient × Storm trigger coefficient) n )

[0134] Wherein, the base period is a preset default value, the priority coefficient is the coefficient corresponding to the priority of the SMI interrupt storm, the system load coefficient is the coefficient corresponding to the system operating load, the storm trigger coefficient is a preset default value greater than 1, and n is the number of storm triggers.

[0135] The above-described device corresponds to the interrupt handling method provided in the above embodiments. For specific details, please refer to the description of the interrupt handling method in the above embodiments, which will not be repeated here.

[0136] It is understood that the circuit structures, names, and parameters described in the above embodiments are merely examples. Those skilled in the art can also make readily conceived combinations and adjustments to the structural features of the above embodiments according to their needs, and the concept of this application should not be limited to the specific details of the above examples.

[0137] This application also provides an electronic device, including a processor and a memory, wherein the memory stores multiple instructions, and the processor is used to read the instructions and execute any of the methods described in the first aspect above. The processor and memory can be connected via a bus or other means, taking a bus connection as an example. The processor can be a Central Processing Unit (CPU). The processor can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or combinations of the above-mentioned types of chips.

[0138] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the methods in the embodiments of this application. The processor executes various functional applications and data processing by running the non-transitory software programs, instructions, and modules stored in the memory, thereby implementing the methods in the above-described method embodiments.

[0139] The memory may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created by the processor, etc. Furthermore, the memory may include high-speed random access memory and non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory may optionally include memory remotely located relative to the processor, which can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0140] This application also provides a computer program product comprising computer instructions that can be loaded and executed by the processor to enable the processor to perform the methods described in the above method embodiments.

[0141] Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. An interrupt processing method characterized by comprising: include: If an SMI interrupt storm is detected, the interrupt source that caused the SMI interrupt storm is blocked. Start a timer with a default timing period, and generate a timer SMI interrupt after the timer reaches its timing period; In response to a timer SMI interrupt, if the SMI interrupt storm still exists, the error corresponding to the SMI interrupt storm is handled. The timer's timing period is recalculated based on set factors, including system load, the priority of the SMI interrupt storm, and / or the number of storm triggers of the corresponding interrupt source of the SMI interrupt storm. After recalculating the timer's timing period as the timer's timing period, the timer is restarted. Once the timer's timing period is reached, a new timer SMI interrupt is generated, and the process jumps to the steps corresponding to the timer SMI interrupt. If the SMI interrupt storm still exists, the steps for handling the error corresponding to the SMI interrupt storm are executed.

2. The interrupt handling method according to claim 1, characterized in that, If an SMI interruption storm is detected, the interruption source that caused the SMI interruption storm is blocked, including: In response to an SMI outage event, check if an SMI outage storm has occurred; If an SMI interruption storm occurs, the interruption source that caused the SMI interruption storm will be blocked. Handle the error corresponding to the SMI interrupt event.

3. The interrupt handling method according to claim 2, characterized in that, The method further includes: In response to an SMI interruption event, the storm trigger count corresponding to the interruption source that caused the SMI interruption event is incremented by 1.

4. The interruption handling method according to claim 2 or 3, characterized in that, The method further includes: In response to a timer SMI interrupt, if the SMI interrupt storm does not exist, the interrupt source is restored and the current process ends.

5. The interrupt handling method according to any one of claims 1-3, characterized in that, The method further includes: In response to a timer SMI interrupt, if the SMI interrupt storm still exists, the storm trigger count corresponding to the interrupt source of the SMI interrupt storm will be incremented by 1.

6. The interrupt handling method according to any one of claims 1-3, characterized in that, If an SMI interruption storm is detected prior to the method, the method includes: By counting the number of interrupts triggered for the same interrupt source, it can be determined whether an SMI interrupt storm has occurred.

7. The interrupt handling method according to any one of claims 1-3, characterized in that, Before starting a timer with a default timing period, the method further includes: Handle the errors corresponding to the SMI interruption storm.

8. The interrupt handling method according to any one of claims 1-3, characterized in that, The setting factor is the system operating load, and the timing period of the recalculated timer is directly proportional to the system operating load.

9. The interrupt handling method according to any one of claims 1-3, characterized in that, The setting factor is the priority of the SMI interrupt storm, and the timing period of the recalculated timer is inversely proportional to the priority of the SMI interrupt storm.

10. The interrupt handling method according to claim 5, characterized in that, The setting factor is the number of times the interrupt source corresponding to the SMI interrupt storm is triggered. The timing period of the recalculated timer is proportional to the number of times the interrupt source corresponding to the SMI interrupt storm is triggered.

11. The interrupt handling method according to any one of claims 1-3, characterized in that, The setting factors include system operating load, the priority of SMI interrupt storm, and the number of storm triggers of the corresponding interrupt source of the SMI interrupt storm. The recalculated timing period is calculated as follows: Timing period = base period x (priority factor x system load factor x storm trigger factor n ) Wherein, the base period is a preset default value, the priority coefficient is the coefficient corresponding to the priority of the SMI interrupt storm, the system load coefficient is the coefficient corresponding to the system operating load, the storm trigger coefficient is a preset default value greater than 1, and n is the number of storm triggers.

12. An interrupt handling device, characterized in that, include: The shielding module is configured to shield the interrupt source that generates the SMI interrupt storm if an SMI interrupt storm is detected. The startup module is configured to start a timer with a default timing period to generate a timer SMI interrupt after the timer reaches its timing period. The processing module is configured to respond to a timer SMI interrupt and, if the SMI interrupt storm still exists, process the error corresponding to the SMI interrupt storm. The calculation module is configured to recalculate the timer's timing period based on set factors, including system load, the priority of the SMI interrupt storm, and / or the number of storm triggers of the interrupt source corresponding to the SMI interrupt storm. The restart module is configured to restart the timer after using the recalculated timer period as the timer period, so as to generate a new timer SMI interrupt after the timer reaches its period and jump to the processing module.

13. An electronic device, characterized in that, It includes a processor and a memory, the memory storing multiple instructions, and the processor being used to read the instructions and execute the interrupt handling method as described in any one of claims 1-11.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a plurality of instructions, which can be read by a processor and executed by the interrupt handling method as described in any one of claims 1-11.

15. A computer program product, characterized in that, It includes computer instructions, wherein when executed by a processor, the computer instructions implement the interrupt handling method according to any one of claims 1-11.

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