Test mode generation method and equipment

Abstract

A test pattern generation method includes: obtaining design data about a circuit under test (CUT); generating, based on the design data, a first test pattern for detecting transition delay (TD) faults and a pre-detection fault list (PDFL) including fixed type (SA) faults respectively corresponding to detectable TD faults included in the detectable TD fault list and detectable by simulation; and generating a second test pattern for detecting the SA fault based on the design data and the PDFL.

Description

Cross Reference to Related Applications

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0083744, filed on June 26, 2024, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2024-0111626, filed on August 20, 2024, in the Korean Intellectual Property Office, the disclosure of each of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] One or more example embodiments of the present disclosure relate to a test pattern generation method and a test pattern generation device, and more particularly, to a test pattern generation method and a test pattern generation device capable of reducing the number of test patterns while maintaining test coverage. BACKGROUND

[0003] Modern digital circuits include millions of gates and flip-flops in many cases, making it almost impossible to manually generate test patterns for the gates and flip-flops. Therefore, there is a need to develop an automatic test pattern generator (ATPG) tool capable of supporting various fault models and automatically generating effective test patterns at high speed. In particular, there is a need for a technology capable of generating test patterns by reflecting various fault models and effectively detecting faults through the test patterns. SUMMARY

[0004] One or more example embodiments of the present disclosure provide a test pattern generation method and a test pattern generation device capable of reducing the number of required test patterns while maintaining test coverage.

[0005] According to an aspect of example embodiments of the present disclosure, there is provided a method of generating test patterns performed by at least one processor, the method including: obtaining design data about a circuit under test (CUT); generating, based on the design data, a first test pattern for detecting transition delay (TD) faults and a pre-detected fault list (PDFL), wherein the PDFL includes stuck-at (SA) faults respectively corresponding to detectable TD faults included in a list of detectable TD faults and capable of being detected through simulation; and generating, based on the design data and the PDFL, a second test pattern for detecting SA faults, wherein the generating of the second test pattern includes: generating, based on the design data, first SA fault candidates for a modeled circuit of the CUT; generating, based on the PDFL and the first SA fault candidates, second SA fault candidates; and generating, based on the second SA fault candidates, the second test pattern.

[0006] According to an aspect of the example embodiments of the present disclosure, there is provided a test pattern generation apparatus including at least one processor to implement: a transition delay (TD) automatic test pattern generator (ATPG) module configured to obtain design data about a circuit under test (CUT), and generate a first test pattern for detecting transition delay (TD) faults and a pre-detection fault list (PDFL) based on the design data, wherein the PDFL includes stuck-at (SA) faults respectively corresponding to detectable TD faults included in a list of detectable TD faults and capable of being detected through simulation; and a SA ATPG module configured to generate a second test pattern for detecting the SA faults based on the design data and the PDFL, wherein the SA ATPG module is configured to generate first SA fault candidates for a modeled circuit of the CUT based on the design data, generate second SA fault candidates based on the PDFL and the first SA fault candidates, and generate the second test pattern based on the second SA fault candidates.

[0007] According to an aspect of the example embodiments of the present disclosure, there is provided a system for testing a circuit under test (CUT) using a test pattern, including: a test pattern generation apparatus configured to obtain design data about the CUT, and generate a first test pattern for detecting transition delay (TD) faults and a pre-detection fault list (PDFL) based on the design data, wherein the PDFL includes stuck-at (SA) faults respectively corresponding to detectable TD faults included in a list of detectable TD faults and capable of being detected through simulation; and a SA ATPG module configured to generate a second test pattern for detecting the SA faults based on the design data and the PDFL, wherein the SA ATPG module is configured to generate first SA fault candidates for a modeled circuit of the CUT based on the design data, generate second SA fault candidates based on the PDFL and the first SA fault candidates, and generate the second test pattern based on the second SA fault candidates. BRIEF DESCRIPTION OF DRAWINGS

[0008] The example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, and by comparison to the comparative examples, in which:

[0009] Figure 1 is a block diagram illustrating a test system for a circuit under test (CUT) according to an example embodiment of the present disclosure;

[0010] Figure 2 is a data flow diagram illustrating a test pattern generation method performed by a test pattern generation apparatus according to a comparative example;

[0011] Figure 3 is a data flow diagram illustrating a test pattern generation method performed by a test pattern generation apparatus according to an example embodiment of the present disclosure;

[0012] Figure 4 is a diagram illustrating a test pattern generation method according to an example embodiment of the present disclosure;

[0013] Figure 5 is a flowchart illustrating a test pattern generation method according to an example embodiment of the present disclosure;

[0014] Figure 6 is a flowchart of operation S120 of a more detailed test pattern generation method according to an example embodiment of the present disclosure;

[0015] Figure 7 is a diagram illustrating a method of generating a pre-detect fault list (PDFL) according to an example embodiment of the present disclosure;

[0016] Figure 8 is a flowchart of operation S130 of a more detailed test pattern generation method according to an example embodiment of the present disclosure;

[0017] Figure 9 illustrates a computing device for performing a test pattern generation method according to an example embodiment of the present disclosure; and

[0018] Figure 10 is a block diagram illustrating a test system according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] Hereinafter, one or more example embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0020] Hereinafter, for convenience of description, terms such as "test pattern", "pattern", "test vector", and "vector" are used interchangeably. According to the context of the embodiment, these terms can have the same meaning or different meanings, and the meaning of each term will be understood according to the context of the embodiment to be described.

[0021] Figure 1 is a block diagram illustrating a test system 1 for a circuit under test (CUT) according to an example embodiment of the present disclosure.

[0022] Figure 1 is a block diagram illustrating a test system 1 according to an example embodiment.

[0023] Referring to Figure 1, the test system 1 can include a test pattern generation device 100, a test device 200, and a CUT 300. According to an embodiment, the CUT 300 can include the test pattern generation device 100 and / or the test device 200, and thus, the test pattern generation device 100 and / or the test device 200 can be implemented as a built-in self-test (BIST) circuit of the CUT 300.

[0024] The test pattern generation device 100 can receive design data DESIGN DATA_CUT for the CUT 300 as an input value, and generate a test pattern based on the design data DESIGN DATA_CUT.

[0025] Here, the design data DESIGN DATA_CUT can include, for example, but not limited to, netlist data, library data of devices in a circuit, and / or data of parasitic components of circuit wiring.

[0026] The netlist data can be data of connection information of a circuit, and can include information about each device (e.g., a transistor, a resistor, a capacitor, etc.) in the circuit, and information about a connection relationship between the devices in the circuit. The library data of devices in a circuit can include information about characteristics and operations of devices used in the circuit, and can be referred to as a standard cell library. The data of parasitic components of circuit wiring can include, for example, but not limited to, information about parasitic resistance, parasitic capacitance, and parasitic inductance of circuit wiring.

[0027] In other words, the netlist data can define operations of a circuit by defining logical connectivity of the circuit, the library data of devices in a circuit can be used for circuit synthesis and timing analysis by defining a cell library, and the data of parasitic components of circuit wiring can be used for timing analysis.

[0028] According to an embodiment, the netlist data can be in the format of a SPICE netlist or a Verilog netlist, the library data of devices in a circuit can be in the format of a lib file, and the data of parasitic components of circuit wiring can be in the format of a spf file.

[0029] The test pattern generation device 100 can be referred to as an automatic test pattern generator (ATPG), and the test pattern generation device 100 can model the CUT 300 based on the design data DESIGN DATA_CUT, model potential faults by using various fault models of the modeled CUT 300, and generate a test pattern by simulating the modeled CUT 300 based on the modeled potential faults. For example, the CUT 300 can be a digital circuit.

[0030] Here, the test pattern can include a test input pattern and a predicted output pattern. The test input pattern can be a combination of specific signals input to the digital circuit, and can cause a specific operation of the digital circuit. Also, the predicted output pattern can refer to an output expected from a normal digital circuit having no fault when the test input pattern is input to the digital circuit.

[0031] The test device 200 can receive the test pattern as an input value, and perform a test operation for detecting a fault of the CUT 300 based on the test pattern.

[0032] For example, the CUT 300 can receive the test input pattern as an input value from the test device 200, and operate based on the test input pattern to provide a result of the test input pattern to the test device 200. When the result of the test input pattern of the CUT 300 matches the predicted output pattern, the test device 200 can determine that the CUT 300 has no fault corresponding to the test input pattern, and when the result of the test input pattern of the CUT 300 does not match the predicted output pattern, the test device 200 can determine that the CUT 300 has a fault corresponding to the test input pattern.

[0033] The test pattern generation device 100 can generate a pattern for detecting a static fault of the digital circuit based on the design data DESIGN DATA_CUT. Here, the static fault can mean a fault in which the digital circuit always outputs an incorrect value for a specific input regardless of an operation speed of the digital circuit. The static fault can be detected by a single operation.

[0034] That is, when a specific input vector is applied to the digital circuit, when an output of the digital circuit is different from an expected value, it can be determined that there is a static fault.

[0035] For example, the static fault can include a stuck-at (SA) fault.

[0036] The SA fault can indicate a fault in which a specific signal within the digital circuit is always stuck at 0 or 1.

[0037] Here, the SA fault in which a specific node of the digital circuit is always "logic 1" is referred to as an SA1 fault, and the SA fault in which a specific node of the digital circuit is always "logic 0" is referred to as an SA0 fault. That is, the SA fault can include the SA0 fault and the SA1 fault.

[0038] Also, the test pattern generation device 100 can generate a pattern for detecting a dynamic fault of the digital circuit based on the design data DESIGN DATA_CUT. Here, the dynamic fault can mean a fault in which the digital circuit outputs an incorrect value for a specific input at a specific operation speed of the digital circuit. The dynamic fault can be detected by a plurality of operations.

[0039] That is, when a specific input vector is applied to a digital circuit operating at a specific operating speed, when the output of the digital circuit is different from an expected value, it can be determined that a dynamic fault exists.

[0040] For example, the dynamic fault can include a transition delay (TD) fault. Here, the TD fault can also be referred to as a transition fault.

[0041] The TD fault can indicate a fault in which a transition of a specific signal in the digital circuit is not completed within a predicted time.

[0042] Here, a fault in which a transition of a signal of a specific node of the digital circuit from "logic 1" to "logic 0" is not completed within a predicted time is referred to as a slow falling TD (STF TD) fault, and a fault in which a transition of a signal of a specific node of the digital circuit from "logic 0" to "logic 1" is not completed within a predicted time is referred to as a slow rising TD (STR TD) fault. That is, the TD fault can include the STF TD fault and the STR TD fault.

[0043] That is, the test pattern generated by the test pattern generation device 100 can include a TD test pattern and an SA test pattern according to a fault to be detected.

[0044] According to an embodiment, the test pattern generation device 100 can reduce the number of patterns required for testing by not generating an SA test pattern for a node (or a path) for which a TD test pattern is generated.

[0045] That is, according to an example embodiment of the disclosure, the test pattern generation device 100 can first generate a pattern capable of detecting a TD fault (or referred to as a TD test pattern), and generate a pattern capable of detecting an SA fault (or referred to as an SA test pattern) only for a node (or a path) capable of detecting an SA fault among nodes not corresponding to a TD fault, thereby avoiding repeated generation of test patterns. Accordingly, the number of test patterns required for testing can be reduced, and the simulation period of the ATPG module generating as many test patterns as reduced can be shortened. This will be described in detail with reference to Figures 2 to 8 This will be described in detail.

[0046] Figure 2 A data flow diagram of a test pattern generation method performed by the test pattern generation device 100' according to a comparative example is illustrated. Figure 3 A data flow diagram of a test pattern generation method performed by the test pattern generation device 100 according to an example embodiment of the disclosure is illustrated.

[0047] The test pattern generation device 100 according to an example embodiment of the present disclosure can be implemented as software, hardware, or a combination of hardware and software. According to some embodiments, the test pattern generation device 100 can be implemented as a computing device or computing system, and the test pattern generation method according to an example embodiment of the present disclosure can be executed by a computing device or computing system.

[0048] For example, the test pattern generation method according to an example embodiment of this disclosure can be executed by a computing system, as described later. Figure 9 As described above. For example, Figure 2 and Figure 3 Each module shown may correspond to hardware, software, or a combination of hardware and software included in a computing system. Hardware may include at least one programmable component, such as a central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), a reconfigurable component (such as a field-programmable gate array (FPGA)), or a component providing pre-designed functionality (such as an integrated property (IP) block). Software may include at least one of a set of instructions executable by programmable components or code that can be translated into a set of instructions by a compiler, and may be stored in a non-transitory storage medium.

[0049] Reference Figure 2 and Figure 3 Each of the test mode generation device 100' and the test mode generation device 100 may include a TD ATPG module 110 and an SA ATPG module 120.

[0050] First, refer to Figure 2 This describes a test pattern generation method performed by a test pattern generation device 100' based on a comparison example.

[0051] Based on the test mode generation device 100' of the comparison example, it independently generates a TD test mode that can detect TD faults and an SA test mode that can detect SA faults.

[0052] Reference Figure 2 The TD ATPG module 110 can receive design data DESIGN DATA_CUT 10 and generate TD test mode 20 based on the received design data 10. Furthermore, the SA ATPG module 120 can receive design data 10 and generate SA test mode 30 based on the received design data 10. That is, each of the TD ATPG module 110 and SA ATPG module 120 can independently generate its corresponding test mode.

[0053] On the other hand, the test pattern generation device 100 according to the example embodiment of the present disclosure can determine a detectable TD fault, generate a TD test pattern for the detectable TD fault, and generate an SA test pattern based on the PDFL generated according to the determination result.

[0054] Reference Figure 3 The TD ATPG module 110 can receive design data 10, determine detectable TD faults based on the received design data 10, and generate a TD test mode 20 for the detectable TD faults. Here, the TD ATPG module 110 can generate PDFL 40 based on the detectable TD faults and provide PDFL 40 to the SA ATPG module 120.

[0055] In addition, the SA ATPG module 120 can receive design data 10 and PDFL 40, and generate SA test mode 30 based on the received design data 10 and PDFL 40.

[0056] In other words, SA ATPG module 120 can generate SA test patterns by referring to the detectable TD faults determined when generating the TD test patterns of TD ATPG module 110. Here, the SA faults corresponding to the generated SA test patterns can correspond to nodes other than those corresponding to detectable TD faults among all SA fault candidates. Accordingly, the number of patterns required for SA fault testing and TD fault testing can be reduced.

[0057] See below for reference Figure 4 According to the example embodiment, SA faults at specific nodes of a digital circuit can be detected using the TD test mode. Accordingly, according to the example embodiment of this disclosure, even without generating test modes for all detectable SA faults, the test coverage based on test modes generated for some SA faults and test modes generated for TD faults according to the example embodiment of this disclosure can be similar to the test coverage based on test modes for all SA faults and test modes for TD faults.

[0058] Reference Figure 4 The text describes in detail how SA faults can be detected for specific nodes in digital circuits using the TD test mode.

[0059] Figure 4 This is a diagram illustrating a test pattern generation method according to an example embodiment of the present disclosure.

[0060] Reference Figure 4 It can be seen that there is an SA0 fault in the output pin Y of the assumed logic AND circuit.

[0061] The test mode (A, B) used to detect an SA0 fault in the output pin Y can be (1, 1). For example, an SA0 fault may exist in the output pin Y when the value of Y is logic 0 due to the test mode (1, 1).

[0062] Furthermore, when an SA0 fault exists in output pin Y, the output pin Y cannot be changed from logic 0 to logic 1, therefore an STR TD fault may exist in output pin Y. Similarly, when an SA1 fault exists in output pin Y, the output pin Y cannot be changed from logic 1 to logic 0, therefore an STR TD fault may exist in output pin Y.

[0063] The test mode used to detect STR TD faults in output pin Y can be a set of test modes including two test modes (A, B). For example, the first test mode set may include a first mode (1 or 0, 0) and a second mode (1, 1), and the second test mode set may include a first mode (0 or 1, 0) and a second mode (1, 1). For example, at a specific operating speed of a logic AND circuit, a STR TD fault may exist in output pin Y when the value of Y is logic 0 due to the first mode (1 or 0, 0) and the second mode (1, 1).

[0064] Here, since both the first and second test mode sets include the second mode (1,1), the test mode used to detect STR TD faults can also be used to detect SA0 faults. Similarly, the test mode used to detect STFTD faults can be used to detect SA1 faults.

[0065] Therefore, the test mode used to detect TD faults can be used to detect SA faults.

[0066] In the following text, reference will be made to Figures 5 to 7 An example of a test pattern generation method performed by a test pattern generation device 100 according to an exemplary embodiment of the present disclosure is described in more detail.

[0067] Figure 5 This is a flowchart illustrating a test pattern generation method according to an example embodiment of the present disclosure.

[0068] Reference Figure 1 and Figure 5 During operation S110, the test mode generation device 100 can obtain the design data DESIGNDATA_CUT.

[0069] Furthermore, in operation S120, the test pattern generation device 100 can generate TD test patterns and PDFL based on the design data DESIGN DATA_CUT.

[0070] Furthermore, in operation S130, the test pattern generation device 100 can generate SA test patterns based on the design data DESIGN DATA_CUT and PDFL.

[0071] Figure 6 This is a flowchart of operation S120 of a test pattern generation method according to an exemplary embodiment of the present disclosure.

[0072] Reference Figure 6 Operation S120 may include operations S121, S123 and S125.

[0073] In operation S121, the test mode generation device 100 (e.g., TD ATPG module 110) can generate TD fault candidates for circuits modeled based on design data DESIGN DATA_CUT.

[0074] Here, TD fault candidates can be generated based on the potential location and / or type of TD faults that may occur in the digital circuit. For example, TD fault candidates may correspond to specific nodes (or specific signal paths) within the digital circuit where TD faults may occur. In embodiments, TD fault candidates may correspond one-to-one with all nodes in the digital circuit. For example, test pattern generation device 100 (e.g., TD ATPG module 110) can generate TD fault candidates by applying a TD fault model (e.g., STR fault model or STF fault model) to all nodes and paths identified in the netlist data.

[0075] In an embodiment, the test pattern generation device 100 (e.g., TD ATPG module 110) can classify the generated TD fault candidates into an undetected (ND) state (or category). Here, ND can refer to a test pattern for which no corresponding TD fault candidate has been generated.

[0076] In operation S123, the test pattern generation device 100 (e.g., TD ATPG module 110) can identify one or more detectable TD faults from the TD fault candidates.

[0077] In an embodiment, the test pattern generation device 100 (e.g., TD ATPG module 110) can determine one or more detectable TD faults from the TD fault candidates based on whether one or more detectable TD faults are detectable by simulation based on the TD fault model.

[0078] Specifically, the test pattern generation device 100 (e.g., TD ATPG module 110) can generate multiple test vectors for each TD fault candidate based on a TD fault model. Subsequently, the test pattern generation device 100 (e.g., TD ATPG module 110) can perform a simulation applying each of the multiple test vectors to the modeled circuit. Based on the simulation results, the test pattern generation device 100 (e.g., TD ATPG module 110) can select at least one optimal test vector capable of detecting an actual TD fault. When a TD fault cannot be actually detected through simulation applying multiple test vectors to a corresponding TD fault candidate, the test pattern generation device 100 (e.g., TD ATPG module 110) can determine the corresponding TD fault candidate as a potentially undetectable TD fault.

[0079] In an embodiment, the test pattern generation device 100 (e.g., TD ATPG module 110) can classify detectable TD faults as detectable (DT) states (or categories) and undetectable (UD) TD faults as UD states (or categories). Here, DT can refer to a test pattern for which a corresponding fault candidate has been generated, and UD can refer to a test pattern for which a corresponding fault candidate cannot be generated.

[0080] In operation S125, the test pattern generation device 100 (e.g., TD ATPG module 110) can generate TD test patterns and PDFL.

[0081] In an embodiment, the test pattern generation device 100 (e.g., TD ATPG module 110) can generate TD test patterns by collecting test vectors selected for detectable TD faults and the predicted output patterns corresponding to the selected test vectors.

[0082] In addition, the test mode generation device 100 (e.g., TD ATPG module 110) can generate PDFL based on detectable TD faults.

[0083] Here, PDFL can include SA faults corresponding to TD faults, which can be detected by simulation using TD test modes and included in the list of detectable TD faults. PDFL can be used by test mode generation device 100 (e.g., SA ATPG module 120) to generate SA test modes.

[0084] Reference Figure 7 A method for generating PDFL based on detectable TD faults, performed by a test mode generation device 100 (e.g., TD ATPG module 110), is described in detail.

[0085] Figure 7This is a diagram illustrating a method for generating PDFL according to an example embodiment of the present disclosure.

[0086] In addition to generating TD test patterns based on detectable TD faults, the test pattern generating device 100 (e.g., TDATPG module 110) can also generate a list (or a list of detectable TD faults) 21 that includes TD faults detectable using TD test patterns.

[0087] The list 21 of TD faults that can be detected using the TD test mode includes information such as fault identifier, fault type, fault location, and detection type.

[0088] Here, the fault identifier can indicate an ID or number that can uniquely identify each fault. Furthermore, the fault type can indicate whether the fault is an SA fault or a TD fault. In an embodiment, the fault type can indicate whether the fault is an SA0 fault or an SA1 fault, an STR TD fault or an STF TD fault. Additionally, the fault location can indicate information about the specific location and / or node where the circuit fault occurred.

[0089] In addition, the detection type can indicate how to detect the fault or the intensity and / or characteristics of the detection.

[0090] For example, the detection type can be represented as detection by simulation (DS) or detection by suggestion (DI), depending on how the fault is detected.

[0091] The DS detection type can be represented by applying the test patterns generated by the ATPG module to the simulation of the modeled circuit to confirm whether a fault is detected, thereby detecting a fault. In other words, DS can detect faults in the corresponding nodes based on the simulation of directly applying the test patterns.

[0092] DI detection types can represent faults detected using implicit logic relationships, and can be identified by determining how the state of another signal or node is determined. In other words, DI indicates a situation where a fault can be detected based on specific logical conditions even without applying a direct test pattern. Examples of DI-type faults can include scan chain faults, control logic faults, clock gating faults, etc.

[0093] Furthermore, in some embodiments, for example, the detection type can be additionally represented as strong detection, weak detection, robust detection, or non-robust detection, depending on the intensity of the detection.

[0094] Reference Figure 7 As can be seen, the list 21 of TD faults that can be detected using the TD test mode is generated by the test mode generating device 100 (e.g., TD ATPG module 110).

[0095] Reference Figure 7 The list 21 of TD faults that can be detected using the TD test mode may include an index corresponding to the fault identifier, a fault type indicating one of the STR corresponding to the STR TD fault or the STF corresponding to the STF TD fault, a detection (DT) type indicating one of the DS and DI according to how the corresponding fault is detected, and an example of the location corresponding to the fault location.

[0096] Test pattern generation device 100 (e.g., TD ATPG module 110) can generate a PDFL 40 for SA faults by selecting only faults with DS detection type as the detection type from the list 21 of TD faults detectable using the TD test pattern and generating a list of selected SA faults. In other words, among the TD faults in the list 21 of TD faults detectable using the TD test pattern, faults with DS as the detection type can correspond to the SA faults included in the PDFL 40.

[0097] Furthermore, in PDFL 40, fault types with TD faults using DS as the detection type can be reclassified as SA0 or SA1. (See reference...) Figure 4 As stated above, since SA0 faults can be detected using the test mode for detecting STR TD faults, and SA1 faults can be detected using the test mode for detecting STF TD faults, STR faults can be reclassified as SA0 faults, and STF faults can be reclassified as SA1 faults.

[0098] For example, refer to Figure 7 When the fault type of the TD fault with DS as the detection type in the list 21 of TD faults that can be detected using the TD test mode is STR fault, the fault type of the corresponding fault in PDFL 40 can be reclassified as SA0.

[0099] Similarly, when the fault type of a TD fault with DS as the detection type in the list 21 of TD faults detectable using the TD test mode is an STF fault, the fault type of the corresponding fault in PDFL 40 can be reclassified as SA1.

[0100] Figure 8 This is a flowchart of operation S130 of a test pattern generation method according to an exemplary embodiment of the present disclosure.

[0101] Reference Figure 8 Operation S130 may include operations S131, S133, S135 and S137.

[0102] In operation S131, the test mode generation device 100 (e.g., SA ATPG module 120) can generate a first SA fault candidate for the circuit modeled based on the design data DESIGN DATA_CUT. Hereinafter, the first SA fault candidate may refer to an SA fault candidate generated based on the design data DESIGN DATA_CUT.

[0103] Here, the first SA fault candidate can be generated based on the potential location and / or type of SA faults that may occur in the digital circuit. For example, the first SA fault candidate may correspond to a specific node (and / or a specific signal path) within the digital circuit where an SA fault may occur. In embodiments, the first SA fault candidate may correspond one-to-one with all nodes in the digital circuit. For example, the test pattern generation device 100 (e.g., SA ATPG module 120) can generate the first SA fault candidate by applying an SA fault model (e.g., an SA0 fault model or an SA1 fault model) to all nodes and / or paths identified in the netlist data.

[0104] In an embodiment, the test pattern generation device 100 (e.g., SA ATPG module 120) can classify the generated SA fault candidates into ND states (or categories). Here, ND can refer to a test pattern for which a corresponding fault candidate has not yet been generated.

[0105] In operation S133, the test mode generation device 100 (e.g., SA ATPG module 120) can generate a second SA fault candidate based on the first SA fault candidate and PDFL.

[0106] In an embodiment, the test pattern generation device 100 (e.g., SA ATPG module 120) can generate a second SA fault candidate by removing SA faults included in both the first SA fault candidate and PDFL from the first SA fault candidate. That is, the second SA fault candidate can be a fault candidate obtained by removing SA faults included in PDFL from the first SA fault candidate.

[0107] In this embodiment, the test pattern generation device 100 can generate a second SA fault candidate by classifying SA faults included in the PDFL from the first SA fault candidate to a DT state (or category). Here, DT can refer to the test pattern of the corresponding fault candidate that has already been generated. Furthermore, no test pattern is actually generated for the SA faults included in the PDFL, but the test pattern generation device 100 can remove the SA faults included in the PDFL from the first SA fault candidate by allowing the SA ATPG module 120 to recognize that a test pattern has already been generated for the SA faults included in the PDFL. That is, the second SA fault candidate can be generated based on the SA fault candidate corresponding to the SA fault candidate previously classified as a DT state in the first SA fault candidate.

[0108] In operation S135, the test pattern generation device 100 (e.g., SA ATPG module 120) can identify detectable SA faults among the second SA fault candidates.

[0109] In an embodiment, the test pattern generation device 100 (e.g., SA ATPG module 120) can determine the detectable SA faults in the second SA fault candidates based on whether the detectable SA faults are detectable by simulation based on the SA fault model.

[0110] Specifically, the test pattern generation device 100 (e.g., SA ATPG module 120) can generate multiple test vectors for each of the second SA fault candidates based on the SA fault model. Subsequently, the test pattern generation device 100 (e.g., SA ATPG module 120) can perform a simulation applying each of the multiple test vectors to the modeled circuit. Based on the simulation results, the test pattern generation device 100 (e.g., SA ATPG module 120) can select at least one optimal test vector capable of detecting the actual SA fault. When the corresponding SA fault cannot be actually detected through simulation applying multiple test vectors to the corresponding SA fault candidate, the test pattern generation device 100 can determine the corresponding SA fault candidate as a potentially undetectable SA fault.

[0111] In an embodiment, the test pattern generation device 100 (e.g., SA ATPG module 120) can classify detectable SA faults in the second SA fault candidates as DT state (or category) and classify undetectable SA faults in the second SA fault candidates as UD state (or category). Here, DT can refer to a test pattern for which a corresponding fault candidate has been generated, and UD can refer to a test pattern for which a corresponding fault candidate cannot be generated.

[0112] In operation S137, the test mode generation device 100 (e.g., SA ATPG module 120) can generate an SA test mode based on a detectable SA fault.

[0113] Specifically, the test pattern generation device 100 (e.g., SA ATPG module 120) can generate SA test patterns by collecting test vectors selected for detectable SA faults in the second SA fault candidates and the predicted output patterns corresponding to the selected test vectors.

[0114] In other words, the TD test patterns generated by the test pattern generation device 100 (e.g., TD ATPG module 110) may include test patterns capable of detecting SA faults included in the PDFL. Furthermore, the SA test patterns generated by the test pattern generation device 100 (e.g., SAATPG module 120) may include test patterns for detectable SA faults in the second SA fault candidate, but may not include test patterns for SA faults included in the PDFL.

[0115] According to an embodiment, the test pattern generation device 100 can reduce the number of patterns required for testing by not generating SA test patterns for nodes (and / or paths) that generate TD test patterns.

[0116] In other words, according to the example embodiments of this disclosure, the test pattern generation device 100 can first generate a pattern (or TD test pattern) capable of detecting TD faults, and only generate SA test patterns for nodes (and / or paths) capable of detecting SA faults among nodes that do not correspond to TD faults, thereby preventing the repeated generation of test patterns. Accordingly, the number of test patterns required for testing can be reduced, and the simulation cycle of the ATPG module, which generates as many test patterns as the number of reduced test patterns, can be shortened.

[0117] Accordingly, according to the example embodiments of this disclosure, even if no test patterns are generated for all detectable SA faults, the test coverage based on test patterns generated for some SA faults and test patterns generated for TD faults according to the example embodiments of this disclosure can be similar to the test coverage based on test patterns for all SA faults and test patterns for TD faults.

[0118] Figure 9 A computing device 1000 for performing a test pattern generation method according to an example embodiment of the present disclosure is shown.

[0119] Figure 9 The computing device 1000 can correspond to the reference. Figures 1 to 8 The test pattern generation device 100 of one or more example embodiments described herein. Here, the computing device 1000 may also be referred to as a computing system.

[0120] Reference Figure 9 The computing device 1000 may include a processor 1100 and a memory 1200. Figure 9 A processor 1100 is shown, but this disclosure is not limited thereto, and the computing device 1000 may include multiple processors.

[0121] The processor 1100 may include one or more cores (not shown) and a GPU (not shown) and / or connection channels (e.g., buses, etc.) for sending signals to and receiving signals from other components.

[0122] Processor 1100 may execute references to one or more exemplary embodiments of the present disclosure. Figures 1 to 8 The described test pattern generation method operates as follows. For example, processor 1100 can generate test patterns for detecting CUT faults based on design data DESIGN DATA_CUT.

[0123] The processor 1100 may also include random access memory (RAM) and read-only memory (ROM) for temporary and / or permanent storage of signals (or data) processed in the processor 1100. Furthermore, the processor 1100 may be implemented as a system-on-a-chip (SoC) including at least one of a GPU, RAM, or ROM.

[0124] Memory 1200 may store programs (or one or more instructions) for processing and controlling processor 1100. Memory 1200 may include multiple modules in which the test pattern generation method according to an example embodiment of this disclosure is implemented. For example, memory 1200 may include references to... Figure 3 The TD ATPG module 110 and SA ATPG module 120 are described.

[0125] Figure 10 This is a block diagram illustrating a test system 2000 according to an example embodiment of the present disclosure.

[0126] Reference Figure 10 This document describes various structures of the test system 2000 or memory system according to embodiments, but the scope of this disclosure is not limited thereto. For ease of description, detailed descriptions of the above components will be omitted below.

[0127] Reference Figure 10 The test system 2000 may include a test pattern generation device 2100 and a cutout 2200. The cutout 2200 may include a test device 2210. That is, the test device 2210 may be implemented as a BIST circuit.

[0128] In this embodiment, test device 2210 may be an automated test device (ATE) for testing CUT 2200. Test device 2210 may receive test patterns for testing CUT 2200 from test pattern generation device 2100. Here, test pattern generation device 2100 may be based on reference to... Figures 1 to 9 The test pattern generation method described in one or more example embodiments generates test patterns.

[0129] According to the example embodiments, at least one of the components, elements, modules, or units (collectively referred to as "components" in this paragraph) indicated by blocks in the drawings can be embodied as various numbers of hardware, software, and / or firmware structures performing the corresponding functions described above. For example, at least one of these components can use direct circuit structures, such as memory, processor, logic circuits, lookup tables, etc., which can perform various functions under the control of one or more microprocessors or other control devices. Furthermore, at least one of these components can be specifically embodied as part of a module, program, or code containing one or more executable instructions for performing a specified logical function, and executed by one or more microprocessors or other control devices. Additionally, at least one of these components can include or be implemented by a processor (such as a central processing unit (CPU), microprocessor, etc.) performing the various functions. Two or more of these components can be combined into a single component, which performs all the operations or functions of the combined two or more components. Furthermore, at least a portion of the functionality of at least one of these components can be performed by another component. Moreover, although a bus is not shown in the above block diagrams, communication between components can be performed via a bus. The functional aspects of the above example embodiments can be implemented as algorithms executed on one or more processors. Furthermore, the components or processing steps represented by the boxes can utilize any number of related technologies for electronic configuration, signal processing and / or control, data processing, etc.

[0130] Although this disclosure has been specifically shown and described with reference to exemplary embodiments thereof, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method for generating test patterns executed by at least one processor, the method comprising: Obtain design data for the circuit under test (CUT); Based on the design data, a first test mode and a pre-detected fault list PDFL are generated for detecting conversion delay (TD) faults. The PDFL includes fixed-type SA faults, each SA fault corresponding to a detectable TD fault included in the detectable TD fault list and capable of being detected through simulation. Based on the design data and the PDFL, a second test mode is generated for detecting the SA fault. The generation of the second test mode includes: Based on the design data, a first SA fault candidate is generated for the modeling circuit of the CUT; Based on the PDFL and the first SA fault candidate, a second SA fault candidate is generated; and The second test mode is generated based on the second SA fault candidate.

2. The method according to claim 1, wherein, Each SA fault included in the PDFL is classified as an SA fault based on the fault type of each detectable TD fault included in the detectable TD fault list.

3. The method according to claim 2, wherein, Based on the fact that the fault type of each detectable TD fault in the detectable TD faults is a slowly rising STR fault, the fault type of the STR fault is reclassified as an SA0 fault, and Among them, based on the fault type of each detectable TD fault in the detectable TD faults being a slow-decreasing STF fault, the fault type of the STF fault is reclassified as SA1 fault.

4. The method according to claim 1, wherein, Generating the second SA fault candidate includes removing SA faults that are included in both the first SA fault candidate and the PDFL from the first SA fault candidate.

5. The method according to claim 1, wherein, Generating the second SA fault candidate includes classifying the SA faults included in the PDFL as detectable DT states in the first SA fault candidate.

6. The method according to claim 1, wherein, The second test mode includes a test mode for detectable SA faults in the second SA fault candidates, but does not include a test mode for the SA faults included in the PDFL.

7. The method according to claim 1, wherein, The first test mode includes a test mode capable of detecting the SA faults included in the PDFL.

8. A test pattern generation device, comprising at least one processor to implement: The Automatic Test Mode Generator (ATPG) module for Transition Delay (TD) is configured to: obtain design data about the circuit under test (CUT), and generate a first test mode and a pre-detection fault list (PDFL) based on the design data for detecting TD faults. The PDFL includes fixed SA faults, which correspond to detectable TD faults included in the list of detectable TD faults and can be detected by simulation. as well as The SA ATPG module is configured to generate a second test mode for detecting SA faults based on the design data and the PDFL. The SA ATPG module is configured to: when generating the second test mode, Based on the design data, a first SA fault candidate is generated for the modeling circuit of the CUT; Based on the PDFL and the first SA fault candidate, a second SA fault candidate is generated, and The second test mode is generated based on the second SA fault candidate.

9. The test pattern generation device according to claim 8, wherein, Each SA fault included in the PDFL is classified as an SA fault based on the fault type of each detectable TD fault in the detectable TD fault list.

10. The test pattern generation device according to claim 9, wherein, Based on the fact that the fault type of each detectable TD fault in the detectable TD faults is a slowly rising STR fault, the fault type of the STR fault is reclassified as an SA0 fault, and Based on the fact that the fault type of each detectable TD fault is a slow-decreasing STF fault, the fault type of the STF fault is reclassified as SA1 fault.

11. The test pattern generation device according to claim 8, wherein, The SA ATPG module is configured to generate a second SA fault candidate by removing SA faults included in both the first SA fault candidate and the PDFL from the first SA fault candidate.

12. The test pattern generation device according to claim 8, wherein, The SA ATPG module is configured to generate a second SA fault candidate by classifying the SA faults included in the PDFL as detectable DT states in the first SA fault candidate.

13. The test pattern generation device according to claim 8, wherein, The second test mode includes a test mode for detectable SA faults in the second SA fault candidates, but does not include a test mode for the SA faults included in the PDFL.

14. The test pattern generation device according to claim 8, wherein, The first test mode includes a test mode capable of detecting the SA faults included in the PDFL.

15. A system for testing a circuit under test (CUT) using a test mode, the system comprising: The test pattern generation device is configured to acquire design data about the CUT and generate test patterns. as well as The test equipment is configured to test the CUT using the test mode. The test pattern generation device includes at least one processor to implement: The Automatic Test Pattern Generator (ATPG) module for Converter Delay (TD) is configured to: generate a first test pattern and a pre-detected fault list (PDFL) for detecting TD faults based on the design data, wherein the PDFL includes fixed-type SA faults, each SA fault corresponding to a detectable TD fault included in the detectable TD fault list and capable of being detected through simulation; and The SA ATPG module is configured to generate a second test mode for detecting SA faults based on the design data and the PDFL. The SA ATPG module is configured to: when generating the second test mode, Based on the design data, a first SA fault candidate is generated for the modeling circuit of the CUT; Based on the PDFL and the first SA fault candidate, a second SA fault candidate is generated, and The second test mode is generated based on the second SA fault candidate.

16. The system according to claim 15, wherein, Each SA fault included in the PDFL is classified as an SA fault based on the fault type of each detectable TD fault in the detectable TD fault list.

17. The system according to claim 16, wherein, Based on the fact that the fault type of each detectable TD fault in the detectable TD faults is a slowly rising STR fault, the fault type of the STR fault is reclassified as an SA0 fault, and Based on the fact that the fault type of each detectable TD fault is a slow-decreasing STF fault, the fault type of the STF fault is reclassified as SA1 fault.

18. The system according to claim 15, wherein, The SA ATPG module is configured to generate a second SA fault candidate by removing SA faults included in both the first SA fault candidate and the PDFL from the first SA fault candidate.

19. The system according to claim 15, wherein, The SA ATPG module is configured to generate a second SA fault candidate by classifying the SA faults included in the PDFL as detectable DT states in the first SA fault candidate.

20. The system according to claim 15, wherein, The second test mode includes a test mode for detectable SA faults in the second SA fault candidates, but does not include a test mode for the SA faults included in the PDFL.

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