An evaluation device for a graph neural network-based FPGA interconnect architecture

Abstract

The disclosure provides an evaluation device of a FPGA interconnection architecture based on a graph neural network, which comprises: an input unit configured to obtain description information of a target FPGA architecture and corresponding timing report information; an intra-block graph construction unit configured to obtain corresponding wiring resource graphs and global features according to the description information conversion; a node frequency label extraction unit configured to obtain frequency information of critical path node occurrence according to the timing report information; and a prediction unit configured to obtain the routability and area delay product value of the target FPGA according to the obtained wiring resource graphs and global features and the frequency information of critical path node occurrence. The evaluation device provided in some embodiments of the disclosure can predict the routability and area delay product of the interconnection architecture through the GEF model, and significantly reduce the number of calls of the traditional evaluation tool.

Description

Technical Field

[0001] This disclosure relates to the field of chip design technology, and more specifically to an evaluation device for an FPGA interconnect architecture based on graph neural networks. Background Technology

[0002] FPGA interconnect architecture design space exploration is inefficient, primarily due to non-general-purpose parameterization methods and the high runtime overhead of traditional evaluation tools (such as VTR). Existing methods struggle to quickly and accurately predict the runnability and area-delay product of different interconnect architectures, leading to long design iteration cycles and a high risk of missing optimal solutions. Traditional statistical models cannot effectively capture the structural diversity and complexity of interconnect topologies.

[0003] Existing methods and approaches suffer from several technical limitations: for example, they rely on manual design or limited automation strategies (such as simulated annealing and Bayesian optimization), making them unsuitable for large-scale design spaces. Furthermore, existing machine learning methods (such as CNNs and random forests) only provide performance predictions for different circuits on fixed FPGA architectures, failing to address the issue of hardware architecture diversity.

[0004] Therefore, existing technologies still need to be improved and enhanced.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] To address at least one of the aforementioned problems, as well as one or more other potential problems, this disclosure proposes an evaluation apparatus for FPGA interconnect architectures based on graph neural networks (hereinafter referred to as GEF in some embodiments of this disclosure), which can predict the deployability and area-delay product of interconnect architectures through GEF models, significantly reducing the number of calls to traditional evaluation tools.

[0007] In a first aspect of this disclosure, an evaluation apparatus for an FPGA interconnect architecture based on a graph neural network is proposed, comprising: an input unit for acquiring description information and corresponding timing report information of a target FPGA architecture; an intra-block graph construction unit for acquiring a corresponding routing resource graph and global features based on the description information; a node frequency label extraction unit for calculating the frequency information of critical path nodes based on the timing report information; and a prediction unit for acquiring the routing availability and area-delay product values ​​of the target FPGA based on the acquired routing resource graph, global features, and the frequency information of critical path nodes.

[0008] Furthermore, in some embodiments, the above-mentioned intra-block graph construction unit is provided with an intra-block graph routing resource graph extractor for extracting routing resource graph information of the target FPGA architecture. The routing resource graph information includes node information, which includes connection relationship information between wires, pins, or MUXs.

[0009] Furthermore, in some embodiments, the above-mentioned node information is divided into wire in, wire out, pin in, pin out, and multiplexer out, wherein the above-mentioned wire in and the above-mentioned wire out are also provided with corresponding direction, scale, and relative coordinate information.

[0010] Furthermore, in some embodiments, the above-mentioned block diagram construction unit is also provided with a physical block pin structure extractor for extracting internal pins and connection information within the physical block of the target FPGA architecture.

[0011] Furthermore, in some embodiments, the above-mentioned block graph construction unit is provided with a global feature extractor for extracting global characteristics of the target FPGA architecture, including channel width, total number of multiplexers, and total number of wires of each length.

[0012] Furthermore, in some embodiments, the node frequency label extraction unit is configured to perform the following steps: extracting the critical path from the timing report; identifying the wiring resource graph nodes traversed by the critical path and mapping the wiring resource graph nodes to corresponding positions in the block graph; and counting the traversal of all nodes aggregated within the block.

[0013] Furthermore, in some embodiments, the prediction unit is provided with a deployability predictor based on a graph neural network. The deployability predictor is constructed to consist of multiple convolutional layers, each followed by an SAGPool layer, a ReLU activation function, and a readout layer for extracting graph-level information.

[0014] Furthermore, in some embodiments, the prediction unit is also provided with an area-delay product predictor, which is integrated with a node frequency head, a graph neural network module, and a multilayer perceptron module.

[0015] Furthermore, in some embodiments, the prediction unit is also provided with an area-delay product predictor, which is configured to: in the node embedding extraction stage, extract features layer by layer by stacking multiple graph convolutional layers and splicing them together to finally generate hierarchical information that simultaneously contains low-level and high-level feature representations.

[0016] Furthermore, in some embodiments, the area-delay product predictor is also configured to: extract a compact graph embedding through pooling operations as input to the final multilayer perceptron module for area-delay product prediction; and in the node frequency header module, use the multilayer perceptron module to predict the label of each node and output the routing delay value.

[0017] This disclosure has the following advantages over the prior art:

[0018] The Evaluation Apparatus (GEF) provided in some embodiments of this disclosure innovatively introduces intra-tile graph construction units to encode complex routing patterns in a compact form. This evaluation apparatus further integrates two types of predictors: Rou-P, which uses SAGPool for routing predictor capabilities, and ADP-P, which uses an intermediate supervision mechanism for ADP prediction. Experimental results show that Rou-P achieves a prediction accuracy of 94.56%, and ADP-P achieves an average accuracy of 94.57% on different datasets. In applications of FPGA routing architecture design space exploration (DSE) platforms, GEF improves exploration efficiency by more than 15 times and continuously optimizes architecture performance. Attached Figure Description

[0019] The above and other features, advantages and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description, wherein:

[0020] Figure 1 A schematic diagram of an evaluation apparatus for an FPGA interconnect architecture based on a graph neural network according to an embodiment of the present disclosure is shown.

[0021] Figure 2 A general schematic diagram of an evaluation apparatus for an FPGA interconnect architecture based on a graph neural network according to an embodiment of the present disclosure is shown.

[0022] Figure 3 A schematic diagram of data processing for an evaluation apparatus based on a graph neural network-based FPGA interconnect architecture according to an embodiment of the present disclosure is shown.

[0023] Figure 4 A schematic diagram showing the wire types and corresponding labels of an evaluation device for a graph neural network-based FPGA interconnect architecture according to an embodiment of the present disclosure is illustrated.

[0024] Figure 5 A detailed schematic diagram of a prediction unit in an evaluation apparatus for an FPGA interconnect architecture based on a graph neural network, according to an embodiment of the present disclosure, is shown.

[0025] Figure 6A schematic diagram comparing the VTR routing resource diagram and the in-block routing resource diagram of an evaluation device for an FPGA interconnect architecture based on a graph neural network according to an embodiment of the present disclosure during dataset construction is shown.

[0026] Figure 7 An example illustration of a pruning algorithm for GEF in the DSE process according to an embodiment of the present disclosure is shown;

[0027] Figure 8 An ADP improvement curve over time according to an embodiment of the present disclosure is shown; and

[0028] In the various figures, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0029] Embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the accompanying drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0030] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "this embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below. It should also be understood that the term "and / or" as used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0031] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0032] It should be noted that the tile in this disclosure may be referred to as a “slice” or “logic slice” in some embodiments; the routability in this disclosure may be referred to as wired or routable in some embodiments; it should be understood that the FPGA interconnect architecture evaluation device based on graph neural networks proposed in this disclosure may also have a corresponding FPGA interconnect architecture evaluation method based on graph neural networks; an FPGA interconnect architecture evaluation architecture based on graph neural networks, wherein the FPGA interconnect architecture evaluation architecture based on graph neural networks in this document may be abbreviated as GEF.

[0033] It should be understood that existing methods struggle to quickly and accurately predict the deployability and area-delay product of different interconnect architectures, leading to long design iteration cycles and a high risk of missing optimal solutions. Furthermore, traditional statistical models cannot effectively capture the structural diversity and complexity of interconnect topologies. Generally, the shortcomings of existing technologies are considered to be: 1) their reliance on manual design or limited automation strategies (such as simulated annealing and Bayesian optimization) makes them unsuitable for large-scale design spaces; 2) existing machine learning methods (such as CNNs and random forests) only provide performance predictions for different circuits on fixed FPGA architectures, failing to address the issue of hardware architecture diversity.

[0034] To address at least one of the aforementioned problems, as well as one or more other potential problems, this disclosure proposes an evaluation device for FPGA interconnect architectures based on graph neural networks, which can predict the deployability and area-delay product of the interconnect architecture through a GEF model, significantly reducing the number of calls to traditional evaluation tools.

[0035] The following explanation, in conjunction with the accompanying drawings, will provide further details.

[0036] Figure 1 A schematic diagram of an evaluation apparatus for a graph neural network-based FPGA interconnect architecture according to an embodiment of the present disclosure is shown; and Figure 2 A general schematic diagram of an evaluation apparatus for an FPGA interconnect architecture based on a graph neural network according to an embodiment of the present disclosure is shown. See also Figure 1 and Figure 2 An example embodiment illustrates a schematic diagram of the overall framework of a graph neural network (GNN)-based evaluation device, the GEF model, in particular, as shown in... Figure 2As shown, the evaluation device presents an end-to-end framework that takes an FPGA architecture description file as input and directly outputs an evaluation. The GEF primarily comprises an intra-block graph construction unit, a node frequency label extraction unit, and two GNN-based predictors, named Rou-P and ADP-P, respectively. To aid understanding of this disclosure, the training and inference workflows are outlined here. The first process, training: The raw data consists of an FPGA architecture description file and its implementation results generated by VPR on various benchmarks. To compress the large amount of routing information and efficiently extract key connectivity features, this disclosure introduces a novel IR, namely, intra-block graphs. During data preprocessing, the intra-block graph construction unit converts the architecture description file into a graphical representation, while the node frequency label extraction unit derives node-level labels from the time-series report to aid in time-series prediction. Furthermore, the implementation results provide graphical-level labels, including routable and ADP. Through this process, this disclosure constructs the Rou-P and ADP-P datasets. Using these datasets, routable prediction is modeled as a binary classification task (1 indicates routable, 0 indicates unroutable), while ADP prediction is represented as a regression task. Notably, ADP-P can be further enhanced through the Node Frequency Header (NFH). It applies element-wise multiplication between node embeddings and node delay features, enhancing the learning of routing delays. Furthermore, an intermediate supervision mechanism is integrated, utilizing auxiliary labels extracted by the node frequency extractor to further guide the learning process. The second process, inference, handles the FPGA architecture, which is not previously visible. Similarly, these architectures are first converted into intra-block graphs and fed into Rou-P and ADP-P as inputs. Then, the predictor generates deployability and ADP predictions as evaluation metrics for a given architecture device.

[0037] Figure 3 A schematic diagram of data processing for an evaluation apparatus based on a graph neural network-based FPGA interconnect architecture, according to an embodiment of the present disclosure, is shown. Figure 3As shown, the data preprocessing workflow mainly consists of two units (components): an intra-block graph construction unit and a node frequency tag extraction unit. In some embodiments, regarding the intra-block graph construction unit, it should be understood that traditional evaluation tools (e.g., VTR) use routing resource graphs (RRGs) to describe the FPGA routing structure in detail. However, for modern large-scale FPGAs, this graph structure may be too large for subsequent processing and lacks sufficient granularity in distinguishing different pins. To address these limitations, this disclosure proposes an intra-block graph construction unit and three corresponding dedicated extractors: an intra-block graph routing resource graph (RRG) extractor, a physical block pin (PB) structure extractor, and a global feature (e.g., including channel width) extractor. These extractors respectively acquire functions related to routing patterns, physical block pins, and the overall FPGA architecture. The following examples provide a more specific explanation: 1) Intra-block graph routing resource graph (RRG) extractor: Here, the input architecture description file can be represented as χ. The intra-block graph routing resource graph (RRG) extractor extracts the graph structure, represented as G. R = (N, ε), where N is the set of nodes and ε is the set of edges. Each node N ∈ N represents a connection between wires, pins, or MUXs. Each edge E = {N...} i N j}∈ε represents node N i and N j Possible connections between nodes via programmable switchers. It should be noted that each node N∈N is associated with two fundamental attributes: type and delay. The type of the node (denoted as T) N This is categorized into one of the following: WireIn, WireOut, Opin, Ipin, and Medium. Specifically, WireIn or WireOut represents the wire entering or leaving the tile, respectively, and Medium represents the MUX output. Additionally, delay (denoted as D) N The attribute represents the latency of the driver multiplexer (MUX) of node N.

[0038] It should also be understood that, given that the above embodiments analyze an intra-block range, critical wire patterns, such as length and bending characteristics, may be overlooked. To address this limitation, corresponding embodiments propose additional specific attributes for WireIn and WireOut, including orientation, scale, and relative coordinates. Figure 4 As shown, further details are provided: 1) The FPGA architecture is modeled as a two-dimensional mesh, where each tile is assigned a unique coordinate (x, y). The current tile serves as a reference point, with the positive x-axis aligned with the east (E) direction and the positive y-axis aligned with the north (N) direction; 2) Orientation feature d NSpecify the transmission direction of the conductor, where d N ∈{E, S, W, N} (i.e., East, South, West, North); 3) Proportional characteristics P N This quantifies the relative importance of each conductor within the cabling architecture, which can be defined as the total number of conductors of length L divided by the channel width, i.e., P. N =Number of wires of length L / Channel width; 4) Relative coordinate characteristics △ N This represents the spatial relationship between a conductor and the tile it connects to. Correspondingly, it's also necessary to understand the relevant formula: △ N ={(x src , y src ), (x dest , y dest )}; where the former (x src , y src ) represents the coordinates of the source tile from which the wire originates, while the latter (x) dest , y dest ) indicates the coordinates of the target tile to which the wire points; 5) Furthermore, the delay of the wire is the sum of the delay driving the MUX and the propagation delay of the wire itself. For example, taking the wire marked E3.out as an example, Figure 4 As shown. The wire originates from the reference tile, extends eastward, bends counterclockwise at the first node, and spans a total length of 2; at this point, the relative coordinates of the wire are ΔE3.out = {(0, 0), (1, 1)}. Through these specific properties, the granularity represented by the wire within the tile is significantly improved. In summary, for the generated graph G... R For each node N∈N, the node feature F R It can be defined as a tuple: F R N = (T N D N , d N , P N ,△ N ).

[0039] In some embodiments, this disclosure also proposes a physical block pin (PB) structure extractor. This physical block pin (PB) structure extractor is based on the aforementioned G... R The PB structure extractor contains internal pins and connections within the physical block. The resulting diagram (denoted as G) P The following relation is satisfied: G P =G R ∪(N pb , ε pb ); where N pb and ε pbThese represent internal nodes (e.g., lookup table (LUT) outputs, trigger (FF) ports) and internal connections (e.g., pin links, LUT-FF paths). For combinational logic like LUTs, their inputs are connected to G. P The output in the code annotates the propagation delay. Conversely, sequential elements such as FF define the boundaries of timing paths: the D port of an FF marks the end, while the Q port indicates the start. Additionally, in some embodiments, a hierarchical feature H is defined, representing the physical module to which a pin or port belongs; thus, the node feature can be updated to: F P N = F R N ∪H. It should be noted that in some embodiments, the addition of a physical block pin (PB) structure extractor results in an approximately 4% improvement in the area delay product prediction accuracy.

[0040] In some embodiments, this disclosure also proposes a global feature extractor. The global feature in this global feature extractor (denoted as F) G This provides a representation of the entire hardware. Specifically, there can be F... G =(CW, Num mux Num wire, l ), where the components represent the channel width, the total number of multiplexers, and the total number of wires of each length.

[0041] Furthermore, in this embodiment of the disclosure, the block graph construction unit is interpreted using a function, for example, expressed as Φ. C Its formula satisfies the following relationship: Φ C : χ → {G P , F G}; where G P (Referred to as an intra-block graph) captures the internal structure.

[0042] It should be understood that, compared to traditional Route Resource Graph (RRG)-based representations or parametric descriptions of specific architectures, the intra-block graph approach exhibits the following three advantages: 1) Compactness: Intra-block graphs extract the internal architecture of only a few blocks, eliminating the redundancy inherent in RRG-based representations. For FPGAs with a 50×50 layout, this method reduces the number of nodes by approximately three orders of magnitude. 2) Completeness: Intra-block graphs more faithfully preserve the original architecture description and enrich pin features by incorporating structures into physical blocks. 3) Universality: Unlike parametric descriptions of specific architectures, intra-block graphs are applicable to all modern logically blocky architectures, thus serving as a more general and scalable representation.

[0043] In some embodiments, this disclosure also proposes a node frequency extraction unit (in some embodiments, it is also referred to as a node frequency tag extraction unit). Figure 3 In the example embodiment, a node frequency extraction unit Φ is shown. F The workflow, which can be formalized as a mapping: Φ F :{ χ, τ}→ λ; For a given time series report τ, first extract the critical path P. Then, identify the RRG nodes traversed by this path and map them to their corresponding positions in the block graph. Finally, aggregate the node traversal counts across all blocks.

[0044] It should be understood that node N i Frequency label λ i Defined as the number of times a node's latency accumulates on the critical path, its relationship is expressed as: ;where P (t) Let λ represent the t-th intra-block node in the critical path resolved from τ, where T is the path length. The resulting λ is used as the absolute ground truth for Node Frequency Prediction (NFH) training to capture the contribution of each node to the critical path latency.

[0045] Furthermore, in some other embodiments of this disclosure, a prediction unit is also proposed, which further includes a routability predictor (Rou-P) and an area-delay product predictor (ADP-P). In some embodiments, a GNN-based routability predictor (Rou-P) is proposed; it should be understood that in other embodiments, routability is also referred to as routableness. Figure 5 As shown, the Rou-P (Robustibility Predictor) architecture consists of multiple convolutional layers, each followed by a SAGPool layer, a ReLU activation function, and a readout layer for extracting graph-level information. It should be understood that the multi-level graph convolutional layers extract local features; each convolutional layer is followed by a SAGPool layer (self-attention graph pooling) for hierarchical node sampling; the ReLU activation function introduces non-linearity; and a global readout layer is set at the end to generate graph-level representations through mean pooling. The hierarchical readout results are integrated into graph embeddings and further aggregated with global features. The final aggregated vector is then subjected to binary classification using a fully connected multilayer perceptron (MLP) with a sigmoid activation function and optimized using the binary cross-entropy (BCE) loss function.

[0046] In some embodiments, an area-delayed product predictor (ADP-P) is proposed. Figure 5 The structure of ADP-P is shown, which integrates NFH, GNN, and MLP. In the node embedding extraction stage, multiple graph convolutional layers are stacked to extract features layer by layer and concatenate them, ultimately generating hierarchical information containing both low-level and high-level feature representations. Subsequently, the utilization of node embeddings is divided into two stages: (i) Graph embedding generation: compact graph embeddings are extracted through pooling operations and used as input to the final MLP for ADP prediction; (ii) Node-level prediction: in the NFH module, the MLP is used to predict the labels of each node and output the routing delay value, which is also used as input to the final MLP. It is worth noting that node label prediction is treated as an auxiliary task during training (corresponding to...). Figure 5 (Intermediate supervision mechanism in the model). NFH, by predicting the traversal frequency of nodes in the critical path, acts as an auxiliary component to prevent gradient vanishing and accelerate model convergence. For ADP prediction, area-related key features are included in the global features, while NFH emphasizes delay-related features. In time series analysis, the critical path delay satisfies the relationship: τ critical =τ logic + ; where τ logic This represents the delay from combinational logic, while λ i and D i These represent the nodes N traversed. i The frequency and latency of the nodes are considered. NFH uses an MLP to transform node embeddings into frequency predictions as an intermediate objective for model training. The total loss function consists of two components: one for graph-level ADP prediction error and the other for auxiliary node frequency prediction loss. Optimizing these two components using mean squared error (MSE) satisfies the following relationship:

[0047] ,

[0048] Furthermore, some embodiments of this disclosure are explained through experimental methods. For example, a set of more than 1500 different FPGA architectures, spanning a wide range of routing modes, were first generated, wherein the parameters used to generate the dataset ranged from 120 to 300; the wire length from 1 to 12; and the number of each wire type from 0 to 40; F CThe values ​​range from 0.1 to 0.5; the MUX topology is a hybrid level; the SB modes include general mode, Wilton mode, discontinuous mode, GRB mode, and VIB mode. Then, circuit designs were implemented from the VTR standard benchmark suite using the VTR tool, and the deployability and area-delay product results of these architectures were evaluated. It is worth noting that the deployability evaluation was based on the complete benchmark suite. An architecture was considered deployable only if all circuit designs could be successfully deployed on it. Therefore, one dataset for evaluating deployability and 18 datasets for ADP prediction were obtained, each ADP dataset corresponding to a specific circuit design. Furthermore, based on the constructed datasets, five cross-validations were implemented to rigorously evaluate the accuracy of the model. Furthermore, the model hyperparameters were systematically explored using a grid search method. Specific parameter ranges are as follows: learning rate 1e-3, 5e-3, 1e-4, 5e-4, 1e-5; hidden layer scale 64, 128, 256; weight decay 1e-3, 1e-4, 1e-5; pooling ratio 1 / 2, 1 / 4; number of network layers 2, 3, 4; convolution types: Graph Convolutional Network (GCN), Graph Attention Network (GAT), and Graph Sampling and Aggregation Network (SAGE). All experiments were performed on a 20-core Intel Xeon Platinum 8354H CPU.

[0049] Furthermore, regarding the accuracy evaluation of the Rou-P (Rou-P) predictor. Rou-P is a binary classification problem with labels 0 / 1, and the ratio of samples from each class in the dataset is 2:1. To comprehensively evaluate the performance of the Rou-P model, we use precision, recall, and F1 score as evaluation metrics. These satisfy the following relationship:

[0050] ; ; Where TP (True Positives) represents the number of architectures correctly predicted as routable, FP (False Positives) represents the number of architectures incorrectly predicted as routable, and FN (False Negatives) represents the number of architectures incorrectly predicted as unroutable. The optimal hyperparameter combination optimized for F1 score achieved a remarkable 94.56% F1 score, with precision reaching 92.18% and recall reaching 97.06%. The optimal hyperparameter combination and experimental results for the Rou-P model are as follows: 3 network layers; SAGE convolution type; test precision of 92.18%; test recall of 97.06%; test F1 score of 94.56%. These results demonstrate that the model effectively filters out unroutable designs, minimizes unnecessary VTR tool calls and time waste, while ensuring that almost all routable architectures are identified.

[0051] Furthermore, comparative analysis of the Area Delayed Product Predictor (ADP-P) is conducted, using metrics such as correlation coefficient (R), coefficient of determination (R²), and mean absolute percentage error (MAPE) to evaluate the prediction accuracy between the predicted value y' and the true value y. Further, according to the benchmark tests published by VTR, the accuracy of ADP-P can be obtained, with R, R², and MAPE values ​​of 0.90, 0.81, and 5.43%, respectively. Using 1-MAPE as the evaluation metric, the accuracy of ADP-P reaches 94.57%. To analyze the superior performance of ADP-P, ablation experiments can be conducted by removing key strategies. The core strategies of ADP-P include: 1) intra-block RRG extractor; 2) PB structure extractor; 3) Graph Neural Network (GNN); 4) Intermediate supervision and NFH. Benchmark tests also provide ablation experiment results. Further, 1) Removing the intra-block RRG extractor: To verify the compactness of the intra-chip RRG extractor, datasets can be constructed using both complete RRGs and intra-chip RRGs. like Figure 6 As shown, the comparison between RRG and in-block RRG in dataset construction demonstrates that the in-block RRG dataset achieves a two-order-of-magnitude reduction in both size and construction time, thus accelerating GEF prediction. In contrast, the dataset constructed using the full RRG exceeds memory limits during training, leading to… Figure 6Detailed prediction accuracy results cannot be displayed. Further, 2) Removing the PB structure extractor: Removing this module resulted in a 2% and 4% decrease in R and R², respectively, indicating its important role in maintaining ADP-P accuracy. For example, for circuits like mkDelayWorker32B, the change in prediction accuracy was minimal because routing delay accounts for more than 75% of the total critical path delay, thus weakening the impact of prediction errors within the PB. Further, 3) Removing the GNN: Compared to the case without GNN, ADP-P's R² improved by 59%, highlighting the significant contribution of GNN to prediction performance. Further, 4) Removing the NFH: After removing NFH, R and R² decreased by 6% and 12%, respectively, confirming the crucial role of NFH and intermediate supervision in improving prediction performance. For boundtop and stereovision3, the prediction accuracy differed little from ADP-P. This is because the high connectivity of I / O blocks in boundtop leads to significant differences in the critical path across different architectures, while the dual-clock design of stereovision3 increases the complexity of node frequency prediction. The scatter plot can visually display the prediction results of ADP-P, and the results show that the predicted values ​​are completely consistent with the actual values, intuitively presenting the strong correlation under multiple architectures.

[0052] Furthermore, in some embodiments, the application of GEF in FPGA routing architecture design space exploration (DSE) is discussed. To verify the specific acceleration effect of GEF in FPGA routing architecture design space exploration (DSE), we reproduced the GRAEBO experimental platform and conducted a series of comparative experiments by integrating two different predictors to evaluate the performance advantage of the prediction model. The experimental scheme specifically includes: 1) a conventional DSE process based on VTR evaluation; 2) using Rou-P to predict unroutable architectures and pruning them, skipping VTR evaluation; 3) a complete process where GEF completely replaces VTR. The traditional CB-SB architecture is used as the comparison baseline. The application process of GEF in DSE is as follows: Figure 7 As shown in the algorithm example, a pruning strategy is used to accelerate the process. The input parameters are the current iteration number (Iter) and the newly generated architecture (new_arch). First, GEF predicts the routability of the architecture. pred ) and ADP value (ADP pred (line 1). If Routable predIf the result is False, a failure status is returned directly to the DSE engine (line 5), assigning a larger loss value to characterize performance degradation. For wired architectures, a threshold is designed to determine whether the ADP value is close to the optimal solution of the current iteration (line 3). To reduce the impact of prediction error, architectures that meet the threshold still need to be accurately evaluated through the VTR process (line 10). It is worth noting that the initial threshold is set to a negative value (threshold0 < 0) and gradually decays with iterations (i.e., the absolute value increases). This design aims to balance the trade-off between DSE convergence speed and the final architecture performance.

[0053] also, Figure 8 The graph illustrates the trend of ADP improvement rate over time for the optimal architecture of DSE search. The curves show that exploration using GEF achieves significant ADP improvements in a very short time; while the DSE process using only Rou-P has limited acceleration. Notably, GEF achieves a 38% ADP improvement within 4 hours, while the traditional framework takes 60 hours to achieve the same result, demonstrating that GEF's speedup exceeds 15 times.

[0054] In summary, this disclosure presents an FPGA routing architecture design space exploration (DSE) prediction evaluation device (GEF) based on graph neural networks. This evaluation device (GEF) innovatively introduces an intermediate representation called Intra-Tile Graph to encode complex routing patterns in a compact form. The evaluation device further integrates two types of predictors: Rou-P, which uses SAGPool for routing architecture prediction, and ADP-P, which uses an intermediate supervision mechanism for ADP prediction. Experimental results show that Rou-P achieves a prediction accuracy of 94.56%; ADP-P achieves an average accuracy of 94.57% on different datasets; and in the application of FPGA routing architecture design space exploration (DSE) platforms, GEF improves exploration efficiency by more than 15 times and continuously optimizes architecture performance.

[0055] Furthermore, according to embodiments of this disclosure, an electronic device is also provided, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the method used by the evaluation apparatus as described above.

[0056] Additionally, according to embodiments of this disclosure, a computer-readable storage medium is provided that stores a computer program thereon, wherein the computer program, when executed by a processor, implements the steps of the method used by the evaluation apparatus as described above.

[0057] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0058] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. An evaluation device for an FPGA interconnect architecture based on graph neural networks, characterized in that, include: The input unit is used to obtain the description information of the target FPGA architecture and the corresponding timing report information; The block-intragraph graph construction unit is used to obtain the corresponding wiring resource graph and global features based on the description information. The node frequency label extraction unit is used to statistically analyze the frequency information of critical path nodes based on the time series report information. The prediction unit is used to obtain the routing availability and area delay product values ​​of the target FPGA based on the acquired routing resource map, global features, and frequency information of critical path nodes.

2. The evaluation device according to claim 1, characterized in that, The block graph construction unit is equipped with a block graph routing resource graph extractor for extracting routing resource graph information of the target FPGA architecture. The routing resource graph information includes node information, which includes connection relationship information between wires, pins, or MUXs.

3. The evaluation apparatus according to claim 2, characterized in that, The node information is divided into wire in, wire out, pin in, pin out, and multiplexer out, wherein the wire in and the wire out are also set with corresponding direction, scale and relative coordinate information.

4. The evaluation apparatus according to claim 1, characterized in that, The block diagram construction unit is also equipped with a physical block pin structure extractor, which is used to extract the internal pins and connection information within the physical blocks of the target FPGA architecture.

5. The evaluation apparatus according to claim 1, characterized in that, The block graph construction unit is equipped with a global feature extractor for extracting global characteristics of the target FPGA architecture, including channel width, total number of multiplexers, and total number of wires of each length.

6. The evaluation apparatus according to claim 1, characterized in that, The node frequency tag extraction unit is configured to perform the following steps: Extract the key paths from the time-series report; Identify the routing resource graph nodes traversed by the critical path and map the routing resource graph nodes to the corresponding positions in the block graph; Count the number of nodes that are aggregated within the block.

7. The evaluation apparatus according to claim 1, characterized in that, The prediction unit is equipped with a deployability predictor based on a graph neural network. The deployability predictor is constructed to consist of multiple convolutional layers, each followed by an SAGPool layer, a ReLU activation function, and a readout layer for extracting graph-level information.

8. The evaluation apparatus according to claim 7, characterized in that, The prediction unit is also equipped with an area delay product predictor, which integrates a node frequency head, a graph neural network module, and a multilayer perceptron module.

9. The evaluation apparatus according to claim 8, characterized in that, The prediction unit is further provided with an area-delayed product predictor, which is configured to: In the node embedding extraction stage, multiple graph convolutional layers are stacked to extract features layer by layer and then concatenate them to generate hierarchical information that contains both low-level and high-level feature representations.

10. The evaluation apparatus according to claim 9, characterized in that, The area-delayed product predictor is also configured to: Compact graph embeddings are extracted through pooling operations and used as input to the final multilayer perceptron module for area-delay product prediction. In the node frequency header module, a multilayer perceptron module is used to predict the label of each node and output the routing delay value.

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