LDPC (Low Density Parity Check) code check matrix construction method, encoder, transceiving end and experimental system

Abstract

The invention discloses an LDPC (Low Density Parity Check) code check matrix construction method, which is used for processing a low earth orbit satellite ground foundation zone, and comprises the following steps of: A1, determining degree distribution of a basis matrix under a high code rate by adopting an extrinsic information transfer graph EXIT, and realizing construction of the basis matrix under the constraint of optimal degree distribution through extrinsic information transfer P-EXIT based on a basic model graph; a2, based on the code length and the code rate of FEC coding of the DVB-S2 protocol, determining the size and the expansion factor of a basis matrix corresponding to each code rate; a3, determining a finite field and a generator based on an expansion factor, and constructing a linearly independent shift value row vector and cycle coefficient table; a4, selecting row vectors from the cyclic coefficient table to construct a cyclic shift matrix, and performing short ring identification and elimination on the cyclic shift matrix; and A5, performing matrix hashing on the basis of the basis matrix and the cyclic shift matrix to obtain an LDPC check matrix.

Description

Technical Field

[0001] This disclosure belongs to the technical field of satellite communication technology, and specifically relates to a method for constructing an LDPC check matrix suitable for low-Earth orbit satellite ground-based band, as well as its encoder, transceiver, and experimental system. Background Technology

[0002] In recent years, satellite communication technology has developed rapidly and is becoming an important pillar of the global communications field. With the accelerated deployment and commercial operation of low-Earth orbit satellite constellations, satellite communication not only fills the coverage gaps of traditional terrestrial networks, but also demonstrates irreplaceable value in remote areas, oceans, aviation and other scenarios.

[0003] Currently, low-Earth orbit (LEO) satellite communication systems widely adopt DVB-S2 (Digital Video Broadcasting - Satellite - Second Generation) as their baseband protocol standard, and it has been widely used in scenarios such as high-definition television broadcasting and broadband internet access. The DVB-S2 protocol was officially released by the European Telecommunications Standards Institute (ETS) in 2005, aiming to improve the spectral efficiency and data transmission rate of satellite communications. This protocol employs a concatenated coding structure, using LDPC (Low-Density Parity-Check) codes with high error correction capabilities as the primary code, supplemented by BCH (Bose–Chaudhuri–Hocquenghem) codes as outer codes for enhanced error correction. LDPC codes are linear block codes approaching the Shannon limit, constructed through a sparse parity-check matrix, possessing excellent error correction performance and good parallel decoding characteristics, making them particularly suitable for high-throughput hardware implementations. In the DVB-S2 protocol, LDPC codes, combined with adaptive modulation and coding mechanisms (ACM), significantly improve the system's robustness and transmission efficiency under varying channel conditions, becoming a key core technology in modern satellite communication systems.

[0004] As satellite communication evolves towards high throughput and low latency, the coding schemes in low-Earth orbit satellite-to-ground baseband systems based on the DVB-S2 standard suffer from the following shortcomings: In terms of coding performance, the short loop structure in the matrix leads to decreased decoding convergence, especially in low signal-to-noise ratio environments where significant error leveling occurs. Furthermore, the complex encoding and decoding process of concatenated codes results in significant processing latency and low decoding throughput. With the continuous increase in transmitted data volume and transmission rate, these shortcomings will have a certain impact on applications with high real-time requirements. Therefore, a LDPC code is needed that is compatible with existing baseband protocol standards while possessing better error correction coding performance and lower complexity.

[0005] In terms of hardware implementation, Field Programmable Gate Arrays (FPGAs) have been widely used in the hardware implementation of low-Earth orbit satellite ground-to-ground baseband systems due to their outstanding performance in high-throughput data processing and real-time parallel computing. However, the hardware resources on satellites (such as memory units, logic gates, etc.) are very limited. The encoding and decoding module usually accounts for about one-third of the power consumption of the baseband RF chip. Therefore, designing an encoder with low complexity and high throughput is crucial for the overall energy efficiency and performance of the satellite baseband system. Summary of the Invention

[0006] This disclosure proposes a method for constructing an LDPC parity-check matrix and an encoder applicable to low-Earth orbit (LEO) satellite-to-ground baseband systems. The method designs the base matrix based on EXIT and PEXIT, determines the sub-block size and spread factor using the code length and code rate of the DVB-S2 protocol, generates a linearly independent cyclic coefficient table using finite fields, constructs a cyclic shift matrix, optimizes the short-loop structure, and forms the final parity-check matrix through matrix hashing. The encoder uses random access memory (RAM) instead of a barrel shift register to implement cyclic shift operations, simplifying the complex large-bit-width register shift process to address-based RAM reading, including information bit serial-to-parallel conversion, cyclic shift address storage, message storage, parity bit calculation and buffering, codeword parallel-to-serial conversion, and a control module. This invention redesigns and optimizes the LDPC parity-check matrix in the DVB-S2 standard and implements a high-efficiency LDPC encoder, suitable for LEO satellite-to-ground baseband physical layer design based on the DVB-S2 standard.

[0007] This disclosure improves the transmission robustness and throughput of low-Earth orbit satellite baseband systems. It redesigns and optimizes the LDPC coding in the DVB-S2 standard and implements a high-efficiency LDPC encoder, solving key problems such as short code performance, multi-code rate adaptation and complexity balance in satellite communication, and providing technical support for the design of the physical layer of low-Earth orbit satellite ground-based baseband based on the DVB-S2 standard. Attached Figure Description

[0008] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of the invention are illustrated in the drawings by way of example and not limitation, wherein:

[0009] Figure 1 The LDPC check matrix structure diagram according to one embodiment of this disclosure.

[0010] Figure 2 A flowchart for constructing an LDPC check matrix according to one embodiment of this disclosure.

[0011] Figure 3A 4 / 5 bitrate LDPC check matrix diagram according to one embodiment of the present disclosure for the DVB-S2 standard.

[0012] Figure 4 A 4 / 5 code rate LDPC check matrix diagram constructed according to one embodiment of the present disclosure.

[0013] Figure 5 An end-to-end LDPC performance simulation experiment system architecture diagram according to one of the embodiments of this disclosure.

[0014] Figure 6 A comparison chart of LDPC code frame error rate performance at different code rates according to one of the embodiments of this disclosure.

[0015] Figure 7 A comparison chart of LDPC code error rate performance at different code rates according to one of the embodiments of this disclosure.

[0016] Figure 8 A hardware architecture diagram of an LDPC encoder according to one embodiment of this disclosure.

[0017] Figure 9 A diagram showing the file content read by the LDPC encoder cyclic shift address storage module according to one embodiment of this disclosure.

[0018] Figure 10 Timing simulation waveform diagram of LDPC encoder according to one embodiment of this disclosure Detailed Implementation

[0019] This disclosure studies existing solutions for low-Earth orbit satellite ground-based LDPC encoders. Patent document CN120185622A discloses an LDPC encoder based on the DVB-S2 protocol, but this encoder still has the following shortcomings and limitations:

[0020] This paper directly uses the original parity-check matrix defined in the DVB-S2 standard for coding design. Although the scheme meets the specification requirements at the protocol level, the parity-check matrix structure used is not optimized for the actual application scenarios of low-Earth orbit satellite communication, such as strong link dynamics, complex channel conditions, and high bit error rate. This results in a large number of short loops in the matrix, which is not conducive to the convergence of the decoding algorithm and the performance of error correction, thus limiting the bit error performance and robustness of the overall baseband system.

[0021] Furthermore, this paper requires additional preprocessing of the original strip-structured LDPC parity-check matrix of the DVB-S2 standard during encoding, including rearrangement and index extraction, to convert it into a quasi-cyclic structure before encoding. This process introduces additional complex control logic and burdens the encoder's hardware implementation, limiting its throughput. During parity bit calculation, this paper uses a traditional barrel register to implement the cyclic shift operation. This method consumes a large amount of lookup table (LUT) resources under conditions of large code length and high parallelism, increasing hardware logic resource overhead.

[0022] To address key issues in existing solutions, such as short code performance, multi-rate adaptation, and hardware implementation complexity, this disclosure redesigns and optimizes the LDPC encoding in the DVB-S2 standard and implements a high-efficiency LDPC encoder, providing technical support for the design of the ground-based physical layer for low-Earth orbit satellites based on the DVB-S2 standard.

[0023] To make the objectives and implementation methods of this disclosure clearer, the exemplary embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings of the exemplary embodiments thereof.

[0024] According to one or more embodiments, a method for constructing an LDPC parity-check matrix suitable for low-Earth orbit satellite ground-based networks uses a rapid tornado code (Raptor) structure for base matrix design. It employs external information transfer graph (EXIT) technology and a basis graph-based external information transfer (P-EXIT) technology to optimize the decoding threshold; it uses an algebraic method to design the cyclic coefficient table, and then uses loop analysis technology to design the cyclic shift matrix to optimize the error plane; based on the designed core matrix, it implements a fixed codeword length multi-rate encoding scheme conforming to the DVB-S2 standard through puncturing and shortening operations. The construction process of the LDPC parity-check matrix construction method includes the following steps:

[0025] Step 1: Use EXIT technology to determine the degree distribution of the basis matrix at high bitrate, and then use the P-EXIT algorithm to jointly design the core part and its extended part of the basis matrix under the constraint of optimal degree distribution;

[0026] Step 2: Determine the size of the base matrix submatrix and the spread factor for each code rate based on the code length and code rate of the DVB-S2 protocol FEC encoding;

[0027] Step 3: Determine the finite field and generator based on the extension factor, and construct a linearly independent row vector of shift values ​​and a table of cyclic coefficients;

[0028] Step 4: Select row vectors from the cyclic coefficient table to construct a cyclic shift matrix, and perform short-cycle identification and elimination on the cyclic shift matrix;

[0029] Step 5: Perform matrix hashing based on the base matrix and the cyclic shift matrix to obtain the final LDPC parity check matrix;

[0030] The construction process of the basis matrix includes:

[0031] The EXIT curve is initialized to have a precision T of positive infinity, and the signal-to-noise ratio R is also initialized to positive infinity.

[0032] Iterate through all degree distribution combinations of variable nodes (VN) and check nodes (CN). For each VN and CN degree distribution combination, iterate through a series of different signal-to-noise ratio (SNR) values ​​and calculate the input-output information entropy of the variable nodes and check nodes. Use the information entropy relationship to fit two curves of the EXIT graph.

[0033] Calculate the fitting accuracy T, update the current optimal signal-to-noise ratio, construct the basis matrix based on the degree distribution when the signal-to-noise ratio is optimal, and further filter out the high-bitrate LDPC basis matrix with optimal performance using the P-EXIT method;

[0034] Traverse each row of the extension region matrix, explore all possible design combinations, combine the high bitrate portion of the base matrix with the extension matrix, and fill the identity matrix portion. Use the P-EXIT method to evaluate the performance of different combinations and select the optimal solution.

[0035] Furthermore, according to the DVB-S2 protocol, the bit rate R, information bit length k, and frame length n, the number of columns in the base matrix submatrix n_b = ⌈k_b / R⌉, the number of rows m_b = n_b-22, where k_b = 22; the spread factor Z is the smallest prime number greater than ⌈16200 / n_b⌉ minus one.

[0036] Furthermore, for a given expansion factor Z, the construction process of the cyclic coefficient table includes setting a finite field GF(q), where q is the smallest prime number greater than Z, and obtaining the generator α of GF(q);

[0037] Two subsets of the finite field GF(q) are obtained by raising α to a power, and the elements of the subsets are used to obtain a table of cycle coefficients through polynomial operations;

[0038] In a cyclic coefficient table, each row or column element is distinct from the next, and the cyclic coefficient matrix constructed from the cyclic coefficient table does not contain a four-ring.

[0039] The construction process of the cyclic shift matrix includes:

[0040] For a given expansion factor Z, extract the submatrix used from the basis matrix BG1;

[0041] Select row vectors from the cycle coefficient table to fill the submatrix, minimizing the number of four-ring and six-ring matrices.

[0042] Each -1 element in the submatrix is ​​expanded into a Z*Z matrix of all zeros, where Z represents the expansion factor;

[0043] Each zero element in the submatrix is ​​expanded into a Z*Z identity matrix;

[0044] For each element in the submatrix except for the -1 element and the zero element, perform the following operation: expand it into a cyclic permutation matrix according to the value P of the element. The corresponding cyclic permutation matrix is ​​a Z*Z identity matrix with each row cyclically shifted right by P positions.

[0045] According to one or more embodiments, an LDPC encoder suitable for low-Earth orbit satellite ground-based bands is implemented based on the aforementioned LDPC check matrix construction method. It uses random access memory (RAM) instead of a traditional barrel shift register to implement cyclic shift operations, simplifying the originally complex large-bit-width register shift process to address-based RAM reading. The encoder includes the following modules:

[0046] (1) Information bit serial-to-parallel conversion module, used to divide the serial information bit data into blocks and store them in the message storage module and the output buffer module, so as to facilitate subsequent parallel computing and output;

[0047] (2) Circular shift address storage module, used to store the circular shift value of the circular shift matrix. The circular shift values ​​of the circular shift matrix of all code rates are stored in ROM, and stored in blocks according to the code rate from smallest to largest. The read address of the message storage module is generated when calculating the parity bit;

[0048] (3) Message storage module, used to store the information bit blocks after serial-to-parallel conversion, is divided into two parts: a high-bit-rate storage area and an extended storage area. The high-bit-rate storage area is the high-bit-rate part of the parity check matrix information bits, consisting of 22 RAMs. The extended storage area is the extended redundant part of the parity check matrix information bits, consisting of 22 RAMs. The high-bit-rate storage area and the extended storage area store the information bit blocks according to the distribution of non-negative values ​​of the base matrix.

[0049] (4) Intermediate parity bit storage module, used to store intermediate parity bit values ​​during the parity bit calculation process, consists of 4 RAMs;

[0050] (5) Calculation module, used to retrieve row vectors from message storage module and check bit intermediate storage module according to control signal of control module, perform XOR calculation to generate check bit intermediate value, and store check bit in output buffer module;

[0051] (6) Output buffer module, used to buffer information bits and parity bits, including information bit buffer FIFO and parity bit buffer FIFO;

[0052] (7) Codeword parallel-to-serial conversion module, used for rate matching and data aggregation output;

[0053] (8) Control module, used to calculate code parameter information based on code selection signal and generate read / write control signals for other sub-modules.

[0054] The serial-to-parallel conversion module divides the serial input data into blocks according to the expansion factor Z, then outputs them in parallel and stores them in the message storage module for subsequent parallel calculation and output. The process of the codeword parallel-to-serial conversion module rate matching is as follows: for the expansion factor Z, the FIFO read enable signal is controlled to first punch the first 2Z columns of the information bits and shorten the 0 sequence filled at the end of the information bits, and then punches the check bits according to the frame length.

[0055] The working process of the LDPC encoder includes the following steps:

[0056] Step 1: Encoder initialization. The top-level module receives external configuration parameters (information bit length, code rate), the control module calculates the encoding parameters and writes them into the register, and then generates an encoder reset signal to complete the initialization.

[0057] Step 2: Data reception and buffering. Serial information bits are received starting from the frame header signal. Each Z bit received is converted into parallel data by the serial-to-parallel conversion module. The parallel data is simultaneously written to the message storage module and the output buffer module.

[0058] Step 3: High-rate check bit calculation. After the control module detects the data reception completion signal, it reads the cyclic shift value as the address, reads the corresponding information bits from the message storage module, and calculates the high-rate check bit.

[0059] Step 4: Extended parity bit calculation. After receiving the signal indicating that the high-rate parity bit calculation is complete, read the information bits from the message storage module and the intermediate storage module to calculate the extended parity bit.

[0060] Step 5: Codeword assembly and output. After encoding, data is read in parallel from the output buffer module, and parallel-to-serial conversion is performed. Punching and shortening operations are achieved through counting control.

[0061] Step 6: Frame encapsulation and transmission. Add a frame header and a frame validity indicator signal, and serially output the complete encoded frame to complete the entire encoding process.

[0062] Therefore, this disclosure presents a method for constructing an LDPC parity-check matrix and an encoder device for low-Earth orbit satellite ground-based communication. On one hand, this disclosure redesigns and optimizes the LDPC parity-check matrix in the DVB-S2 standard, achieving a performance gain of 0.1~0.3dB in frame error rate and bit error rate compared to the DVB-S2 standard error correction code, significantly enhancing the system's robustness and verifying the application potential of this scheme in practical satellite communication environments. On the other hand, the encoder of this disclosure can achieve a throughput of 12Gbps at a 100MHz clock frequency, significantly reducing the resource usage of LUTs and FFs, which is beneficial for deployment on resource-constrained FPGA platforms.

[0063] According to one or more embodiments, an LDPC code parity check matrix construction method is applicable to the LDPC parity check matrix construction method of low-Earth orbit satellite ground-based zone. A quasi-cyclic LDPC code (QC-LDPC) parity check matrix is ​​constructed. The structure of the parity check matrix adopts a Raptor code-like structure. The Raptor code is an extension of the Luby Transform (LT) code. The parity check matrix is ​​composed of multiple cyclic shift submatrices. It can be constructed by simply shifting the cyclic shift submatrices. Both the generator matrix and the parity check matrix have cyclic shift characteristics, which can relatively easily realize fast hardware encoding and parallel decoding, and support flexible code length and code rate.

[0064] The structure of the LDPC check matrix is ​​as follows: Figure 1 As shown, submatrices A and B are the high-rate portions of the parity-check matrix, assembled from cyclic permutation matrices and all-zero matrices. Submatrice A corresponds to the information bits, and submatrice B is a double-diagonal matrix corresponding to the parity bits. Submatrices C and D are parity-check matrices extended from the high-rate matrix. Matrix Z is an all-zero matrix, and matrix E is a one-diagonal matrix composed of identity matrices. By increasing the number of rows and columns in the matrix extension, LDPC parity-check matrices with arbitrary bit rates can be obtained.

[0065] Figure 2 A schematic diagram illustrating the construction process of the LDPC code parity-check matrix provided in this disclosure includes the following steps:

[0066] S101, the EXIT technique is used to determine the degree distribution of the basis matrix at high bitrates. Then, the core part and its extended part of the basis matrix are jointly designed using the P-EXIT algorithm under the constraint of optimal degree distribution. This step specifically includes the following steps one to four.

[0067] Step 1: Initialize the EXIT curve proximity accuracy Since the initial signal-to-noise ratio R is positive infinity, it is also positive infinity.

[0068] Step 2: Traverse all degree distribution combinations of variable nodes (VN) and check nodes (CN). For each VN and CN degree distribution combination, traverse a series of different signal-to-noise ratio (SNR) values. Calculate the input and output information entropy of variable nodes and check nodes according to formulas (1) and (2). Use the information entropy relationship to fit the two curves of the EXIT graph.

[0069]

[0070]

[0071] in, : Verify the node's EXIT function;

[0072] : The EXIT function for variable nodes;

[0073] ;

[0074] : Input mutual information for variable nodes;

[0075] : Indicates the proportion of CNs with a degree of d out of the total number of CNs;

[0076]

[0077] : Verify the maximum degree of the node;

[0078] : Maximum degree of the variable node;

[0079] J ;

[0080] The calculation method is as follows:

[0081]

[0082] Step 3: Calculate the fitting accuracy Update the current optimal signal-to-noise ratio (SNR), construct the basis matrix based on the degree distribution when the SNR is optimal, and further filter out the high-bit-rate LDPC basis matrix with optimal performance using the P-EXIT method.

[0083] Step 4: Traverse each row of the extension region matrix and all possible design combinations. Combine the high bitrate part of the base matrix with the extension matrix and fill the identity matrix part. Use the P-EXIT method to evaluate the performance of different combinations and select the optimal solution.

[0084] S102, the base matrix size and spread factor corresponding to each code rate are determined based on the FEC coding parameters of the DVB-S2 protocol. First, the number of columns in the base matrix submatrix is ​​obtained based on the DVB-S2 protocol's code rate R, information bit length k, and frame length n. , number of rows ,in ; expansion factor greater than The smallest prime number Subtract one, This is used to construct a cyclic shift coefficient table. The parameters of the constructed scheme are shown in Table 1.

[0085] Table 1. Parameters of the parity-check matrix construction scheme at different code rates

[0086]

[0087] S103, based on the extension factor, determines the finite field and generator, constructs linearly independent shift-value row vectors and a table of cyclic coefficients, that is, uses the method of finite field algebra to generate... Cyclic coefficient table ( First, based on the expansion factor and prime number determined in the second step. Set up a finite field The prime number can be used to determine if there are primes in the prime field. Different elements and generators ,pass The power of is completely expressed q elements. Then define a set. ,get Two arbitrary subsets of the following and ,in ,and and yes The elements in Formed according to formula (3) On Cycle coefficient table .

[0088]

[0089] Here, Finite field ,

[0090] m, n: The number of elements in sets S1 and S2, which must satisfy m + n = q.

[0091] S104: Select row vectors from the cyclic coefficient table to construct a cyclic shift matrix. Then, identify and eliminate short cycles within the cyclic shift matrix, i.e., construct and optimize the cyclic shift matrix. First, select different combinations of row vectors from the cyclic coefficient table to fill the basis matrix to obtain the initial cyclic shift matrix. Then, the loop characteristics of the initial cyclic shift matrix are analyzed to count the number of 4-loops and 6-loops in the matrix. The number of loops with a length of 2d can be calculated and determined by the shift value constraint shown in equation (4). Finally, the loop optimization process is implemented. Based on the detection results, the row vector combination in the cyclic coefficient table is iteratively adjusted to dynamically update the cyclic shift value in the shift matrix until the number of 4-loops and 6-loops in the matrix is ​​minimized.

[0092]

[0093] in,

[0094] Z: Expansion factor;

[0095] d: Loop identifier, the short loop length is 2*d, d = 2 or 3.

[0096] S105, based on the base matrix and the cyclic shift matrix, performs matrix hashing to obtain the final LDPC parity check matrix, i.e., the cyclic shift matrix... Hash, which converts all elements of a circular shift matrix into a single array. Replace the matrix. If If so, replace it with a matrix of all zeros. If so, then replace it with the identity matrix. Then, a cyclic permutation matrix is ​​used for replacement. The corresponding cyclic permutation matrix is ​​an identity matrix with each row cyclically shifted to the right. Bit.

[0097] Taking a bitrate of 4 / 5 as an example, the DVB-S2 standard and the LDPC parity-check matrix constructed in this disclosure are as follows: Figure 3 As shown and Figure 4 As shown.

[0098] Furthermore, to evaluate the performance of the LDPC code designed in this disclosure, an LDPC performance simulation experimental system based on the DVB-S2 protocol was built on the MATLAB platform, from the transmitter to the receiver. The satellite communication frame structure of the DVB-S2 protocol was adopted, and a satellite communication channel was simulated. The specific architecture of the LDPC performance simulation experimental system is as follows: Figure 5 As shown, specifically including,

[0099] (1) Baseband frame assembly module, used to fragment the data stream and scramble the baseband frames;

[0100] (2) BCH encoder, used to perform BCH encoding on baseband frames to reduce decoding error layers;

[0101] (3) LDPC encoder, used for LDPC encoding;

[0102] (4) Bit interleaver, used to break up data to combat burst errors and enhance signal robustness;

[0103] (5) Modulator, which maps the encoded bitstream onto a constellation diagram for modulation;

[0104] (6) Satellite communication channel, used to add noise and impair the signal transmitted by the transmitter.

[0105] (7) Signal synchronization module, used for signal time-frequency synchronization and phase synchronization.

[0106] (8) Demodulator, which samples and demodulates the synchronized data to obtain the probability likelihood value of the data stream;

[0107] (9) Deinterleaver, used to restore a random data stream to its original order.

[0108] (10) LDPC decoder, used for LDPC encoding;

[0109] (11) BCH decoder, used for BCH decoding;

[0110] (12) Baseband frame decomposition module, used to recover the bit data carried in the baseband frame;

[0111] (13) Bit error rate statistics module, used to count the number of error bits after LDPC encoding and decoding under different channel conditions;

[0112] (14) Frame error rate statistics module, used to count the number of erroneous frames after LDPC encoding and decoding under different channel conditions;

[0113] The LDPC performance simulation experimental system first adds carrier frequency offset (±3MHz) and phase noise (10°RMS) to the AWGN channel to simulate the dynamic channel characteristics of low-Earth orbit satellites. The synchronization module uses a joint frequency offset / phase offset compensation algorithm based on maximum likelihood estimation to achieve closed-loop tracking of symbol timing recovery and carrier synchronization. The code rate range is 1 / 3 to 8 / 9, the modulation method is BPSK, and the LDPC decoding uses the belief propagation decoding algorithm with 50 decoding iterations. The BCH code in the DVB-S2 concatenated code uses the FiBM algorithm.

[0114] like Figure 5As shown, the transmitted data passes through the baseband frame assembly module, BCH encoder, LDPC encoder, bit interleaver, and QPSK modulator of the LDPC performance simulation experimental system. It then travels through the satellite communication channel, followed by the signal synchronization module, QPSK demodulator, deinterleaver, LDPC decoder, BCH decoder, and baseband frame decomposition module to obtain the received data. The transmit / receive LDPC frame error rate statistics module is connected to the input of the baseband frame assembly module and the output of the baseband frame decomposition module. The LDPC bit error rate statistics module is connected to the input of the LDPC encoder and the output of the LDPC decoder.

[0115] Figure 6 and Figure 7 The graph shows a performance comparison between the LDPC code and the DVB-S2 standard protocol concatenated code designed in this scheme at different code rates, as provided in this disclosure. The horizontal axis in the graph represents the signal-to-noise ratio of the channel. Figure 4 The vertical axis represents the post-correction frame error rate (FER) after error correction. Figure 5 The vertical axis represents the bit error rate (BER) after error correction. Experimental results show that, under typical low-Earth orbit satellite channel conditions, this construction method offers an average performance gain of 0.1–0.3 dB compared to the DVB-S2 protocol concatenated code at a frame error rate of 10⁻⁴, and an average performance gain of 0.11 dB at a BER of 10⁻⁴. By optimizing the parity-check matrix, the baseband system exhibits stronger robustness, verifying the applicability of this disclosed construction scheme in practical satellite communication scenarios.

[0116] According to one or more embodiments, this disclosure implements a corresponding encoder device based on a constructed LDPC parity check matrix. Traditional LDPC encoders typically first perform serial-to-parallel conversion on the input bitstream, then perform cyclic shift operations on the parallelized data using a barrel shift register to calculate the parity vector. After generating the parity vector, a parallel-to-serial conversion operation is performed to concatenate the parity bits with the information bits to form the final output codeword stream. This process involves significant data channel control and logic resource consumption, especially the reliance on the barrel shift register in the cyclic shift operation, resulting in high overhead for lookup tables (LUTs) and flip-flops (FFs).

[0117] To overcome the aforementioned problems, this disclosure adopts an optimization scheme based on random access memory (RAM). Specifically, this disclosure uses RAM to complete the storage and cyclic shifting operations of input information, replacing the logic of traditional barrel shift registers with RAM address access. Logical data shifting is achieved by adjusting the read address, avoiding the resource overhead caused by performing actual shifting operations on large-bit-width data in registers. This design significantly reduces the resource quantity of LUTs and FFs by sacrificing a small amount of block RAM (BRAM) resources, thereby improving the implementation efficiency and applicability of the encoder on the FPGA platform. The specific method is as follows:

[0118] 1) LDPC encoding algorithm

[0119] The LDPC parity check matrix constructed in this disclosure can be divided into 6 sub-block matrices, and the H matrix after row and column transformation is denoted as shown in equation (5). The region is a matrix of all zeros. The region is a global unit matrix.

[0120]

[0121] For ease of representation, the codeword is divided into three parts, represented as follows: Information bits The number of digits and Same column number, check digit and The number of blocks respectively and and They are in the same column.

[0122] according to It can be obtained.

[0123]

[0124] It can be obtained

[0125]

[0126] In the verification matrix of this design, the basis matrix corresponding to region B is a double diagonal matrix, and the content of region B is...

[0127]

[0128] Based on the above double-diagonal structure, the corresponding parity bits can be represented as follows: ,in Indicates continuity bits, This is the expansion factor size.

[0129] definition Based on the special characteristics of the cyclic shift coefficient values ​​corresponding to region B, we can obtain

[0130]

[0131] Organized As shown in equation (10),

[0132]

[0133] By utilizing the special structure of part B of the parity-check matrix, the matrix inversion operation can be omitted in the encoding algorithm, and the matrix can be directly used. and The linear mathematical relationship between them Calculation results Calculate the check digit The check digit is obtained according to equation (7). Finally, the results are concatenated to obtain the encoded codeword. This simplifies the encoding algorithm. In hardware implementation, this simplified approximate lower triangular matrix encoding algorithm is used; the core design of the overall encoding structure consists of only a few parts. This structure reduces the complexity of the encoding hardware implementation, enabling fast encoding.

[0134] The parameter definitions involved in formulas (5), (6), (7), (8), (9), and (10) include:

[0135]

[0136]

[0137] B:

[0138] C and D are parity check matrices extended from the high-rate matrix;

[0139] Z is a matrix consisting entirely of zeros;

[0140] E is a one-diagonal matrix composed of an identity matrix;

[0141]

[0142] U: Information bit;

[0143]

[0144]

[0145]

[0146] .

[0147] 2) Encoder hardware implementation architecture

[0148] This disclosure implements an LDPC encoder device based on the above encoding algorithm. Figure 8 The hardware architecture design of the encoder is described in detail. This design includes several key modules, each performing a specific function to implement the LDPC encoding process. The hardware architecture includes the following modules:

[0149] (1) Information bit serial-to-parallel conversion module, used to divide the serial information bit data into blocks and store them in the message storage module and the output buffer module, so as to facilitate subsequent parallel computing and output;

[0150] (2) Circular shift address storage module, used to store the circular shift values ​​of the circular shift matrix. It stores the circular shift values ​​of the circular shift matrix for all code rates by loading a COE file from the ROM, and stores them in blocks according to the code rate from smallest to largest. The stored content is as follows: Figure 9 As shown in the data example, the read address for the message storage module is generated when calculating the check bit;

[0151] (3) Message storage module, used to store the information bit blocks after serial-to-parallel conversion, is divided into two parts: a high-bit-rate storage area and an extended storage area. The high-bit-rate storage area is the high-bit-rate part of the parity check matrix information bits, consisting of 22 RAMs. The extended storage area is the extended redundant part of the parity check matrix information bits, consisting of 22 RAMs. The high-bit-rate storage area and the extended storage area store the information bit blocks according to the distribution of non-negative values ​​of the base matrix.

[0152] (4) Intermediate parity bit storage module, used to store intermediate parity bit values ​​during the parity bit calculation process, consists of 4 RAMs;

[0153] (5) Calculation module, used to retrieve row vectors from message storage module and check bit intermediate storage module according to control signal of control module, perform XOR calculation to generate check bit intermediate value, and store check bit in output buffer module;

[0154] (6) Output buffer module, used to buffer information bits and parity bits, including information bit buffer FIFO and parity bit buffer FIFO;

[0155] (7) Codeword parallel-to-serial conversion module, used for rate matching and data aggregation output;

[0156] (8) Control module, used to calculate code parameter information based on code selection signal and generate read / write control signals for other sub-modules.

[0157] exist Figure 8The encoder hardware includes: the output of the information bit serial-to-parallel (S2P) conversion module is connected to the message storage (RAM_Inform) module and the encoding result buffer module (FIFO_Code), while the output of the encoding result buffer module (FIFO_Code) is connected to the codeword parallel-to-serial (P2S) conversion module; the output of the calculation module (Caculate) is connected to the encoding result buffer module (FIFO_Code), the message storage (RAM_Inform) module, and the intermediate parity bit storage (RAM_temp) module; the output of the cyclic shift value storage (ROM) module is connected to the calculation module (Caculate); the control module (Control_Encoding) is connected to the aforementioned modules through control signals to coordinate the entire encoding process. Information is input to the information bit serial-to-parallel (S2P) conversion module, which converts serial information bits into parallel format; the codeword parallel-to-serial (P2S) conversion module outputs information, completing the entire encoding process.

[0158] In hardware implementation, the encoder is designed to be configurable to a corresponding operating mode based on parameters. The entire encoder workflow includes:

[0159] The top-level module first receives the external input parameters, including the bit length and bit rate. The control module then begins working, calculating the parameters required by the subsequent encoding modules. After the parameter calculations are complete, the parameters are written to the corresponding registers, generating an encoder reset signal and completing the encoder initialization. Then, based on the input frame header and frame validity indicator signal, the encoder begins receiving information bits. These information bits are transmitted serially to the encoder serial-to-parallel conversion module and the encoding result combination buffer module. Whenever input... When the information bits are 1, the serial-to-parallel module outputs them as a group of data in parallel and transmits them to the high code rate storage area and extended storage area of ​​the message storage module, as well as the information bit buffer FIFO of the encoding result combination buffer module.

[0160] Furthermore, upon receiving the information bit reception completion signal, the control unit begins encoding counting and generates a synchronous read address signal. Using the cyclic shift value in the ROM of the cyclic shift value storage module as the address, it reads the corresponding information bit from the high-rate storage area of ​​the message storage module and sends it to the calculation module for encoding. The calculation module completes the encoding in equation (9). The buffer is stored in the register, and the control unit sends ( The value is fed back to the input of the control module and shifted cyclically to the right to calculate the parity bit. The data is then stored in the RAM of the intermediate storage module for the check bit and used in subsequent encoding. arrive The data is stored in the parity FIFO of the output buffer module. The encoding control unit receives... The calculation is complete, and encoding counting begins. The corresponding information bits and parity bits are read from the extended storage area of ​​the message storage module and the intermediate parity bit storage module, respectively, and sent to the calculation module for encoding. The calculation module then processes the data according to the formula... Finish The calculated parity bits are then fed into the parity bit FIFO of the output buffer module.

[0161] After encoding the entire frame of data, an encoding completion signal is sent to the encoding control module. Information bits and parity bits are then read sequentially from the information bit FIFO and parity bit FIFO in the output buffer module, and parallel-to-serial conversion is performed. Punching and shortening operations are controlled by counting the output of the FIFOs. Finally, a frame header and a frame validity indicator signal are added to the output codeword, completing the serial output of the entire frame of data. This concludes the encoding of one codeword.

[0162] In these processing steps, the use of multi-port RAM and ROM is key to achieving efficient data processing. By using custom multi-port RAM and ROM, data from multiple addresses can be read in parallel within a single clock cycle, improving the efficiency of data access for parity check matrix calculation in the LDPC encoder. Specifically, the multi-port RAM improves the parallelism of data reading by accessing multiple data simultaneously using different address lines, while the multi-port ROM stores the addresses of the cyclic shift values ​​of the parity check matrix, enabling fast data access through multiple read ports.

[0163] Furthermore, to verify the implemented parallelized LDPC encoder, this disclosure establishes a hardware test platform for implementation verification and performance testing. The technical effects of this disclosure are further illustrated through simulation and its results, combined with embodiments. The encoder device is designed using Verilog language for RTL, and the hardware resource usage after synthesis and implementation on the Vivado platform is shown in Table 3.

[0164] Table 3 Resource Proportion for LDPC Encoder Hardware Implementation

[0165]

[0166] Timing simulation of the encoder device was performed, and board-level verification was conducted using the Zynq-7000 XC7Z035-2FFG900I development board. Software fixed-point programs were randomly generated. The bit information is fed into the encoder, and the encoded result is compared with the result of the software simulation program. Figure 10 The waveform diagram of the timing simulation is shown. The simulation results show that the output results of the two are consistent, and all indicator signals are working normally, indicating that the encoder function is correct.

[0167] The clock frequency used for the encoder performance test in this disclosure is 100MHz, and the throughput is calculated according to equation (11). Indicates clock frequency. Indicates the length of the information bits. This indicates that the coding period is equal to 12. This indicates the encoding computation time. Based on this, the corresponding maximum throughput is 12Gbps.

[0168]

[0169] Table 2 Comparison of relevant research and the present invention

[0170]

[0171] Research document 1: NANNIPIERI P, BARTOLACCI G, BERTOLUCCI M, et al. Design andImplementation of a Configurable Fully Compliant DVB-S2 LDPC Encoder for HighData-Rate Downlink Payload[J]. IEEE Access, 2024, 12: 39204-39220.

[0172] Research Document 2: CN120185622A, An LDPC encoder, transmitter and test platform based on DVB-S2 protocol.

[0173] Table 2 shows a comparison of the resource usage of the encoder implemented in this disclosure with that of related research literature. While maintaining the same clock frequency (100MHz) and equivalent throughput (12Gbps), the resource usage of the lookup table (LUT) and flip-flop (FF) in this disclosure is reduced by approximately 69.2% and 74.1% respectively compared with research literature 1, and by approximately 37.4% and 75.1% respectively compared with research literature 2. Although the BRAM usage is slightly increased, the overall hardware resource usage is significantly optimized compared with the latest related research.

[0174] In summary, this disclosure presents a method for constructing an LDPC parity-check matrix and an encoder device for low-Earth orbit satellite ground-based communication. On one hand, this disclosure redesigns and optimizes the LDPC parity-check matrix in the DVB-S2 standard, achieving a performance gain of 0.1~0.3dB in frame error rate and bit error rate compared to the DVB-S2 standard error correction code, significantly enhancing the system's robustness and verifying the application potential of this scheme in practical satellite communication environments. On the other hand, the encoder of this disclosure can achieve a throughput of 12Gbps at a 100MHz clock frequency, significantly reducing the resource usage of LUTs and FFs compared to existing technologies, which is beneficial for deployment on resource-constrained FPGA platforms.

[0175] It should be understood that in the embodiments of the present invention, the term "and / or" is merely a description of the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, the character " / " in this document generally indicates that the preceding and following associated objects have an "or" relationship.

[0176] It is worth noting that although the spirit and principles of this invention have been described with reference to several specific embodiments, it should be understood that this invention is not limited to the disclosed specific embodiments, and the division of aspects does not imply that the features in these aspects cannot be combined; such division is merely for the convenience of description. This invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A method for constructing an LDPC code parity-check matrix for low-Earth orbit satellite ground-based processing, characterized in that, The method includes: A1 uses the external information transfer graph EXIT to determine the degree distribution of the basis matrix at high code rates, and constructs the basis matrix by using the external information transfer P-EXIT based on the basis graph under the constraint of optimal degree distribution. A2, based on the code length and code rate of the DVB-S2 protocol FEC encoding, determines the size of the base matrix submatrix and the expansion factor corresponding to each code rate; A3, based on the expansion factor, determine the finite field and generator, and construct a linearly independent row vector of shift values ​​and a table of cyclic coefficients; A4. Select row vectors from the cyclic coefficient table to construct a cyclic shift matrix, and perform short-loop identification and elimination on the cyclic shift matrix; A5, based on the base matrix and the cyclic shift matrix, performs matrix hashing to obtain the LDPC parity check matrix.

2. The method according to claim 1, characterized in that, The method for constructing the basis matrix includes: The EXIT curve is initialized to have a precision T of positive infinity, and the signal-to-noise ratio R is also initialized to positive infinity. Traverse all degree distribution combinations of variable node VN and check node CN. For each combination of VN and CN degree distributions, traverse a series of different signal-to-noise ratio (SNR) values, calculate the input-output information entropy of variable node and check node, and use the information entropy relationship to fit the two curves of EXIT graph. Calculate the fitting accuracy T, update the current optimal signal-to-noise ratio, construct the basis matrix based on the degree distribution when the signal-to-noise ratio is optimal, and further filter out the high-bitrate LDPC basis matrix with optimal performance using the P-EXIT method; Traverse each row of the extension region matrix, explore all possible design combinations, combine the high bitrate portion of the base matrix with the extension matrix, and fill the identity matrix portion. Use the P-EXIT method to evaluate the performance of different combinations and select the optimal solution.

3. The method according to claim 1, characterized in that, The method for constructing the cyclic shift matrix includes: For a given expansion factor Z, extract the submatrix used from the basis matrix BG1; Select row vectors from the cycle coefficient table to fill the submatrix, minimizing the number of four-ring and six-ring matrices. Each -1 element in the submatrix is ​​expanded into a Z*Z matrix of all zeros, where Z represents the expansion factor; Each zero element in the submatrix is ​​expanded into a Z*Z identity matrix; For each element in the submatrix except for the -1 element and the zero element, perform the following operation: expand it into a cyclic permutation matrix according to the value P of the element. The corresponding cyclic permutation matrix is ​​a Z*Z identity matrix with each row cyclically shifted right by P positions.

4. An LDPC encoder, characterized in that, The LDPC code check matrix is ​​constructed using the method described in any one of claims 1 to 3.

5. The encoder according to claim 4, characterized in that, The encoder includes an information bit serial-to-parallel conversion module, a cyclic shift address storage module, a message storage module, a check bit intermediate storage module, a calculation module, an encoding output buffer module, a codeword parallel-to-serial conversion module, and a control module. The output of the information bit serial-to-parallel conversion module is connected to the message storage module and the encoding output buffer module, and the output of the encoding output buffer module is connected to the codeword parallel-to-serial conversion module. The output of the calculation module is connected to the encoding output buffer module, the message storage module, and the check bit intermediate storage module; The output of the cyclic shift address storage module is connected to the computing module; The control module connects to other modules in the encoder and controls the encoding process. Information is input to the serial-to-parallel conversion module, which converts serial information bits into parallel format; The parallel-to-serial conversion module outputs information to complete the encoding process.

6. The encoder according to claim 5, characterized in that, The encoder's operation includes the following steps: Encoder initialization: The top-level module receives external configuration parameters, the control module calculates the encoding parameters and writes them into the register, and then generates an encoder reset signal to complete the initialization. Data reception and buffering: Serial information bits are received starting from the frame header signal. Every Z bits received are converted into parallel data by the serial-to-parallel conversion module. The parallel data is simultaneously written to the message storage module and the output buffer module. High-rate check bit calculation: After the control module detects the data reception completion signal, it reads the cyclic shift value as the address, reads the corresponding information bits from the message storage module, and calculates the high-rate check bit. Extended parity bit calculation: After receiving the high-rate parity bit calculation completion signal, information bits are read from the message storage module and intermediate storage module to calculate the extended parity bit; The codeword is assembled and output. After encoding, data is read in parallel from the output buffer module and converted from parallel to serial. Punching and shortening operations are achieved through counting control. The frame is encapsulated and transmitted, with a frame header and a frame validity indicator signal added. The complete encoded frame is then output serially to complete the encoding process.

7. A low-Earth orbit satellite-to-ground communication transmitter, characterized in that, Includes the LDPC encoder as described in claim 4.

8. A low-Earth orbit satellite-to-ground communication receiver, characterized in that, Receive and demodulate the communication signal transmitted from the transmitter as described in claim 7.

9. An FPGA encoder integrated circuit, characterized in that, Includes the LDPC encoder as described in claim 4.

10. An LDPC performance simulation experimental system, characterized in that, The system includes a baseband frame assembly module, a BCH encoder, an LDPC encoder, a bit interleaver, a QPSK modulator, a satellite communication channel, a signal synchronization module, a QPSK demodulator, a deinterleaver, an LDPC decoder, a BCH decoder, a baseband frame decomposition module, a transmit / receive LDPC frame error rate statistics module, and an LDPC bit error rate statistics module. The transmitted data passes through a baseband frame assembly module, a BCH encoder, an LDPC encoder, a bit interleaver, and a QPSK modulator. It then travels through a satellite communication channel, followed by a signal synchronization module, a QPSK demodulator, a deinterleaver, an LDPC decoder, a BCH decoder, and a baseband frame decomposition module to obtain the received data. The LDPC frame error rate statistics module is connected to the input of the baseband frame assembly module and the output of the baseband frame decomposition module. The LDPC bit error rate statistics module is connected to the input of the LDPC encoder and the output of the LDPC decoder.

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