Equalizer and chip

Abstract

The invention provides an equalizer and a chip, and relates to the field of artificial intelligence chips. The equalizer comprises a first-stage receiving circuit, and the first-stage receiving circuit comprises a pre-amplification sub-circuit, a dynamic latch sub-circuit and a phase selection sub-circuit. The input end of the pre-stage amplification sub-circuit is electrically connected with the signal input end of the first-stage receiving circuit, the first output end of the pre-stage amplification sub-circuit is electrically connected with the first input end of the dynamic latch sub-circuit, and the second output end of the pre-stage amplification sub-circuit is electrically connected with the second input end of the dynamic latch sub-circuit; the first output end of the dynamic latch sub-circuit is electrically connected with the first input end of the phase selection sub-circuit, the second output end of the dynamic latch sub-circuit is electrically connected with the second input end of the phase selection sub-circuit, and the first output end and the second output end of the phase selection sub-circuit are electrically connected with the signal output end of the first-stage receiving circuit. The problem that an existing equalizer is large in occupied area and high in power consumption is solved.

Description

Technical Field

[0001] This application relates to the field of artificial intelligence chips, and in particular to an equalizer and chip. Background Technology

[0002] With the rapid development of artificial intelligence, the total amount of data processed is constantly increasing, and the requirements for data transmission rates are also becoming increasingly stringent. During high-speed data transmission, it is essential to ensure high-quality signal transmission. By incorporating equalizer circuitry into the equalizer, channel loss can be compensated for, signal distortion corrected, and thus reliable data reception ensured.

[0003] However, current equalizers occupy a large area and consume a lot of power, which cannot meet the application needs of portable devices, high-density computing clusters and other scenarios with strict requirements for chip area and energy efficiency. Summary of the Invention

[0004] The embodiments disclosed in this application provide an equalizer and chip, aiming to improve the problems of large footprint and high power consumption in existing equalizers. The embodiments of this application adopt the following technical solutions: In a first aspect, an equalizer is provided, comprising: a first-stage receiving circuit, the first-stage receiving circuit including: a pre-amplifier sub-circuit, a dynamic latch sub-circuit, and a phase selection sub-circuit. The input terminal of the preamplifier sub-circuit is electrically connected to the signal input terminal of the first-stage receiver circuit. The first output terminal of the preamplifier sub-circuit is electrically connected to the first input terminal of the dynamic latch sub-circuit. The second output terminal of the preamplifier sub-circuit is electrically connected to the second input terminal of the dynamic latch sub-circuit. The first output terminal of the dynamic latch sub-circuit is electrically connected to the first input terminal of the phase selection sub-circuit. The second output terminal of the dynamic latch sub-circuit is electrically connected to the second input terminal of the phase selection sub-circuit. The first output terminal of the phase selection sub-circuit is electrically connected to the signal output terminal of the first-stage receiver circuit. The second output terminal of the phase selection sub-circuit is electrically connected to the signal output terminal of the first-stage receiver circuit.

[0005] The equalizer provided in this application embodiment achieves amplification, shaping, and phase selection of differential input signals by sequentially arranging a pre-amplifier sub-circuit, a dynamic latch sub-circuit, and a phase selection sub-circuit in its overall structure. When enabled, the pre-amplifier sub-circuit provides controllable gain compensation to the input differential signal; when disabled, it is a simple digital circuit structure, effectively reducing power consumption in standby mode. The dynamic latch sub-circuit can cross-couple and shape the pre-amplified differential signal, improving the eye diagram opening and noise immunity of the differential signal. The phase selection sub-circuit, through register control, enables selective switching of the output path, allowing the output phase to be selected to match the positive or negative input as needed, enhancing the circuit's compatibility with different signal polarities. With this structure, the equalizer of this application not only achieves equalization compensation for high-frequency attenuated signals in the analog domain, replacing the effect of traditional programmable gain amplifiers, but also significantly reduces the overall number of components due to simplified transistor structure and standard unit implementation, thus possessing advantages such as small area, low power consumption, simple design, and easy integration into high-speed digital interfaces.

[0006] In one possible implementation of the first aspect, a preamplifier sub-circuit is used to receive an initial differential signal and perform an amplification operation on the initial differential signal to obtain a first differential signal; a dynamic latch sub-circuit is used to receive the first differential signal and perform a shaping operation on the first differential signal to obtain a second differential signal; and a phase selection sub-circuit is used to receive the second differential signal and perform a phase selection operation on the second differential signal to obtain a target signal.

[0007] In one possible implementation of the first aspect, the first-stage receiving circuit further includes a first register sub-circuit, the control terminal of the first register sub-circuit being electrically connected to the input terminal of the pre-amplifier sub-circuit, the first register sub-circuit being configured to: turn off the pre-amplifier sub-circuit when outputting a first enable signal, and turn on the pre-amplifier sub-circuit to perform amplification on the initial differential signal when outputting a second enable signal.

[0008] The equalizer provided in this application embodiment achieves flexible switching between two working modes: off and on, by setting a controllable first register sub-circuit. When the enable signal is off, the pre-amplifier sub-circuit does not participate in analog amplification, and the overall circuit is a simple digital logic link, which significantly reduces static power consumption. When the enable signal is on, the pre-amplifier sub-circuit provides gain compensation for high-frequency attenuated signals, laying the signal amplitude foundation for subsequent dynamic latching shaping and phase selection.

[0009] In one possible implementation of the first aspect, the first-stage receiving circuit further includes a second register sub-circuit, the control terminal of the second register sub-circuit being electrically connected to the first input terminal and the second input terminal of the phase selection sub-circuit, the second register sub-circuit being used to: switch the signal output path of the phase selection sub-circuit according to the type of the output enable signal.

[0010] The equalizer provided in this application embodiment can flexibly adjust the phase of the output signal by setting a controllable second register sub-circuit, thereby achieving different signal polarity and direction control. Specifically, the phase selection sub-circuit can provide flexible phase adjustment according to the needs of different subsequent digital circuits by dynamically switching different signal paths, ensuring the consistency and stability of the signal during transmission.

[0011] In one possible implementation of the first aspect, the input terminals of the preamplifier sub-circuit include a first sub-input terminal and a second sub-input terminal. The first sub-input terminal is used to receive a first initial differential numerator signal, and the second sub-input terminal is used to receive a second initial differential numerator signal. The second register sub-circuit is specifically used to: when outputting a first enable signal, make the target signal input to the phase selection sub-circuit have the same phase as the first initial differential numerator signal; and when outputting a second enable signal, make the target signal output by the phase selection sub-circuit have the same phase as the second initial differential numerator signal.

[0012] The equalizer provided in this application embodiment also has an inverting function, enabling the output signal to flexibly switch to a phase opposite to the input signal. This function not only facilitates phase adjustment of the signal under different operating conditions but also provides convenience for designing functional tests. Through the inverting function, testers can easily generate and verify forward and reverse signals, thereby simplifying test cases for signal integrity and timing analysis and ensuring the stability of the system's functionality and performance under different operating modes.

[0013] In one possible implementation of the first aspect, the preamplifier sub-circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first constant current source, and a second constant current source. A first terminal of the first transistor is electrically connected to a first voltage terminal, a second terminal of the first transistor is electrically connected to the first terminal of the second transistor, a control terminal of the first transistor is electrically connected to a first sub-input terminal, a second terminal of the second transistor is electrically connected to the first terminal of the first constant current source, a control terminal of the second transistor is electrically connected to the first sub-input terminal, a first terminal of the third transistor is electrically connected to a second voltage terminal, and a second terminal of the third transistor is electrically connected to the second terminal of the first transistor. The control terminal is electrically connected to the third voltage terminal; the first terminal of the fourth transistor is electrically connected to the first terminal of the second constant current source; the second terminal of the fourth transistor is electrically connected to the first terminal of the fifth transistor; the control terminal of the fourth transistor is electrically connected to the second sub-input terminal; the second terminal of the fifth transistor is electrically connected to the ground terminal; the control terminal of the fifth transistor is electrically connected to the second sub-input terminal; the first terminal of the sixth transistor is electrically connected to the second terminal of the fourth transistor; the second terminal of the sixth transistor is electrically connected to the ground terminal; the control terminal of the sixth transistor is electrically connected to the ground terminal; the second terminal of the first constant current source is electrically connected to the ground terminal; the second terminal of the second constant current source is electrically connected to the fourth voltage terminal; and the amplification gain of the third transistor and the sixth transistor is the same.

[0014] The equalizer provided in this application embodiment achieves good symmetry in the differential amplification path of the pre-amplifier sub-circuit by setting a third transistor and a sixth transistor with the same gain. This symmetry ensures that the two paths of the differential input signal receive completely consistent amplification, thereby improving the common-mode rejection ratio of the circuit and effectively suppressing common-mode noise and power supply disturbances. Simultaneously, it avoids output signal distortion caused by gain mismatch between the two paths, ensuring the fidelity of the amplified signal waveform and providing a clear and symmetrical input signal for the subsequent dynamic latching circuit, ultimately achieving high-precision, high-linearity signal amplification.

[0015] In one possible implementation of the first aspect, the third transistor is a P-channel MOS transistor and the sixth transistor is an N-channel MOS transistor.

[0016] In one possible implementation of the first aspect, the dynamic latch sub-circuit includes a first inverter and a second inverter, wherein the input terminal of the first inverter is connected to the output terminal of the second inverter, and the input terminal of the second inverter is connected to the output terminal of the first inverter.

[0017] The equalizer provided in this application embodiment achieves mutual compensation and shaping of signals through a dynamic latch composed of two inverters. When the input signal suffers from edge degradation or inter-symbol interference after amplification, its internal positive feedback mechanism can be used to quickly and forcibly regenerate and lock the signal. The two inverters act as loads and drivers for each other, compensating and accelerating each other during state switching, enabling the output signal to quickly move away from the unstable intermediate level and be shaped into a complete digital waveform with stable amplitude and steep edges. This effectively suppresses noise and jitter, improves the quality and integrity of the output signal, and thus ensures that the equalizer can stably and reliably recover data in high-speed data links.

[0018] In one possible implementation of the first aspect, the equalizer further includes a second-stage receiving circuit, the signal output terminal of which is electrically connected to the signal input terminal of the first-stage receiving circuit. The second-stage receiving circuit is used to perform suppression and recovery operations on the input signal to obtain an initial differential signal, and the first-stage receiving circuit is used to perform amplification, shaping, and phase selection operations on the input initial differential signal to obtain a target signal.

[0019] In a second aspect, a chip is provided, including a substrate and an equalizer disposed on the substrate, the equalizer including the equalizer of the first aspect.

[0020] Understandably, the technical effects of the second aspect refer to the technical effects of the first aspect and any of its embodiments, and will not be repeated here. Attached Figure Description

[0021] Figure 1 This is one of the circuit structure diagrams of an equalizer provided in an embodiment of this application; Figure 2 This is a second schematic diagram of the circuit structure of an equalizer provided in an embodiment of this application; Figure 3 This is the third schematic diagram of the circuit structure of an equalizer provided in the embodiments of this application; Figure 4 This is the fourth schematic diagram of the circuit structure of an equalizer provided in the embodiments of this application; Figure 5 Fifth schematic diagram of the circuit structure of an equalizer provided in the embodiments of this application; Figure 6 This is the sixth schematic diagram of the circuit structure of an equalizer provided in the embodiments of this application. Detailed Implementation

[0022] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0023] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, a particular feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0024] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0025] In describing some embodiments, the term "electrical connection" and its derivative expressions may be used. For example, the term "electrical connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact; in this case, "electrical connection" can also be described as "electrical connection". Furthermore, the term "electrical connection" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0026] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0027] "A and / or B" includes three combinations: A only, B only, and a combination of A and B. The use of "applies to" or "configured to" in this document implies open and inclusive language, which does not preclude applicability to or configuration to perform additional tasks or steps on devices. Additionally, the use of "based on" implies openness and inclusivity, as processes, steps, calculations, or other actions "based on" one or more conditions or values ​​may in practice be based on additional conditions or values ​​beyond those conditions.

[0028] The use of “configured as” in this article implies an open and inclusive language that does not exclude the applicability to or configuration of devices to perform additional tasks or steps.

[0029] In high-speed communication systems, the receiver (RX) circuit is a crucial component for signal recovery and processing, and its performance directly impacts the reliability and energy efficiency of the entire system. With the continuous advancement of semiconductor technology and the rapid development of artificial intelligence, data transmission rates are constantly increasing, placing more stringent demands on the RX circuit. It not only needs to implement complex functions within a limited area but also needs to minimize power consumption to meet the ever-growing design requirements of high-speed, highly integrated communication chips.

[0030] During signal transmission and reception by the radio frequency module, digital information is transmitted in the channel in the form of symbols, each symbol carrying several bits of data. However, due to constraints imposed by actual physical conditions, signal waveforms often undergo distortion during transmission, causing adjacent symbols to overlap in the time domain, resulting in inter-symbol interference (ISI). The causes of ISI can include channel bandwidth limitations, delay spread due to multipath propagation, and nonlinearity and frequency-selective fading of the transmission medium. Bandwidth limitations weaken high-frequency components of the signal, causing waveform broadening. Multipath effects cause the same signal to propagate along different paths, generating multiple delayed copies that superimpose at the receiver to form interference. Furthermore, imperfect receiver filter design can exacerbate ISI. ISI significantly increases the bit error rate and degrades signal quality, thus limiting the upper limits of system channel capacity and transmission rate.

[0031] To suppress the impact of ISI on signal integrity, an equalization circuit can be set in the receiving path to compensate for the distortion introduced by the channel and reconstruct the original signal waveform. The equalization circuit can dynamically adjust its frequency response according to the channel characteristics. Commonly used equalization circuits can include feed-forward equalization (FFE), continuous-time linear equalizer (CTLE), and decision-feedback equalizer (DFE).

[0032] FFE (Front-Field Equalization) is a typical time-domain linear equalization method, usually placed at the front end of the receiver link. Its core idea is to linearly superimpose the input signal with several historical symbol copies generated at different delays according to preset weights. By adjusting the weights of each tap, it compensates for inter-symbol interference caused by adjacent symbols in the channel. Due to its relatively simple structure, FFE is particularly suitable for handling scenarios where the channel response is symmetrical and crosstalk is mainly contributed by the current and a small number of neighboring symbols. CTLE (Cross-Field Equalization) is also a linear equalization method, often integrated into analog front-end circuits, used to address amplitude distortion caused by high-frequency attenuation. CTLE typically uses an analog filter network with high-frequency boosting characteristics to amplify the high-frequency components of the signal, thereby compensating for high-frequency losses caused by limited channel bandwidth and significantly improving eye diagram opening and signal edge quality. DFE (Dual-Field Equalization) is a type of nonlinear equalization architecture that uses the symbols already determined at the receiver as feedback terms to cancel interference on the currently processed symbol. Unlike FFE, which only performs forward linear processing, DFE introduces a feedback loop that can compensate for residual interference generated by past symbols. It is particularly suitable for high-speed links where linear equalization is difficult to completely eliminate crosstalk, and can significantly improve bit error rate performance under high code rate conditions.

[0033] In one feasible implementation, see [reference] Figure 1 The equalizer 100 shown may include a continuous-time linear equalizer 101 (CTLE) and a programmable gain amplifier (PGA) 102. The differential output of CTLE 101 is connected to the differential input of PGA 102. CTLE 101, as the first-stage processing unit in the receiving path, is responsible for performing continuous-time domain equalization on the input signal, effectively suppressing high-frequency noise and recovering the target signal attenuated by the channel. PGA 102, as the second stage, is used to adjust the signal amplitude, and its gain can be configured according to system requirements.

[0034] However, in the above implementation, the PGA's circuit structure is relatively complex, thus occupying a large physical area, which contradicts the design trend of modern chips towards small area and high integration. Furthermore, to ensure stable gain performance under various process deviations, voltage fluctuations, and temperature changes, the PGA needs to consider sufficient performance margins during the design phase and undergo complex gain configuration and calibration after production or during operation. This not only increases the time and cost of chip testing and calibration but also poses challenges to the overall reliability of the circuit. The core function of the PGA is to linearly amplify signals within the target frequency band. In high-speed data communication, the signal bandwidth is extremely wide, requiring the PGA to have a sufficiently high unity-gain bandwidth. To achieve this wideband amplification characteristic, the PGA often uses a large bias current, thus significantly increasing the overall static power consumption of the PGA module. This high power consumption cost for achieving bandwidth severely restricts the applicability of the receiving circuit in power-sensitive applications (such as mobile devices).

[0035] To address the aforementioned issues, embodiments of this application provide an equalizer that replaces the PGA's functionality by employing a simpler circuit structure and fewer components.

[0036] An equalizer may include a first-stage receiver circuit; see, for example, [link to example]. Figure 2 The schematic diagram of the circuit module structure of the first-stage receiving circuit 200 shown indicates that the first-stage receiving circuit 200 may include a pre-amplifier sub-circuit 201, a dynamic latch sub-circuit 202, and a phase selection sub-circuit 203. The input terminal of the pre-amplifier sub-circuit 201 is electrically connected to the signal input terminal of the first-stage receiving circuit 200. The first output terminal of the pre-amplifier sub-circuit 201 is electrically connected to the first input terminal of the dynamic latch sub-circuit 202, and the second output terminal of the pre-amplifier sub-circuit 201 is electrically connected to the second input terminal of the dynamic latch sub-circuit 202. The first output terminal of the dynamic latch sub-circuit 202 is electrically connected to the first input terminal of the phase selection sub-circuit 203, and the second output terminal of the dynamic latch sub-circuit 202 is electrically connected to the second input terminal of the phase selection sub-circuit 203. The first and second output terminals of the phase selection sub-circuit 203 are both electrically connected to the signal output terminal of the first-stage receiving circuit 200.

[0037] To achieve balanced output of high-speed differential signals, the first-stage receiving circuit 200 of this embodiment completes the entire process of signal enhancement, shaping, and phase selection in a step-by-step manner. First, the pre-amplifier sub-circuit 201 receives the initial differential signal from the signal input terminal, amplifies the amplitude of the initial differential signal through its internal amplification structure, and suppresses high-frequency attenuation due to link loss, thereby obtaining the first differential signal. Subsequently, the dynamic latch sub-circuit 202 acquires the first differential signal output from the pre-amplifier sub-circuit 201, and uses a dynamic latch structure composed of two inverters to shape and compensate the edges of the differential signal, enhancing the signal swing and transition speed, thereby forming a second differential signal with better transition characteristics. Finally, the phase selection sub-circuit 203 receives the second differential signal output from the dynamic latch sub-circuit 202, and selects different signal paths based on the enable control signal from the register, outputting the signal corresponding to either the first or second terminal as the final target signal, thus achieving flexible selection of the output signal phase.

[0038] Through the above-described step-by-step processing chain, the equalizer in this embodiment of the application can not only achieve equalization compensation for high-frequency attenuated signals in the analog domain, thus replacing the traditional programmable gain amplifier, but also significantly reduce the overall number of components by relying on simplified transistor structure and standard unit implementation method, thereby having the advantages of small area, low power consumption, simple design, and easy integration in high-speed digital interfaces.

[0039] In order to enable the preamplifier sub-circuit to switch flexibly between different operating modes, reduce system power consumption and analog noise interference when amplification is not required, and quickly restore normal operating gain when equalization is required, in one feasible implementation, the equalizer may also include a first register sub-circuit.

[0040] For example, see Figure 3 The first-stage receiving circuit 200 may further include a first register sub-circuit 204. The control terminal of the first register sub-circuit 204 is electrically connected to the input terminal of the pre-amplifier sub-circuit 201, and is used to provide an enable control signal EN to the pre-amplifier sub-circuit 201. In a specific implementation, when the enable signal EN output by the first register sub-circuit 204 is 0, the pre-amplifier sub-circuit 201 is turned off, and the internal transistors are in a cutoff or weak conduction state, so that the amplification path no longer works. At this time, the equalizer front end is equivalent to a pure digital logic structure, which can significantly reduce static power consumption and avoid noise and bias errors caused by analog amplification. When the enable signal EN output by the first register sub-circuit 204 is 1, the pre-amplifier sub-circuit 201 is turned on, the differential input path re-establishes the working bias, the circuit enters analog gain mode, and performs amplification operation on the initial differential input signal, providing a first differential signal with improved amplitude and edge for subsequent dynamic latching shaping and phase selection.

[0041] By configuring the first register sub-circuit described above, the equalizer in this embodiment can flexibly switch between off and on modes. In the off state, the equalizer is a purely digital circuit structure with extremely low power consumption, stable structure, and is suitable for system waiting or low load conditions. In the on state, the equalizer is an analog gain circuit, providing differential amplification capability to compensate for high-frequency losses in the preceding links and achieve effective equalization.

[0042] This not only improves the power efficiency of the entire equalization link, but also enhances the reliability and flexibility of the analog front end, ensuring optimal performance under different system operating conditions.

[0043] In one feasible implementation, in order to precisely control the phase of the equalizer output signal and maintain an adjustable and stable phase relationship with the input differential signal, the equalizer may also include a second register sub-circuit.

[0044] For further examples, please refer to [link / reference]. Figure 3 The first-stage receiving circuit 200 may further include a second register sub-circuit 205. The control terminal of the second register sub-circuit 205 is electrically connected to the first input terminal and the second input terminal of the phase selection sub-circuit 203, respectively, and is used to provide an enable control signal EN to the phase selection sub-circuit 203 to control the phase selection sub-circuit to switch the output between different differential paths.

[0045] Specifically, when the enable control signal EN is in the first state, the second register sub-circuit 205 outputs a corresponding enable signal, causing the phase selection sub-circuit 203 to select an output path that maintains a first phase relationship with the input differential signal. When the enable control signal EN is in the second state, the second register sub-circuit 205 outputs another set of enable signals, causing the phase selection sub-circuit 203 to switch to an output path that maintains a second phase relationship with the input differential signal.

[0046] As an example, the input terminals of the preamplifier sub-circuit include a first sub-input terminal and a second sub-input terminal. The first sub-input terminal is used to receive a first initial difference numerator signal, and the second sub-input terminal is used to receive a second initial difference numerator signal. When the enable signal EN output by the second register sub-circuit 205 is 1, the target signal output by the phase selection sub-circuit is in phase with the first initial difference numerator signal; when the enable signal EN output by the second register sub-circuit 205 is 0, the target signal output by the phase selection sub-circuit is in phase with the second initial difference numerator signal. Alternatively, when the enable signal EN output by the second register sub-circuit 205 is 0, the target signal output by the phase selection sub-circuit is in phase with the first initial difference numerator signal; when the enable signal EN output by the second register sub-circuit 205 is 1, the target signal output by the phase selection sub-circuit is in phase with the second initial difference numerator signal. The specific matching relationship can be adjusted according to actual needs, and this embodiment does not limit it.

[0047] In this way, the second register sub-circuit 205 can dynamically select the path of the phase selection sub-circuit 203, so that the equalizer can dynamically adjust the phase relationship of the output signal according to actual needs.

[0048] See Figure 4 The schematic diagram of the first-stage receiving circuit 200 shown includes a dynamic latch sub-circuit 202, which may include a first inverter 2021 and a second inverter 2022 for shaping and compensating the input differential signal. Specifically, the amplified differential signals are output to the dynamic latch sub-circuit 202 and then form a complementary dynamic latch structure through the first inverter 2021 and the second inverter 2022. In this structure, the two inverters provide feedback to each other, and the differential signal is rapidly compensated and shaped through dynamic latching.

[0049] The circuit structure of the preamplifier sub-circuit can linearly amplify the input differential signal and provide sufficient driving capability to ensure that the subsequent dynamic latch sub-circuit can obtain a first differential signal with stable amplitude and moderate swing under high-speed conditions.

[0050] For example, see Figure 5The equivalent circuit diagram of the preamplifier sub-circuit shown includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a first constant current source I1, and a second constant current source I2. The first terminal of the first transistor M1 is electrically connected to a first voltage terminal, the second terminal of the first transistor M1 is electrically connected to the first terminal of the second transistor M2, and the control terminal of the first transistor M1 is electrically connected to a first sub-input terminal. The second terminal of the second transistor M2 is electrically connected to the first terminal of the first constant current source I1, and the control terminal of the second transistor M2 is electrically connected to the first sub-input terminal. The first terminal of the third transistor M3 is electrically connected to a second voltage terminal, the second terminal of the third transistor M3 is electrically connected to the second terminal of the first transistor M1, and the control terminal of the third transistor M3 is electrically connected to a third voltage terminal. The first terminal of the fourth transistor M4 is electrically connected to a second voltage terminal, the second terminal of the fourth transistor M4 is electrically connected to the first terminal of the fifth transistor M5, and the control terminal of the fourth transistor M4 is electrically connected to a second sub-input terminal. The second terminal of the fifth transistor M5 is electrically connected to the ground terminal, and the control terminal of the fifth transistor M5 is electrically connected to the second sub-input terminal. The first terminal of the sixth transistor M6 is electrically connected to the second terminal of the fourth transistor M4, and the second terminal of the sixth transistor M6 is electrically connected to the ground terminal. The control terminal of the sixth transistor M6 is also electrically connected to the ground terminal. The second terminal of the first constant current source I1 is electrically connected to the ground terminal, and the second terminal of the second constant current source is electrically connected to the fourth voltage terminal.

[0051] In one feasible implementation, the third transistor M3 can be a P-channel MOS transistor, and the sixth transistor M6 can be an N-channel MOS transistor. The source of the third transistor M3 is connected to the second voltage terminal to provide pull-up current to the differential node, the drain is connected to the connection node of the first transistor M1 and the second transistor M2 to perform pull-up drive on the amplification node, and the gate is connected to the third voltage terminal to control the conduction state of the PMOS.

[0052] The source of the sixth transistor M6 is connected to the ground terminal to provide a fast discharge path for the connection node of the fourth transistor M4 and the fifth transistor M5. The drain is connected to the second terminal of the fourth transistor M4 to perform pull-down drive for the differential node. The gate is connected to the ground terminal or fixed low level to keep the transistor in the off state, thereby providing a stable bias condition for the common mode level.

[0053] In addition, to ensure that the differential amplifier structure obtains consistent current drive capability and voltage gain on both amplification paths, in one alternative implementation, the third transistor M3 and the sixth transistor M6 can be of the same size, so that the amplification gain of the two differential paths remains the same.

[0054] By setting the third and sixth transistors to have the same gain, the differential amplification path of the pre-amplifier sub-circuit achieves good symmetry. This symmetry ensures that the two paths of the differential input signal receive completely identical amplification, thereby improving the circuit's common-mode rejection ratio and effectively suppressing common-mode noise and power supply disturbances. Simultaneously, it avoids output signal distortion caused by gain mismatch between the two paths, guaranteeing the fidelity of the amplified signal waveform and providing a clear and symmetrical input signal for the subsequent dynamic latching circuit, ultimately achieving high-precision, high-linearity signal amplification.

[0055] This implementation also provides an equalizer, see [link / reference] Figure 6 The equalizer 300 may include a continuous-time linear equalizer 101 (second-stage receiving circuit) and a first-stage receiving circuit 200. The continuous-time linear equalizer 101 and the first-stage receiving circuit 200 are electrically connected. The continuous-time linear equalizer 101 is used to perform suppression and recovery operations on the input signal to obtain an initial differential signal. The first-stage receiving circuit 200 is used to perform amplification, shaping, and phase selection operations on the input initial differential signal to obtain a target signal.

[0056] Thirdly, a chip is provided, including a substrate and an equalizer disposed on the substrate, the equalizer including the equalizer provided in the above embodiments.

[0057] It should be noted that the chip provided in the embodiments of this application can be any one of a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), a neural network processing unit (NPU), a deep learning processing unit (DPU), an accelerated processing unit (APU), and a general-purpose graphics processing unit (GPGPU).

[0058] It should be noted that the above division of modules is only for the convenience of description and functional division. In actual implementation, a module can be implemented by multiple modules, and the functions of multiple modules can also be implemented by the same module. These modules can be located in the same device or in different devices.

[0059] The hardware modules in the implementation can be implemented mechanically or electronically. For example, a hardware module may include specially designed permanent circuitry or logic devices (such as dedicated processors, such as FPGAs or ASICs) to perform specific operations. For instance, specific operations can be performed within various types of chips (e.g., artificial intelligence chips). Hardware modules may also include programmable logic devices or circuitry (such as general-purpose processors or other programmable processors) temporarily configured by software to perform specific operations. The choice between mechanical implementation, dedicated permanent circuitry, or temporarily configured circuitry (e.g., software-configured) for the hardware module can be based on cost and time considerations.

[0060] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification. The above embodiments only illustrate several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this application's patent. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

[0061] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features in the formula. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An equalizer, characterized in that, It includes a first-stage receiving circuit, which includes: a pre-amplifier sub-circuit, a dynamic latch sub-circuit, and a phase selection sub-circuit. The input terminal of the preamplifier sub-circuit is electrically connected to the signal input terminal of the first receiving circuit, the first output terminal of the preamplifier sub-circuit is electrically connected to the first input terminal of the dynamic latch sub-circuit, and the second output terminal of the preamplifier sub-circuit is electrically connected to the second input terminal of the dynamic latch sub-circuit. The first output terminal of the dynamic latch sub-circuit is electrically connected to the first input terminal of the phase selection sub-circuit, and the second output terminal of the dynamic latch sub-circuit is electrically connected to the second input terminal of the phase selection sub-circuit. The first output terminal of the phase selection sub-circuit is electrically connected to the signal output terminal of the first-stage receiving circuit, and the second output terminal of the phase selection sub-circuit is electrically connected to the signal output terminal of the first-stage receiving circuit.

2. The equalizer according to claim 1, characterized in that, The preamplifier sub-circuit is used to receive the initial differential signal and amplify the initial differential signal to obtain the first differential signal; The dynamic latch sub-circuit is used to receive the first differential signal and perform a shaping operation on the first differential signal to obtain the second differential signal; The phase selection sub-circuit is used to receive the second differential signal and perform a phase selection operation on the second differential signal to obtain the target signal.

3. The equalizer according to claim 2, characterized in that, The first-stage receiving circuit also includes a first register sub-circuit, the control terminal of which is electrically connected to the input terminal of the pre-amplifier sub-circuit; The first register sub-circuit is used to: turn off the preamplifier sub-circuit when the first enable signal is output; When the second enable signal is output, the preamplifier sub-circuit is turned on to perform an amplification operation on the initial differential signal.

4. The equalizer according to claim 1, characterized in that, The first-stage receiving circuit also includes a second register sub-circuit, the control terminal of which is electrically connected to the first and second input terminals of the phase selection sub-circuit. The second register sub-circuit is used to switch the signal output path of the phase selection sub-circuit according to the type of the output enable signal.

5. The equalizer according to claim 4, characterized in that, The input terminals of the preamplifier sub-circuit include a first sub-input terminal and a second sub-input terminal. The first sub-input terminal is used to receive a first initial difference numerator signal, and the second sub-input terminal is used to receive a second initial difference numerator signal. The second register sub-circuit is specifically used to: when outputting the first enable signal, make the target signal output by the phase selection sub-circuit have the same phase as the first initial difference numerator signal; When the second enable signal is output, the target signal output by the phase selection sub-circuit is made to have the same phase as the second initial difference numerator signal.

6. The equalizer according to claim 5, characterized in that, The preamplifier sub-circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first constant current source, and a second constant current source; The first terminal of the first transistor is electrically connected to the first voltage terminal, the second terminal of the first transistor is electrically connected to the first terminal of the second transistor, and the control terminal of the first transistor is electrically connected to the first sub-input terminal. The second terminal of the second transistor is electrically connected to the first terminal of the first constant current source, and the control terminal of the second transistor is electrically connected to the first sub-input terminal; The first terminal of the third transistor is electrically connected to the second voltage terminal, the second terminal of the third transistor is electrically connected to the second terminal of the first transistor, and the control terminal of the third transistor is electrically connected to the third voltage terminal. The first terminal of the fourth transistor is electrically connected to the first terminal of the second constant current source, the second terminal of the fourth transistor is electrically connected to the first terminal of the fifth transistor, and the control terminal of the fourth transistor is electrically connected to the second sub-input terminal. The second terminal of the fifth transistor is electrically connected to the ground terminal, and the control terminal of the fifth transistor is electrically connected to the second sub-input terminal; The first terminal of the sixth transistor is electrically connected to the second terminal of the fourth transistor, the second terminal of the sixth transistor is electrically connected to the ground terminal, and the control terminal of the sixth transistor is electrically connected to the ground terminal. The second end of the first constant current source is electrically connected to the ground terminal; The second terminal of the second constant current source is electrically connected to the fourth voltage terminal, and the third transistor has the same amplification gain as the sixth transistor.

7. The equalizer according to claim 6, characterized in that, The third transistor is a P-channel MOS transistor, and the sixth transistor is an N-channel MOS transistor.

8. The equalizer according to claim 1, characterized in that, The dynamic latch sub-circuit includes a first inverter and a second inverter; The input terminal of the first inverter is connected to the output terminal of the second inverter; The input terminal of the second inverter is connected to the output terminal of the first inverter.

9. The equalizer according to any one of claims 1-8, characterized in that, The equalizer further includes a second-stage receiving circuit, the signal output terminal of which is electrically connected to the signal input terminal of the first-stage receiving circuit. The second-stage receiving circuit is used to perform suppression and recovery operations on the input signal to obtain an initial differential signal. The first-stage receiving circuit is used to perform amplification, shaping, and phase selection operations on the input initial differential signal to obtain a target signal.

10. A chip, characterized in that, It includes a substrate and an equalizer disposed on the substrate, the equalizer including the equalizer as described in any one of claims 1-9.

Images