Dual feedback integral type bit synchronization loop and bit synchronization method of digital communication system
By using a dual-feedback integral-type bit synchronization loop, combined with a filter feedback loop and a threshold feedback loop, the threshold is dynamically adjusted, solving the problems of long acquisition time and phase jitter in digital communication systems, and achieving fast and stable bit synchronization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-28
- Publication Date
- 2026-04-14
AI Technical Summary
In existing digital communication systems, the digital phase-locked loop (PLL) method has a long acquisition time and phase jitter in a stable state. Traditional filtering methods are difficult to accurately determine the threshold and cannot adapt to scenarios where the sampled quantization value changes dynamically.
A dual-feedback integral-type position synchronization loop is adopted, which combines a filter feedback loop and a threshold feedback loop. Through the coordinated operation of an arbitrator, the filter feedback loop outputs the local position synchronization signal clock of the filter feedback loop in the capture state, and the threshold feedback loop outputs the local position synchronization signal clock of the threshold feedback loop in the phase-locked state. The threshold threshold is dynamically adjusted to overcome the problems of phase jitter and inaccurate threshold.
It achieves fast acquisition and stable bit synchronization, avoids phase jitter in phase-locked loop, and adapts to dynamic changes in sampled quantization values, thereby improving the synchronization accuracy and applicability of the system.
Smart Images
Figure CN121217529B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of digital communication technology, and more specifically to a dual-feedback integral bit synchronization loop and bit synchronization method for a digital communication system. Background Technology
[0002] Bit synchronization, also known as symbol synchronization, timing synchronization, or code element synchronization, is a unique synchronization technique in the field of digital communication. After coherent demodulation and sampling decision-making, the receiver recovers the original signal from the transmitter. However, due to channel transmission delays and clock discrepancies between the transmitter and receiver, the receiver's sampling decision cannot be performed at the optimal time, resulting in a deviation between the recovered signal and the transmitted signal. To obtain the optimal sample value for recovering the transmitted signal, the receiver's clock must be synchronized with the transmitter's clock; this process of adjusting the receiver's clock synchronization is called bit synchronization.
[0003] Currently, the mainstream bit synchronization methods include pilot methods, filtering methods, interpolation methods, and digital phase-locked loops (PLLs). Among them, although the digital PLL can achieve synchronization by adjusting the local clock frequency and phase, and has the advantages of high accuracy, minimal steady-state error, and adaptability to a certain range of frequency offsets, its acquisition time is relatively long, and phase jitter may exist in the steady state. Summary of the Invention
[0004] This application addresses the shortcomings of existing technologies by providing a dual-feedback integral-type bit synchronization loop and bit synchronization method for a digital communication system. Through the synergy of a filtering feedback loop and a threshold feedback loop, this application effectively overcomes the problem that traditional threshold-based bit synchronization techniques cannot accurately determine the threshold value in the capture state (phase adjustment state), making them difficult to apply to scenarios with dynamically changing sampled quantization values. Simultaneously, it overcomes the persistent and difficult-to-eliminate phase jitter problem after phase locking in traditional filtering-based bit synchronization techniques. The specific technical solution adopted in this application is as follows.
[0005] First, to achieve the above objectives, a dual-feedback integral-type position synchronization loop for a digital communication system is proposed, comprising: a clock conversion circuit for generating two clock signals; a filter feedback loop for generating a local position synchronization signal clock signal based on the input signal and the clock signal; a threshold feedback loop for generating a threshold feedback loop local position synchronization signal clock signal based on the input signal and the clock signal; and an arbitrator that outputs the local position synchronization signal clock signal when the filter feedback loop meets the requirements, and adjusts the threshold feedback loop and outputs the threshold feedback loop local position synchronization signal clock signal when the filter feedback loop fails to meet the requirements. The filter feedback loop performs lead-lag phase detection and generates a position synchronization signal according to the principle of an improved random oscillation filtering method. Simultaneously, its controller generates a filter loop phase-locked state signal, which is initially low and pulls high when the filter feedback loop enters the phase-locked state and generates stable jitter. The filter feedback loop sends this filter loop phase-locked state signal and the quadrature signal generated by the integrator to the arbitrator.
[0006] Optionally, the dual-feedback integral-type position synchronization loop of the digital communication system described above includes: a first integrator for integrating the input signal; a first phase detector for phase detection of the integrated signal; a first filter for cyclically counting based on the detection signals of the lead and lag states output by the first phase detector; and a first controller that is triggered to output a phase-locked state signal of the filter loop when the filter count is full, and performs phase adjustment on the clock signal output by the clock conversion circuit based on the lead and lag signals to generate a local position synchronization signal clock for the filter feedback loop.
[0007] Optionally, in any of the above-described digital communication systems, a dual-feedback integral-type position synchronization loop is provided, wherein the threshold feedback loop specifically performs the following steps: a second integrator, used to sequentially integrate the input signal; a second phase detector, used to perform phase detection when the absolute value of the integration reaches a threshold; and a second controller, used to adjust the phase of the clock signal output by the clock conversion circuit according to the detection signals of the leading and lagging states output by the second phase detector, thereby generating a local position synchronization signal clock for the threshold feedback loop.
[0008] Optionally, in the dual-feedback integral-type position synchronization loop of the digital communication system described above, the arbitrator outputs the local position synchronization signal clock of the filter feedback loop when the filter feedback loop enters the capture state, based on the phase-locked state signal of the filter loop, and sets the threshold of the threshold feedback loop according to the voltage value of the current input signal when entering the tracking stage, and outputs the local position synchronization signal clock of the threshold feedback loop.
[0009] Optionally, in any of the above-described digital communication systems, a dual-feedback integral-type position synchronization loop is provided, wherein the arbitrator also switches to outputting the local position synchronization signal clock of the filter feedback loop when the filter feedback loop is in the capture state.
[0010] Optionally, in the dual-feedback integral-type position synchronization loop of the digital communication system described above, the arbitrator also sets the threshold of the threshold feedback loop to 0 while outputting the local position synchronization signal clock of the filter feedback loop.
[0011] Optionally, the dual-feedback integral-type position synchronization loop of the digital communication system described above is provided, wherein the threshold of the threshold feedback loop is set according to the absolute value of the output signal of the first integrator in the filter feedback loop.
[0012] To achieve the above objectives, this application also provides a bit synchronization method that uses a dual-feedback integral bit synchronization loop of the digital communication system described above. The steps include: based on the phase-locked loop state signal of the filter loop, outputting a local bit synchronization signal clock signal of the filter feedback loop when the filter feedback loop enters the capture state, and outputting a local bit synchronization signal clock signal of the threshold feedback loop when the filter feedback loop enters the tracking stage; wherein the filter feedback loop independently generates the local bit synchronization signal clock signal of the filter feedback loop based on the input signal; and the threshold feedback loop dynamically generates the local bit synchronization signal clock signal of the threshold feedback loop based on the input signal according to the threshold adjusted by the filter feedback loop.
[0013] Optionally, in any of the bit synchronization methods described above, the step for determining whether the filter feedback loop meets the requirements is: the filter feedback loop is in the capture state, or the filter feedback loop is in the locked state and no phase stability jitter occurs.
[0014] Alternatively, the bit synchronization method described above may be used in which the filtering feedback loop and the threshold feedback loop operate independently of each other.
[0015] Beneficial effects
[0016] The dual-feedback integral-type bit synchronization loop and bit synchronization method for digital communication systems provided in this application simultaneously trigger the filter feedback loop and the threshold feedback loop to independently generate local bit synchronization signal clock signals for the filter feedback loop and the threshold feedback loop, based on the local clock and the input signal. Then, according to the state of the filter feedback loop, one of them is selected for output. Therefore, this application can utilize the filter feedback loop to avoid potential non-convergence of the threshold feedback loop due to inaccurate threshold settings. Correspondingly, after the filter feedback loop successfully captures and enters phase-locked state, it switches to the synchronization clock of the threshold feedback loop, thereby avoiding the phase jitter problem caused by continuing to use the filter feedback loop in phase-locked state through the threshold feedback loop.
[0017] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing this application. Attached Figure Description
[0018] The accompanying drawings are provided to further illustrate the present application and form part of the specification. Together with the embodiments of the present application, they serve to explain the present application but do not constitute a limitation thereof. In the drawings:
[0019] Figure 1 This is a schematic diagram of the principle of a traditional integral-type synchronization loop;
[0020] Figure 2 yes Figure 1 A schematic diagram of the signal that causes lead-lag phase jitter after the medium-integration synchronous loop reaches the phase-locked state;
[0021] Figure 3 This is a schematic diagram of the dual-feedback integral-type position synchronization loop of the digital communication system used in this application;
[0022] Figure 4 yes Figure 3 The signal diagram of the dual-feedback integral-type position synchronization loop is shown below;
[0023] Figure 5 This is a schematic diagram of the threshold phase detector used in the threshold feedback loop of the dual-feedback integral-type position synchronization loop in this application;
[0024] Figure 6 yes Figure 5 The signal diagram of the threshold phase detector is shown below.
[0025] Figure 7 This is a schematic diagram of the improved filter used in the filter feedback loop of the dual-feedback integral-type position synchronization loop in this application;
[0026] Figure 8 yes Figure 7 The signal diagram of the threshold phase detector is shown. Detailed Implementation
[0027] To make the objectives and technical solutions of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the described embodiments of this application without creative effort are within the scope of protection of this application.
[0028] Those skilled in the art will understand that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless defined as herein.
[0029] The term "connection" as used in this application can mean a direct connection between components or an indirect connection between components through other components.
[0030] Figure 1 The existing bit synchronization technology uses an integrating synchronization loop consisting of an integrator, phase detector, controller, frequency divider, and clock conversion circuit. The input signal is integrated to generate an integral signal for phase detection. The phase detector detects whether the polarity signal generated by the integrator is ahead or behind. The clock conversion circuit generates two pulse sequences staggered by one local crystal oscillator clock. The trigger controller controls the input pulse sequence of the frequency divider based on the lead / lag signal and the pulse signal generated by the local crystal oscillator. Ultimately, the frequency divider generates two local bit synchronization signal clocks based on the adjusted lead / lag clock. This integrating bit synchronization circuit benefits from the advantages of the integrator and has good anti-interference capabilities. However, even after reaching phase-locked state, it still exhibits phase jitter due to lead and lag, such as... Figure 2 As shown, pd_bef and pd_aft are the lead and lag signals, respectively. It can be seen that stable jitter still exists in the phase-locked state.
[0031] To address the jitter issue, this application provides a novel bit synchronization method, which independently generates a local bit synchronization signal clock signal for the filter feedback loop based on the local crystal oscillator and the input signal, and generates a local bit synchronization signal clock signal for the threshold feedback loop based on the threshold feedback loop.
[0032] Both signals are input to the arbitrator, which outputs a local position synchronization clock signal for the filter feedback loop based on the state of the filter feedback loop: when the filter feedback loop meets the requirements, it outputs a local position synchronization clock signal for the threshold feedback loop; when the filter feedback loop fails to meet the requirements, it outputs a local position synchronization clock signal for the threshold feedback loop. This avoids the problems caused by the threshold feedback loop: if the threshold value is too large, the AND gate Chk will be normally closed, preventing phase adjustment of the position synchronization loop; or if the threshold value is too small, the AND gate Chk will be normally open, rendering the detection meaningless. Simultaneously, it effectively solves the synchronization accuracy problem caused by the reversible counter of the filter feedback loop oscillating around the N value when lead and lag signals occur randomly, failing to output either lead or lag signals and thus not adjusting the phase of the synchronization signal.
[0033] For details, please refer to the following: Figure 3 The dual-feedback integral-type position synchronization loop of the digital communication system provided in this application can be specifically configured to include:
[0034] The clock conversion circuit generates two clock signals based on a local crystal oscillator and simultaneously feeds them into a filter feedback loop and a threshold feedback loop;
[0035] The filtering feedback loop generates a local local synchronization clock signal based on the input signal and the clock signal.
[0036] The threshold feedback loop generates a local position synchronization signal clock signal based on the input signal and the clock signal.
[0037] The outputs of both loops are simultaneously fed into the arbitrator. When the filter feedback loop meets the criteria, i.e., when it enters the acquisition state, the arbitrator selects the local local synchronization signal clock signal of the filter feedback loop for output. When the filter feedback loop does not meet the criteria, i.e., when the phase jitter in the acquisition stage tends to stabilize (such as when there is a regular periodic switching between lead and lag), when it enters the tracking stage, the threshold feedback loop is adjusted, and the arbitrator is switched to select the local local synchronization signal clock signal of the threshold feedback loop for output.
[0038] Its working principle is as follows: The input signal data_in is sent to the integrators of the two feedback loops, which perform in-phase and quadrature integration respectively. The filter feedback loop performs lead-lag phase detection and generates a bit synchronization signal according to the principle of the improved random lingering filter method. At the same time, its controller generates the filter loop phase-locked state signal (stb_jit). stb_jit is initially low. When the filter feedback loop enters the phase-locked state and generates stable jitter, stb_jit is pulled high. The filter feedback loop sends the stb_jit signal and the quadrature signal generated by the integrator to the arbiter. The threshold of the threshold feedback loop is no longer a fixed constant, but uses the int_q_thr generated by the arbiter as the absolute value of the threshold. The arbiter first selects the bit synchronization clock based on stb_jit. When stb_jit is low, the bit synchronization signal of the filter feedback loop is selected, and int_q_thr is set to 0 (equivalent to not adding a threshold to the threshold feedback loop). When stb_jit is high, the bit synchronization signal of the threshold feedback loop is selected, and the absolute value of the quadrature signal generated by the filter feedback loop is given to the int_q_thr output, and adjusted in real time according to the minimization operation (updating to this value when a smaller absolute value of the quadrature signal is available). In this way, the threshold obtained by the threshold feedback loop is updated in real time entirely based on the voltage value of the current input signal. If the filter feedback loop exits the phase-locked state and re-enters the capture state due to signal instability, the arbiter will reselect the bit synchronization signal of the filter feedback loop and set int_q_thr to 0.
[0039] In other words, when in the capture state, a filter feedback loop is used for capture (avoiding the possibility of non-convergence due to inaccurate threshold settings in the threshold feedback loop). After successful capture and entering the phase-locked state, the circuit switches to the threshold feedback loop for tracking. At this time, the threshold is an accurate quadrature integral signal of the filter feedback loop in the phase-locked state, which can ensure that the threshold feedback loop will converge and also avoid the phase jitter problem caused by continuing to use the filter feedback loop.
[0040] The results are as follows Figure 4As shown in the diagram, the upper red box represents the filter feedback loop signal, the lower red box represents the threshold feedback loop, and the final rec_clk (pink signal) is the final output bit synchronization clock. It can be seen that when stb_jit (purple signal) is low, the filter feedback loop is still in the capture phase, and rec_clk takes the bit synchronization clock output (clk_i_0) from the filter feedback loop. When stb_jit goes high, indicating that the filter feedback loop has completed capture and entered phase-locked loop (PLL) mode, rec_clk takes the bit synchronization clock output (clk_i_1) from the threshold feedback loop. Although the lead / lag signal of the filter feedback loop fluctuates back and forth at this time, it does not affect the final output rec_clk. Therefore, this application can effectively overcome phase jitter and ensure output convergence, thereby stably obtaining the bit synchronization clock.
[0041] In the specific implementation process, this application may adopt Figure 5 The principle shown is used to construct the threshold phase detector in the threshold feedback loop. It judges the output of the quadrature integrator; only when the absolute value of the integral is greater than a certain threshold is phase adjustment allowed; otherwise, phase adjustment is not performed. This effectively filters out jitter in the phase-locked loop and obtains... Figure 6 The waveform is shown. The result of the threshold feedback loop operating independently is shown in throughput 6. After entering the phase-locked loop state, pd_bef and pd_aft no longer generate pulse signals. However, it can be seen that when the threshold loop operates independently, due to the relatively mechanical setting of the threshold value, if the threshold value is too large, the AND gate Chk will be in a normally closed state, and the bit synchronization loop will not be able to perform phase adjustment; if the threshold value is too small, the AND gate Chk will be in a normally open state, losing its detection significance. Therefore, in this application, through... Figure 7 The filter loop shown dynamically determines the appropriate decision threshold.
[0042] In this filtering loop, a counter is used to raise the output condition for leading or lagging signals. A random oscillation filter structure is used, with the input of the random oscillation filter set to the leading and lagging signals output by the phase detector, and its counter is initially set to N. Therefore, when a leading pulse arrives, the counter increments by 1; when a lagging pulse arrives, the counter decrements by 1. Only when the counter reaches 2N or 0 will it output a leading or lagging signal, and simultaneously reset the counter to N. When leading and lagging signals occur randomly, the 2N reversible counter oscillates around the value of N, without outputting a leading or lagging signal, and thus does not adjust the phase of the synchronization signal.
[0043] This application preferably adds two more flip-flops to control the switching of lead and lag signals: when there are more than N consecutive lead (or lag) signals input, the filter outputs one lead (or lag) signal, causing flip-flop C1 (or C2) to output a high-level signal and open AND gate A1 (or A2). The input lead (or lag) signals can then be applied to the phase adjustment circuit through these two AND gates. If the phase detector continues to output lead (or lag) signals at this time, since the output of the flip-flop has already opened the AND gate, these pulses can be continuously sent to the phase adjustment circuit without waiting for the digital filter to count N pulses before outputting one pulse, thus shortening the phase adjustment time.
[0044] The operating results of this improved filter when operating alone are as follows: Figure 8 As shown, (taking a leading signal as an example), after a continuous pd_bef pulse generates one ms_bef, another bef_bef is generated, and a new ms_bef is generated immediately, greatly reducing the phase adjustment time. For random interference, sporadic leading (or lagging) signals from the phase detector output will set flip-flop C2 (or C1) to 0, at which point the entire circuit returns to the state of a normal random oscillation filter, still possessing good anti-interference capability. Simultaneously, it can be seen that when this filter loop operates independently, although it can solve the problem of excessively long phase adjustment time by adding flip-flops, phase jitter after phase locking still exists (although its jitter frequency is greatly reduced compared to a traditional integrating phase synchronization loop), and its jitter frequency is affected by N; the larger N is, the smaller the jitter frequency.
[0045] However, when this application dynamically links the filtering loop and the threshold loop through the arbitrator setting, it can utilize the advantages of the threshold method to eliminate phase jitter in the phase-locked state, and also utilize the advantages of the filtering method to ensure that the threshold of the capture state (phase adjustment state) can be flexibly adjusted according to the dynamic changes in the sampled quantization value. Simultaneously, this application can also utilize the advantages of the filtering method to use a trigger to solve the problem of excessively long phase adjustment time, and, through the supplement of the threshold method, avoid phase jitter in the output signal after phase-locking in the filtering loop.
[0046] This application combines the filtering method and the threshold method in an integral-type position synchronization loop to design a dual-feedback loop integral-type position synchronization loop. It cleverly uses an arbitrator to solve the problem of selecting the recovery clock. During the acquisition phase, the position synchronization clock of the filtering feedback loop is selected; during the phase-locked loop phase, the position synchronization clock of the threshold feedback loop is selected. Simultaneously, the absolute value of one of the signals output by the integrator in the filtering loop can be used to adjust the threshold in the threshold loop. Based on the quadrature integral signal when the filtering feedback loop enters the phase-locked state, the convergence of the threshold feedback loop is guaranteed.
[0047] In summary, this application, through a dual-loop design and the selection of an arbitrator, can eliminate phase jitter in phase-locked state using a threshold feedback loop, and overcome the problem that the threshold feedback loop cannot accurately determine the threshold threshold in the capture state (phase adjustment state) and cannot adapt to scenarios with dynamically changing sampled quantization values by using the output of the filter feedback loop. Simultaneously, it can also solve the problem of excessively long phase adjustment time using the filter feedback loop, and avoid phase jitter after phase-locking by supplementing the threshold feedback loop. While combining the advantages of the two loop schemes, it can also effectively eliminate the disadvantages of each by selecting the output signal.
[0048] Furthermore, this application addresses the issue of unstable signal levels in practical applications by adjusting the threshold value determined in the threshold feedback loop from a fixed value to a dynamic value based on the absolute value of the quadrature signal generated by the filter feedback loop (i.e., the absolute value of one of the signals output by the integrator in the filter feedback loop). Therefore, this application can determine the threshold threshold based on the current input signal voltage, avoiding the limitation of a single threshold method being unable to determine the threshold. Through the filter feedback loop, this application can generate a more optimal threshold value for the current situation when tracking is achieved, which is used for the threshold loop to perform tracking. This provides more precise control for the threshold feedback loop, thereby further improving the overall output quality of the system and making it suitable for a wider range of application scenarios.
[0049] The above are merely embodiments of this application, and their descriptions are quite specific and detailed, but they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application.
Claims
1. A dual-feedback integral-type position synchronization loop for a digital communication system, characterized in that, include: Clock conversion circuit, used to generate two clock signals; The filter feedback loop is used to generate the local local synchronization signal clock signal of the filter feedback loop based on the input signal and the clock signal. The threshold feedback loop is used to generate a local position synchronization signal clock signal for the threshold feedback loop based on the input signal and the clock signal. The arbitrator outputs a local synchronization clock signal for the filter feedback loop when the filter feedback loop meets the requirements, and adjusts the threshold feedback loop and outputs a local synchronization clock signal for the threshold feedback loop when the filter feedback loop fails to meet the requirements. The filter feedback loop performs lead-lag phase detection and generates a bit synchronization signal according to the principle of the improved random wandering filter method. At the same time, it generates a filter loop phase-locked state signal through its controller. The filter loop phase-locked state signal is initially low level. When the filter feedback loop enters the phase-locked state and generates stable jitter, it is pulled high. The filter feedback loop sends the filter loop phase-locked state signal and the quadrature signal generated by the integrator to the arbitrator. The filter feedback loop includes: The first integrator is used to integrate the input signal; The first phase detector is used to perform phase detection processing on the integrated signal; The first filter is used to cyclically count based on the detection signals of the leading and lagging states output by the first phase detector; The first controller is triggered to output the phase-locked state signal of the filter loop when the filter counter is full, and adjusts the phase of the clock signal output by the clock conversion circuit according to the lead signal and the lag signal to generate the local synchronization signal clock of the filter feedback loop.
2. The dual-feedback integral-type position synchronization loop of the digital communication system as described in claim 1, characterized in that, The threshold feedback loop specifically executes the following steps: The second integrator is used to integrate the input signal sequentially. The second phase detector is used to perform phase detection when the absolute value of the integral reaches a threshold. The second controller is used to adjust the phase of the clock signal output by the clock conversion circuit according to the detection signals of the leading and lagging states output by the second phase detector, and generate a local position synchronization signal clock for the threshold feedback loop.
3. The dual-feedback integral-type position synchronization loop of the digital communication system as described in claim 2, characterized in that, The arbitrator, based on the phase-locked state signal of the filter loop, outputs a local synchronization signal clock for the filter feedback loop when the filter feedback loop enters the capture state, and sets the threshold of the threshold feedback loop according to the voltage value of the current input signal when entering the tracking stage, and outputs a local synchronization signal clock for the threshold feedback loop.
4. The dual-feedback integral-type position synchronization loop of the digital communication system as described in claim 3, characterized in that, The arbitrator also switches to outputting the local local synchronization signal clock of the filter feedback loop when the filter feedback loop is in the capture state.
5. The dual-feedback integral-type position synchronization loop of the digital communication system as described in claim 3, characterized in that, The arbitrator also sets the threshold of the threshold feedback loop to 0 while outputting the local position synchronization signal clock of the filter feedback loop.
6. The dual-feedback integral-type position synchronization loop of the digital communication system as described in claim 3, characterized in that, The threshold of the threshold feedback loop is set according to the absolute value of the output signal of the first integrator in the filter feedback loop.
7. A bit synchronization method, characterized in that, Using a dual-feedback integral-type position synchronization loop in a digital communication system as described in any one of claims 1-6, the steps include: Based on the phase-locked state signal of the filter loop, when the filter feedback loop enters the capture state, the local position synchronization signal clock signal of the filter feedback loop is output, and when the filter feedback loop enters the tracking stage, the local position synchronization signal clock signal of the threshold feedback loop is output. The filter feedback loop independently generates a local position synchronization clock signal based on the input signal. The threshold feedback loop adjusts its threshold according to the filter feedback loop, and dynamically generates a local position synchronization clock signal for the threshold feedback loop based on the input signal according to the threshold.
8. The bit synchronization method as described in claim 7, characterized in that, The steps for determining whether the filter feedback loop meets the requirements are as follows: The filter feedback loop is in the capture state, or the filter feedback loop is in the locked state and no phase stability jitter occurs.
9. The bit synchronization method as described in claim 7, characterized in that, The filter feedback loop and the threshold feedback loop operate independently of each other.