Silicon carbide groove MOSFET device

Abstract

The invention relates to the technical field of power semiconductor devices, and discloses a silicon carbide trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device, which comprises an N-type substrate, the N-type drift region is arranged on the N-type substrate; the trench is arranged in the N-type drift region and extends downwards from the upper surface of the device; the gate structure is accommodated in the groove and comprises a polysilicon gate medium and a polysilicon gate; a P-well region disposed in the N-type drift region and adjacent to the trench; the N + contact region is arranged in the P-well region; the shielding structure is located below the P-well region, the shielding structure comprises a P-shield 1 region and a P-shield 2 region, the P-shield 1 region and the P-shield 2 region are transversely arranged at an interval, and a CSL region is arranged between the P-shield region and the P-shield region. The heterojunction diode formed by the P + poly region and the N + contact region is integrated in the device, so that the energy efficiency and the working reliability of the device in high-frequency application are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power semiconductor devices, in particular to a silicon carbide trench MOSFET device. BACKGROUND

[0002] As one of the third generation wide band gap semiconductor materials, silicon carbide (Silicon Carbide) material has wider band gap (3 times) than silicon material, higher critical electric field (10 times), higher carrier saturation drift speed (2 times), higher thermal conductivity (2.5 times) and other advantages, is an excellent material for preparing high-voltage power electronic devices, and has broad application prospects in high-power, high-temperature, high-voltage and anti-radiation power electronic fields.

[0003] MOSFET is the most widely used gate-controlled device structure in silicon carbide power devices. Since silicon carbide MOSFET is a device characterized by unipolar transport working mechanism, there is no charge storage effect, so it can realize lower switching loss and higher frequency characteristics compared with bipolar devices, and its low on-resistance and excellent high temperature characteristics make silicon carbide MOSFET become a new generation of low-loss power device with strong competitiveness.

[0004] Silicon carbide MOSFET can be divided into planar and trench types. Trench type SiC MOSFET has high channel density and no JFET area resistance, and the SiC trench sidewall has higher channel mobility, which will effectively reduce the channel resistance, so it is more popular.

[0005] Body diode loss is a key problem of silicon carbide MOS, in the structure of SiC MOSFET, the body diode formed by P-type base region and N-type drift region is used to turn on the current from the source electrode to the drain electrode. Compared with the opening voltage 0.7V of Si-based body diode, the wide band gap characteristics of SiC make the opening voltage of its body diode reach about 3V, which will increase the power loss.

[0006] SiC MOSFET has been improved in specific on-resistance and breakdown voltage, and high gate oxide electric field. However, SiC MOSFET still has reliability problems. Specifically, compared with Si IGBT, 4H-SiC MOSFE provides worse short circuit capability due to high electric field at PN junction in MOSFET structure and higher current density. At the same time, the short channel effect of SiC MOSFET will reduce the threshold voltage, resulting in unsaturated drain current. The peak current of device short circuit depends on its saturation current, and affects the short circuit capability of the device. However, the improvement of short circuit capability and the reduction of on-state loss (i.e. low specific on-resistance) are contradictory. Therefore, for the device design of SiC MOSFET, it is necessary to realize the trade-off between low specific on-resistance and high short circuit capability.

[0007] In view of the high loss and bipolar degeneration problem of SiC MOSFET body diode, the contradiction between low on-resistance and high short-circuit capability, and the high electric field problem of gate oxide layer, the application proposes and researches a SiC MOSFET integrated with heterojunction diode and double P-type shielding area. The proposed MOSFET is characterized by integrating heterojunction diode HJD and double P-type shielding area DP. The heavily doped P+ polysilicon is embedded between the source electrode trench and the gate trench and is connected to the source electrode, and the integrated HJD is formed by P-type doped polysilicon and N-type SiC area. The DP is composed of P-shield1 and P-shield2, both of which are connected to the source electrode and jointly protect the gate, so that the gate oxide layer is protected from high electric field. In addition, P-shield1, CSL and P-shield2 form a longitudinal JFET channel, and the DP controls the width of the on-current path through the longitudinal JFET channel. The integrated HJD and body diode of the MOSFET device are connected in parallel to the source-drain electrodes, and the integrated HJD will effectively suppress the opening of the parasitic body diode in the reverse on mode. SUMMARY

[0008] In view of the deficiencies of the prior art, the application provides a silicon carbide trench MOSFET device, which solves the contradiction between balancing the high loss and bipolar degeneration problem of SiC MOSFET body diode, low on-resistance and high short-circuit capability.

[0009] To achieve the above object, the application is implemented by the following technical scheme: the first aspect of the application provides a silicon carbide trench MOSFET device, which optimizes the reverse current flow characteristics and short-circuit resistance of the device without sacrificing the on-state performance through structural synergy.

[0010] Specifically, the silicon carbide trench MOSFET device comprises:

[0011] an N-type substrate;

[0012] an N-type drift region disposed on the N-type substrate;

[0013] a trench extending downward from the top surface of the device and disposed in the N-type drift region;

[0014] a gate structure accommodated in the trench,

[0015] the gate structure comprises a polysilicon gate dielectric and a polysilicon gate;

[0016] a P-well region disposed in the N-type drift region and adjacent to the trench;

[0017] and an N+ contact region disposed in the P-well region.

[0018] Preferably, the P-shield region and the P-shield region are laterally spaced apart, and a CSL region is disposed between the P-shield region and the P-shield region.

[0019] Preferably, the P+ poly region is in contact with the N+ contact region, thereby forming a heterojunction diode to provide a high-efficiency reverse freewheeling path for the device.

[0020] The device further comprises a source electrode electrically connected to the N+ contact region and the P+ poly region, and a drain electrode electrically connected to the N-type substrate.

[0021] Preferably, the P-shield region and the P-shield region are both electrically connected to the source electrode. This connection reliably clamps the two P-type shield regions at the source electrode potential, enabling them to effectively shield the high-voltage electric field below in the blocking state of the device, thereby protecting the reliability of the gate oxide layer.

[0022] In a specific embodiment, the P-shield region, the P-shield region, and the CSL region therebetween collectively form a vertical junction field effect transistor (JFET) structure. The working principle is as follows: when the device is short-circuited, the drain electrode bears a high voltage, which causes the PN junction between the P-shield region and the P-shield region and the CSL region to bear a large reverse bias, causing the space charge region depletion layer to rapidly expand into the CSL region. When the depletion layers expand to contact each other, the conductive channel in the CSL region is pinched off, thereby actively clamping the short-circuit current flowing through the device at a preset saturation level, effectively suppressing the rapid accumulation of Joule heat, and greatly enhancing the short-circuit resistance of the device.

[0023] Preferably, the heterojunction diode has a lower turn-on voltage than the intrinsic body diode formed by the P-well region and the N-type drift region. The beneficial effect is that when the device is used as a freewheeling diode, the current will preferentially pass through the heterojunction diode with a low turn-on voltage, rather than the intrinsic body diode with high conduction loss. In addition, since the heterojunction diode is a majority carrier conduction device, its reverse recovery charge is almost zero, thereby fundamentally eliminating the switching loss and oscillation problems caused by the reverse recovery process.

[0024] In a preferred embodiment, the shield structure is an asymmetric structure, wherein the P-shield region is not disposed directly below the trench where the gate structure is located.

[0025] Further, in the above asymmetric structure, the CSL region extends to the area directly below the trench. This asymmetric design significantly reduces the overlapping area between the gate electrode and the underlying shielding structure. Since the shielding structure is connected to the source electrode potential, this design effectively reduces the Miller capacitance Cgd between the gate and the drain, thereby speeding up the switching speed of the device, reducing the loss during switching, and making the device more suitable for high-frequency application scenarios.

[0026] Preferably, the source electrode is also electrically connected to the P-well region. This connection short-circuits the body region P-well region of the device with the source electrode, effectively suppressing the opening of the parasitic NPN transistor inside the device, improving the anti-latch-up capability and reliability of the device.

[0027] In a specific embodiment, the N-type doping concentration of the CSL region is higher than that of the N-type drift region. This design allows current to pass through a channel with lower resistivity when the device is forward conducting, which helps to reduce the total on-resistance of the device. At the same time, the doping concentration of the CSL region can be precisely designed to cooperatively regulate the pinch-off voltage and saturation current value of the above-mentioned JFET structure.

[0028] In an embodiment, the P+poly region is contained in a source electrode trench, which is laterally spaced apart from the trench containing the gate structure. This clear structural layout separates the main switching unit MOSFET from the freewheeling unit heterojunction diode in the process, facilitating the manufacturing and integration of the device.

[0029] Further, the semiconductor material of the device is preferably silicon carbide.

[0030] The present application provides a silicon carbide trench MOSFET device. It has the following advantages:

[0031] 1. The present application integrates a heterojunction diode composed of a P+poly region and an N+ contact region in the device. This heterojunction diode provides a dedicated freewheeling path with lower turn-on voltage and almost no reverse recovery charge. This fundamentally eliminates the huge switching loss and voltage spike caused by traditional diode freewheeling, significantly improving the energy efficiency and operational reliability of the device in high-frequency applications.

[0032] 2、The application sets a composite shielding structure composed of P-shield region, P-shield region and CSL region below the P-well region, which is physically equivalent to a longitudinal JFET, and when the device is short-circuited, the JFET structure can actively clamp the uncontrolled short-circuit current at a safe saturation level through the pinch-off effect of the depletion layer, thereby avoiding the thermal failure of the device due to instantaneous overcurrent and greatly enhancing the ruggedness and short-circuit resistance of the device.

[0033] 3、By adopting an asymmetric shielding structure, i.e. the P-shield2 region is not arranged directly below the gate trench, the design eliminates the direct overlap of the gate electrode and the lower ground shielding region, which effectively reduces the key parasitic parameter of the device, i.e. the gate-drain capacitance, thereby speeding up the switching speed of the device, further reducing the switching loss, and making the device more suitable for high-frequency application scenarios with strict requirements on switching performance. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 It is a traditional trench type SiCMOSFET device structure diagram;

[0035] Figure 2 It is a device structure diagram of embodiment 1 of the application;

[0036] Figure 3 It is a device structure diagram of embodiment 2 of the application;

[0037] Figure 4 It is a comparison diagram of reverse conduction characteristics of the traditional trench device and the device of the application

[0038] Figure 5 It is a comparison diagram of reverse recovery characteristics of the traditional trench device and the device of the application

[0039] Figure 6 It is a comparison diagram of switching characteristics of the traditional trench device and the device of the application

[0040] Figure 7 It is a comparison diagram of short-circuit characteristics of the traditional trench device and the device of the application.

[0041] 1, source electrode; 2, P+poly region; 3, N+contact region; 4, P-well region; 5, polysilicon gate; 6, P-shield2 region; 7, CSL region; 8, P-shield1 region; 9, N-type drift region; 10, N-type substrate; 11, drain electrode; 12, polysilicon gate dielectric. DETAILED DESCRIPTION

[0042] Clearly, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments of the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0043] Please refer to the accompanying drawings of the present application Figure 1 - the accompanying drawings Figure 7 The embodiment of the present application provides a silicon carbide trench MOSFET device, which comprises: an N-type substrate 10; an N-type drift region 9 arranged on the N-type substrate 10; a trench extending downward from the upper surface of the device and arranged in the N-type drift region 9; a gate structure accommodated in the trench, the gate structure comprising a polysilicon gate dielectric 12 and a polysilicon gate 5; a P-well region 4 arranged in the N-type drift region 9 and adjacent to the trench; an N+ contact region 3 arranged in the P-well region 4; a shielding structure below the P-well region 4, the shielding structure comprising P-shield1 regions 8 and P-shield2 regions 6 arranged laterally and spaced apart, and a CSL region 7 between the P-shield1 regions 8 and the P-shield2 regions 6; a P+ poly region 2 in contact with the N+ contact region 3 to form a heterojunction diode; a source electrode 1 electrically connected to the N+ contact region 3 and the P+ poly region 2; and a drain electrode 11 electrically connected to the N-type substrate 10, the P-shield1 regions 8 and the P-shield2 regions 6 are electrically connected to the source electrode 1, the P-shield1 regions 8, the P-shield2 regions 6 and the CSL region 7 therebetween jointly form a vertical junction field effect transistor (JFET) structure for limiting current when the device is short-circuited, the turn-on voltage of the heterojunction diode is lower than that of an intrinsic body diode formed by the P-well region 4 and the N-type drift region 9, the shielding structure is an asymmetric structure, wherein the P-shield2 regions 6 are not arranged directly below the trench, the CSL region 7 extends to the area directly below the trench for reducing the gate-drain capacitance of the device, the source electrode 1 is also electrically connected to the P-well region 4, the N-type doping concentration of the CSL region 7 is higher than that of the N-type drift region 9, the P+ poly region 2 is accommodated in a source electrode 1 trench, the source electrode 1 trench is arranged laterally and spaced apart from the trench accommodating the gate structure, the semiconductor material of the device is silicon carbide, and the conductivity types of the semiconductor regions in the device are opposite.

[0044] Specifically, the device is based on an N-type doped silicon carbide substrate, and an N-type drift region 9 is epitaxially grown on the upper surface of the N-type substrate 10, which will serve as the main region of the device to withstand high voltage and conduct current. The core structure of the device is one or more trenches formed in the N-type drift region 9 by etching process, which vertically extend downward from the upper surface of the device. Inside each trench, a gate structure of the device is accommodated. The gate structure is composed of a layer of silicon dioxide polysilicon gate dielectric 12 formed along the sidewall and bottom of the trench, and a polysilicon gate 5 filled therein. In the upper part of the N-type drift region 9 and adjacent to the trench, a P-well region 4 is provided. The gate voltage is applied through the polysilicon gate 5 to form a conductive channel at the trench sidewall of the P-well region 4. Inside the P-well region 4, a heavily doped N+ contact region 3 is also provided to provide low-resistance electrical contact for the source electrode of the device, and a composite shielding structure is provided below the P-well region 4. The structure includes two laterally spaced P-type shielding regions, namely P-shield1 region 8 and P-shield2 region 6. In the preferred embodiment of the present application, the shielding structure is of asymmetric layout, in which the P-shield2 region 6 is not provided directly below the trench where the gate structure is located. The region between the P-shield1 region 8 and the P-shield2 region 6 composed of N-type semiconductor is a current spreading layer CSL region 7. Due to the displacement of the P-shield2 region 6, the CSL region 7 extends laterally to the area directly below the gate trench. This asymmetric design significantly reduces the overlap of the gate electrode 5 and the lower ground shielding region, thereby effectively reducing the gate leakage capacitance Miller capacitance of the device, improving the switching speed, and integrating a high-performance freewheeling diode. A P+ doped polysilicon P+poly region 2 is provided on the upper surface of the device and directly contacts the N+ contact region 3, and the two together form a heterojunction diode. Through material and process optimization, the turn-on voltage of the heterojunction diode is designed to be significantly lower than that of the intrinsic body diode composed of the P-well region 4 and the N-type drift region 9, thereby providing a low-loss, high-speed freewheeling path for the device. In terms of physical layout, the P+poly region 2 is accommodated in a separate source electrode trench, which is laterally spaced apart from the trench accommodating the gate structure in layout, and in terms of electrical connection, the source electrode 1 at the top of the device forms a total common electrode, which simultaneously forms a reliable ohmic contact with the N+ contact region 3, the P+poly region 2, the P-well region 4, the P-shield1 region 8 and the P-shield2 region 6. This connection mode ensures that the P-well region 4 body region and the two P-type shielding regions are reliably clamped at the source electrode potential. The bottom of the device is connected to the N-type substrate 10 through the drain electrode 11, and the composite shielding structure of the device also has a short circuit protection function.The P-shieldl region 8, the P-shield2 region 6 and the CSL region 7 therebetween together form a longitudinal junction field effect transistor (JFET) structure. In the event of a short circuit, the JFET structure actively limits the current flow by the pinch-off effect of the depletion layer, greatly improving the ruggedness of the device. To further optimize the on-state performance, the N-type doping concentration of the CSL region 7 is designed to be higher than that of the N-type drift region 9, so as to reduce the total on-state resistance of the device. The semiconductor material of the device is preferably silicon carbide (SiC) so as to fully utilize the advantages of high voltage, high temperature and high frequency performance.

[0045] Embodiment 1: Referring to a symmetric structure of a silicon carbide trench MOSFET device as shown in FIG. 1, the device is constructed on an N-type substrate 10. An N-type drift region 9 is provided above the N-type substrate 10, which is usually formed by epitaxial growth. A P-well region 4 is provided in the upper region of the N-type drift region 9. Figure 2

[0046] ​A N+ contact region 3 is provided in the P-well region 4 near the top surface of the device. A trench structure extends vertically downwards from the top surface of the device, passing through the N+ contact region 3 and the P-well region 4 in sequence, and ending in the N-type drift region 9. A gate structure is provided in the trench. The gate structure includes a polysilicon gate dielectric 12 grown along the sidewalls and the bottom of the trench, and a polysilicon gate 5 filling the trench. The polysilicon gate 5 and the polysilicon gate dielectric 12 together form a MOS gate of the device. A P+ poly region 2 is provided on the top surface of the device, in contact with the N+ contact region 3. The P+ poly region 2 forms a heterojunction diode with the SiC material of the N+ contact region 3. A shielding structure is provided below the P-well region 4 and in the N-type drift region 9. The shielding structure includes two P-type shielding regions, P-shield1 region 8 and P-shield2 region 6, which are laterally separated. In the symmetrical embodiment, the P-shield1 region 8 and the P-shield2 region 6 are symmetrically distributed below the two sides of the trench where the gate structure is provided. The N-type drift region 9 between the P-shield1 region 8 and the P-shield2 region 6 is defined as a CSL region 7, i.e. a N-type current spreading layer. A source electrode 1 is provided on the top of the device, and a drain electrode 11 is provided on the bottom of the device. The drain electrode 11 is electrically connected to the back of the N-type substrate 10. In electrical connection of the device, the source electrode 1 is electrically connected to the N+ contact region 3, the P+ poly region 2, the P-well region 4, the P-shield1 region 8 and the P-shield2 region 6 on the top surface of the device, usually as an ohmic contact. This connection reliably clamps the body region P-well region 4 and the two P-type shielding regions at the source electrode potential. In the forward conduction state of the device, when a positive voltage higher than the threshold voltage is applied to the polysilicon gate 5, an N-type inversion channel is induced at the interface of the P-well region 4 adjacent to the polysilicon gate dielectric 12. At this time, if a positive voltage is applied to the drain electrode 11, electrons will be injected from the source electrode 1, flow through the N+ contact region 3, the N-type inversion channel, and then enter the CSL region 7 below. The N-type doping concentration of the CSL region 7 is higher than that of the N-type drift region 9, so the CSL region 7 provides a low-resistance lateral extension channel for electrons. After the electrons are extended, they flow vertically through the entire N-type drift region 9 and N-type substrate 10, and finally reach the drain electrode 11, forming a conduction current. In the reverse blocking state of the device, the gate potential is zero or negative. At this time, the PN junction formed by the P-well region 4 and the N-type drift region 9 bears the main drain-source reverse high voltage.Since P-shieldl region 8 and P-shield2 region 6 are reliably grounded by the source electrode 1, they act as shielding electrodes, effectively modulating the electric field distribution inside the N-type drift region 9, significantly reducing the peak electric field intensity at the bottom of the gate trench polysilicon gate dielectric 12, thus ensuring the long-term reliability of the gate oxide under high voltage. In the reverse freewheeling mode of operation of the device, the gate of the device is turned off, and the external circuit forces the current to flow from the drain electrode 11 to the source electrode 1. At this time, there are two parallel freewheeling channels inside the device: one is the intrinsic body diode PIN diode formed by the P-well region 4 and the N-type drift region 9; the other is the heterojunction diode formed by the P+poly region 2 and the N+contact region 3. Through material selection and band engineering design, the turn-on voltage of the heterojunction diode formed by the P+poly region 2 and the N+contact region 3 is designed to be significantly lower than that of the intrinsic body diode. Therefore, the freewheeling current will preferentially pass through the heterojunction diode conduction. The heterojunction diode mainly relies on majority carrier conduction, and its reverse recovery charge Qrr is extremely low, thus fundamentally eliminating the huge reverse recovery loss and voltage spike problems brought about by the intrinsic body diode in high-frequency switching applications. In the short-circuit operating state of the device, i.e. the gate 5 is still kept open, and the drain electrode 11 and the source electrode 1 are subjected to high voltage due to a fault. At this time, the huge high voltage of the drain electrode 11 will cause the PN junction formed by the grounded P-shieldl region 8 and P-shield2 region 6 and the CSL region 7 between them to be subjected to a huge reverse bias. This causes the space charge layer depletion layer of the two P-type shielding regions to rapidly expand into the CSL region 7. The P-shieldl region 8, P-shield2 region 6, and CSL region 7 together form a longitudinal junction field effect transistor JFET structure. As the voltage of the drain electrode 11 rises, the depletion layers eventually contact each other within the CSL region 7, causing the current channel to be completely pinched off. This pinching effect actively clamps the short-circuit current flowing through the device at a preset saturation value, preventing a catastrophic rise in current, thus greatly improving the short-circuit resistance of the device.

[0047] Embodiment 2: A silicon carbide trench MOSFET device of asymmetric structure as shown in Figure 3 The device of this embodiment is substantially the same as that of Embodiment 1 in overall structure, material composition, and electrical connection, and the core difference lies in the specific layout of the shielding structure.

[0048] In this embodiment, the shielding structure located below the P-well region 4 is designed as an asymmetric structure. Specifically, unlike the symmetric layout of Embodiment One, the P-shield2 region 6 in this embodiment is no longer disposed directly below the trench where the gate structure is located. That is, from the vertical cross-section of the device, there is no P-type shielding region directly below the gate structure. Corresponding to the above structural change, the lateral range of the CSL region 7 has changed. The CSL region 7 extends laterally to fill the space region that was originally occupied by the P-shield2 region 6, which is located directly below the gate trench. The other components of the device, including the N-type substrate 10, the N-type drift region 9, the P-well region 4, the N+ contact region 3, the P+poly region 2, the gate structure, and the electrodes, have the same structure and function as in Embodiment One. This asymmetric shielding structure design brings significant performance improvement to the device. In MOSFET devices, the capacitance between the gate and the drain electrode 11, i.e., the gate-drain capacitance (Cgd), also known as the Miller capacitance, is a key parasitic parameter that determines the switching speed and switching loss of the device. In the symmetric structure of Embodiment One, there is an unavoidable overlapping region between the gate electrode 5 and the P-shield2 region 6 grounded through the source electrode 1, and this overlapping region is an important component of the gate-drain capacitance. In the asymmetric structure of this embodiment, by removing the P-shield2 region 6 from directly below the gate trench, the direct overlap between the gate electrode 5 and the P-type shielding region below is completely eliminated. The region directly below the gate electrode 5 becomes the CSL region 7, which is not at the source electrode potential during device operation. This structural change significantly reduces the capacitive coupling effect between the gate and the drain electrode 11, effectively reducing the total gate-drain capacitance (Cgd) value of the device. The reduction of the gate-drain capacitance directly reflects on the switching performance of the device. During the turn-on and turn-off processes of the device, lower gate-drain capacitance means reduced charging and discharging requirements for the gate drive circuit, and shorter Miller plateau duration during the switching transient process. This enables the device to complete the turn-on and turn-off actions at a faster speed, thereby significantly reducing the energy loss generated in each switching cycle. Therefore, the asymmetric structure device provided in this embodiment is particularly suitable for high-frequency power electronic application scenarios that have higher requirements for switching speed and efficiency.

[0049] Working principle: By integrating a heterojunction diode composed of the P+poly region 2 and the N+ contact region 3, which is in parallel with the intrinsic body diode composed of the P-well region 4 and the N-type drift region 9, since the heterojunction diode has a lower turn-on voltage and almost no reverse recovery charge, during reverse current conduction, the current preferentially passes through this dedicated channel, fundamentally eliminating the large switching loss and voltage spike caused by the intrinsic body diode.

[0050] Another case ingeniously utilizes the P-shield1 region 8, CSL region 7 and P-shield2 region 6 composite structure located below the P-well region 4, which physically forms a longitudinal junction field effect transistor (JFET). When the device is short-circuited, the high voltage of the drain electrode 11 causes the depletion layers of the grounded P-shield1 region 8 and P-shield2 region 6 to expand towards the CSL region 7 and eventually pinch off the CSL region 7, thereby actively clamping the short-circuit current to a safe saturation value, greatly enhancing the robustness of the device. In normal operation, when the polysilicon gate 5 applies a positive voltage, electrons flow from the source electrode 1, through the N+ contact region 3 and the inversion channel formed in the P-well region 4, into the CSL region 7 with higher doping concentration. This region acts as a low-resistance layer, reducing the overall on-resistance of the device. Subsequently, the electrons flow longitudinally through the N-type drift region 9 and the N-type substrate 10 to the drain electrode 11. In the reverse blocking state, the P-shield1 region 8 and P-shield2 region 6 act as an electric field shielding layer, effectively reducing the electric field peak at the polysilicon gate dielectric 12 at the bottom of the gate trench, ensuring the long-term reliability of the device.

Claims

1. A silicon carbide trench MOSFET device, characterized by, Comprising: an N-type substrate (10); an N-type drift region (9) disposed on the N-type substrate (10); a trench disposed within the N-type drift region (9) and extending downward from a top surface of the device; a gate structure housed within the trench, the gate structure comprising a gate dielectric (12) and a gate electrode (5); a P-well region (4) disposed within the N-type drift region (9) and adjacent to the trench; an N+ contact region (3) disposed within the P-well region (4); a shield structure located below the P-well region (4), the shield structure comprising P-shield1 region (8) and P-shield2 region (6) disposed laterally apart from each other, with a CSL region (7) between the P-shield1 region (8) and the P-shield2 region (6); a P+ poly region (2) in contact with the N+ contact region (3) to form a heterojunction diode; a source electrode (1) electrically connected to the N+ contact region (3) and the P+ poly region (2); and a drain electrode (11) electrically connected to the N-type substrate (10).

2. The silicon carbide trench MOSFET device of Claim 1, wherein, The P-well region (4), the P-shield1 region (8) and the P-shield2 region (6) are all electrically connected to the source electrode (1).

3. The silicon carbide trench MOSFET device of Claim 1, wherein, The P-shield1 region (8), the P-shield2 region (6) and the CSL region (7) therebetween together form a JFET structure for limiting current in the event of a short circuit in the device.

4. The silicon carbide trench MOSFET device of Claim 1, wherein, The heterojunction diode has a lower turn-on voltage than an intrinsic body diode formed by the P-well region (4) and the N-type drift region (9).

5. The silicon carbide trench MOSFET device of Claim 1, wherein, The shield structure is asymmetric, wherein the P-shield2 region (6) is not disposed directly below the trench.

6. The silicon carbide trench MOSFET device of Claim 1, wherein, The CSL region (7) extends to an area directly below the trench for reducing gate-drain capacitance of the device.

7. The silicon carbide trench MOSFET device of Claim 1, wherein, The gate dielectric (12) is silicon dioxide and the gate electrode (5) is polysilicon.

8. The silicon carbide trench MOSFET device of Claim 1, wherein, The N-type doping concentration of the CSL region (7) is higher than the N-type doping concentration of the N-type drift region (9).

9. The silicon carbide trench MOSFET device of Claim 1, wherein, The P+ poly region (2) is housed within a source electrode (1) trench, which is laterally spaced apart from the trench housing the gate structure.

10. The silicon carbide trench MOSFET device of any one of claims 1-9, wherein, The semiconductor material of the device is silicon carbide, and the conductivity types of the semiconductor regions in the device are opposite.

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