Photoelectric co-sealing optical module structure and manufacturing method thereof

Abstract

The invention belongs to the technical field of semiconductor packaging, and particularly relates to a photoelectric co-packaging optical module structure and a manufacturing method thereof, and the photoelectric co-packaging optical module structure comprises an aluminum nitride intermediate layer and a substrate. The aluminum nitride intermediate layer has insulativity and comprises an upper surface and a lower surface, the upper surface is provided with an engineering layer, the engineering layer is in surface contact with the photoelectric co-packaging chip and the switch chip, connecting holes are formed in the aluminum nitride intermediate layer and located below the photoelectric co-packaging chip and the switch chip, a loop is arranged between the connecting holes, and the aluminum nitride intermediate layer is arranged in the loop. The connecting hole and the loop are filled with conductive metal; the substrate is provided with a connector, the aluminum nitride intermediate layer is arranged on the substrate and is electrically connected with the substrate, the photoelectric co-packaging chip is composed of an electronic integrated circuit and a photon integrated circuit, and a tail fiber is led out of the photon integrated circuit and is connected with the outside through the connector. The invention shortens the connection path, improves the efficiency, increases the heat dissipation area and heat dissipation efficiency, and improves the service life of the chip and the stability of the system.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, and particularly relates to an optoelectronic co-packaged optical module structure and its manufacturing method. Background Technology

[0002] With the rapid development of applications such as generative artificial intelligence and high-performance computing (HPC), the demand for data processing speed and transmission bandwidth in AI computing centers is exploding. As a core component of high-speed interconnects in data centers, optical modules have accelerated their transmission rates from the existing 400G and 800G to 1.6T and even 3.2T levels. This increase in speed not only means an expansion of single-channel bandwidth, but also brings higher signal frequencies, more complex modulation formats, and greater power density, posing unprecedented challenges to packaging structures.

[0003] In high-frequency, high-speed signal transmission, the dielectric constant and dielectric loss of the interposer material directly affect signal integrity and system bandwidth. Excessive dielectric loss can lead to signal attenuation and increased bit error rate. Secondly, with the development of technologies such as co-packaged optoelectronics (CPO) and silicon photonics integration, the integration density of circuits and optical devices in optical modules has significantly increased, placing higher demands on the electrical insulation and reliability of the interposer material to avoid breakdown and crosstalk issues. Furthermore, the power consumption density of high-speed devices increases rapidly, significantly increasing the pressure on thermal management within the package. Traditional interposer materials often struggle to simultaneously meet the requirements of low dielectric loss and high thermal conductivity, easily causing localized overheating and affecting device lifespan and system stability.

[0004] Currently, silicon is the most commonly used interposer material, although glass has also been proposed. While silicon offers mature manufacturing processes and allows for high wiring density, its limitations become increasingly apparent when targeting higher speeds and frequencies: silicon has relatively poor electrical insulation, requiring additional insulating layers, increasing process complexity, and easily generating parasitic capacitance; furthermore, silicon has a high dielectric constant and high dielectric loss, especially in high-frequency signal transmission. Glass, while possessing good electrical insulation and low dielectric loss, has low thermal conductivity, making effective heat dissipation difficult, and is also more challenging to process. With the demands of next-generation optical modules and high-speed interconnect packaging, the performance bottlenecks of these materials are becoming increasingly apparent, making it difficult to meet the requirements of future high-speed, high-power, and high-density packaging. Summary of the Invention

[0005] The purpose of this invention is to address the aforementioned technical problems by providing a co-encapsulated optoelectronic module structure and its manufacturing method, which achieves the effects of shortening the connection path, improving efficiency, maintaining signal integrity during high-speed and high-frequency transmission, reducing thermal cycling stress, and improving system reliability.

[0006] In view of this, the present invention provides a photoelectric co-packaged optical module structure, comprising: An aluminum nitride interposer layer is provided, which is insulating. The aluminum nitride interposer layer includes an upper surface and a lower surface. An engineering layer is provided on the upper surface. The engineering layer forms a surface contact with the optoelectronic co-packaged chip and the switch chip. A connection hole is provided on the aluminum nitride interposer layer below the optoelectronic co-packaged chip and the switch chip. A circuit is provided between the connection holes. The connection holes and the circuit are filled with conductive metal. A substrate is provided with a connector. An aluminum nitride interlayer is disposed on the substrate and electrically connected to the substrate. The optoelectronic co-packaged chip is composed of an electronic integrated circuit and a photonic integrated circuit. The photonic integrated circuit has a pigtail that is connected to the outside through a connector.

[0007] In this technical solution, the optoelectronic co-packaged chip, the switch chip, the aluminum nitride interposer, and the substrate are electrically connected through connection holes and metal materials in the circuit, shortening the connection path and improving efficiency; the optoelectronic co-packaged chip and the switch chip form surface contact with the high thermal conductivity aluminum nitride interposer through bonding, increasing the heat dissipation area and heat dissipation efficiency, and improving chip life and system stability.

[0008] Aluminum nitride interposers possess excellent electrical insulation, a coefficient of thermal expansion that matches the chip material, high mechanical strength, and low dielectric loss. They can maintain signal integrity, reduce thermal cycling stress, improve system reliability, withstand packaging stress, reduce warpage, and simplify manufacturing processes during high-speed, high-frequency transmission.

[0009] Furthermore, the optoelectronic co-packaged chip includes an optical chip and an electrical chip.

[0010] Furthermore, the thermal conductivity of the aluminum nitride interlayer is higher than 170 W / (m·K).

[0011] Furthermore, the thickness of the aluminum nitride interlayer is less than 0.1 mm.

[0012] Furthermore, the diameter of the connecting hole is less than 100 μm.

[0013] Furthermore, the conductive metal filling the connection hole and the circuit is one or more of gold, silver, platinum, copper, nickel, molybdenum, and tungsten.

[0014] Furthermore, the engineering layer material is one or more of silicon, aluminum gallium nitride, aluminum nitride, silicon carbide, boron nitride, oxides, and diamond.

[0015] Furthermore, the engineering layer thickness is less than 1 μm, and the surface roughness Ra is less than 1 nm.

[0016] Furthermore, the optoelectronic co-packaged chip and the switch chip are chips manufactured using one or more materials selected from Si, GaAs, lnP, GaN, SiC, and SiN.

[0017] Furthermore, the aluminum nitride interlayer is welded to the substrate surface via bumps.

[0018] Furthermore, the substrate used as a packaging substrate is a ceramic substrate or an organic substrate.

[0019] Furthermore, the substrate is an aluminum nitride ceramic substrate.

[0020] Furthermore, the manufacturing method of the optoelectronic co-packaged optical module structure includes the following steps: S1: An insulating aluminum nitride interlayer with a thermal conductivity higher than 170 W / (m·K) is provided. It is formed by hot isostatic pressing, wire-cut, chamfered, and polished to create an aluminum nitride ceramic wafer with a thickness less than 0.1 mm and a surface roughness Ra less than 5 nm. An epitaxial engineering layer is then applied to the surface of the aluminum nitride ceramic wafer to create circuits and interconnects. Metal materials are filled into the circuits and interconnects to form a circuit. S2: Using bonding, switch chips and optoelectronic co-packaged chips are fixed on the surface of the engineering layer to form electrical circuits and thermal paths; S3: The aluminum nitride interposer is soldered to the upper surface of the substrate through bumps to form an electrical connection. The pigtail of the optoelectronic co-packaged chip is connected to the outside through a connector set on the surface of the substrate.

[0021] Furthermore, the filling of the metal material in the circuit and connection holes is carried out by chemical plating or electroplating.

[0022] Furthermore, the bonding method is hybrid bonding.

[0023] The beneficial effects of this invention are: 1. The optoelectronic co-packaged chip, switch chip, aluminum nitride interposer, and substrate are electrically connected through connection holes and metal materials in the circuit, shortening the connection path and improving efficiency; the optoelectronic co-packaged chip and switch chip form surface contact with the high thermal conductivity aluminum nitride interposer through bonding, increasing the heat dissipation area and heat dissipation efficiency, and improving chip life and system stability.

[0024] 2. The aluminum nitride interposer has excellent electrical insulation, a coefficient of thermal expansion that matches the chip material, high mechanical strength, and low dielectric loss. It can maintain signal integrity, reduce thermal cycling stress, improve system reliability, withstand packaging stress, reduce warpage, and simplify the manufacturing process during high-speed and high-frequency transmission. Attached Figure Description

[0025] Figure 1 This is a half-sectional view of the packaging structure of the present invention; Figure 2 This is a schematic diagram of the present invention; Figure 3 yes Figure 1 A magnified view of the internal packaging structure.

[0026] The markings in the diagram are as follows: 1. Aluminum nitride interposer; 2. Optoelectronic co-packaged chip; 3. Switch chip; 4. Optical fiber; 5. Connector; 6. Substrate; 7. Circuit; 8. Connecting hole; 9. Bump; 11. Engineering layer; 12. Aluminum nitride ceramic wafer; 21. Optical chip; 22. Electrical chip. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0028] In the description of this application, it should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. For ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following drawings denote similar items; therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0029] It should be noted that the terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0030] It should be noted that in the description of this application, the directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application. The directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0031] It should be noted that, in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0032] Example 1: like Figure 1-3 As shown, A co-packaged optoelectronic module structure includes: An aluminum nitride interposer 1 is provided, which is insulating. The aluminum nitride interposer 1 includes an upper surface and a lower surface. An engineering layer 11 is provided on the upper surface. The engineering layer 11 forms a surface contact with the optoelectronic co-packaged chip 2 and the switch chip 3. A connection hole 8 is provided on the aluminum nitride interposer 1 below the optoelectronic co-packaged chip and the switch chip 3. A circuit 7 is provided between the connection holes 8. The connection holes 8 and the circuit 7 are filled with conductive metal. The substrate 6 has a connector 5 on it. An aluminum nitride interlayer 1 is disposed on the substrate 6 and electrically connected to the substrate 6. The optoelectronic co-packaged chip 2 is composed of an electronic integrated circuit and a photonic integrated circuit. The photonic integrated circuit has a pigtail that is connected to the outside through the connector 5.

[0033] The optoelectronic co-packaged chip 2, the switch chip 3, the aluminum nitride interposer 1, and the substrate 6 are electrically connected through the connection hole 8 and the metal material in the circuit 7, which shortens the connection path and improves efficiency. The optoelectronic co-packaged chip 2 and the switch chip 3 form a surface contact with the aluminum nitride interposer 1 with high thermal conductivity through bonding, which increases the heat dissipation area and heat dissipation efficiency, and improves chip life and system stability.

[0034] The aluminum nitride interposer 1 has excellent electrical insulation, a coefficient of thermal expansion that matches the chip material, high mechanical strength, and low dielectric loss. It can maintain signal integrity, reduce thermal cycling stress, improve system reliability, withstand packaging stress, reduce warpage, and simplify the manufacturing process during high-speed and high-frequency transmission.

[0035] The optoelectronic co-packaged chip 2 includes an optical chip 21 and an electrical chip 22.

[0036] The thermal conductivity of the aluminum nitride interlayer 1 is higher than 170 W / (m·K).

[0037] The thickness of the aluminum nitride interlayer 1 is less than 0.1 mm.

[0038] The diameter of the connecting hole 8 is less than 100 μm.

[0039] The conductive metal filled in the connection hole 8 and the circuit 7 is one or more of gold, silver, platinum, copper, nickel, molybdenum and tungsten.

[0040] The engineering layer 11 is made of one or more of silicon, aluminum gallium nitride, aluminum nitride, silicon carbide, boron nitride, oxides, and diamond.

[0041] The thickness of engineering layer 11 is less than 1 μm, and the surface roughness Ra is less than 1 nm.

[0042] The optoelectronic co-packaged chip 2 and the switch chip 3 are chips manufactured using one or more materials selected from Si, GaAs, lnP, GaN, SiC, and SiN.

[0043] The aluminum nitride interlayer 1 is welded to the surface of the substrate 6 via bumps 9.

[0044] The substrate 6, which serves as the packaging substrate 6, is either a ceramic substrate 6 or an organic substrate 6.

[0045] The substrate 6 is an aluminum nitride ceramic substrate 6.

[0046] Example 2: The manufacturing method of the optoelectronic co-packaged optical module structure includes the following steps: S1: An insulating aluminum nitride interposer 1 with a thermal conductivity higher than 170 W / (m·K) is provided. It is formed by hot isostatic pressing, wire-cut, chamfered, and ground / polished to create an aluminum nitride ceramic wafer 12 with a thickness less than 0.1 mm and a surface roughness Ra less than 5 nm. An epitaxial engineering layer 11 is then applied to the surface of the aluminum nitride ceramic wafer 12, and circuits 7 and connecting holes 8 are formed. Metal material is filled into the circuits 7 and connecting holes 8 to form a circuit. S2: The switch chip 3 and the opto-co-packaged chip 2 are fixed on the surface of the engineering layer 11 by bonding to form an electrical circuit 7 and a thermal path. The bonding method is hybrid bonding. S3: The aluminum nitride interposer 1 is soldered to the upper surface of the substrate 6 through the bump 9 to form an electrical connection. The pigtail of the optoelectronic co-packaged chip 2 is connected to the outside through the optical fiber 4 connector 5 disposed on the surface of the substrate 6.

[0047] The metal material filling in circuit 7 and connection hole 8 is achieved by chemical plating or electroplating.

[0048] The embodiments of this application have been described above with reference to the accompanying drawings. Unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other. This application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. An opto-electronic co-packaged optical module structure, characterized by , comprising: An aluminum nitride interposer (1) having insulation, the aluminum nitride interposer (1) comprising an upper surface and a lower surface, the upper surface being provided with an engineering layer (11), the engineering layer (11) being in surface contact with a photoelectric co-encapsulation chip (2) and a switch chip (3), a connecting hole (8) being formed in the aluminum nitride interposer (1) below the photoelectric co-encapsulation chip and the switch chip (3), a loop (7) being provided between the connecting holes (8), and the connecting holes (8) being filled with a conductive metal in the loop (7); A substrate (6) provided with a connector (5), the aluminum nitride interposer (1) being provided on the substrate (6) and electrically connected to the substrate (6), the photoelectric co-encapsulation chip (2) being composed of an electronic integrated circuit and a photonic integrated circuit, and a tail fiber of the photonic integrated circuit being connected to the outside through the connector (5).

2. An opto-electronic co-packaged optical module structure according to claim 1, wherein, The photoelectric co-encapsulation chip (2) comprises an optical chip (21) and an electrical chip (22).

3. An optoelectronic common package optical module structure according to claim 1, wherein, The thermal conductivity of the aluminum nitride interposer (1) is higher than 170 W / (m·K).

4. An opto-electronic co-packaged optical module structure according to claim 1, wherein, The thickness of the aluminum nitride interposer (1) is less than 0.1 mm.

5. An opto-electronic co-packaged optical module structure according to claim 1, wherein, The aperture of the connecting hole (8) is less than 100 μm.

6. An opto-electronic co-packaged optical module structure according to claim 1, wherein, The conductive metal filled in the connecting hole (8) and the loop (7) is one or more of gold, silver, platinum gold, copper, nickel, molybdenum, and tungsten.

7. An optoelectronic common package optical module structure according to claim 1, wherein, The material of the engineering layer (11) is one or more of silicon, aluminum gallium nitride, aluminum nitride, silicon carbide, boron nitride, oxide, and diamond.

8. An optoelectronic common package optical module structure according to claim 1, wherein, The thickness of the engineering layer (11) is less than 1 μm, and the surface roughness Ra is less than 1 nm.

9. A method for manufacturing a photoelectric co-packaged optical module structure, characterized in that, The photoelectric co-encapsulation optical module structure according to any one of claims 1-8, comprising the following steps: S1: providing an insulating aluminum nitride interposer (1) having a thermal conductivity higher than 170 W / (m·K), the aluminum nitride interposer (1) being formed by hot isostatic pressing sintering, wire cutting, chamfering, and polishing to have a thickness less than 0.1 mm and a surface roughness Ra less than 5 nm, and an engineering layer (11) being epitaxially formed on the upper surface of the aluminum nitride ceramic wafer (12), the loop (7) and the connecting hole (8) being provided, and the metal material being filled in the loop (7) and the connecting hole (8) to form a circuit; S2: using bonding to fix the switch chip (3) and the photoelectric co-encapsulation chip (2) on the surface of the engineering layer (11) to form an electrical loop (7) and a thermal loop; S3: the aluminum nitride interposer (1) being welded to the upper surface of the substrate (6) by a bump (9) to form an electrical connection, and the tail fiber of the photoelectric co-encapsulation chip (2) being connected to the outside through the connector (5) provided on the surface of the substrate (6).

10. The method of claim 9, wherein the method further comprises: The filling of the metal material in the loop (7) and the connecting hole (8) is performed by chemical plating or electroplating. ​

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