System-on-chip startup control method and device, storage medium and electronic equipment

Abstract

The application discloses a system-on-chip startup control method and device, a storage medium and electronic equipment. The application relates to the field of system-on-chip startup technology and aims to solve the problem that a system-on-chip with low cost and limited resources cannot be normally started due to the lack of on-chip static random access memory. After the system-on-chip is powered on, a central processing unit initializes a cache memory controller, enables data caching and write distribution functions; when the central processing unit initiates a write operation to a preset cache back-end response area to write startup data for the first time, the cache memory controller completes a write distribution operation through a system bus to automatically allocate a cache block in the data cache; and the central processing unit loads and executes startup code and startup data in the cache block, so that the system-on-chip without on-chip static random access memory can be started.

Description

Technical Field

[0001] This invention relates to the field of system-on-a-chip (SoC) boot technology, and more particularly to a boot control method, apparatus, storage medium, and electronic device for SoC. Background Technology

[0002] In System-on-Chip (SoC) design, the boot process typically relies on on-chip Static Random-Access Memory (SRAM) as a temporary storage medium. After the Central Processing Unit (CPU) powers on, it reads and executes initialization code from the read-only memory (ROM), loads the necessary data structures and boot image into the on-chip SRAM, and then continues execution to Dynamic Random Access Memory (DRAM).

[0003] However, in low-cost or resource-constrained systems-on-chip (SoCs), the capacity of on-chip static random access memory (SRAM) is often severely limited, and some designs even completely omit SRAM to simplify hardware structure, save chip area and cost. In this case, the traditional diskless boot ROM interface boot process cannot run normally due to the lack of necessary temporary storage medium, resulting in system boot failure. Summary of the Invention

[0004] The purpose of this invention is to provide a boot control method, apparatus, storage medium, and electronic device for a system-on-a-chip (SoC) to solve the technical problem that a low-cost, resource-constrained SoC cannot boot normally due to the lack of on-chip static random access memory.

[0005] In a first aspect, the present invention provides a boot control method for an on-chip system, applied to an on-chip system, the on-chip system comprising: a central processing unit, a boot read-only memory, and a system bus, the central processing unit including a cache memory controller; the method comprising the following steps:

[0006] S100, after the on-chip system is powered on, the central processing unit initializes the high-speed cache memory controller and enables data caching and write allocation functions;

[0007] S200: When the central processing unit initiates a write operation to the preset cache back-end response area for the first time to write startup data, and the write operation fails, the cache memory controller completes the write allocation operation via the system bus and automatically allocates a cache block in the data cache.

[0008] In the address space of the startup read-only memory, a reserved address space is designated as the cache backend response area, and the reserved address space can respond to read and write requests on the system bus;

[0009] S300, the central processing unit loads and executes the startup code and the startup data in the cache block.

[0010] Furthermore, step S100 also includes: enabling the monitoring mechanism and instruction cache, disabling the cache prefetch function and the automatic adjustment of write allocation strategy function.

[0011] Furthermore, in step S200, the response mode of the reserved address space on the system bus includes: returning a preset constant for read requests and returning a normal response signal for write requests.

[0012] Further, in step S200, the reserved address space is mapped to the physical address area of ​​the boot read-only memory.

[0013] Further, step S200 includes:

[0014] The cache memory controller sends a read request to the cache back-end response area to the system bus;

[0015] The cache memory controller receives read data returned from the system bus and merges the read data with the startup data to be written;

[0016] Allocate a cache block in the data cache and store the merged data into the cache block;

[0017] The status of the cache block is marked as modified.

[0018] Furthermore, in step S300, the total capacity of the startup code and the startup data does not exceed the available space of the data cache.

[0019] Furthermore, the method also includes:

[0020] When the startup phase requires initialization of the external master control device, the external master control device accesses the data cache of the central processing unit through the input / output consistency interface.

[0021] Secondly, the present invention provides a boot control device for a system-on-a-chip, applied to a system-on-a-chip, the system-on-a-chip including: a central processing unit, a boot read-only memory, and a system bus, the central processing unit including a cache memory controller; the device includes:

[0022] An initialization module is used to initialize the high-speed cache memory controller through the central processing unit after the on-chip system is powered on, enabling data caching and write allocation functions;

[0023] The cache allocation module is used to automatically allocate a cache block in the data cache when the central processing unit first initiates a write operation to the preset cache back-end response area to write startup data. If the write operation fails, the cache memory controller completes the write allocation operation via the system bus. In the address space of the startup read-only memory, a reserved address space is designated as the cache back-end response area. The reserved address space can respond to read and write requests on the system bus.

[0024] An execution module is used to load and execute the startup code and startup data in the cache block via the central processing unit.

[0025] Thirdly, the present invention provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in the first aspect above.

[0026] Fourthly, the present invention provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the method described in the first aspect.

[0027] The present invention has the following advantages: it can complete the boot process of the read-only memory stage without on-chip static random access memory, saving chip area and cost, and is especially suitable for low-cost or resource-constrained on-chip systems; it can be implemented under the standard central processing unit architecture without modifying the hardware structure, reducing design complexity and development cost; since the access latency of the cache memory is much lower than that of external flash memory or dynamic random access memory, the boot speed is significantly improved; at the same time, it has strong versatility and is suitable for central processing units that support cache memory write allocation mechanisms, and can be widely used in various on-chip system boot scenarios that lack on-chip static random access memory. Attached Figure Description

[0028] To more clearly illustrate the technical solution of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0029] Figure 1 This is a flowchart of the on-chip system startup control method of the present invention. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention. The technical solutions provided by various embodiments of this invention will be described in detail below with reference to the accompanying drawings.

[0031] Please see Figure 1 This invention provides a startup control method for a system-on-a-chip, which is applied to a system-on-a-chip, including a central processing unit, a boot read-only memory, a system bus, and an external main control interface module.

[0032] The central processing unit (CPU) is the core component, integrating a cache controller. This controller manages the operating modes of the data cache (D-Cache) and instruction cache (I-Cache), including enabling write-allocate functionality and snooping mechanisms, among other key configurations, to enable the core logic of subsequently replacing on-chip static random-access memory (SRAM) with cache. The boot read-only memory (ROM) serves as the initial storage medium for the boot code. A reserved address region is designated in its address space, mapped to the cache back-end response area. This area is used to respond to the CPU's read and write requests to the cache on the system bus, ensuring normal data interaction between the cache and memory units. The system bus is the crucial pathway connecting the CPU, boot ROM, and other peripherals. The cache controller uses the system bus to perform read and write operations on the reserved address space. For example, when a write operation misses the cache, it initiates a read request and receives response data, thereby completing the allocation of cache blocks. In addition, the external master control interface module is used to connect external advanced eXtensible Interface (AXI) master devices such as Direct Memory Access (DMA). When such devices need to be initialized during the startup phase, this module must support external devices to access the CPU cache through the input / output (IO) consistency interface to ensure the consistency and correctness of data access.

[0033] The on-chip system startup control method of the present invention specifically includes the following steps:

[0034] S100, after the on-chip system is powered on, the central processing unit initializes the high-speed cache memory controller and enables data caching and write allocation functions.

[0035] Furthermore, the monitoring mechanism and instruction cache are enabled, while cache prefetching and automatic write allocation strategy adjustment are disabled. In this step, the CPU initializes the cache memory controller and performs a series of functional configurations. Enabling the data cache provides temporary high-speed storage space during the boot phase, replacing the on-chip static random access memory (SRAM) in traditional solutions. This allows the CPU to temporarily store boot code and data there. The characteristics of the cache make data access much faster than external storage devices, significantly improving data read and write efficiency during boot. Enabling the write allocation function ensures that when the CPU initiates a write operation to the cache back-end response area for the first time and misses, the cache memory controller can automatically allocate a cache block to store the data. This avoids the problem of data having nowhere to be stored due to a lack of on-chip SRAM, ensuring effective storage of boot data and realizing dynamic allocation and management of data in the absence of on-chip SRAM.

[0036] Enabling the snooping mechanism maintains cache consistency. When multiple devices in the system may access the cache, such as external master devices accessing the data cache through an I / O consistency interface in subsequent steps, the snooping mechanism ensures that all devices see consistent cached data, improving the reliability and accuracy of system data interaction and avoiding errors caused by data inconsistency. Enabling the instruction cache allows the CPU to temporarily store startup code in the instruction cache, accelerating instruction reading and execution. Through the fast access characteristics of the cache, the latency of reading instructions from external storage is reduced, thereby speeding up the execution efficiency of startup code. Disabling cache prefetching prevents the cache memory controller from proactively prefetching data from external storage without explicit request. During the startup phase, the total amount of startup code and data is usually fixed and controllable. Prefetching may lead to unnecessary bus bandwidth consumption and cache space waste. Disabling cache prefetching avoids invalid data occupying cache space, allowing limited cache resources to be used efficiently and dedicated to storing critical code and data required for startup. Disabling the automatic write allocation policy adjustment function can ensure the stability of the write allocation policy, so that the write allocation function always works in the preset way and will not change automatically due to changes in certain conditions during system operation. This ensures the determinism and predictability of write allocation operations during startup, avoids startup data storage anomalies that may be caused by automatic policy adjustment, and thus ensures the stability and reliability of the entire startup process.

[0037] S200: When the central processing unit initiates a write operation to the preset cache back-end response area for the first time to write startup data, and the write operation fails, the cache memory controller completes the write allocation operation via the system bus and automatically allocates a cache block in the data cache.

[0038] Specifically, in the address space of the startup read-only memory, a reserved address space is designated as the cache backend response area, and the reserved address space can respond to read and write requests on the system bus.

[0039] Specifically, the reserved address space responds to the system bus by returning a preset constant for read requests and a normal response signal for write requests. The reserved address space is mapped to the physical address area of ​​the boot read-only memory.

[0040] In this embodiment, read requests consistently return the constant 0x0. When the CPU triggers write-allocate due to a write miss and initiates a read request to the reserved address space, the bus response returns a fixed value of 0. This mechanism allows the cache controller to allocate a new cache line based on this empty data, and then merge the data actually written by the CPU with the 0 value before storing it in the cache line. This allows for the dynamic construction of writable storage space through the cache memory even without on-chip static random access memory. Write requests can be ignored but must return a normal response signal (OKAY) because the data written to the reserved address during startup is actually stored in the cache memory and does not need to be written to external storage media. Ignoring write operations avoids unnecessary bus overhead. However, returning a normal response signal is necessary to meet bus protocol specifications, ensure the CPU's write operation process is completed normally, and prevent cache controller interruption or startup process blockage due to abnormal responses. The combination of these two mechanisms achieves both the functionality of simulating static random access memory using the cache memory and ensures the correctness and efficiency of bus interaction.

[0041] Mapping the reserved address space to the physical address region of the boot ROM aims to leverage the boot ROM's bus response capability to provide a back-end mapping for the cache memory. Since the boot ROM is a memory unit directly accessible to the CPU after the system powers on, its address space is designed in hardware to stably respond to bus requests. By reusing this address region as the cache back-end, the cache controller's access requirements for the back-end memory can be met without designing separate virtual address response logic: read requests return 0x0 to trigger write allocation, and write requests are ignored but return a normal response signal to complete the cache block allocation process. In scenarios without on-chip static random access memory, this implements the function of the cache memory as a temporary writable storage medium, while avoiding the addition of new hardware modules, simplifying system design, reducing costs, and ensuring that code and data during the boot ROM phase can be efficiently loaded and executed through the cache memory.

[0042] Specifically, the cache memory controller sends a read request to the system bus for the cache back-end response area; the cache memory controller receives the read data returned from the system bus and merges the read data with the startup data to be written; allocates a cache block in the data cache and stores the merged data into the cache block; and marks the status of the cache block as modified.

[0043] When the CPU first misses a write operation to the cache back-end response area, the cache controller performs a write allocation operation via the system bus. In the absence of on-chip static random access memory (SRAM), it dynamically constructs temporary writable storage space using the data cache. After the controller sends a read request to the system bus, it receives a fixed 0x0 data return and merges it with the startup data to be written. This ensures that even if there is no valid data in the original address area, a complete executable code or data block can be generated in the cache through the merging operation. Subsequently, a cache block is allocated and the merged data is stored, effectively providing a temporary high-speed storage medium for the startup data. Marking the cache block as modified tracks data changes, preventing data loss due to subsequent cache replacement. Dynamic management of startup data can be achieved without relying on on-chip SRAM. The high-speed characteristics of the cache improve data access efficiency, while the write allocation mechanism and status marking ensure data consistency. This allows code and data in the startup read-only memory stage to be executed directly in the cache, simplifying system hardware design and reducing costs. When the CPU accesses the same address again, since the data already exists in the cache (i.e., a cache hit occurs), the CPU can directly read or modify the data from the cache without needing to access external storage devices via the bus, thus avoiding the latency caused by bus transmission.

[0044] S300, the central processing unit loads and executes the startup code and the startup data in the cache block.

[0045] Specifically, the total capacity of the startup code and startup data does not exceed the available space of the data cache. The central processing unit (CPU) loads and executes the startup code and startup data in the cache block, limiting their total capacity to no more than the available space of the data cache. This serves to ensure that, in the absence of on-chip static random access memory (SRAM), the cache acts as a temporary executable and writable storage medium, allowing the CPU to directly access and run the code and data during the startup phase. Since the access speed of the cache is much higher than that of external storage devices, this method avoids startup process interruptions due to a lack of on-chip SRAM. Furthermore, by controlling the capacity to not exceed the available cache space, cache overflow or frequent cache replacement operations are prevented, keeping the startup code and data valid in the cache and reducing reliance on external storage and access latency. This eliminates the need for an additional on-chip SRAM hardware module, saving chip area and cost. Simultaneously, the high-speed characteristics of the cache improve the execution efficiency of the startup code, ensuring the stability and speed of the startup process, enabling the entire startup process to be completed smoothly on a resource-constrained on-chip system.

[0046] As an optional implementation, the method further includes: when the external master control device needs to be initialized during the startup phase, the external master control device accesses the data cache of the central processing unit through an input / output consistency interface.

[0047] When the external master device needs to be initialized during the startup phase, it accesses the CPU's data cache through the input / output consistency interface. This allows the external master device to directly read or modify the startup data stored in the data cache. Since the startup data is stored in the data cache rather than on-chip static random access memory (SRAM), the external master device can share the information in the data cache with the CPU through this interface, avoiding the problem of the external device being unable to obtain startup data due to the lack of on-chip SRAM. Without the need for additional storage media, the external master device can directly access the data cache, reducing data transmission paths, improving the initialization efficiency of the external device during the startup phase, while maintaining data access consistency. This ensures that the operation results of the external device and the CPU are mutually visible, conforming to the bus protocol specifications and simplifying system design. In the Advanced Scalable Interface (ASI) bus signals, the memory attribute signal AXCACHE[3:0] is configured as a four-bit binary value 1111. This ensures that when the external master device accesses the CPU's data cache through the input / output consistency interface, it can correctly identify the status of the cache block, achieving efficient data reading and writing and consistency maintenance, avoiding data access errors or performance degradation caused by cache policy mismatch.

[0048] This invention provides a boot control device for a system-on-a-chip (SoC), applied to an SoC including: a central processing unit (CPU), a boot read-only memory (ROM), and a system bus; the CPU includes a cache memory controller; the device includes:

[0049] An initialization module is used to initialize the high-speed cache memory controller through the central processing unit after the on-chip system is powered on, enabling data caching and write allocation functions;

[0050] The cache allocation module is used to automatically allocate a cache block in the data cache when the central processing unit first initiates a write operation to the preset cache back-end response area to write startup data. If the write operation fails, the cache memory controller completes the write allocation operation via the system bus. In the address space of the startup read-only memory, a reserved address space is designated as the cache back-end response area. The reserved address space can respond to read and write requests on the system bus.

[0051] An execution module is used to load and execute the startup code and startup data in the cache block via the central processing unit.

[0052] This invention provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the on-chip system startup control method of this invention.

[0053] This invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that the processor executes the computer program to implement the steps of the system-on-chip startup control method of this invention.

[0054] The embodiments of the present invention described above do not constitute a limitation on the scope of protection of the present invention.

Claims

1. A method of boot control of a system on chip, applied to a system on chip, characterized in that, The system on chip includes a central processing unit, a boot read-only memory and a system bus, the central processing unit includes a cache memory controller; the method includes the following steps: S100, after the system on chip is powered on, the central processing unit initializes the cache memory controller, enables the data cache and the write allocation function; S200, when the central processing unit initiates a write operation to a preset cache back-end response area for the first time to write boot data, the write operation is missed, the cache memory controller completes a write allocation operation in the data cache via the system bus to automatically allocate a cache block; Wherein, in the address space of the boot read-only memory, a reserved address space is designated as a cache back-end response area, the reserved address space can respond to read and write requests on the system bus; wherein, the cache memory controller sends a read request to the cache back-end response area to the system bus; the cache memory controller receives read data returned from the system bus and merges the read data with the boot data to be written; a cache block is allocated in the data cache and the merged data is stored in the cache block; the state of the cache block is marked as modified; S300, the central processing unit loads and executes the boot code and the boot data in the cache block.

2. The method of boot control of a system on chip according to claim 1, wherein, Step S100 further includes: enabling a monitoring mechanism and an instruction cache, disabling a cache prefetch function and automatically adjusting a write allocation strategy function.

3. The method of boot control of a system on chip according to claim 1, wherein, In step S200, the response mode of the reserved address space on the system bus includes: returning a preset constant to a read request and returning a normal response signal to a write request.

4. The method of boot control of a system on chip according to claim 1, wherein, In step S200, the reserved address space is mapped to a physical address area of the boot read-only memory.

5. The method of boot control of a system on chip according to claim 1, wherein, In step S300, the total capacity of the boot code and the boot data does not exceed the available space of the data cache.

6. The method of boot control of a system on chip according to claim 1, wherein, Further comprising: When the boot stage needs to initialize an external host device, the external host device accesses the data cache of the central processing unit through an input-output consistency interface.

7. A start-up control apparatus of a system on chip, applied to a system on chip, characterized by comprising: The system on chip includes a central processing unit, a boot read-only memory and a system bus, the central processing unit includes a cache memory controller; the device includes: An initialization module, configured to initialize the cache memory controller through the central processing unit after the system on chip is powered on, enable the data cache and the write allocation function; The cache allocation module is configured to, when the central processing unit initiates a write operation to the preset cache back-end response area for writing start-up data for the first time, and the write operation is not hit, complete a write allocation operation via the system bus through the cache controller to automatically allocate a cache block in the data cache; wherein, in the address space of the start-up ROM, a reserved address space is designated as the cache back-end response area, and the reserved address space can respond to read and write requests on the system bus; wherein, the cache controller sends a read request to the cache back-end response area to the system bus; the cache controller receives read data returned from the system bus and merges the read data with the start-up data to be written; a cache block is allocated in the data cache, and the merged data is stored in the cache block; and the state of the cache block is marked as modified; The execution module is configured to load and execute start-up code and the start-up data in the cache block through the central processing unit.

8. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 6.

9. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the steps of the method in any one of claims 1 to 6.

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