A large number multiplication and addition acceleration method and architecture based on static random access memory in-memory computing

Abstract

The application discloses a large number modular multiplication acceleration method and architecture based on static random access memory (SRAM) in-memory computing. According to the input multiplicand, multiplier and modulus, the modular multiplication operation is decomposed into multiple large integer multiplication operations based on the Barrett modular multiplication process. According to the components in the decomposed large integer multiplication operations as the polling operands, the components are sequentially input into the in-memory computing multiplication-addition macro array in the SRAM to perform multiplication-addition operations and generate partial sums. The partial sums are aggregated and added to obtain the execution results of the large integer multiplication operations. The execution results are subjected to a shift and truncation operation, and the results after the shift and truncation are subtracted from the modulus to obtain the modular multiplication result of the multiplicand and the multiplier with respect to the modulus. The application reduces the iteration number and resource occupation of high-bit-width modular multiplication operation through hardware reuse and parallel scheduling based on the SRAM in-memory computing and the Barrett modular multiplication process, and improves the operation efficiency and scalability.

Description

Technical Field

[0001] This invention belongs to the field of information security hardware acceleration technology, and in particular relates to a method and architecture for accelerating large number modular multiplication based on in-memory computation of static random access memory. Background Technology

[0002] With the development of applications such as privacy computing, trusted computing, and blockchain, terminals and servers frequently invoke public-key cryptography algorithms, such as elliptic curve cryptography (ECC), RSA, homomorphic encryption (HE), and zero-knowledge proofs (ZKP), in tasks such as identity authentication, key exchange, and digital signatures. The underlying core of these algorithms heavily relies on large integer modular arithmetic, with the most typical and time-consuming operation being large integer modular multiplication (R = A·B mod M). When the bit width reaches hundreds of bits or more, modular multiplication becomes the main bottleneck for system latency and energy consumption.

[0003] Existing software or general-purpose processors often adopt the "multiply first, then reduce" approach. To avoid the high cost of direct division, methods such as Barrett reduction or Montgomery modular multiplication are commonly introduced to transform division into a combination of shifting, addition, subtraction, and multiplication to improve efficiency.

[0004] To reduce data transfer overhead, in-memory computing (CiM) has been proposed. It utilizes SRAM or ReRAM arrays to trigger bitwise logic operations or partial product generation and accumulation within the memory, reducing data round trips between the memory and processor, and thus reducing memory access power consumption to some extent.

[0005] However, for large integer modular multiplication scenarios with bit widths of 224 bits to 512 bits and above, existing in-memory computation schemes still have the following shortcomings: First, existing solutions employ a process of "bit-by-bit iteration + multiple rounds of accumulation + multiple reductions," where the number of iteration rounds is directly proportional to the bit width. This leads to a significant increase in array trigger counts, external carry chains, and control overhead with increasing bit width, limiting throughput and energy efficiency improvements. Second, a single high-bit-width modulo multiplication requires hundreds of clock cycles, during which the SRAM array is occupied for an extended period, making it impossible to handle regular memory accesses or other computational tasks simultaneously, resulting in resource locking and decreased system parallelism. Third, bit width expansion is costly: without increasing array size, the number of cycles skyrockets; increasing array size leads to a simultaneous increase in area, power consumption, and complexity, creating a dilemma between "latency degradation" and "area surge."

[0006] Therefore, how to improve the throughput and resource utilization efficiency of large-bit-width modular multiplication operations without significantly increasing hardware overhead, and adapt to the bit-width expansion requirements of different security levels, is a challenge faced by those skilled in the art. Summary of the Invention

[0007] To address the aforementioned technical problems, this invention provides a method for accelerating large number modular multiplication based on in-memory computation using static random access memory, comprising the following steps: Based on the input multiplicand, multiplier, and modulus, the modular multiplication operation is broken down into multiple large integer multiplication operations according to the Barrett modular multiplication process; Decompose the operands in each large integer multiplication operation into multiple low-width components; The components that serve as resident operands in each decomposed large integer multiplication operation are written into the static random access memory to calculate the multiply-accumulate macro array. Based on the components used as polling operands in each decomposed large integer multiplication operation, they are sequentially input into the multiply-accumulate macro array stored in the static random access memory, triggering the array to execute multiply-accumulate operations in parallel to generate partial sums; The partial sums are aggregated and accumulated using an outer addition tree and accumulation units to obtain the execution results of each large integer multiplication operation; The shift unit is invoked to perform a shift truncation operation on the result of the multiplication operation of the specified second largest integer, and the subtractor is invoked to perform subtraction refinement on the modulus based on the shifted and truncated result, so as to obtain the modular multiplication result of the multiplicand and multiplier with respect to the modulus.

[0008] Optionally, based on the input multiplicand, multiplier, and modulus, the modular multiplication operation is broken down into multiple large integer multiplication operations according to the Barrett modular multiplication process, including: Based on the modulus, pre-calculate and store the Barrett modular multiplication constant; The first large integer multiplication is performed by calling the computational multiply-add macroarray stored in the static random access memory, and the first product is obtained based on the multiplicand and the multiplier. The shift unit is invoked to truncate the high bits of the first product, and based on the truncation result and the Barrett modular multiplication constant, the static random access memory is invoked to perform a second large integer multiplication using the in-memory computational multiply-add macroarray to obtain the second product; The shift unit is invoked to truncate the high-order bits of the second product, and based on the truncation result and the modulus, the multiply-add macroarray stored in the static random access memory is invoked to perform a third large integer multiplication to obtain the third product.

[0009] Optionally, the operands in each large integer multiplication operation are decomposed into multiple low-bit-width components, including: Each operand in each large integer multiplication operation is decomposed into multiple operand components according to a fixed low bit width.

[0010] Optionally, the components used as resident operands in each decomposed large integer multiplication operation are written into a multiply-accumulate macro array stored in static random access memory, including: Before each large integer multiplication operation is performed, the operand components, which are resident operands, are written into the static random access memory to compute the multiply-accumulate macro array through the input buffer.

[0011] Optionally, based on the components used as polling operands in each of the decomposed large integer multiplication operations, the components are sequentially input into the static random access memory's multiply-accumulate macroarray to trigger the array to perform multiply-accumulate operations in parallel, generating partial sums, including: According to the preset timing sequence, the operand components, which are used as polling operands, are sequentially input into the static random access memory (SRAM) containing the resident operands to calculate the multiply-accumulate macro array. The static random access memory-in-memory computation multiply-accumulate macroarray performs multiple multiply-accumulate operations corresponding to the low-bit width components in parallel within each cycle and outputs a partial sum; The partial sums of the outputs of each cycle are aggregated by using an outer addition tree and an accumulation unit, and the aggregated result is carried over to obtain the complete large integer multiplication result.

[0012] Optionally, the static random access memory stores a multiply-accumulate macro array consisting of multiple macros configured in parallel, and the method further includes: Based on the workload of large integer multiplication operations to be performed, the dispatcher distributes them to multiple parallel macros for parallel execution; The parallel execution results of multiple macros are merged through an addition tree, reducing the number of cycles required to complete a single large integer multiplication.

[0013] Optionally, it also includes: When the bit width of the large integer multiplication operation to be performed exceeds the preset threshold, the controller optimizes the input timing by workload grouping. The workload grouping optimization includes dividing effective multiply-accumulate tasks into multiple workload groups according to predetermined rules, allocating tasks within the same workload group to multiple parallel macros for parallel processing within the same cycle, and controlling the input buffer to skip redundant cycles that only contain invalid padding.

[0014] On the other hand, the present invention also proposes a large number modular multiplication acceleration architecture based on static random access memory (SRAM) computation for implementing the method, comprising: The controller is used to control the execution order of modular multiplication operations according to the Barrett modular multiplication process; A static random access memory (SRAM) in-memory multiply-accumulate macroarray is used to write resident operands and perform multiply-accumulate operations in parallel based on the input polled operands, outputting a partial sum; An input buffer, connected to the static random access memory, is used to input polling operand components into the array under the control of the controller. The addition tree and accumulation unit are connected to the output of the multiply-accumulate macro array stored in the static random access memory, and are used to aggregate and accumulate the partial sums to generate large integer multiplication results; Intermediate result buffer, used to temporarily store intermediate results of each large integer multiplication operation; A shift unit is used to perform shift and truncation operations on the intermediate results; A subtractor is used to perform subtraction refinement based on the result of the last large integer multiplication and the modulus to obtain the final modular multiplication result; A distributor, under the control of the controller, routes data to the intermediate result buffer or the subtractor.

[0015] Optionally, there are multiple static random access memory (SRAM) in-memory multiply-accumulate macro arrays, and the acceleration architecture further includes an addition tree. The input of the addition tree is connected to the output of the multiple SRAM in-memory multiply-accumulate macro arrays, for merging the parallel execution results of the multiple macros.

[0016] Optionally, the controller is further configured to optimize the input timing by workload grouping when the bit width of the large integer multiplication operation to be performed is extended to a preset threshold or above, divide the effective multiply-accumulate tasks into multiple workload groups according to a predetermined rule, allocate the tasks in the same workload group to multiple parallel macros for parallel processing in the same cycle, and control the input buffer to skip redundant cycles that only contain invalid padding.

[0017] Compared with the prior art, the present invention has the following advantages and technical effects: This invention employs Barrett modular multiplication as the overall computational path, breaking down a complete modular multiplication operation into three large integer multiplications and a small number of shift truncation and subtraction refinements. Through controller scheduling, these three multiplications reuse the same SRAM-based in-memory computational multiply-add macroarray and adder tree path, while the multiplier, modulus, and pre-calculated constants are pre-written into the array as resident data. Based on this, this invention significantly reduces the repeated loading and handling of data between different stages during modular multiplication, lowers the dependence on external storage bandwidth, and allows computational resources to be more consistently allocated to effective computation, avoiding idle waiting caused by frequent operand loading, thereby improving overall computational efficiency.

[0018] This invention decomposes large integers into multiple components with a fixed low bit width, and inputs these components into SRAM at a fixed timing sequence for multiplication and addition operations. Externally, an addition tree is used to aggregate the partial sums of the macro outputs, and carry and combination are completed by writing the low-order parts to a result register and the high-order parts to a temporary register, accumulating across cycles. This approach avoids the hardware overhead of introducing large-bit-width carry chains and complex external multipliers in traditional schemes, ensuring a high effective computational density of the macro array within each computation cycle. Simultaneously, the carry processing and accumulation processes are naturally integrated into the pipeline rhythm, guaranteeing computational accuracy without adding extra computation cycles.

[0019] This invention supports both single-macro serial and multi-macro parallel operating modes. In the multi-macro parallel configuration, a distributor feeds different input segments of the same multiplication into multiple SRAM macros in parallel, and an addition tree is used to merge the outputs of each macro, so that the number of cycles required to complete one multiplication decreases synchronously as the number of macros increases. When the bit width is extended to a higher security level, this invention further optimizes the input timing by workload grouping, dividing the effective multiply-accumulate tasks into multiple workload groups according to rules, allocating tasks in the same group to multiple macros for parallel processing within the same cycle, and skipping redundant cycles containing only zero padding. This effectively suppresses the macro idling problem under high bit width, and the number of cycles maintains a steady increase as the bit width increases. Designers can flexibly configure the number of macros according to area budget, achieving a balance between performance and cost.

[0020] Based on the above-mentioned technical means, this invention improves the overall efficiency, resource utilization, and scalability of modular multiplication operations. By reusing hardware paths to reduce redundant loading, simplifying peripheral circuits through bitwise decomposition and cross-cycle accumulation, and suppressing high-bit-width cycle expansion through multi-macro parallelism and grouping optimization, this invention provides more efficient underlying operator support for high-bit-width modular multiplication-intensive applications such as homomorphic encryption and zero-knowledge proofs. Attached Figure Description

[0021] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram of the method flow according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the system structure according to an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the mapping of large integer multiplication workloads to SRAM memory for multiply-add macros in an embodiment of the present invention. Figure 4 This is a schematic diagram of the input timing and multi-macro parallel processing in an embodiment of the present invention; Figure 5This is a comparative diagram of naive scaling and workload grouping optimization under high bit-width expansion according to an embodiment of the present invention; wherein, Figure 5 (a) is a schematic diagram of input timing and macro utilization under naive scaling. Figure 5 (b) is a schematic diagram of input timing and macro utilization under the workload grouping optimization method; Figure 6 This is a comparison curve of the multiplication delay under different bit widths in an embodiment of the present invention. Detailed Implementation

[0022] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0023] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0024] Example 1 like Figure 1 As shown, this embodiment proposes a method for accelerating large number modular multiplication based on in-memory computation using static random access memory, such as... Figure 1 As shown, this embodiment proposes a method for accelerating large number modular multiplication based on in-memory computation using static random access memory. This method consists of, as follows: Figure 2 The hardware architecture shown will be used for execution. The following will combine... Figure 1 and Figure 2 The technical solution of this embodiment will be described in detail.

[0025] like Figure 1 As shown, this method uses Barrett modular multiplication as the main thread, breaking down a complete modular multiplication operation into three large integer multiplications and subsequent subtraction and refinement steps. Specifically, the first multiplication is performed to calculate the product C of A and B; then, combined with the pre-calculated Barrett constant M', the second multiplication is performed to obtain the intermediate quantity u; next, u is shifted and truncated before the third multiplication is performed to obtain P; finally, through subtraction and refinement adjustments of C and P, the final modular multiplication result R is output. Throughout the entire process, the three multiplications reuse the same SRAM in-memory computation hardware path.

[0026] Specifically, the following steps are included: Based on the input multiplicand, multiplier, and modulus, the modular multiplication operation is broken down into multiple large integer multiplication operations according to the Barrett modular multiplication process; Decompose the operands in each large integer multiplication operation into multiple low-width components; The components that serve as resident operands in each decomposed large integer multiplication operation are written into the static random access memory to calculate the multiply-accumulate macro array. Based on the components used as polling operands in each decomposed large integer multiplication operation, they are sequentially input into the multiply-accumulate macro array stored in the static random access memory, triggering the array to execute multiply-accumulate operations in parallel to generate partial sums; The partial sums are aggregated and accumulated using an outer addition tree and accumulation units to obtain the execution results of each large integer multiplication operation; The shift unit is invoked to perform a shift truncation operation on the result of the multiplication operation of the specified second largest integer, and the subtractor is invoked to perform subtraction refinement on the modulus based on the shifted and truncated result, so as to obtain the modular multiplication result of the multiplicand and multiplier with respect to the modulus.

[0027] like Figure 2 As shown, this embodiment also provides a large number modular multiplication acceleration architecture based on in-memory computation in static random access memory (SRAM) for implementing the method. This architecture mainly includes: a controller, an input buffer, a shift unit, an in-memory MAC macroarray, an addition tree and an accumulation / temporary register, a dispatcher, an intermediate result buffer, a subtractor, and a result register. The controller schedules three multiplication and refinement operations according to the Barrett flow; the input buffer is used to input polling operands into the macroarray; the shift unit performs the required "take high-order bit / right shift truncation" operation; the dispatcher is responsible for routing the results to the corresponding buffer or subtractor at different stages; the intermediate result buffer is used to store intermediate quantities such as C and u; and the subtractor array performs the final refined subtraction.

[0028] As one feasible implementation method, the architecture specifically includes: The controller is used to control the execution order of modular multiplication operations according to the Barrett modular multiplication process; A static random access memory (SRAM) in-memory multiply-accumulate macroarray is used to write resident operands and perform multiply-accumulate operations in parallel based on the input polled operands, outputting a partial sum; An input buffer, connected to the static random access memory, is used to input polling operand components into the array under the control of the controller. The addition tree and accumulation unit are connected to the output of the multiply-accumulate macro array stored in the static random access memory, and are used to aggregate and accumulate the partial sums to generate large integer multiplication results; Intermediate result buffer, used to temporarily store intermediate results of each large integer multiplication operation; A shift unit is used to perform shift and truncation operations on the intermediate results; A subtractor is used to perform subtraction refinement based on the result of the last large integer multiplication and the modulus to obtain the final modular multiplication result; A distributor, under the control of the controller, routes data to the intermediate result buffer or the subtractor.

[0029] Furthermore, there are multiple static random access memory (SRAM) in-memory computation multiply-accumulate macro arrays, and the acceleration architecture also includes an addition tree. The input of the addition tree is connected to the output of the multiple SRAM in-memory computation multiply-accumulate macro arrays, which is used to merge the parallel execution results of the multiple macros.

[0030] As a specific implementation method, this embodiment provides a large integer modular multiplication implementation scheme based on in-memory computation of multiply-add macros in static random access memory (SRAM), targeting 256-bit, 512-bit, and higher bit-width modular multiplication operations commonly used in scenarios such as homomorphic encryption and zero-knowledge proofs. This scheme uses the Barrett modular multiplication process as the main computational thread, breaking down a single modular multiplication into "three large integer multiplications + a small number of subtractions for refinement," and uniformly mapping the three multiplications to an in-memory SRAM MAC macro array for execution, thereby reducing the array occupancy cycle of a single modular multiplication and improving scalability.

[0031] Implementable, based on the input multiplicand, multiplier, and modulus, the modular multiplication operation is broken down into multiple large integer multiplication operations according to the Barrett modular multiplication process, including: Based on the modulus, the Barrett modular multiplication constant is pre-calculated and stored; the static random access memory (SRAM) is used to perform the first large integer multiplication using the in-memory multiplication and addition macroarray, and the first product is obtained based on the multiplicand and multiplier; the shift unit is used to truncate the high-order bits of the first product, and based on the truncation result and the Barrett modular multiplication constant, the SRAM is used to perform the second large integer multiplication, and the second product is obtained; the shift unit is used to truncate the high-order bits of the second product, and based on the truncation result and the modulus, the SRAM is used to perform the third large integer multiplication, and the third product is obtained.

[0032] Furthermore, the operands in each large integer multiplication operation are decomposed into multiple low-width components, including: decomposing each operand in each large integer multiplication operation according to a fixed low-width to obtain multiple operand components.

[0033] Furthermore, the components that serve as resident operands in each decomposed large integer multiplication operation are written into the static random access memory (SRAM) multiply-accumulate macro array. This includes: before each large integer multiplication operation is executed, the operand components that serve as resident operands are written into the SRAM multiply-accumulate macro array through an input buffer.

[0034] As a specific implementation method, to illustrate the modular multiplication objective, let the input be an n-bit unsigned integer. First calculate the product The modular multiplication result satisfies: This embodiment preferably employs an "offline pre-calculation + online triple multiplication" approach. In the offline stage, due to the modulus... Typically fixed within the same application, the constants can be pre-calculated: And Write to on-chip storage for reuse in the online phase.

[0035] In practice, based on the components used as polling operands in each decomposed large integer multiplication operation, the components are sequentially input into the static random access memory's multiply-accumulate macroarray to trigger the array to perform multiply-accumulate operations in parallel, generating partial sums, including: According to the preset timing sequence, the operand components, which are used as polling operands, are sequentially input into the static random access memory (SRAM) in-memory computation multiply-accumulate macro array, which has been written with resident operands. The SRAM in-memory computation multiply-accumulate macro array performs multiple multiply-accumulate operations corresponding to the low-width components in parallel in each cycle and outputs a partial sum. The partial sums output in each cycle are aggregated through an external addition tree and an accumulation unit, and the aggregated result is carried over to obtain the complete large integer multiplication result.

[0036] The specific process includes: The first step in the online phase is computation. To adapt large integer multiplication to the SRAM-in-memory MAC macroarray, this embodiment decomposes the input into 8 bits and represents it in weighted sum form (as shown in the following formula), where and For 8-bit components: Based on this, the product can be expressed as a weighted sum of the products of each 8-bit component: like Figure 3 As shown, this embodiment will The data is written to the SRAM array to form reusable multiplication "resident" operands, which are then periodically fed into the input buffer. The SRAM-stored MAC macro performs multiple 8-bit multiplication and addition in parallel within each cycle, and the output of the current cycle is aggregated by the external addition tree / accumulation unit, thereby gradually obtaining the weighted partial sum required by equation (4), and writing it into the result register to form the weighted partial sum. This "resident data + polling input" approach effectively reduces data transfer costs.

[0037] like Figure 4As shown, when multiple SRAM-in-memory MAC macros are configured, this embodiment distributes the workload of different columns / segments of the same multiplication to multiple macros for parallel execution, and merges the outputs of each macro through an addition tree, thereby reducing the number of cycles required to complete C without changing the mathematical meaning of equation (4). Compared with single-macro serial processing, multi-macro parallel processing can significantly reduce the number of cycles required to complete one multiplication and improve throughput performance. Furthermore, when the bit width is extended to 1024 bits and above, naive scaling will still introduce boundary idle cycles. This embodiment... Figure 5 The corresponding high bit width optimization method is given in the document.

[0038] like Figure 5 As shown in (a), when the bit width is extended to 1024 bits or more, if the following method is used... Figure 4 The input timing shown is naively scaled. Due to the sparse effective terms in the boundary stage of large integer multiplication, there will be a large number of zero-filled or insufficient effective workload cycles in the input sequence. This causes some MAC macros in SRAM to be idle (idling) or underutilized for multiple cycles, resulting in resource waste and increasing the total number of cycles required to complete one multiplication.

[0039] like Figure 5 As shown in (b), in order to reduce the idle overhead caused by the high bit width expansion, this embodiment further proposes workload grouping optimization: when generating input timing, the controller divides the effective multiply-accumulate tasks into several workload groups according to a predetermined rule, and allocates the tasks to multiple SRAM macros for parallel execution within the same group, so that each SRAM macro can process effective input as much as possible in the same cycle; at the same time, redundant cycles containing only zero padding are skipped or not scheduled for execution, thereby reducing invalid calculation cycles and improving the actual utilization of multi-macro parallelism, further reducing the execution cycle of high bit width multiplication and improving the scalability of bit width expansion.

[0040] After completing the first step of multiplication, we get Subsequently, this embodiment continues to execute the second and third multiplications and subtraction refinement in the Barrett process, and these two multiplications are also reused. Figure 2 The same SRAM-based MAC multiplication path can be used, which can be completed simply by switching the input source and shift parameters through the controller. During the online phase, the following steps are executed sequentially: ; ; ; ; ; Then the subtractor performs refinement: according to and The size relationship, for Perform one or two subtractions to bring the result back to the previous state. The range is determined to obtain the final remainder. ,Right now or or Through the above "unified multiplication mapping (equations (3) and (4)) + multi-macro parallel input timing scheduling ( Figure 4 ) + High-bandwidth workload grouping optimization ( Figure 5 With its overall organization of "multiplication using the same SRAM MAC path for three multiplications + a small number of subtractions for refinement", this embodiment can reduce invalid computations and long-term resource locking in high-bit-width scenarios while ensuring the correctness of modular multiplication, providing higher throughput and more easily scalable underlying support for privacy computing such as HE and ZKP.

[0041] Large integer modular multiplication is a core fundamental operation in applications such as elliptic curve cryptography, RSA, zero-knowledge proofs, and homomorphic encryption. Its performance often directly determines the end-to-end throughput and response latency of a system. Meanwhile, security levels are typically achieved by increasing bit width, which significantly increases the computational cost of modular multiplication. This leads to problems such as rapidly increasing latency and decreasing energy efficiency in existing implementations at high bit widths. Therefore, the key to evaluating the engineering value of a modular multiplication acceleration technique lies in its ability to maintain good scalability while continuously increasing bit width, and to achieve a stable advantage under acceptable implementation costs (such as area).

[0042] like Figure 6 As shown, the latency of modular multiplication generally increases as the bit width increases from lower security levels to higher security levels such as 256 bits, 512 bits, and 1024 bits. Compared to other solutions, the curve corresponding to this embodiment is generally lower, and its advantage is more obvious in the high bit width range. This indicates that this embodiment is not only effective at a single bit width, but also maintains good scalability as the bit width increases. It can alleviate the problem of "excessively rapid latency growth and significant throughput decline" in existing technologies in high bit width scenarios, and is more suitable for applications that heavily rely on high bit width modular multiplication, such as zero-knowledge proofs and homomorphic encryption.

[0043] To further reflect the above trends at the implementation level, Figure 6 This paper presents a comparison of this embodiment with several existing solutions in terms of target applications, bit width coverage, operating frequency, number of cycles required to complete one operation, and comprehensive indicators related to area. Overall, it can be seen that this embodiment not only addresses the typical high-bit-width modular multiplication requirements of elliptic curve cryptography and RSA, but also completes a modular multiplication in fewer cycles at the same operating frequency, thus directly resulting in lower single-operation latency.

[0044] Table 1 Specifically, taking 256-bit modular multiplication as an example, Table 1 shows that the cycle time required to complete one operation in this embodiment is significantly less than that of the comparative scheme (104 cycles in this invention, while 767 cycles in the comparative scheme ModSRAM). Under operating frequencies of 400MHz and 420MHz respectively, converted to a time scale, this embodiment achieves approximately 0.26 microseconds per modular multiplication, corresponding to approximately 7.02 times the latency reduction / speed improvement. Meanwhile, from the perspective of the more practical engineering metric of "latency × area," this embodiment has a smaller value (e.g., 0.029 in this invention, compared to 0.09 for ModSRAM and 0.073 for BP-NTT), indicating that this invention is not only "faster" but also achieves higher overall efficiency under chip area constraints, avoiding the unsustainable path of trading speed for a significant increase in area.

[0045] Furthermore, Table 1 also reflects that many existing in-memory computing acceleration solutions are mainly aimed at specific operators such as number-theoretic transformation (NTT) in post-quantum cryptography or homomorphic encryption, and the bit width coverage is often concentrated in the lower bit width range; while this embodiment is aimed at the needs of high bit width modular multiplication mainline and has a more flexible bit width expansion capability (shown in the table as supporting arbitrary bit width), so that it can still reuse the same operator route and hardware organization method when upgrading to different security levels, making engineering migration and expansion more convenient.

[0046] In summary, combining Figure 6 Compared with the implementation metrics in Table 1, this embodiment achieves lower latency (e.g., an advantage of about 7.02 times under 256-bit) and better overall efficiency (e.g., an improvement of about 3.10 times in latency × area metrics compared to ModSRAM) in high-bit-width modular multiplication scenarios, thereby significantly improving the overall throughput and scalability of modular multiplication-intensive privacy computing and secure computing systems.

[0047] The above are merely preferred embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for accelerating large number modular multiplication based on in-memory computation using static random access memory, characterized in that, Includes the following steps: Based on the input multiplicand, multiplier, and modulus, the modular multiplication operation is broken down into multiple large integer multiplication operations according to the Barrett modular multiplication process; Decompose the operands in each large integer multiplication operation into multiple low-width components; The components that serve as resident operands in each decomposed large integer multiplication operation are written into the static random access memory to calculate the multiply-accumulate macro array. Based on the components used as polling operands in each decomposed large integer multiplication operation, they are sequentially input into the multiply-accumulate macro array stored in the static random access memory, triggering the array to execute multiply-accumulate operations in parallel to generate partial sums; The sums of the aforementioned parts are aggregated to obtain the execution results of each large integer multiplication operation; The result of the multiplication operation of the specified second largest integer is shifted and truncated, and the result of the shifted and truncated multiplication is subtracted from the modulus to refine the result, so as to obtain the modular multiplication result of the multiplicand and multiplier with respect to the modulus.

2. The method according to claim 1, characterized in that, Based on the input multiplicand, multiplier, and modulus, and following the Barrett modular multiplication process, the modular multiplication operation is broken down into multiple large integer multiplication operations, including: Based on the modulus, pre-calculate and store the Barrett modular multiplication constant; The first large integer multiplication is performed by calling the computational multiply-add macroarray stored in the static random access memory, and the first product is obtained based on the multiplicand and the multiplier. The shift unit is invoked to truncate the high bits of the first product, and based on the truncation result and the Barrett modular multiplication constant, the static random access memory is invoked to perform a second large integer multiplication using the in-memory computational multiply-add macroarray to obtain the second product; The shift unit is invoked to truncate the high-order bits of the second product, and based on the truncation result and the modulus, the multiply-add macroarray stored in the static random access memory is invoked to perform a third large integer multiplication to obtain the third product.

3. The method according to claim 1, characterized in that, Each large integer multiplication operation decomposes the operands into multiple low-bit components, including: Each operand in each large integer multiplication operation is decomposed into multiple operand components according to a fixed low bit width.

4. The method according to claim 1, characterized in that, The components used as resident operands in each of the decomposed large integer multiplication operations are written into the static random access memory (SRAM) to compute a multiply-accumulate macro array, including: Before each large integer multiplication operation is performed, the operand components, which are resident operands, are written into the static random access memory to compute the multiply-accumulate macro array through the input buffer.

5. The method according to claim 1, characterized in that, Based on the components used as polling operands in each decomposed large integer multiplication operation, they are sequentially input into the multiply-accumulate macroarray stored in the static random access memory, triggering the array to execute multiply-accumulate operations in parallel to generate partial sums, including: According to the preset timing sequence, the operand components, which are used as polling operands, are sequentially input into the static random access memory (SRAM) containing the resident operands to calculate the multiply-accumulate macro array. The static random access memory-in-memory computation multiply-accumulate macroarray performs multiple multiply-accumulate operations corresponding to the low-bit width components in parallel within each cycle and outputs a partial sum; The partial sums of the outputs of each cycle are aggregated by using an outer addition tree and an accumulation unit, and the aggregated result is carried over to obtain the complete large integer multiplication result.

6. The method according to claim 5, characterized in that, The static random access memory in-memory computation multiply-accumulate macro array consists of multiple macros configured in parallel, and the method further includes: Based on the workload of large integer multiplication operations to be performed, the dispatcher distributes them to multiple parallel macros for parallel execution; The parallel execution results of multiple macros are merged through an addition tree, reducing the number of cycles required to complete a single large integer multiplication.

7. The method according to claim 6, characterized in that, Also includes: When the bit width of the large integer multiplication operation to be performed exceeds the preset threshold, the controller optimizes the input timing by workload grouping. The workload grouping optimization includes dividing effective multiply-accumulate tasks into multiple workload groups according to predetermined rules, allocating tasks within the same workload group to multiple parallel macros for parallel processing within the same cycle, and controlling the input buffer to skip redundant cycles that only contain invalid padding.

8. A large number modular multiplication acceleration architecture based on static random access memory (SRAM) computation for implementing the method of any one of claims 1 to 7, characterized in that, include: The controller is used to control the execution order of modular multiplication operations according to the Barrett modular multiplication process; A static random access memory (SRAM) in-memory multiply-accumulate macroarray is used to write resident operands and perform multiply-accumulate operations in parallel based on the input polled operands, outputting a partial sum; An input buffer, connected to the static random access memory, is used to input polling operand components into the array under the control of the controller. The addition tree and accumulation unit are connected to the output of the multiply-accumulate macro array stored in the static random access memory, and are used to aggregate and accumulate the partial sums to generate large integer multiplication results; Intermediate result buffer, used to temporarily store intermediate results of each large integer multiplication operation; A shift unit is used to perform shift and truncation operations on the intermediate results; A subtractor is used to perform subtraction refinement based on the result of the last large integer multiplication and the modulus to obtain the final modular multiplication result; A distributor, under the control of the controller, routes data to the intermediate result buffer or the subtractor.

9. The architecture according to claim 8, characterized in that, The static random access memory (SRAM) in-memory computation multiply-accumulate macro arrays are multiple, and the acceleration architecture also includes an addition tree. The input of the addition tree is connected to the output of the multiple SRAM in-memory computation multiply-accumulate macro arrays, and is used to merge the parallel execution results of the multiple macros.

10. The architecture according to claim 8, characterized in that, The controller is also used to optimize the input timing by workload grouping when the bit width of the large integer multiplication operation to be performed is extended to a preset threshold or above. It divides the effective multiply-accumulate tasks into multiple workload groups according to a predetermined rule, allocates the tasks in the same workload group to multiple parallel macros for parallel processing in the same cycle, and controls the input buffer to skip redundant cycles that only contain invalid padding.

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