An SRAM integrated circuit structure, a static random access memory and its fabrication method

Abstract

This invention relates to the field of memory structure design technology, and discloses an SRAM integrated circuit structure, a static random access memory (SRAM), and its fabrication method. This invention proposes a novel SRAM integrated circuit structure through the design of five active regions and four polysilicon regions. In this structure, the first pull-up transistor and the second pull-down transistor of the same type are both formed on the fifth active region, making the overall integrated circuit structure design simpler. Furthermore, adjacent transistors can share drains or sources to reduce the integrated circuit area. Therefore, the SRAM integrated circuit structure of this invention reduces the complexity of the SRAM integrated circuit structure. On the other hand, in this invention, the metal layer connects the active region and the polysilicon region through contact structures. This eliminates the need for the contact structures to traverse uneven areas; they can directly connect the metal layer to the polysilicon region or the active region, which reduces the fabrication difficulty of the SRAM integrated circuit structure.

Description

Technical Field

[0001] This invention relates to the field of memory structure design technology, and in particular to an SRAM integrated circuit structure, a static random access memory and its fabrication method. Background Technology

[0002] Static Random-Access Memory (SRAM), as an important branch of semiconductor memory, has become an indispensable key component in modern computing systems since its inception due to its core advantages such as high-speed access, low power consumption, and full compatibility with standard CMOS processes. After years of development and widespread application, its circuit design and chip structure design have gradually formed some mainstream existing designs.

[0003] like Figure 1 As shown, Figure 1 The 6T SRAM circuit described is currently the mainstream SRAM circuit. This circuit mainly includes NMOS type first transfer transistor PG1, first pull-down transistor PD1, second pull-down transistor PD2, and second transfer transistor PG2; PMOS type first pull-up transistor PU1 and second pull-up transistor PU2; and word line WL and bit line BL / BLB. The four transistors PD1, PD2, PU1, and PU2 form a cross-coupled CMOS inverter pair. PU1 and PD1 form an inverter with an output at storage node SNR. PU2 and PD2 form another inverter with an output at storage node SNL. Read and write operations of this SRAM circuit are achieved by controlling the access transistors via word line WL and transmitting data via bit line BL / BLB.

[0004] like Figure 2 As shown, Figure 2 The 6T SRAM integrated circuit structure is the current mainstream SRAM integrated circuit structure. It includes four parallel active regions and four parallel polysilicon regions. The active regions and polysilicon regions are cross-contacted to form individual transistors, and are connected to the active regions and polysilicon regions through shared contact holes, thereby enabling... Figure 2 SRAM integrated circuit structure implementation Figure 1 The SRAM circuit in it.

[0005] On the one hand, with the increasingly widespread application of static random access memory (SRAM), the optimization design of its structure is constantly underway, and there is still room for improvement in the design complexity of existing SRAM integrated circuit structures. On the other hand, Figure 2The SRAM integrated circuit structure in SRAM is actually a three-dimensional structure, with the polysilicon region formed above the active region, creating a height difference between them. Therefore, if a shared contact hole is used to connect the active and polysilicon regions, the contact hole must traverse this uneven area, increasing the manufacturing complexity and often becoming the root cause of yield loss. In conclusion, it is necessary to continue improving the existing SRAM integrated circuit structure to optimize its design complexity and reduce its manufacturing difficulty. Summary of the Invention

[0006] This invention discloses an SRAM integrated circuit structure, a static random access memory, and a method for fabricating the same, which are used to optimize the complexity of SRAM integrated circuit structure design and reduce the process difficulty of SRAM integrated circuit structure.

[0007] The first aspect of this invention discloses an SRAM integrated circuit structure, the circuit structure comprising: First active region, second active region, third active region, fourth active region, fifth active region; First polysilicon region, second polysilicon region, third polysilicon region, fourth polysilicon region; Wherein, the first polysilicon region and the first active region are in contact to form a first pull-down transistor; the second polysilicon region and the second active region are in contact to form a second transmission transistor; the third polysilicon region and the third active region are in contact to form a first transmission transistor; the fourth polysilicon region and the fourth active region are in contact to form a second pull-down transistor; the first polysilicon region and the fourth polysilicon region are in contact with the fifth active region to form a first pull-up transistor and a second pull-up transistor, respectively. First metal layer and second metal layer; The first metal layer is connected to the drain of the first pull-down transistor, the source of the first pull-up transistor, the drain of the first transmission transistor, and the fourth polysilicon region via contact structures; the second metal layer is connected to the drain of the second pull-down transistor, the source of the second pull-up transistor, the drain of the second transmission transistor, and the first polysilicon region via contact structures.

[0008] As an optional implementation, in the first aspect of the present invention, the first active region, the second active region, the third active region and the fourth active region all extend along a first direction; The fifth active region, the second polysilicon region, and the third polysilicon region all extend along the second direction; The first polysilicon region includes a first polysilicon region A extending along a second direction and a first polysilicon region B extending along a first direction; the fourth polysilicon region includes a fourth polysilicon region A extending along a second direction and a fourth polysilicon region B extending along a first direction. Wherein, the first polysilicon region A and the first active region are in contact to form a first pull-down transistor, the first polysilicon region B and the fifth active region are in contact to form a first pull-up transistor, the fourth polysilicon region A and the fourth active region are in contact to form a second pull-down transistor, and the fourth polysilicon region B and the fifth active region are in contact to form a second pull-up transistor. The first direction and the second direction are different.

[0009] As an optional implementation, in the first aspect of the present invention, a first power supply point is provided on the source of the first pull-down transistor, a second bit line is provided on the source of the second transmission transistor, a first bit line is provided on the source of the first transmission transistor, and a second power supply point is provided on the source of the second pull-down transistor. A third power supply point is provided on the drain shared by the first pull-up transistor and the second pull-up transistor; Word lines are provided on the second polysilicon region and the third polysilicon region; The voltages at the first power supply point and the second power supply point are the same.

[0010] As an optional implementation, in the first aspect of the present invention, the contact structure is a point-shaped contact hole, which is obtained by etching holes in the circuit structure and then filling them with metal.

[0011] As an optional implementation, in a first aspect of the present invention, the first metal layer includes a first metal layer A portion extending along a first direction and a first metal layer B portion extending along a second direction. Wherein, one end point of the first metal layer A and one end point of the first metal layer B are connected, the first metal layer A is connected to the drain of the first pull-down transistor, the source of the first pull-up transistor, and the drain of the first transmission transistor through contact structures respectively; the first metal layer B is connected to the fourth polysilicon region through contact structures.

[0012] As an optional implementation, in a first aspect of the present invention, the first metal layer A portion is connected to the source of the first pull-up transistor via a contact structure, including: The second extended metal portion on the first metal layer A extends into the source region of the first pull-up transistor, and the second extended metal portion is connected to the source of the first pull-up transistor through a contact structure.

[0013] As an optional implementation, in a first aspect of the present invention, the second metal layer includes a second metal layer A portion extending along a first direction and a second metal layer B portion extending along a second direction; In this configuration, one end point of the second metal layer A portion and one end point of the second metal layer B portion are connected. The second metal layer A portion is connected to the drain of the second pull-down transistor, the source of the second pull-up transistor, and the drain of the second transmission transistor through contact structures, respectively. The second metal layer B portion is connected to the first polysilicon region through contact structures.

[0014] As an optional implementation, in a first aspect of the invention, the first direction and the second direction are perpendicular to each other, such that the channel directions of the first pull-down transistor, the second transmission transistor, the first transmission transistor, and the second pull-down transistor are perpendicular to the channel directions of the first pull-up transistor and the second pull-up transistor.

[0015] As an optional implementation, in a first aspect of the present invention, the first active region, the second active region, the third active region, the fourth active region, the first polysilicon region B portion, and the fourth polysilicon region B portion are presented as stripes extending along a first direction; the fifth active region, the second polysilicon region, the third polysilicon region, the first polysilicon region A portion, and the fourth polysilicon region A portion are presented as stripes extending along a second direction.

[0016] As an optional implementation, in the first aspect of the present invention, the strip width of the first active region and the fourth active region is W2, the strip width of the second active region and the third active region is W1, and the strip width of the fifth active region is W3; wherein, W2>W1>W3; The strip width of the second polysilicon region and the third polysilicon region is L1, the strip width of the first polysilicon region A and the fourth polysilicon region A is L2, and the strip width of the first polysilicon region B and the fourth polysilicon region B is L3; wherein, L1>L2=L3.

[0017] As an optional implementation, in the first aspect of the present invention, the first active region, the second active region, the third active region, the fourth active region, the fifth active region, the first polysilicon region, the second polysilicon region, the third polysilicon region, the fourth polysilicon region, the first metal layer, and the second metal layer are generally centrally symmetrically distributed in a plane.

[0018] The second aspect of the present invention discloses a static random access memory, wherein a plurality of SRAM integrated circuit structures, as described in any of the first aspects of the present invention, are formed on the static random access memory according to a preset rule.

[0019] A third aspect of this invention discloses a method for fabricating a static random access memory (SRAM), wherein, for any operating region on the memory used to form an SRAM integrated circuit structure, the method includes: Based on the ion implantation process, P-type wells corresponding to the first active region, the second active region, the third active region, the fourth active region, and the N-type well corresponding to the fifth active region are formed on the operating region. Based on the furnace tube process, a gate oxide layer is formed on the P-type well and the N-type well, and then a polysilicon layer is deposited. The first polysilicon region, the second polysilicon region, the third polysilicon region, and the fourth polysilicon region are formed on the polysilicon layer by an etching process. N-type ion implantation is performed in the regions where the first polysilicon region and the first active region, the second polysilicon region and the second active region, the third polysilicon region and the third active region, and the fourth polysilicon region and the fourth active region to form an NMOS type first pull-down transistor, a second transmission transistor, a first transmission transistor, and a second pull-down transistor; P-type ion implantation is performed in the regions where the first polysilicon region, the second polysilicon region, and the fifth active region are respectively in contact with the fifth active region to form a PMOS type first pull-up transistor and a second pull-up transistor. A first metal layer is connected to the drain of the first pull-down transistor, the source of the first pull-up transistor, the drain of the first transmission transistor, and the fourth polysilicon region via a contact structure; a second metal layer is connected to the drain of the second pull-down transistor, the source of the second pull-up transistor, the drain of the second transmission transistor, and the first polysilicon region via a contact structure.

[0020] As an optional implementation, in a third aspect of the present invention, the method further includes: After all the transistors are formed, nickel silicide interconnect layers are formed on the active region and gate of all the transistors, respectively; An etch stop layer composed of silicon nitride is formed on the nickel silicide interconnect layer, and then an insulating layer is formed on the etch stop layer; CT sites are provided in the source and drain regions of all the transistors, and holes are etched at each CT site based on a dry etching process. Each hole is obtained after etching is stopped when the nickel silicide layer is reached. After filling each hole with metal, all point-like contact holes are obtained. These point-like contact holes are used to form the contact structure corresponding to the metal layer or to connect with the external circuit structure.

[0021] As an optional implementation, in a third aspect of the present invention, the formation of P-type wells corresponding to the first active region, the second active region, the third active region, and the fourth active region, and an N-type well corresponding to the fifth active region on the operating region based on the ion implantation process includes: A deep N-well is formed in the operating region; The injection regions corresponding to the first active region, the second active region, the third active region, the fourth active region, and the fifth active region are determined on the deep N-well using a photomask; Based on the ion implantation process, P-type wells corresponding to the first active region, the second active region, the third active region, the fourth active region, and the N-type well corresponding to the fifth active region are formed on the implanted region.

[0022] As an optional implementation, the static random access memory (SRAM) preparation method disclosed in the third aspect of the present invention is used to prepare any of the static random access memories disclosed in the second aspect of the present invention.

[0023] Compared with the prior art, the unexpected technical effects achieved by the present invention are as follows: This invention proposes a novel SRAM integrated circuit structure through the design of five active regions and four polysilicon regions. In this structure, the first pull-up transistor and the second pull-down transistor of the same type are both formed on the fifth active region, resulting in a simpler overall integrated circuit design. Furthermore, adjacent transistors can share drains or sources, reducing the integrated circuit area. Therefore, the SRAM integrated circuit structure of this invention reduces the complexity of SRAM integrated circuit structures. On the other hand, in this invention, the metal layer connects the active regions and the polysilicon regions through contact structures. An unexpected effect is that these contact structures do not need to traverse uneven areas; they can directly connect the metal layer to the polysilicon regions or the active regions, which reduces the manufacturing difficulty of the SRAM integrated circuit structure. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a circuit diagram of an existing 6T SRAM; Figure 2This is a schematic diagram of an existing 6T SRAM integrated circuit structure; Figure 3 This is a schematic diagram of an SRAM integrated circuit structure disclosed in Embodiment 1; Figure 4 This is a circuit diagram corresponding to an SRAM integrated circuit structure disclosed in Embodiment 1; Figure 5 This is a schematic diagram of a portion of the polysilicon region and metal layer structure in an SRAM integrated circuit structure disclosed in Embodiment 1; Figure 6 This is a schematic diagram of the state after depositing a stress film when the channel direction of the NMOS transistor disclosed in Embodiment 1 is perpendicular to the channel direction of the PMOS transistor. Figure 7 This is a schematic diagram showing the dimensions of the active region and polysilicon region in an SRAM integrated circuit structure disclosed in Embodiment 1; Figure 8 This is a schematic diagram of the formation of P-type and N-type wells in a static random access memory fabrication method disclosed in Embodiment 2; Figure 9 This is a schematic diagram of the state after the formation of the polycrystalline silicon region in a static random access memory fabrication method disclosed in Example 2; Figure 10 This is a planar schematic diagram of the basic structure of an SRAM integrated circuit fabricated by the static random access memory fabrication method disclosed in Embodiment 2; Figure 11 This is a schematic diagram of the state of forming point-like contact holes in a static random access memory fabrication method disclosed in Embodiment 2; Figure 12 This is a cross-sectional view of the integrated circuit structure before contact hole etching in a static random access memory fabrication method disclosed in Embodiment 2; Figure 13 This is a cross-sectional view of the integrated circuit structure after forming dot-shaped contact holes in a static random access memory fabrication method disclosed in Embodiment 2.

[0026] In the diagram: 110 - First active region; 120 - Second active region; 130 - Third active region; 140 - Fourth active region; 150 - Fifth active region; 210 - First polysilicon region; 220 - Second polysilicon region; 230 - Third polysilicon region; 240 - Fourth polysilicon region; 310 - First metal layer; 320 - Second metal layer; 211 - Part A of the first polysilicon region; 212 - Part B of the first polysilicon region; 241 - Part A of the fourth polysilicon region; 242 - Part B of the fourth polysilicon region; 311 - Part A of the first metal layer; 312 - Part B of the first metal layer; 321 - Part A of the second metal layer; 322 - Part B of the second metal layer. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, apparatus, product, or end that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or ends.

[0029] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0030] This invention discloses an SRAM integrated circuit structure, a static random access memory, and a method for fabricating the same, which optimizes the complexity of SRAM integrated circuit structure design and reduces the fabrication difficulty of SRAM integrated circuit structures. These are described in detail below.

[0031] Example 1 SRAM integrated circuit structure is the implementation of SRAM circuits on a chip in the form of integrated circuits. For Static Random-Access Memory (SRAM), its most basic structure is a 4T, 6T, or 8T SRAM circuit, for example... Figure 1 The SRAM circuit in the chip. The SRAM circuit is constructed on the chip using CMOS technology. For a static random access memory, it often includes many SRAM integrated circuit structures that are distributed and connected according to a preset rule. Each SRAM integrated circuit structure is used to implement a 4T, 6T or 8T SRAM circuit.

[0032] Embodiment 1 of the present invention discloses an SRAM integrated circuit structure. Figure 3 This is an exemplary structural diagram of the SRAM integrated circuit. Specifically, the circuit structure first includes: The first active region 110, the second active region 120, the third active region 130, the fourth active region 140, and the fifth active region 150; in this embodiment of the invention, the active region is a silicon region formed on a silicon substrate that, after doping, can form the source and drain of a transistor. For SRAM integrated circuit structures, different active regions are different independent regions, for example... Figure 2 The four active regions are provided. In this embodiment of the invention, five independent active regions are provided to form the source and drain of the transistor.

[0033] The circuit structure also includes a first polysilicon region 210, a second polysilicon region 220, a third polysilicon region 230, and a fourth polysilicon region 240. In this embodiment of the invention, the polysilicon region can be a region formed by photolithography etching of polysilicon material deposited on the gate oxide layer. The polysilicon region spans across the active region, which allows the overlapping portion of the polysilicon and active regions to form the gate of a transistor. For example... Figure 2 Two parallel polysilicon strips, each spanning multiple active regions, form the gates of multiple transistors. In embodiments of the invention, such as... Figure 3 As illustrated, four polysilicon regions are set up on top of the active region to form multiple transistors in the SRAM circuit, with the polysilicon regions forming the gates of the transistors.

[0034] In this embodiment of the invention, a first polysilicon region 210 and a first active region 110 are in contact to form a first pull-down transistor PD1; a second polysilicon region 220 and a second active region 120 are in contact to form a second transmission transistor PG2; a third polysilicon region 230 and a third active region 130 are in contact to form the first transmission transistor PG1; a fourth polysilicon region 240 and a fourth active region 140 are in contact to form the second pull-down transistor PD2; and the first polysilicon region 210 and the fourth polysilicon region 240 are in contact with a fifth active region 150 to form a first pull-up transistor PU1 and a second pull-up transistor PU2.

[0035] Those skilled in the art will understand that "contact" in this embodiment is an abstract description of a static structural state, which includes direct contact and indirect contact, as well as other cooperation methods. For example, from a manufacturing process perspective, "contact" here can actually refer to the formation of a polysilicon region on the active region after the active region is formed, by performing subsequent processes. For example, using a furnace tube process, a certain thickness of polysilicon can be formed in the entire area containing the first active region 110 to the fifth active region 150, and then the gate of the polysilicon region can be defined using a photomask, thus forming the aforementioned first polysilicon region 210, second polysilicon region 220, third polysilicon region 230, and fourth polysilicon region 240. At this time, a gate oxide layer of a certain thickness is formed below the polysilicon region.

[0036] like Figure 3 As illustrated, the first polysilicon region 210 and the first active region 110 are in contact to form the first pull-down transistor PD1; the second polysilicon region 220 and the second active region 120 are in contact to form the second transmission transistor PG2; the third polysilicon region 230 and the third active region 130 are in contact to form the first transmission transistor PG1; the fourth polysilicon region 240 and the fourth active region 140 are in contact to form the second pull-down transistor PD2; the first polysilicon region 210 and the fifth active region 150 are in contact to form the first pull-up transistor PU1; and the fourth polysilicon region 240 and the fifth active region 150 are in contact to form the second pull-up transistor PU2.

[0037] Those skilled in the art will understand that the first transfer transistor PG1, the first pull-down transistor PD1, the second pull-down transistor PD2, and the second transfer transistor PG2 are NMOS transistors; the first pull-up transistor PU1 and the second pull-up transistor PU2 are PMOS transistors. Different types of transistors can be formed by implanting different types of ions into the polysilicon region.

[0038] In this embodiment of the invention, a first pull-up transistor PU1 and a second pull-up transistor PU2 are formed on the fifth active region 150. The two can share a drain, which saves the area of ​​the integrated circuit structure.

[0039] The circuit structure also includes a first metal layer 310 and a second metal layer 320; wherein, the first metal layer 310 is connected to the drain of the first pull-down transistor PD1, the source of the first pull-up transistor PU1, the drain of the first transmission transistor PG1, and the fourth polysilicon region 240 through contact structures; the second metal layer 320 is connected to the drain of the second pull-down transistor PD2, the source of the second pull-up transistor PU2, the drain of the second transmission transistor PG2, and the first polysilicon region 210 through contact structures.

[0040] In this embodiment of the invention, the design of the active region, polysilicon region, metal layer, and contact structure enables... Figure 4 The SRAM circuit in the diagram is implemented on the integrated circuit structure. Figure 4 The SRAM circuit in the middle is Figure 1 This is another representation of the SRAM circuit after rewiring. In this representation, the active region and polysilicon region are used to form transistors, and the metal layer serves as a bridge connecting different transistors.

[0041] What those skilled in the art will understand is that Figure 3 This is an example of an integrated circuit structure shown in a two-dimensional diagram. In reality, this integrated circuit structure is a three-dimensional structure (which is in...). Figure 12 and Figure 13 (This can be seen in the text), for example, polycrystalline silicon regions are often formed above active regions, and other layers are formed between them. In existing technologies, such as... Figure 2 As shown, the connection between the polysilicon region and the active region is indicated by the shared contact hole, as shown by the black bar in the figure. Because there is a height difference between the polysilicon region and the active region, connecting the active region and the polysilicon region through a shared contact hole would require the contact hole to traverse an uneven area, increasing the manufacturing complexity. However, in this embodiment of the invention, the metal layer connects the active region and the polysilicon region through a contact structure, eliminating the need for this contact structure to traverse uneven areas and allowing direct connection between the metal layer and the polysilicon region or the active region. For example… Figure 3 The black square shown indicates a single point-like contact hole. This contact hole only needs to penetrate downwards from a single point to the preset contact position, without needing to cross areas with height differences.

[0042] As can be seen, in the embodiments of the present invention, in the first aspect, a novel SRAM integrated circuit structure is proposed through the design of five active regions and four polysilicon regions. An unexpected technical effect is that the first pull-up transistor PU1 and the second pull-down transistor PD2, of the same type, are both formed on the fifth active region 150, making the overall integrated circuit structure design simpler. Furthermore, adjacent transistors can share a drain or source to reduce the integrated circuit structure area. For example, the first pull-up transistor PU1 and the second pull-up transistor PU2 share a drain. Therefore, the SRAM integrated circuit structure in the embodiments of the present invention reduces the complexity of the SRAM integrated circuit structure. On the other hand, in the embodiments of the present invention, the metal layer connects the active region and the polysilicon region through a contact structure. An unexpected effect is that the contact structure does not need to cross uneven areas; it can directly connect the metal layer and the polysilicon region or the active region, which reduces the manufacturing difficulty of the SRAM integrated circuit structure.

[0043] In an optional embodiment, the first active region 110, the second active region 120, the third active region 130 and the fourth active region 140 all extend along a first direction; The fifth active region 150, the second polysilicon region 220 and the third polysilicon region 230 all extend along the second direction; like Figure 5 As shown, the first polysilicon region 210 includes a first polysilicon region A portion 211 extending along the second direction and a first polysilicon region B portion 212 extending along the first direction; the fourth polysilicon region 240 includes a fourth polysilicon region A portion 241 extending along the second direction and a fourth polysilicon region B portion 242 extending along the first direction. In this configuration, the first polysilicon region A portion 211 contacts the first active region 110 to form the first pull-down transistor PD1, the first polysilicon region B portion 212 contacts the fifth active region 150 to form the first pull-up transistor PU1, the fourth polysilicon region A portion 241 contacts the fourth active region 140 to form the second pull-down transistor PD2, and the fourth polysilicon region B portion 242 contacts the fifth active region 150 to form the second pull-up transistor PU2. The first direction and the second direction are different.

[0044] In this optional embodiment, "extend" is a state description rather than an action description. Extending in a certain direction means that the basic shape of an object can be described as the result of extending in a certain direction, such as a long strip shape obtained by extending along the X direction, a trapezoid obtained by extending along the Y direction, etc.

[0045] The contact between the active region and the polysilicon region enables the formation of the transistor, while the distribution of the active region and the polysilicon region determines the complexity of the fabrication process. In this optional embodiment, the regions extending along the first direction are: a first active region 110, a second active region 120, a third active region 130, a fourth active region 140, a first polysilicon region B portion 212, and a fourth polysilicon region B portion 242; the regions extending along the second direction are: a fifth active region 150, a second polysilicon region 220, a third polysilicon region 230, a first polysilicon region A portion 211, and a fourth polysilicon region A portion 241. Since each part of the active region and the polysilicon region extends in only two directions, etching or ion implantation operations in the fabrication process are more convenient.

[0046] Further optionally, the first direction and the second direction are perpendicular to each other, such that the channel directions of the first pull-down transistor PD1, the second transmission transistor PG2, the first transmission transistor PG1, and the second pull-down transistor PD2 are perpendicular to the channel directions of the first pull-up transistor PU1 and the second pull-up transistor PU2, as shown below. Figure 3 As in the example, the second direction is... Figure 3In the plan view, the vertical direction from top to bottom, the first direction is... Figure 3 The horizontal direction from left to right in the plan view.

[0047] At this point, the unexpected effect of the aforementioned first and second direction constraints is that the channel directions of the first transfer transistor PG1, the first pull-down transistor PD1, the second pull-down transistor PD2, and the second transfer transistor PG2 (belonging to the NMOS type) are along the first direction, while the channel directions of the first pull-up transistor PU1 and the second pull-up transistor PU2 (belonging to the PMOS type) are along the second direction. That is, in this SRAM integrated circuit structure, the channel direction of the NMOS type transistor is perpendicular to the channel direction of the PMOS type transistor. This will bring about advancements in fabrication technology and improvements in SRAM performance, for the following reasons: In a MOS transistor, the channel direction refers to the direction in which charge carriers (electrons or holes) flow from the source to the drain. Channel length (L): the dimension along the current direction, determined by the width of the polysilicon region; channel width (W): the dimension perpendicular to the current direction, determined by the width of the active region.

[0048] In the fabrication process, NMOS transistors and PMOS transistors require different stress types: For example, NMOS transistors correspond to tensile stress, which stretches the silicon lattice and reduces the effective electron mass; while PMOS transistors correspond to compressive stress, which compresses the silicon lattice and reduces the effective hole mass.

[0049] In this optional embodiment, the channel direction of the NMOS transistor is horizontal and the channel direction of the PMOS transistor is vertical. This design allows NMOS and PMOS to be formed using a single compressive stress film, improving the read and write speed of SRAM.

[0050] like Figure 6 As shown, to improve device speed, it is necessary to push NMOS transistors and PMOS transistors respectively. Here, "push" refers to the process of actively changing the characteristics of the transistor through external means (such as stress), for example, it can refer to depositing a thin film with internal stress (such as compressive stress silicon nitride). This thin film is like a "hand" trying to contract or expand. This "hand" will "push" or "pull" the silicon lattice it covers, that is, the channel region of the transistor.

[0051] NMOS transistors prefer tensile stress, while PMOS transistors prefer compressive stress. Therefore, if an NMOS and PMOS transistor are aligned, depositing a film with tensile stress will push the NMOS transistor but suppress the PMOS transistor. However, in this alternative embodiment, the PMOS and NMOS transistors are designed to be perpendicular to each other. For example, if the horizontal film is under tensile stress, the expansion and stretching in the vertical direction will generate compressive stress, thereby pushing the PMOS transistor and increasing its speed. Figure 6 As shown, a stress film with tensile stress, such as a SIN film, can be placed on this L-shaped structure.

[0052] This tensile stress film is equivalent to pulling outwards at points A and B, causing the AB channel to expand and increasing the speed of the NMOS transistor. Since the volume of the object is constant, when it is pulled horizontally, the object will contract vertically. The contraction stress will generate huge compressive stress on the channel in the CD direction. Thus, the performance of NMOS and PMOS transistors can be improved by using a single stress film, thereby reducing the use of photomasks and lowering costs.

[0053] In another alternative embodiment, such as Figure 3 As in the example, a first power supply point VSS1 is provided on the source of the first pull-down transistor PD1, a second bit line BLB is provided on the source of the second transfer transistor PG2, and a second memory node SNR is provided on the drain of the second transfer transistor PG2 (this second memory node SNR is not a real point, but a virtual point that stores data 0 / 1 by means of high and low potential; in fact, the second memory node SNR is several intersecting lines, for example, it can be the entire second metal layer 320, or it can be...). Figure 3 (As shown in the diagram), a first bit line BL is provided on the source of the first transmission transistor PG1, and a first storage node SNL is provided on the drain of the first transmission transistor PG1 (this first storage node SNL is not a real point, but a virtual point that stores data 0 / 1 by means of high and low potential; in fact, the first storage node SNL is several intersecting lines, for example, it can be the entire first metal layer 310, or it can be...). Figure 3 (As shown in the figure), a second power supply point VSS2 is provided on the source of the second pull-down transistor PD2; A second power supply point VCC is provided on the drain shared by the first pull-up transistor PU1 and the second pull-up transistor PU2; Word lines WL are provided on the second polysilicon region 220 and the third polysilicon region 230; The voltages at the first power supply point VSS1 and the second power supply point VSS2 are the same.

[0054] In this optional embodiment, those skilled in the art will understand that power point, bit line, word line WL refers to the functional area defined on the active region or polysilicon region, which is the area connected to the external power supply circuit, read / write circuit, and control circuit. For example, the connection with other circuits can be achieved by setting corresponding contact holes on these functional areas, and these contact holes can be called power point, bit line, or word line.

[0055] In this optional embodiment, the voltages of the first power point VSS1 and the second power point VSS2 are lower than the voltage of the third power point VCC. The specific voltage settings of these three points can be adjusted according to different application scenarios. For example, the third power point VCC can be grounded. In this optional embodiment, a storage node is an abstract point that can be represented by a contact structure at a corresponding location. Similarly, bit lines, word lines WL, and power points can also be implemented by setting contact structures at corresponding locations. The contact structures at the bit lines, word lines WL, and power points are used to connect to external read / write circuits or power circuits.

[0056] The SRAM application principle corresponding to the SRAM integrated circuit structure in this embodiment of the invention is as follows: (1) SRAM read operation: relying on the voltage signal difference between the two bit lines BL / BLB Assuming the SRAM stores 0 data: SNL=0, SNR=1; Assuming the SRAM stores 1 unit of data: SNL=1, SNR=0; Assuming the SRAM currently stores 0 data, the test conditions are as follows: Given BL=BLB=1 and WL=1, under these conditions, since SNL=0 is at a low potential and SNR=1 is at a high potential, we have: 1. The first pull-up transistor PU1 is turned off, the first pull-down transistor PD1 is turned on, the second pull-down transistor PD2 is turned off, and the second pull-up transistor PU2 is turned on; 2. The potential of the second bit line BLB remains unchanged, but the first pull-down transistor PD1 is turned on, causing current to flow from the first bit line BL to the first power supply point VSS1, resulting in a decrease in the potential of the first bit line BL. 3. Initially, BL=BLB=1. After the potential of the first bit line BL drops, a voltage difference will appear between the first bit line BL and the second bit line BLB. This signal will be output through the external amplifier circuit, and the SRAM signal reading is completed.

[0057] (2) SRAM write operation: relying on reversing the potential of the first storage node SNL and the second storage node SNR. Assume the SRAM stores 0 data, SNL=0, SNR=1; the test conditions are as follows: Given BL=1, BLB=0, WL=1, under these conditions: 1. The first pull-up transistor PU1 is turned off, the first pull-down transistor PD1 is turned on, the second pull-down transistor PD2 is turned off, the second pull-up transistor PU2 is turned on. Since BLB=0 and WL=1, the second transmission transistor PG2 is turned on, and the SNR potential of the second storage node gradually decreases. 2. The decrease in the SNR potential of the second storage node causes the first pull-up transistor PU1 to turn on and the first pull-down transistor PD1 to turn off, thus the SNL potential of the first storage node rises. 3. The rise in the SNL potential of the first storage node causes the second pull-down transistor PD2 to turn on and the second pull-up transistor PU2 to turn off, thus completing the data flip.

[0058] (3) SRAM retention operation: The transfer transistor PG is turned off, and no modification is made to the internal circuitry. The test conditions are as follows: BL=BLB=1, WL=0; under these conditions, When the transmission transistor PG is turned off, the first bit line BL and the second bit line BLB cannot modify the held data.

[0059] (4) SRAM read operation: relying on the voltage signal difference between the bit lines and BL / BLB Assuming the SRAM currently stores 1 unit of data, SNL=1, SNR=0, the test conditions are as follows: BL=BLB=1, WL=1, under these conditions: Since SNR=0 is at a low potential, SNL=1 is at a high potential. 1. The second pull-up transistor PU2 is turned off, the second pull-down transistor PD2 is turned on, the first pull-down transistor PD1 is turned off, and the first pull-up transistor PU1 is turned on; 2. The potential of the first bit line BL remains unchanged, but due to the turn-on of the second pull-down transistor PD2, current flows from the second bit line BLB to the first power supply point VSS1, causing the potential of the second bit line BLB to drop. 3. Initially, BL=BLB=1. After the potential of the second bit line BLB drops, a voltage difference will appear between the first bit line BL and the second bit line BLB. This signal will be output through the external amplifier circuit, and the SRAM signal reading is completed.

[0060] (5) SRAM write operation: relying on reversing the potential of the first storage node SNL and the second storage node SNR. The SRAM stores 1 data point, SNL=1, SNR=0; the test conditions are as follows: Given BL=0, BLB=1, WL=1: 1. The second pull-up transistor PU2 is turned off, the second pull-down transistor PD2 is turned on, the first pull-down transistor PD1 is turned off, the first pull-up transistor PU1 is turned on, and since BL=0 and WL=1, the first transmission transistor PG1 is turned on, and the potential of the first storage node SNL gradually decreases. 2. The decrease in the SNL potential of the first storage node causes the second pull-up transistor PU2 to turn on and the second pull-down transistor PD2 to turn off, thus the SNR potential of the second storage node rises. 3. The rise in the SNR potential of the second storage node causes the first pull-down transistor PD1 to turn on and the first pull-up transistor PU1 to turn off, thus completing the data flip.

[0061] (6) SRAM retention operation: PG is off, and no modification is made to the internal circuitry. The test conditions are as follows: BL=BLB=1; WL=0; Under these conditions, the first transmission transistor PG1 is turned off, the second transmission transistor PG2 is turned off, and the first bit line BL and the second bit line BLB cannot modify the data.

[0062] In another alternative embodiment, the contact structure is a dot-shaped contact hole, which is obtained by etching holes in the circuit structure and then filling them with metal.

[0063] In this optional embodiment, the contact structure can be obtained by etching holes in the active region or polysilicon region and then filling them with metal. The point-like contact hole only needs to be etched at one point on the chip, without having to pass through multiple uneven chip structures, thus making the process easier.

[0064] To make the metal layer easier to manufacture, it can be designed as a part connected to the polysilicon region and a part connected to the active region. The two parts together constitute the whole of the metal layer. The unexpected effect is that it can reduce the difficulty of manufacturing the metal layer and make the circuit structure simpler.

[0065] Therefore, as Figure 5 As shown, in an optional embodiment, the first metal layer 310 includes a first metal layer A portion 311 extending along a first direction and a first metal layer B portion 312 extending along a second direction. The first metal layer A part 311 and the first metal layer B part 312 can both be strip-shaped, so that the entire first metal layer 310 is "L" shaped.

[0066] One end of the first metal layer A portion 311 and one end of the first metal layer B portion 312 are connected. The first metal layer A portion 311 is connected to the drain of the first pull-down transistor PD1, the source of the first pull-up transistor PU1, and the drain of the first transmission transistor PG1 through contact structures. The first metal layer B portion 312 is connected to the fourth polysilicon region 240 through contact structures.

[0067] Optionally, the first metal layer A portion 311 may be connected to the source of the first pull-up transistor PU1 via a contact structure, which may include: A first extended metal portion on the first metal layer A portion 311 extends into the source region of the first pull-up transistor PU1, and the first extended metal portion is connected to the source of the first pull-up transistor PU1 through a contact structure. This first extended metal portion may be... Figure 5 The small strip-shaped structure extending downwards from the first metal layer A portion 311, including the first extended metal portion, forms an "F" shape on the plane. Here, "source range" refers to the range on the chip plane above the source electrode, within which a hole can be drilled to connect to the source electrode.

[0068] In another alternative embodiment, the second metal layer 320 includes a second metal layer A portion 321 extending along a first direction and a second metal layer B portion 322 extending along a second direction; The second metal layer A part 321 and the second metal layer B part 322 can both be strip-shaped, so that the entire first metal layer 310 is "L" shaped.

[0069] One end of the second metal layer A portion 321 is connected to one end of the second metal layer B portion 322. The second metal layer A portion 321 is connected to the drain of the second pull-down transistor PD2, the source of the second pull-up transistor PU2, and the drain of the second transmission transistor PG2 through contact structures. The second metal layer B portion 322 is connected to the first polysilicon region 210 through contact structures.

[0070] Optionally, the second metal layer A portion 321 may be connected to the source of the second pull-up transistor PU2 via a contact structure, and may include: The second extended metal portion on the second metal layer A portion 321 extends into the source region of the second pull-up transistor PU2, and the second extended metal portion is connected to the source of the second pull-up transistor PU2 through a contact structure. This second extended metal portion may be... Figure 5 The small strip structure extending upward from the second metal layer A part 321, including the second extended metal part, forms an "F" shape on the plane.

[0071] In another alternative embodiment, the first active region 110, the second active region 120, the third active region 130, the fourth active region 140, the first polysilicon region B portion 212, and the fourth polysilicon region B portion 242 are presented as stripes extending along a first direction; the fifth active region 150, the second polysilicon region 220, the third polysilicon region 230, the first polysilicon region A portion 211, and the fourth polysilicon region A portion 241 are presented as stripes extending along a second direction.

[0072] Since different transistors have different functions, the length and width of their channels need to satisfy a specific relationship. In this alternative embodiment, because the transistor is formed by the "contact" between the active region and the polysilicon region, designing the active region and the polysilicon region as strips extending in a specific direction has the unexpected effect of facilitating the control of the transistor channel length and width. Furthermore, the strip design is also more conducive to etching and ion implantation operations, thereby further reducing the fabrication difficulty of this integrated circuit structure.

[0073] In this optional embodiment, such as Figure 7 As shown, the strip width of the first active region 110 and the fourth active region 140 is W2, the strip width of the second active region 120 and the third active region 130 is W1, and the strip width of the fifth active region 150 is W3; wherein, W2>W1>W3; The strip width of the second polysilicon region 220 and the third polysilicon region 230 is L1, the strip width of the first polysilicon region A part 211 and the fourth polysilicon region A part 241 is L2, and the strip width of the first polysilicon region B part 212 and the fourth polysilicon region B part 242 is L3; wherein, L1>L2=L3.

[0074] In this optional embodiment, such as Figure 7 As shown, L1 is the length of the transmission transistor channel, L2 is the length of the pull-down transistor channel, L3 (equal to L2) is the length of the pull-up transistor channel, W1 is the width of the transmission transistor channel, W2 is the width of the pull-down transistor channel, and W3 is the width of the pull-up transistor channel.

[0075] In this optional embodiment, the device's idsat is proportional to the device's W / L ratio. Assuming device X = PU / PD, Y = PD / PG, Z = PG / PU, W3 / L3 = 9 / 20W2 / L2; W2 / L2 = 56 / 50W1 / L1; W1 / L1 = 2W3 / L3, the allowable fluctuation range between these ratios is 10% to 15%. Here, idsat refers to the saturation drain current of the field-effect transistor in the saturation region.

[0076] Taking a 28nm process as an example, in this optional embodiment: (W3 / L3)=(9 / 20)×(W2 / L2)→that is, PU=0.45×PD (W2 / L2) = (56 / 50) × (W1 / L1) → that is, PD = 1.12 × PG (W1 / L1)=2×(W3 / L3)→that is, PG=2×PU From this, the theoretical target values ​​(TGT) of X, Y, and Z can be derived: X = PU / PD = 0.45 Y = PD / PG = 1.12 Z=PG / PU=2.00 An exemplary device design is shown in the table below, where TGT is the theoretical target value of X, Y, and Z, and A, B, C, and D are other possible ratios.

[0077]

[0078] In actual chip manufacturing, due to process deviations (such as small fluctuations in photolithography, etching, and ion implantation), the dimensions (W and L) of each transistor will vary randomly around its design target (TGT), with a fluctuation range of 10% to 15%.

[0079] For the channel width, in an optional embodiment, W2:W1:W3 = 1.00:0.90:0.45.

[0080] For the channel length, the gate lengths of the PD and PU are usually equal to ensure latch symmetry and simplify the process. By increasing the channel length of the PG, the driving strength of the PG can be effectively reduced. In an optional embodiment, L1:L2 = 1.1~1.3.

[0081] In yet another alternative embodiment, such as Figure 3 As shown, the first active region 110, the second active region 120, the third active region 130, the fourth active region 140, the fifth active region 150, the first polysilicon region 210, the second polysilicon region 220, the third polysilicon region 230, the fourth polysilicon region 240, the first metal layer 310, and the second metal layer 320 are arranged in a centrally symmetrical manner on the plane. Optionally, the center of symmetry of this central symmetry is the second power supply point VCC. This centrally symmetrical distribution can maximize the reduction of signal interference and improve the thermal gradient effect.

[0082] Specifically, the centrally symmetrical design in this optional embodiment can produce the following unexpected beneficial effects: 1. Optimization of process sensitivity The centrally symmetrical transistor layout reduces the threshold voltage mismatch (Vthmismatch) of NMOS and PMOS transistors, reduces the average channel width / length (W / L) process error of cross-coupled inverters by about 18-22%, and the symmetrical structure reduces threshold voltage fluctuation by increasing the effective area (W·L).

[0083] 2. Signal integrity enhancement (1) The symmetry error of the parasitic capacitance of the bit line pair BL / BLB is <5%, while that of the traditional structure can reach 15%; (2) The latency difference of the word line WL drive path is reduced to less than 3ps; (3) The difference in on-resistance of the transmission gate at the read / write port decreased by about 30%.

[0084] 3. Improved anti-interference capability (1) The power supply noise rejection ratio (PSRR) is improved by 6-8 dB; (2) The unit static noise margin (SNM) increases by approximately 50mV; (3) Symmetric structures extend the stable region by optimizing the β ratio (βn / βp).

[0085] 4. Improved thermal gradient effect (1) The difference in thermal coupling coefficient between adjacent units is <0.03°C / μm; (2) The junction temperature fluctuation range was reduced from ±5°C to ±2°C; (3) The matching degree of leakage current with temperature change is improved by 40%.

[0086] 5. Design rule convergence The probability of DRC violations decreased by approximately 65%; LVS verification pass rate increased to over 98%; The sensitivity to the process corner is reduced, and the TT-FF-SS deviation is reduced by 22%.

[0087] Based on the same inventive concept, embodiments of the present invention also disclose a static random access memory, wherein at least a plurality of SRAM integrated circuit structures of any one of the above-mentioned types are formed on the static random access memory according to a preset rule.

[0088] An SRAM integrated circuit structure is an implementation of SRAM circuits on a chip in the form of integrated circuits. In this embodiment of the invention, the static random access memory can be a packaged semiconductor chip on which multiple SRAM integrated circuit structures as described above in this embodiment of the invention are formed using CMOS technology. Those skilled in the art will understand that the semiconductor chip can also be equipped with read, write, and power supply circuits, and the multiple SRAM integrated circuit structures on the semiconductor chip can be distributed according to various known distribution rules. Each SRAM integrated circuit structure is used to implement a 6T SRAM circuit, ultimately enabling the semiconductor chip to achieve the function of a static random access memory.

[0089] Example 2 Embodiment 2 of this invention discloses a method for fabricating a static random access memory (SRAM). Since multiple SRAM integrated circuit structures are formed on the SRAM, the fabrication process also uses a single integrated circuit structure as the operating unit. It should be noted that this does not mean the fabrication process is limited to creating multiple integrated circuit structures. In fact, the fabrication processes of different integrated circuit structures can be performed simultaneously; however, the fabrication process for each operating unit is essentially the same. Furthermore, different operating regions are not completely independent but can have overlapping parts or other connections.

[0090] Therefore, for any operating region on the memory used to form an SRAM integrated circuit structure, the fabrication method may include: S110, Based on the ion implantation process, P-type wells corresponding to the first active region 110, the second active region 120, the third active region 130, the fourth active region 140, and the N-type well corresponding to the fifth active region 150 are formed on the operating region.

[0091] In this embodiment of the invention, the operating region is a region on the chip used to form an SRAM structure, which may be a region divided on a pre-provided substrate.

[0092] In an optional embodiment, step S110 may include: A deep N-well is formed in the operating region; Using a photomask, the injection regions corresponding to the first active region 110, the second active region 120, the third active region 130, the fourth active region 140, and the fifth active region 150 are determined on the deep N-well; wherein, the injection regions of the first active region 110, the second active region 120, the third active region 130, and the fourth active region 140 correspond to Figure 8 The blank rectangular area within the green box is divided into four parts. The fifth active region 150 corresponds to the injection area. Figure 8The long, narrow area within the yellow box shows the rectangular blank space.

[0093] Based on the ion implantation process, P-type wells (PW) corresponding to the first active region 110, the second active region 120, the third active region 130, and the fourth active region 140, and N-type wells (NW) corresponding to the fifth active region 150 are formed on the implantation region.

[0094] S120: Based on the furnace tube process, a gate oxide layer is formed on the P-type well and N-type well, and then a polysilicon layer is deposited.

[0095] In this embodiment of the invention, the gate oxide layer forms an insulator between the gate and the silicon substrate to prevent direct current from passing through. Furthermore, as the core of the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), the gate oxide layer, together with the gate and channel, constitutes a capacitor. The voltage on the gate controls the switching on and off of the channel in the underlying silicon substrate through the field effect of this capacitor. The polysilicon layer provides conductive material for the transistor's gate; by applying a voltage to the polysilicon gate, the switching on and off of the underlying transistor is controlled.

[0096] S130, Based on the etching process, a first polysilicon region 210, a second polysilicon region 220, a third polysilicon region 230, and a fourth polysilicon region 240 are formed on the polysilicon layer.

[0097] In this embodiment of the invention, the etching process is the process of etching a whole layer of polysilicon into individual transistor gates. The length of the gate directly determines the feature size of the transistor. Specifically, the polysilicon region can be defined by a corresponding photomask. In this embodiment of the invention, four polysilicon regions are designed: a first polysilicon region 210, a second polysilicon region 220, a third polysilicon region 230, and a fourth polysilicon region 240. The first polysilicon region 210 contacts the first active region 110 to form a first pull-down transistor PD1; the second polysilicon region 220 contacts the second active region 120 to form a second transmission transistor PG2; the third polysilicon region 230 contacts the third active region 130 to form the first transmission transistor PG1; the fourth polysilicon region 240 contacts the fourth active region 140 to form the second pull-down transistor PD2; and the first polysilicon region 210 and the fourth polysilicon region 240 respectively contact the fifth active region 150 to form a first pull-up transistor PU1 and a second pull-up transistor PU2. The term "contact" here means that the polycrystalline silicon region is formed on top of the active region, and other material layers can be formed in between.

[0098] S140, N-type ion implantation is performed in the regions where the first polysilicon region 210 and the first active region 110 are in contact, the regions where the second polysilicon region 220 and the second active region 120 are in contact, the regions where the third polysilicon region 230 and the third active region 130 are in contact, and the regions where the fourth polysilicon region 240 and the fourth active region 140 are in contact, thereby forming an NMOS type first pull-down transistor PD1, a second transmission transistor PG2, a first transmission transistor PG1 and a second pull-down transistor PD2; P-type ion implantation is performed in the regions where the first polysilicon region 210 and the second polysilicon region 220 are in contact with the fifth active region 150, respectively, thereby forming a PMOS type first pull-up transistor PU1 and a second pull-up transistor PU2.

[0099] In this embodiment of the invention, for NMOS transistors, N-type ions, such as phosphorus or arsenic, are implanted into the contact region to form a lightly doped N-type region on both sides of the gate. For PMOS transistors, P-type ions, such as boron, are implanted into the contact region to form a lightly doped P-type region on both sides of the gate. The resulting polysilicon region is as follows: Figure 9 As shown.

[0100] S150, the first metal layer 310 is connected to the drain of the first pull-down transistor PD1, the source of the first pull-up transistor PU1, the drain of the first transmission transistor PG1, and the fourth polysilicon region 240 through a contact structure; the second metal layer 320 is connected to the drain of the second pull-down transistor PD2, the source of the second pull-up transistor PU2, the drain of the second transmission transistor PG2, and the first polysilicon region 210 through a contact structure.

[0101] After step S150 is completed, an exemplary SRAM circuit structure is obtained as follows: Figure 10 As shown. In the prior art, such as Figure 2 As shown, the connection between the polysilicon region and the active region is indicated by the shared contact hole, as shown by the black bar in the figure. Because there is a height difference between the polysilicon region and the active region, connecting them via a shared contact hole would require the contact hole to traverse an uneven area, increasing the manufacturing complexity. However, in this embodiment of the invention, the metal layer connects the active region and the polysilicon region through a contact structure. The unexpected effect is that this contact structure does not need to traverse uneven areas; it can directly connect the metal layer to the polysilicon region or the active region. For example… Figure 10 The black square shown indicates a single point-like contact hole. This contact hole only needs to penetrate downwards from a single point to the preset contact position, without needing to cross areas with height differences.

[0102] The fabrication method described in this invention produces an SRAM integrated circuit structure on any memory. Through the design of five active regions and four polysilicon regions, a novel SRAM integrated circuit structure is proposed. An unexpected technical effect is that the first pull-up transistor PU1 and the second pull-down transistor PD2 of the same type are both formed on the fifth active region 150, making the overall design of the integrated circuit structure simpler. Furthermore, adjacent transistors can reduce the integrated circuit structure area by sharing a drain or source. For example, the first pull-up transistor PU1 and the second pull-up transistor PU2 share a drain. Therefore, the SRAM integrated circuit structure in this invention reduces the complexity of the SRAM integrated circuit structure.

[0103] On the other hand, in this embodiment of the invention, the metal layer connects the active region and the polysilicon region through a contact structure, so that the contact structure does not need to cross uneven areas and can directly connect the metal layer and the polysilicon region or the active region, which reduces the process difficulty of SRAM integrated circuit structure.

[0104] In an optional embodiment, the preparation method may further include: After all transistors are formed, nickel silicide interconnect layers are formed on the active region and gate of all transistors respectively; An etch stop layer composed of silicon nitride is formed on the nickel silicide interconnect layer, and then an insulating layer is formed on the etch stop layer; CT sites are set in the source and drain regions of all transistors. Holes are etched at each CT site using a dry etching process. Each hole is obtained after etching is stopped when the nickel silicide layer is reached. After filling each hole with metal, all point contact holes are obtained, such as... Figure 11 As shown, dotted contact holes are used to form the contact structure corresponding to the metal layer or to connect with the external circuit structure.

[0105] In an optional embodiment, the process for preparing the point-like contact holes is as follows: After all transistors are formed, an optional transistor structure is as follows: Figure 12 As shown, for the transfer transistor and the pull-down transistor, as Figure 12 As shown on the left, after the transistor is formed, its basic structure can include P-sub SI (P-type silicon substrate), DNW (Deep N-Well), PW (P-Well), and NLDD (N-type Lightly Doped Drain).

[0106] For pull-up transistors, such as Figure 12As shown on the right, after the transistor is formed, its basic structure can include P-subSI (P-type silicon substrate), DNW (Deep N-Well), NW (N-Well), and PLDD (P-type Lightly Doped Drain).

[0107] Subsequently, a nickel silicide interconnect layer formed on the above structure, an etch stop layer composed of silicon nitride formed on the nickel silicide interconnect layer, and an insulating layer formed on the etch stop layer may include: NiSi (Nickel Silicide), SiN (Silicon Nitride), Harp TEOS (High-Density Plasma Deposited Silica), PE TEOS (Plasma Enhanced TEOS), and Recap TEOS (Cap / Redeposited Silica).

[0108] Before etching the contact holes, the following structures can be formed on the basis of the above structure: aC (Amorphous Carbon), SiON (Silicon Oxynitride), OX (Oxide), BARC (Bottom Anti-Reflective Coating), and PR (PhotoResist).

[0109] Subsequently, a multi-step dry etching process will form a shape like... Figure 13 The structure shown involves several considerations for filling each cavity with metal. Firstly, if Ti:W deposition is used, WF6 (tungsten hexafluoride) is employed, which is highly oxidizing and reacts with Ti, forming defects. Therefore, a TiN layer is needed to prevent the diffusion and contact between WF6 and Ti. Secondly, if only TiN is filled, the stress is high, making it prone to peeling. Ti is needed as a mitigating layer to improve adhesion. Therefore, in this alternative embodiment, a wet process is used to clean away any residue left during the etching process, followed by the sequential deposition of Ti100+TiN50A and W.

[0110] In this optional embodiment, the drain of the first pull-down transistor PD1, the source of the first pull-up transistor PU1, the drain of the first transmission transistor PG1, and the dotted contact holes formed on the fourth polysilicon region 240 are used to form the contact structure corresponding to the first metal layer 310; the drain of the second pull-down transistor PD2, the source of the second pull-up transistor PU2, the drain of the second transmission transistor PG2, and the dotted contact holes formed on the first polysilicon region 210 are used to form the contact structure corresponding to the second metal layer 320, and the dotted contact holes formed on the source of the first transmission transistor PG1 are used as the first bit line BL. The point-shaped contact hole formed on the source of the first pull-down transistor PD1 serves as the first power supply point VSS1 and is connected to the external power supply circuit structure. The point-shaped contact hole formed on the source of the second pull-down transistor PD2 serves as the second power supply point VSS2 and is connected to the external power supply circuit structure. The point-shaped contact hole formed on the source of the second transmission transistor PG2 serves as the second bit line BLB and is connected to the external circuit structure. The point-shaped contact hole formed on the drain of the first pull-up transistor PU1 and the second pull-up transistor PU2 serves as the second power supply point VCC and is connected to the external power supply circuit structure.

[0111] The static random access memory (SRAM) fabrication method in any embodiment of the present invention can be used to fabricate the SRAM disclosed in Embodiment 1 of the present invention. The SRAM integrated circuit structure formed on each operating area in the present invention can be any SRAM integrated circuit structure in Embodiment 1.

[0112] Finally, it should be noted that the above embodiments are merely preferred embodiments of the present invention and are only used to illustrate the technical solutions of the present invention, not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An SRAM integrated circuit structure, characterized in that, The circuit structure includes: First active region, second active region, third active region, fourth active region, fifth active region; First polysilicon region, second polysilicon region, third polysilicon region, fourth polysilicon region; Wherein, the first polysilicon region and the first active region are in contact to form a first pull-down transistor; the second polysilicon region and the second active region are in contact to form a second transmission transistor; the third polysilicon region and the third active region are in contact to form a first transmission transistor; the fourth polysilicon region and the fourth active region are in contact to form a second pull-down transistor; the first polysilicon region and the fourth polysilicon region are in contact with the fifth active region to form a first pull-up transistor and a second pull-up transistor, respectively. First metal layer and second metal layer; The first metal layer is connected to the drain of the first pull-down transistor, the source of the first pull-up transistor, the drain of the first transmission transistor, and the fourth polysilicon region via contact structures; the second metal layer is connected to the drain of the second pull-down transistor, the source of the second pull-up transistor, the drain of the second transmission transistor, and the first polysilicon region via contact structures.

2. The SRAM integrated circuit structure according to claim 1, characterized in that, The first active region, the second active region, the third active region, and the fourth active region all extend along the first direction; The fifth active region, the second polysilicon region, and the third polysilicon region all extend along the second direction; The first polysilicon region includes a first polysilicon region A extending along a second direction and a first polysilicon region B extending along a first direction; the fourth polysilicon region includes a fourth polysilicon region A extending along a second direction and a fourth polysilicon region B extending along a first direction. Wherein, the first polysilicon region A and the first active region are in contact to form a first pull-down transistor, the first polysilicon region B and the fifth active region are in contact to form a first pull-up transistor, the fourth polysilicon region A and the fourth active region are in contact to form a second pull-down transistor, and the fourth polysilicon region B and the fifth active region are in contact to form a second pull-up transistor. The first direction and the second direction are different.

3. The SRAM integrated circuit structure according to claim 2, characterized in that, A first power supply point is provided on the source of the first pull-down transistor, and a second bit line is provided on the source of the second transmission transistor. A first bit line is provided on the source of the first transmission transistor, and a second power supply point is provided on the source of the second pull-down transistor. A third power supply point is provided on the drain shared by the first pull-up transistor and the second pull-up transistor; Word lines are provided on the second polysilicon region and the third polysilicon region; The voltages at the first power supply point and the second power supply point are the same.

4. The SRAM integrated circuit structure according to claim 2, characterized in that, The contact structure is a point-shaped contact hole, which is obtained by etching holes in the circuit structure and then filling them with metal.

5. The SRAM integrated circuit structure according to claim 2, characterized in that, The first metal layer includes a first metal layer A portion extending along a first direction and a first metal layer B portion extending along a second direction; Wherein, one end point of the first metal layer A and one end point of the first metal layer B are connected, the first metal layer A is connected to the drain of the first pull-down transistor, the source of the first pull-up transistor, and the drain of the first transmission transistor through contact structures respectively; the first metal layer B is connected to the fourth polysilicon region through contact structures.

6. The SRAM integrated circuit structure according to claim 5, characterized in that, The first metal layer A portion is connected to the source of the first pull-up transistor via a contact structure, including: The second extended metal portion on the first metal layer A extends into the source region of the first pull-up transistor, and the second extended metal portion is connected to the source of the first pull-up transistor through a contact structure.

7. The SRAM integrated circuit structure according to claim 2, characterized in that, The second metal layer includes a second metal layer A portion extending along a first direction and a second metal layer B portion extending along a second direction; In this configuration, one end point of the second metal layer A portion and one end point of the second metal layer B portion are connected. The second metal layer A portion is connected to the drain of the second pull-down transistor, the source of the second pull-up transistor, and the drain of the second transmission transistor through contact structures, respectively. The second metal layer B portion is connected to the first polysilicon region through contact structures.

8. The SRAM integrated circuit structure according to any one of claims 2-7, characterized in that, The first direction and the second direction are perpendicular to each other, so that the channel directions of the first pull-down transistor, the second transmission transistor, the first transmission transistor, and the second pull-down transistor are perpendicular to the channel directions of the first pull-up transistor and the second pull-up transistor.

9. The SRAM integrated circuit structure according to any one of claims 2-7, characterized in that, The first active region, the second active region, the third active region, the fourth active region, the first polysilicon region B, and the fourth polysilicon region B are stripes extending along a first direction; the fifth active region, the second polysilicon region, the third polysilicon region, the first polysilicon region A, and the fourth polysilicon region A are stripes extending along a second direction.

10. The SRAM integrated circuit structure according to claim 9, characterized in that, The strip width of the first active region and the fourth active region is W2, the strip width of the second active region and the third active region is W1, and the strip width of the fifth active region is W3; wherein, W2>W1>W3; The strip width of the second polysilicon region and the third polysilicon region is L1, the strip width of the first polysilicon region A and the fourth polysilicon region A is L2, and the strip width of the first polysilicon region B and the fourth polysilicon region B is L3; wherein, L1>L2=L3.

11. The SRAM integrated circuit structure according to claim 9, characterized in that, The first active region, the second active region, the third active region, the fourth active region, the fifth active region, the first polysilicon region, the second polysilicon region, the third polysilicon region, the fourth polysilicon region, the first metal layer, and the second metal layer are centrally symmetrically distributed on the plane.

12. A static random access memory, characterized in that, The static random access memory has multiple SRAM integrated circuit structures, as described in any one of claims 1-11, formed on it according to a preset rule.

13. A method for fabricating a static random access memory, characterized in that, For any operating region on the memory used to form an SRAM integrated circuit structure, the method includes: Based on the ion implantation process, P-type wells corresponding to the first active region, the second active region, the third active region, the fourth active region, and the N-type well corresponding to the fifth active region are formed on the operating region. Based on the furnace tube process, a gate oxide layer is formed on the P-type well and the N-type well, and then a polysilicon layer is deposited. The first polysilicon region, the second polysilicon region, the third polysilicon region, and the fourth polysilicon region are formed on the polysilicon layer by an etching process. N-type ion implantation is performed in the regions where the first polysilicon region and the first active region, the second polysilicon region and the second active region, the third polysilicon region and the third active region, and the fourth polysilicon region and the fourth active region to form an NMOS type first pull-down transistor, a second transmission transistor, a first transmission transistor, and a second pull-down transistor; P-type ion implantation is performed in the regions where the first polysilicon region, the second polysilicon region, and the fifth active region are respectively in contact with the fifth active region to form a PMOS type first pull-up transistor and a second pull-up transistor. A first metal layer is connected to the drain of the first pull-down transistor, the source of the first pull-up transistor, the drain of the first transmission transistor, and the fourth polysilicon region via a contact structure; a second metal layer is connected to the drain of the second pull-down transistor, the source of the second pull-up transistor, the drain of the second transmission transistor, and the first polysilicon region via a contact structure.

14. The method for preparing a static random access memory according to claim 13, characterized in that, The method further includes: After all the transistors are formed, nickel silicide interconnect layers are formed on the active region and gate of all the transistors, respectively; An etch stop layer composed of silicon nitride is formed on the nickel silicide interconnect layer, and then an insulating layer is formed on the etch stop layer; CT sites are provided in the source and drain regions of all the transistors, and holes are etched at each CT site based on a dry etching process. Each hole is obtained after etching is stopped when the nickel silicide layer is reached. After filling each hole with metal, all point-like contact holes are obtained. These point-like contact holes are used to form the contact structure corresponding to the metal layer or to connect with the external circuit structure.

15. The method for preparing a static random access memory according to claim 13, characterized in that, The process of forming P-type wells corresponding to the first, second, third, and fourth active regions and the N-type well corresponding to the fifth active region on the operating region based on ion implantation includes: A deep N-well is formed in the operating region; The injection regions corresponding to the first active region, the second active region, the third active region, the fourth active region, and the fifth active region are determined on the deep N-well using a photomask; Based on the ion implantation process, P-type wells corresponding to the first active region, the second active region, the third active region, the fourth active region, and the N-type well corresponding to the fifth active region are formed on the implanted region.

Images