A method and system for post mask engineering change for a microcontroller (MCU)

Abstract

The application belongs to the technical field of integrated circuits, and particularly discloses a mask post-engineering change method and system for a microcontroller MCU, which comprises the following steps: first, inserting a Tie Spare Cell into the MCU encryption logic, wherein the Tie Spare Cell is connected to a fixed high level and has an initial output of a first value; then, configuring multiple versions of ROM code to be switched by modifying the connection relationship of Mask Via1; when it is required to change the encryption logic value to a second value and synchronously switch the ROM code version, only the Mask Via1 layer mask needs to be modified once, so that the input connection of the Tie Spare Cell is adjusted to change the encryption value, and the metal layer connection of the ROM code is changed to complete the version switching. The application only needs to modify a single layer mask, thereby reducing the Post-Mask ECO manufacturing cost, improving the competitiveness of the MCU product, and ensuring the encryption and version switching efficiency.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a method and system for post-mask engineering changes for microcontrollers (MCUs). Background Technology

[0002] In microcontroller (MCU) products, the ROM storage unit is a core component. The ROM code needs to be designed in multiple versions to adapt to different application scenarios, and it must be encrypted for data security requirements. Post-mask engineering change is a key means of adjusting functions during MCU product iteration. In traditional solutions, modifying the encrypted logic values ​​and switching ROM code versions require modifying different mask layers separately, resulting in high board manufacturing costs and long iteration cycles.

[0003] Meanwhile, level switching of tie-spare cells in the encryption logic can easily trigger instantaneous power consumption fluctuations. This power consumption characteristic may be captured by side-channel attacks, allowing attackers to deduce the encryption logic's patterns and threaten ROM code security. Existing solutions lack effective protection against this leakage risk and do not consider the power consumption superposition issue between encryption value switching and ROM code version switching, further amplifying security vulnerabilities, affecting product reliability, and failing to meet the security and cost requirements of MCUs in industrial control, IoT, and other scenarios. Summary of the Invention

[0004] To address this issue, the present invention provides a method and system for post-mask engineering changes for microcontrollers (MCUs) to solve the aforementioned technical problems.

[0005] According to one aspect of the present invention, a method for post-mask engineering changes for a microcontroller (MCU) is provided, comprising the following steps:

[0006] Insert at least one Tie Spare Cell into the encryption logic of the MCU. The input pin of the Tie Spare Cell is connected to a fixed high level through the first Tie Cell, so that its output initial logic value is a first value.

[0007] The multiple versions of the MCU's read-only memory ROM code are configured to be switched by modifying the connection relationship of the first mask layer MaskVia1;

[0008] When it is necessary to change the value of the encryption logic from the first value to the second value and simultaneously switch the version of the ROM code, the logic value change and ROM code switch are achieved by performing a mask modification on the Mask Via1 layer.

[0009] The step of performing a mask modification for the Mask Via1 layer includes: modifying the connection of the input pin of the Tie SpareCell, switching it from being connected to the fixed high level to being connected to the fixed low level, thereby changing the output logic value of the Tie Spare Cell from the first value to the second value;

[0010] In addition, the metal layer connection relationship of the ROM code is changed to switch the current version of the ROM code to the target version of the ROM code.

[0011] Preferably, power consumption data is collected when the Tie Spare Cell switches from the first value to the second value, and the power consumption data is compared with a predetermined risk threshold to assess the risk of power leakage. When the assessment result is high risk, a step-by-step modification process of the Tie Spare Cell input pin connection is triggered.

[0012] Preferably, the Mask Via1 of the Tie Spare Cell input pin has multiple independent vias, and the modification of the connection of the Tie Spare Cell input pin specifically includes, in response to an evaluation result of high risk, disconnecting at least two of the multiple independent vias in a predetermined order and timing, so that the input level of the Tie Spare Cell is stabilized to the level value corresponding to the fixed low level after passing through at least one intermediate level.

[0013] Preferably, the stepwise disconnection of at least two of the plurality of independent vias specifically includes controlling the input level of the Tie Spare Cell to sequentially pass through a first intermediate level, a second intermediate level, and a third intermediate level, and finally reach the level value corresponding to the fixed low level, wherein the voltage values ​​of the first intermediate level, the second intermediate level, and the third intermediate level are between the voltage values ​​of the fixed high level and the fixed low level.

[0014] Preferably, the stepwise disconnection of at least two of the plurality of independent vias specifically includes, after disconnecting each via, collecting power consumption feedback data in real time, and dynamically adjusting the timing or dwell time of the next via disconnection operation based on the real-time power consumption feedback data.

[0015] Preferably, the assessment of power leakage risk is achieved through an AI model, which takes the current operating temperature and / or power supply voltage of the MCU and the power consumption data as input, and outputs the risk level of the power leakage risk.

[0016] Preferably, the operation of changing the metal layer connection relationship of the ROM code is staggered from the operation of disconnecting the multiple independent vias in stages by a preset time interval to avoid the superposition of power consumption characteristics.

[0017] Preferably, the step-by-step modification of the Tie Spare Cell input pin connection is performed first, and then the change of the metal layer connection relationship of the ROM code is performed.

[0018] Preferably, if the execution time of the step-by-step switching exceeds a preset maximum value, the ROM code version switching is automatically triggered.

[0019] In another aspect, this application also provides a post-mask engineering change system for a microcontroller (MCU), comprising:

[0020] An initial logic setting module is used to insert at least one Tie Spare Cell into the encryption logic of the MCU. The input pin of the Tie Spare Cell is connected to a fixed high level through the first Tie Cell, so that its output initial logic value is a first value.

[0021] The configuration module is used to configure multiple versions of the MCU's read-only memory ROM code to be switched by modifying the connection relationship of the first mask layer Mask Via1;

[0022] The modification module is used to perform a mask modification on the Mask Via1 layer to change the logic value and switch the ROM code when it is necessary to change the value of the encryption logic from the first value to the second value and switch the version of the ROM code simultaneously.

[0023] The step of performing a mask modification for the Mask Via1 layer includes: modifying the connection of the input pin of the Tie SpareCell, switching it from being connected to the fixed high level to being connected to the fixed low level, thereby changing the output logic value of the Tie Spare Cell from the first value to the second value;

[0024] In addition, the metal layer connection relationship of the ROM code is changed to switch the current version of the ROM code to the target version of the ROM code.

[0025] This invention significantly reduces the cost of Post-Mask ECO fabrication by inserting a Tie Spare Cell with an initial value of 1 into the MCU encryption logic and reusing Mask Via1 layer modification to synchronously change the encrypted value (1→0) and switch the ROM CODE version. It introduces an AI model to assess the risk of power leakage, and combines multi-via step-by-step switching and dynamic dwell time adjustment to avoid instantaneous power consumption changes and side-channel attacks. It also prevents power consumption superposition through timing stagger optimization and has a fault tolerance mechanism to ensure reliability. It takes into account the economic efficiency of MCU product iteration, data security and operational stability, and adapts to the application needs of multiple scenarios. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0027] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0028] Figure 1 This is a flowchart of a post-mask engineering change method for a microcontroller (MCU) provided in an embodiment of the present invention.

[0029] Figure 2 This is a schematic diagram of the structure of the Tie Spare Cell provided in an embodiment of the present invention.

[0030] Figure 3 This is a schematic diagram of the model inference process provided in an embodiment of the present invention.

[0031] Figure 4 This is a schematic diagram of the step-by-step switching execution process provided in an embodiment of the present invention.

[0032] Figure 5 This is a schematic diagram of the timing control flow provided in an embodiment of the present invention.

[0033] Figure 6 This is a schematic diagram of a post-mask engineering change system for a microcontroller (MCU) provided in an embodiment of the present invention. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] like Figure 1 As shown, this embodiment of the invention discloses a post-mask engineering change method 100 for a microcontroller (MCU), comprising the following steps:

[0036] S1, insert at least one Tie Spare Cell into the encryption logic of the MCU. The input pin of the Tie Spare Cell is connected to a fixed high level through the first Tie Cell, so that its output initial logic value is a first value.

[0037] S2, configure multiple versions of the MCU's read-only memory ROM code to switch between them by modifying the connection relationship of the first mask layer MaskVia1;

[0038] S3, when it is necessary to change the value of the encryption logic from the first value to the second value and switch the version of the ROM code simultaneously, the logic value change and ROM code switch are achieved by performing a mask modification on the Mask Via1 layer.

[0039] The step of performing a mask modification for the Mask Via1 layer includes: modifying the connection of the input pin of the Tie SpareCell, switching it from being connected to the fixed high level to being connected to the fixed low level, thereby changing the output logic value of the Tie Spare Cell from the first value to the second value;

[0040] In addition, the metal layer connection relationship of the ROM code is changed to switch the current version of the ROM code to the target version of the ROM code.

[0041] In some embodiments, for step S1, a level-redundant cell (Tie Spare Cell) refers to a redundant logic unit inserted in advance into the digital IC design. It is composed of a combination of a spare cell and a level-fixed cell (Tie Cell). The structure of a Tie Spare Cell typically consists of multiple layers of metal and vias connecting them. For an example, please refer to [link to relevant documentation]. Figure 2The schematic diagram of the Tie Spare Cell in this embodiment of the invention shows that the Tie Spare Cell comprises a first metal layer (M1), a second metal layer (M2), and a via (Via1) connecting them, used to provide an adjustable level signal in the MCU encryption logic. Specifically, Tie1 (left half): Via1 is in the ON state, M1 and M2 are connected through Via1, the input pin of the Tie Spare Cell is connected to a fixed high level (VDD), and the output initial logic value is 1 (corresponding to the initial value of the encryption logic);

[0042] Tie0 (right half): Via1 is in the disconnected state, the connection between M1 and M2 is cut off, the input pin of Tie Spare Cell is switched to a fixed low level (VSS), and the output logic value becomes 0 (corresponding to the target value that needs to be modified in the encryption logic).

[0043] By modifying the mask data of the via mask 1, the on / off state of Via1 can be controlled, thereby changing the encryption logic value from 1 to 0; at the same time, this modification can also synchronously adjust the metal layer connection relationship of the ROM CODE to complete the version switch.

[0044] According to an embodiment of the present invention, in the RTL design stage of the MCU encryption logic, at least one TieSpare Cell needs to be instantiated in advance. This cell is a redundant cell selected from the standard logic cell library, and its core design goal is to provide dynamically adjustable initial logic values ​​for the encryption logic.

[0045] Specifically, the input pin of the Tie Spare Cell is directly connected to the MCU's power supply VDD (fixed high level) through the Tie1 unit (level fixed module). Through this hardware connection, the initial logic value of the Tie Spare Cell's output is stably set to a first value. For example, this first value is logic 1 corresponding to the high level. This logic 1 serves as the initial valid state of the encryption logic, ensuring that the encryption function can start normally according to the preset logic after the MCU is powered on, and that the encryption logic will not be falsely triggered due to level fluctuations in the initial state.

[0046] In some embodiments, the selection of the Tie Spare Cell needs to be compatible with the MCU's process node (such as 28nm, 40nm, etc.) to ensure that its electrical characteristics are consistent with other logic units, avoiding initial level instability due to process deviations. Simultaneously, during the placement and routing phase, the Tie Spare Cell needs to be located close to the core computing unit of the encryption logic to shorten the signal transmission path, reduce delay and interference, and ensure the real-time performance of the encryption logic.

[0047] In some embodiments, for step S2, according to the present invention, the storage logic corresponding to multiple versions of the ROM code (such as firmware versions adapted to different application scenarios such as industrial control, consumer electronics, and the Internet of Things) needs to be mapped to different connection relationships between the first metal layer (Metal1) and the second metal layer (Metal2) of the MCU chip. Specifically, the storage of ROM code is essentially to realize the storage of binary data (0 / 1) through the combination of the on and off states of the metal layers, and different versions of ROM code correspond to a unique metal layer connection combination scheme.

[0048] Mask Via1 serves as a via mask connecting Metal1 and Metal2. The on / off state of its vias directly determines the electrical connection between the two metal layers. Therefore, the metal layer connection schemes corresponding to each ROM code version need to be converted into the via distribution pattern of Mask Via1. For example, ROM code version A corresponds to a distribution pattern of "via 1 on, via 2 off, via 3 on", while ROM code version B corresponds to a distribution pattern of "via 1 off, via 2 on, via 3 off". By modifying the via distribution pattern of Mask Via1, the connection relationship between Metal1 and Metal2 can be changed, thereby achieving ROM code version switching.

[0049] In some embodiments, the mapping relationship between the ROM code version and the Mask Via1 via pattern is stored in the non-volatile configuration area of ​​the MCU. This area can only be updated by mask modification during the Post-Mask ECO stage, ensuring the stability and security of the version switching logic and preventing unauthorized tampering.

[0050] In some embodiments, for step S3, according to the present invention, when the MCU needs to respond to changes in security requirements (such as encryption logic upgrades) or application scenario switching (such as changing the ROM code version), it needs to modify the encryption logic value from the first value (1) to the second value (0) and simultaneously switch the ROM code version. Only one mask data update for the Mask Via1 layer needs to be performed to achieve both functions at the same time. Its core lies in the dual-function reuse design of Mask Via1.

[0051] Specifically, the modification process for the encryption logic is as follows: In the initial state, the via corresponding to the input pin of the Tie Spare Cell in Mask Via1 is in the "conductive" state, Metal1 and Metal2 remain electrically connected, and the Tie Spare Cell continuously receives power from VDD through this conductive path, maintaining a high input level (logic 1). When it is necessary to modify the encryption value, the mask data of Mask Via1 is updated through the Post-Mask ECO process, changing the pattern of the corresponding via from the "conductive state" to the "discontinuous state". After the via is disconnected, the power supply path between the Tie Spare Cell and VDD is cut off, the input pin switches to a fixed low level (such as ground VSS), and its output logic value synchronously changes from 1 to 0, completing the change of the encryption value.

[0052] The modification process for ROM code version switching is as follows: When updating the Mask Via1 mask data, in addition to adjusting the via state corresponding to the TieSpare Cell, the via distribution pattern corresponding to the ROM code storage area will also be adjusted synchronously. For example, if the current ROM code is version A, corresponding to "via 4 is on, via 5 is on", and the target version B corresponds to "via 4 is off, via 5 is off", then by updating the mask data, the state of via 4 and 5 will be changed from on to off, and the connection relationship between Metal1 and Metal2 will change accordingly. The ROM code reading logic will be switched to the metal layer connection combination corresponding to the target version B, thus achieving version synchronization switching.

[0053] In some embodiments, the mask data update of Mask Via1 follows the foundry's Design Rationale (DRC) to ensure that the modified via size, spacing, overlap, and other parameters meet the requirements, avoiding a decrease in chip yield due to process violations. Simultaneously, the modification logic for the dual functions needs to be verified through timing simulation to ensure that the changes in encrypted values ​​and the switching of ROM code versions are completed synchronously, without any functional conflicts caused by delays.

[0054] Preferably, before modifying the connection of the input pin of the Tie Spare Cell, the method further includes: acquiring power consumption data of the Tie Spare Cell when switching from the first value to the second value, comparing the power consumption data with a predetermined risk threshold to assess the power leakage risk, and triggering a step-by-step modification process for the connection of the Tie Spare Cell input pin when the assessment result is high risk. The assessment of power leakage risk is implemented through an AI model, which takes the current operating temperature and / or power supply voltage of the MCU and the power consumption data as input, and outputs the risk level of the power leakage risk.

[0055] Specifically, according to embodiments of the present invention, the acquisition of power consumption data involves two core parameters: power supply voltage fluctuation data and ambient temperature data, which together constitute the basic input for power leakage risk assessment.

[0056] For acquiring power supply voltage fluctuation data, for example, the 12-bit ADC module (analog-to-digital converter) built into the MCU is selected. This module has the characteristics of high sampling rate, low power consumption, and high accuracy, and is suitable for the operating requirements of low-computing-power MCUs. The sampling channel of the ADC is connected to the chip's core power rail (VDD_CORE) through internal wiring. This power rail supplies power to core modules such as encryption logic and ROM storage units, and its voltage fluctuations directly reflect the chip's real-time power consumption changes.

[0057] According to a preferred design of the present invention, the sampling rate of the ADC is set to 1MHz, and the sampling accuracy is controlled within ±1mV. This parameter setting can capture the instantaneous power consumption changes (usually lasting tens of ns) during encrypted value switching, without overloading the MCU computing power due to excessively high sampling rate. During the sampling process, the ADC module collects the voltage value of VDD_CORE at a preset period (e.g., once every 10ns), converts the analog voltage signal into a digital signal, and stores it in the temporary cache area of ​​the on-chip RAM (the address range is exemplarily set to 0x20000000~0x20000FFF). The cache area uses cyclic overwrite storage, retaining only the most recent 1000 sampling points to avoid occupying too much storage resources.

[0058] For ambient temperature data acquisition, temperature detection is achieved using a diode in the MCU's internal bandgap reference circuit. The diode's forward voltage drop exhibits a significant temperature dependence, with a temperature coefficient of approximately -2mV / ℃. The current ambient temperature can be indirectly calculated by measuring the forward voltage drop. In the circuit design, the MCU's analog front-end module provides a constant current (exemplarily set to 10μA) to the diode, ensuring that the forward voltage drop measurement is unaffected by current fluctuations. The temperature sampling period is set to 100μs. After the sampling result is converted into a digital temperature value (in ℃), it is timestamped with the corresponding voltage sampling data to form a "temperature-voltage" data pair, providing complete operating condition information for subsequent power consumption calculations.

[0059] During the data preprocessing stage, real-time power consumption data is calculated based on the equivalent load resistance of the MCU chip. Specifically, the chip's equivalent load resistance R is a preset fixed value (calibrated through chip factory testing and stored in the parameter configuration area of ​​the ROM). According to the circuit power consumption formula P=V² / R (where V is the voltage fluctuation value collected by the ADC), power consumption is calculated for each voltage sampling point to obtain the real-time power consumption value. The continuous power consumption values ​​are arranged in chronological order to form a power consumption curve, which visually reflects the power consumption trend during the transition of the Tie Spare Cell from logic 1 to logic 0.

[0060] According to an embodiment of the present invention, risk assessment is achieved through a lightweight AI model. The core design goal of this model is to quickly and accurately determine the power leakage risk level in the low computing power and limited storage environment of the MCU. Its deployment and inference process are adapted to the hardware resource constraints of the MCU.

[0061] First, optionally, TensorFlow Lite for Microcontrollers (TFLM) is selected as the core AI framework. This framework is designed specifically for resource-constrained devices such as microcontrollers, supports lightweight model compression and integer quantization inference, and can run efficiently in hardware environments with KB-level storage and MHz-level clock speeds. During model compression, INT8 integer quantization technology is used to convert the model's weights, biases, and other parameters from 32-bit floating-point numbers to 8-bit integers. Redundant network layers and parameters are also removed, compressing the model size to the KB level (exemplarily, the final model size is 8KB), fully meeting the requirements for deployment in the ROM code reserved area. The address range of the ROM code reserved area is set to 0x0800F000~0x0800FFFF for example. This area does not occupy user firmware space and is only used to store the AI ​​model and related inference logic, ensuring that model deployment does not affect the original functionality of the MCU.

[0062] During the model training phase, a training dataset covering all operating scenarios of the MCU is constructed to ensure the model's generalization ability. Specifically, the training data collection scenarios include: a temperature range covering the MCU's rated operating temperature (-40℃~125℃), with a gradient set every 5℃, for a total of 34 temperature gradients; a power supply voltage range covering the fluctuation range of the rated voltage (e.g., 3.3V±10%), i.e., 3.0V, 3.1V, 3.2V, 3.3V, 3.4V, 3.5V, and 3.6V, for a total of 7 voltage gradients; and in each "temperature-voltage" combination scenario, 1000 Tie Spare Cell switching actions from 1 to 0 are triggered, collecting 1000 power consumption curves, each curve containing 100 sampling points (corresponding to a 1μs switching process).

[0063] The collected raw data is labeled. Specifically, risk judgment thresholds are set: samples with "peak power consumption exceeding twice the mean of all samples in the scenario" or "absolute value of power consumption curve slope exceeding 0.5A / μs" are labeled as "high leakage risk" samples; the remaining samples are labeled as "low leakage risk" samples.

[0064] The final training dataset contains 34×7×1000=238000 samples, of which high-risk samples account for about 30% (71400 samples) and low-risk samples account for about 70% (166600 samples). The dataset is divided into a training set (166600 samples) and a validation set (71400 samples) in a 7:3 ratio for model training and performance validation.

[0065] The model's network structure employs a lightweight convolutional neural network (CNN), with the following specific design: The input layer consists of a 1×102 feature vector (1 temperature value + 100 power consumption values ​​+ 1 voltage value); there are 3 convolutional layers: the first layer has a 3×3 kernel size, 8 neurons, a stride of 1, and no pooling (to reduce computation), using ReLU6 activation function (to accommodate integer operations and avoid floating-point overflow); the second layer has a 3×3 kernel size, 16 neurons, a stride of 1, and ReLU6 activation function; the third layer has a 3×3 kernel size, 8 neurons, a stride of 1, and ReLU6 activation function; there are 2 fully connected layers: the first layer has 32 neurons, the second layer has 16 neurons, and the output layer has 2 neurons, corresponding to the "high risk" and "low risk" categories, respectively.

[0066] During inference on the MCU side, the model is triggered when the MCU receives the instruction to "modify encrypted values ​​+ switch ROM code versions," at which point a timer (such as Timer0) synchronously triggers temperature sampling, voltage sampling, and model inference. Please refer to [link to relevant documentation]. Figure 3 The specific reasoning steps are as follows:

[0067] S301, Data Preprocessing: Normalize the collected temperature values ​​(e.g., 25℃) to the range [-1, 1], using the formula: Normalized Temperature = (Actual Temperature - 40) / 165 × 2 - 1 (where 40 is the lowest temperature and 165 is the temperature range difference); Normalize the voltage values ​​(e.g., 3.3V) to the range [-1, 1], using the formula: Normalized Voltage = (Actual Voltage - 3.3) / 0.3 × 2 (where 0.3 is the voltage fluctuation range difference); Standardize the sequence of 100 power consumption values ​​into INT8 format (range -128~127), using the formula: Standardized Power Consumption = (Actual Power Consumption - Average Power Consumption) / Power Consumption Standard Deviation × 64 (where 64 is a scaling factor to ensure the values ​​are within the INT8 range); Concatenate the normalized temperature and voltage values ​​with the standardized power consumption sequence to form a 1 × 10² input feature vector.

[0068] S302, Model Inference: The TFLM framework calls the model preloaded into the on-chip RAM and sequentially performs convolution, activation, and fully connected operations. The entire inference process does not involve floating-point operations; all operations are performed using integers. The inference latency is controlled within 50μs (at an MCU clock speed of 80MHz), ensuring that the real-time performance of the encryption logic and ROM code switching is not affected. After inference, the probability values ​​of the two neurons are output (e.g., high-risk probability 0.92, low-risk probability 0.08). The category with the larger probability value is selected as the final risk level output.

[0069] S303, Result Output: Stores the risk level result (high / low) to a specified address in the on-chip RAM (e.g., 0x20001000), and outputs the corresponding control signal to provide a basis for subsequent switching strategy selection.

[0070] According to a preferred embodiment of the present invention, the Mask Via1 controlling the Tie Spare Cell input pin is designed as multiple independent and parallel vias. The core purpose of this design is to achieve graded adjustment of the input level through the step-by-step switching of the vias, thereby enabling a smooth transition in the power consumption curve and avoiding the leakage risk caused by sudden power consumption changes. Optionally, the number of vias is set to three, named Via1-A, Via1-B, and Via1-C respectively. This number can achieve multiple intermediate level outputs without causing excessive mask design complexity due to too many vias.

[0071] Specifically, the hardware design parameters for the three vias are as follows: Via1-A has a Metal2 wiring length of 10μm, a wiring width of 0.5μm (meeting the minimum wiring width requirement of the 40nm process), and an equivalent resistance of 1kΩ; Via1-B has a Metal2 wiring length of 20μm, a wiring width of 0.5μm, and an equivalent resistance of 2kΩ; Via1-C has a Metal2 wiring length of 30μm, a wiring width of 0.5μm, and an equivalent resistance of 3kΩ. The difference in wiring length is achieved through the physical layout of the metal layers. The Metal1 terminals of all three vias are connected to the input pins of the Tie Spare Cell, and the Metal2 terminals are all connected to VDD. Initially, all three vias are in the on state, and the Tie Spare Cell obtains a high level VDD through the three parallel vias, with the input level being VDD (logic 1).

[0072] During the mask design phase, the patterns of the three vias are drawn independently, with each via corresponding to a unique mask data identifier. This ensures that the on / off state of each via can be modified individually during the Post-Mask ECO phase without affecting other vias. Simultaneously, the layout of the three vias meets the minimum spacing requirement (exemplarily, spacing ≥ 0.8 μm) to avoid mutual interference between vias due to parasitic capacitance and resistance, ensuring that the on / off state of each via is independently controllable.

[0073] According to an embodiment of the present invention, when the AI ​​model outputs a high-risk assessment result, a step-by-step modification process is automatically initiated, and three independent vias are disconnected in a preset order, so that the input level of the Tie Spare Cell gradually transitions to a fixed low level through three intermediate levels. The core of this process is to achieve smooth adjustment of the level through the voltage divider principle, thereby controlling the slope of the power consumption curve.

[0074] Please see Figure 4 The specific step-by-step switching execution process is as follows:

[0075] S401, initial state setting: Via1-A, Via1-B, and Via1-C are all in the on state. The resistors corresponding to the three vias (1kΩ, 2kΩ, and 3kΩ) are connected in parallel. The total equivalent resistance R_total = 1 / (1 / 1 + 1 / 2 + 1 / 3)kΩ ≈ 0.55kΩ. The input level of the Tie Spare Cell is VDD (logic 1). At this time, the encryption logic is in the initial secure state, and the ROM code retains the current version.

[0076] S402, First Intermediate Level Transition (0.7VDD): In response to the step-by-step switching instruction of the AI ​​model, the MCU's GPIO control module outputs the first disconnect signal, which modifies the mask state of Via1-C in Mask Via1 through the driver circuit, changing it from on to off. After Via1-C is disconnected, the remaining conducting vias are Via1-A and Via1-B, and the corresponding resistors (1kΩ and 2kΩ) are connected in parallel, with a total equivalent resistance R1 = 1 / (1 / 1 + 1 / 2)kΩ ≈ 0.67kΩ.

[0077] Since the input pin of the Tie Spare Cell is connected between VDD and VSS via a voltage divider resistor (for example, a fixed resistor of 1kΩ is connected in series at the VSS terminal), the input level V1 = VDD × (R1) / (R1 + 1kΩ) = VDD × 0.67 / (0.67 + 1) ≈ 0.7VDD, achieving a stable output of the first intermediate level. The preset dwell time for this step is 100ns. During the dwell time, the ADC module continuously acquires power consumption data at a sampling rate of 1MHz to monitor the smoothness of the power consumption curve in real time.

[0078] S403, Second Intermediate Level Transition (0.5VDD): If the power consumption fluctuation in the first step does not exceed the preset threshold (e.g., slope ≤ 0.1A / μs), the GPIO control module outputs a second disconnect signal, modifying the mask state of Via1-B in Mask Via1, changing it from conductive to disconnected. After Via1-B is disconnected, the only remaining conductive via is Via1-A, with a corresponding resistance of 1kΩ, and a total equivalent resistance R2 = 1kΩ. At this time, the input level V2 = VDD × (R2) / (R2 + 1kΩ) = VDD × 1 / (1 + 1) = 0.5VDD, achieving a stable output of the second intermediate level. The preset dwell time for this step is 80ns, and the power consumption fluctuation is monitored in real time by the ADC module.

[0079] S404, Third Intermediate Level Transition (0.3VDD): If the power consumption fluctuation in the second step meets the requirements, the GPIO control module outputs a third disconnect signal, modifying the mask state of Via1-A in Mask Via1, changing it from on to off. After Via1-A is disconnected, all control vias are in the off state, and the input pin of the Tie Spare Cell is grounded through the fixed resistor at the VSS terminal. The input level V3 = VDD × (0) / (0 + 1kΩ) = 0.3VDD (considering circuit parasitic parameters, the actual level is approximately 0.3VDD), achieving a stable output of the third intermediate level. The preset dwell time for this step is 120ns, continuously monitoring the power consumption curve.

[0080] S405, Final State Transition (0V): If the power consumption fluctuation in the third step is normal, the input pin of the Tie Spare Cell will remain at the third intermediate level for 120ns before automatically stabilizing to a fixed low level (0V), with the corresponding output logic value being 0, thus completing the change of the encrypted value. The total time for the entire step-by-step switching process is approximately 300ns, which is much less than the MCU's clock cycle (e.g., at an 80MHz main frequency, the clock cycle is 12.5ns, and 300ns is only 24 clock cycles), ensuring that it does not affect other real-time tasks of the MCU.

[0081] In some embodiments, the order of step-by-step switching can be dynamically adjusted according to actual operating conditions. For example, when the AI ​​model predicts that the leakage risk is high when a certain via is disconnected, the order of via disconnection can be adjusted to prioritize disconnecting vias with lower leakage risk, thereby further optimizing the smoothness of the power consumption curve.

[0082] According to an embodiment of the present invention, dynamic adjustment of dwell time is the key to ensuring a smooth power consumption curve during step-by-step switching. Its core logic is based on real-time power consumption feedback data, and adjusts the dwell time of each step through a closed-loop control mechanism to avoid sudden power consumption changes caused by changes in operating conditions (such as changes in resistance due to temperature rise).

[0083] Specifically, after each via disconnection operation, the ADC module continuously collects power consumption data, generating a power consumption sample value every 10 ns. The MCU's interrupt handling module triggers an interrupt every 10 ns, reads the sample value, and calculates the slope of the power consumption curve for the current step. The slope calculation uses the two-point difference method, with the formula: slope k = (Pn - Pn-1) / (tn - tn-1), where Pn is the power consumption value at the current sampling point, Pn-1 is the power consumption value at the previous sampling point, and tn-tn-1 is the sampling interval (10 ns).

[0084] The calculated slope is compared with a preset threshold (0.1A / μs): if the slope is ≤0.1A / μs, it indicates that the power consumption transition of the current step is smooth and there is no high risk of leakage. The next operation is performed according to the preset dwell time (e.g., 100ns, 80ns, 120ns); if the slope is >0.1A / μs, it indicates that the power consumption of the current step has a large change and there is a risk of leakage. The dwell time of the current step is automatically extended by 50ns, and the slope is recalculated until the slope is ≤0.1A / μs or the extension is extended 3 times.

[0085] If the slope still exceeds the threshold after three extensions (total dwell time increased by 150ns), it is determined that the current through-hole disconnection operation has an uncontrollable leakage risk. The system will automatically trigger the redundancy switching mechanism, activate the backup Tie Spare Cell (which has the same structure as the main Tie Spare Cell and is independently controlled) to perform encrypted value switching, or send an alarm message to indicate that the switching of the main Tie Spare Cell under the current operating condition has a security risk and requires further investigation.

[0086] During the dynamic adjustment process, the dwell time is limited to a preset range (e.g., minimum 50ns, maximum 300ns) to avoid delays in encryption logic switching due to excessive dwell time, which would affect the real-time performance of the MCU.

[0087] According to embodiments of the present invention, the core purpose of timing stagger optimization is to avoid the superposition of power consumption characteristics of step-by-step switching of encrypted values ​​and switching of ROM code versions, which would lead to excessively high peak total power consumption and thus increase the risk of leakage. This optimization achieves timing control through the timer built into the MCU, ensuring that the two switching actions are completely separated on the time axis with no overlapping intervals.

[0088] For example, a high-precision general-purpose timer (such as Timer1) of the MCU is selected. This timer supports microsecond-level timing accuracy and adapts to the timing control requirements of two switching actions. The clock source of the timer is the core clock of the MCU (such as 80MHz). The clock frequency is divided to 1MHz by a prescaler (prescaler coefficient is 80). At this time, the counting period of the timer is 1μs, ensuring that the timing accuracy meets the requirements of the preset time interval.

[0089] Based on simulation tests and actual operating condition verification, the preset time interval is preferably ≥1μs. This interval ensures that the power consumption curve of the previous switching action fully recovers to stability (typically, the power consumption curve recovers to the baseline within 0.5μs after the switching is completed), while also preventing ROM code version switching delays due to excessively long intervals. In some embodiments, the time interval can be dynamically adjusted according to actual operating conditions. For example, when the AI ​​model predicts a high power consumption peak during ROM code version switching, the interval can be extended to 1.5μs to further reduce the risk of cumulative effects.

[0090] Specifically, please see Figure 5 The timing control process may include:

[0091] S501, initiate encrypted numerical step-by-step switching. When the AI ​​model outputs a high-risk level and generates a step-by-step switching strategy, the MCU's control module first triggers the step-by-step switching process of the Tie Spare Cell, and at the same time starts Timer1 to begin timing, with an initial timing value of 0.

[0092] S502, monitoring the completion of step-by-step switching: The control module monitors the execution status of step-by-step switching in real time. When the last step of step-by-step switching (the third intermediate level transitions to 0V) is completed, a "switching complete" signal is generated. At this time, the count value of Timer1 is t1 (for example, t1=300ns).

[0093] S503, a delayed ROM code switching is triggered. After the control module receives the "switching complete" signal, it continues to wait for Timer1 to count down to the preset time interval (1μs), i.e., from t1=300ns to t2=1μs, with a waiting time of 700ns. During the waiting period, the ADC module continuously monitors the power consumption curve to ensure that the power consumption has recovered to the baseline (e.g., stabilized below 10μA).

[0094] S504, ROM code version switching is performed. When Timer1 reaches 1μs, the control module triggers the control signal for ROM code version switching. By modifying the via state of the corresponding ROM code area in Mask Via1, the connection relationship between Metal1 and Metal2 is adjusted to complete the ROM code version switching. This switching process takes approximately 200ns. The power consumption curve generated during this period is completely separate from the power consumption curve of the encryption value switching on the time axis, with no overlapping intervals.

[0095] In some embodiments, the timing control flow also has a fault tolerance mechanism: if the execution time of the step-by-step switching exceeds the preset maximum value (e.g., 500ns), Timer1 will automatically trigger the ROM code version switching to avoid the entire process from stalling due to step-by-step switching anomalies; at the same time, the anomaly will be recorded in the causal migration record for easy subsequent investigation.

[0096] Furthermore, to further reduce the risk of power consumption accumulation, the AI ​​model also predicts the power consumption characteristics of ROM code version switching (such as peak power consumption and curve slope), and adjusts the dwell time of the third intermediate level during encryption value switching based on the prediction results. For example, if the model predicts a high peak power consumption during ROM code switching (e.g., 5mA), the dwell time of the third intermediate level is extended to 150ns, making the falling edge of the power consumption curve for encryption value switching smoother. Even if there is a slight overlap with the power consumption curve of ROM code switching, it will not lead to an excessively high total power consumption peak.

[0097] Figure 6 A post-mask engineering change system 600 for a microcontroller (MCU) is illustrated. The system embodiment is similar to... Figure 1 Corresponding to the illustrated method embodiments, the specific methods include:

[0098] The initial logic setting module 601 is used to insert at least one Tie Spare Cell into the encryption logic of the MCU. The input pin of the Tie Spare Cell is connected to a fixed high level through the first Tie Cell, so that its output initial logic value is a first value.

[0099] Configuration module 602 is used to configure multiple versions of the MCU's read-only memory ROM code to be switched by modifying the connection relationship of the first mask layer Mask Via1;

[0100] Modification module 603 is used to perform a mask modification on the Mask Via1 layer to change the logic value and switch the ROM code when it is necessary to modify the value of the encryption logic from the first value to the second value and switch the version of the ROM code simultaneously.

[0101] The step of performing a mask modification for the Mask Via1 layer includes: modifying the connection of the input pin of the Tie SpareCell, switching it from being connected to the fixed high level to being connected to the fixed low level, thereby changing the output logic value of the Tie Spare Cell from the first value to the second value;

[0102] In addition, the metal layer connection relationship of the ROM code is changed to switch the current version of the ROM code to the target version of the ROM code.

[0103] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for post-mask engineering changes for microcontrollers (MCUs), characterized in that, The method comprises the following steps: Insert at least one Tie Spare Cell in the encryption logic of the MCU, the input pin of the Tie Spare Cell is connected to a fixed high level through a first Tie Cell, so that its output initial logic value is a first value; Multiple versions of read-only memory (ROM) code of the MCU are configured to be switched by modifying the connection relationship of a first mask layer (Mask Via1); When it is necessary to modify the value of the encryption logic from the first value to a second value and synchronously switch the version of the ROM code, the logic value change and the ROM code switching are realized by performing a mask modification for the Mask Via1 layer once; The execution of the mask modification for the Mask Via1 layer once includes modifying the connection of the input pin of the Tie Spare Cell, so that it is switched from being connected to the fixed high level to being connected to a fixed low level, thereby causing the output logic value of the Tie Spare Cell to change from the first value to the second value; In addition, the metal layer connection relationship of the ROM code is changed to switch the current version of the ROM code to a target version of the ROM code.

2. The method for mask post engineering change of claim 1, wherein, Before modifying the connection of the input pin of the Tie Spare Cell, the method further comprises: Collecting power consumption data when the Tie Spare Cell is switched from the first value to the second value, comparing the power consumption data with a predetermined risk threshold to evaluate the power consumption leakage risk, and triggering a step-by-step modification process for the input pin connection of the Tie Spare Cell when the evaluation result is high risk.

3. The mask post-engineering change method for a microcontroller (MCU) according to claim 2, wherein wherein The Mask Via1 of the input pin of the Tie Spare Cell has multiple independent through holes, and the modification of the connection of the input pin of the Tie Spare Cell specifically includes step-by-step disconnecting at least two of the multiple independent through holes in a predetermined order and timing in response to the evaluation result being high risk, so that the input level of the Tie Spare Cell is stabilized to a level value corresponding to the fixed low level via at least one intermediate level.

4. The mask post-engineering change method for a microcontroller (MCU) according to claim 3, wherein The step-by-step disconnecting of at least two of the multiple independent through holes specifically includes controlling the input level of the Tie Spare Cell to sequentially pass through a first intermediate level, a second intermediate level, and a third intermediate level, and finally reach a level value corresponding to the fixed low level, wherein the voltage values of the first intermediate level, the second intermediate level, and the third intermediate level are between the voltage values of the fixed high level and the fixed low level.

5. The mask post-engineering change method for a microcontroller (MCU) according to claim 3, wherein The step-by-step disconnection of at least two of the plurality of independent vias includes, after the step of disconnecting each via, collecting real-time power consumption feedback data, dynamically adjusting the execution timing or dwell time of the next via disconnection operation based on the real-time power consumption feedback data.

6. The mask post engineering change method for a microcontroller (MCU) according to claim 2, wherein, The evaluation of the power consumption leakage risk is achieved by an AI model, which takes the current operating temperature and / or power supply voltage of the MCU and the power consumption data as input and outputs a risk level of the power consumption leakage risk.

7. The mask post engineering change method for a microcontroller (MCU) according to claim 3, wherein, The operation of changing the metal layer connection relationship of the ROM code is staggered in time from the operation of step-by-step disconnection of the plurality of independent vias by a preset time interval, avoiding the superposition of power consumption characteristics.

8. The mask post engineering change method for a microcontroller (MCU) according to claim 7, wherein, The step-by-step modification of the Tie Spare Cell input pin connection is performed first, and then the change of the metal layer connection relationship of the ROM code is performed.

9. The mask post engineering change method for a microcontroller (MCU) according to claim 8, wherein, If the execution time of the step-by-step switching exceeds a preset maximum value, the ROM code version switching is automatically triggered.

10. A post-mask engineering change system for a microcontroller (MCU), characterized by, Comprise: An initial logic setting module for inserting at least one Tie Spare Cell in the encryption logic of the MCU, the input pin of the Tie Spare Cell being connected to a fixed high level through a first Tie Cell, so that its output initial logic value is a first value; A configuration module for configuring multiple versions of read-only memory (ROM) code of the MCU to be switched by modifying the connection relationship of a first mask layer (Mask Via1); A modification module for modifying the value of the encryption logic from the first value to a second value and simultaneously switching the version of the ROM code by performing a mask modification for the Mask Via1 layer once; Wherein, the execution of the mask modification for the Mask Via1 layer once includes modifying the connection of the input pin of the Tie Spare Cell, so that it is switched from being connected to the fixed high level to being connected to a fixed low level, thereby changing the output logic value of the Tie Spare Cell from the first value to the second value; And, changing the metal layer connection relationship of the ROM code to switch the current version of the ROM code to the target version of the ROM code.

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