Cache reading circuit and method, cache reading and writing circuit and nonvolatile memory chip

Abstract

The invention discloses a cache reading circuit and method, a cache reading and writing circuit and a nonvolatile memory chip. The cache reading circuit comprises a pre-charging control module and a sensitive amplification module. A data transmission line of the pre-charging control module is coupled with a plurality of data ends of the buffer, and the pre-charging control module reads the voltage to be identified stored in the corresponding buffer unit from a target data end of the buffer through the data transmission line in response to the current cache reading operation; wherein the pre-charging control module keeps a pre-charging operation on a data transmission line coupled with a target data end during a previous cache reading operation period; and the sensitive amplification module is coupled with the data transmission line of the pre-charging control module, and the sensitive amplification module responds to the received to-be-identified voltage sent by the pre-charging control module through the data transmission line and performs amplification reading operation on the to-be-identified voltage to obtain data represented by the to-be-identified voltage. In this way, the cache reading speed can be increased.

Description

Technical Field

[0001] This application relates to the field of storage read / write technology, and in particular to cache read circuits and methods, cache read / write circuits, and non-volatile memory chips. Background Technology

[0002] Memory is widely used for data storage to facilitate data reading and writing. Memory can be non-volatile or volatile. NAND flash memory, for example, is a widely used type of memory; it is non-volatile and used for data storage such as video, audio, and programs.

[0003] Typically, memory contains a cache, which can be written to or read from using corresponding read / write circuits. Summary of the Invention

[0004] The cache read circuit and method, cache read / write circuit, and non-volatile memory chip provided in this application can improve cache read speed.

[0005] In a first aspect, this application provides a cache read circuit, comprising: a pre-charge control module, wherein a data transmission line of the pre-charge control module is coupled to several data terminals of a cache, and the pre-charge control module, in response to the current cache read operation, reads the voltage to be identified stored in the corresponding cache unit from the target data terminal of the cache through the data transmission line; wherein the pre-charge control module maintains a pre-charge operation on the data transmission line coupled to the target data terminal during the previous cache read operation; and a sensitive amplification module, coupled to the data transmission line of the pre-charge control module, wherein the sensitive amplification module, in response to receiving the voltage to be identified sent by the pre-charge control module through the data transmission line, amplifies and reads the voltage to be identified to obtain the data represented by the voltage to be identified.

[0006] Each buffer unit corresponds to a data terminal. The precharge control module includes several precharge control units. The data transmission line of each precharge control unit is coupled to the data terminal of a buffer unit and a sensitive amplification module.

[0007] Each cache unit's data terminal includes a first data line and a second data line, which are complementary data lines. Each precharge control unit's data transmission line includes a first data transmission line and a second data transmission line. The first data transmission line and the second data transmission line of each precharge control unit are respectively coupled to the first data line and the second data line. In response to the current read cache operation, the precharge control unit outputs the current voltage on the first data line and the second data line, which is the voltage to be identified, to the sensitive amplification module through the first data line and the second data line, respectively.

[0008] Each precharge control unit includes: a precharge control circuit, which is coupled to the first and second data lines respectively via a first data transmission line and a second data transmission line, for maintaining precharge operation on the first and second data transmission lines during the previous read buffer operation; an inverting circuit, coupled to the precharge control circuit, for outputting a corresponding control signal according to the precharge control circuit; and a switching circuit, whose control terminal is coupled to the output terminal of the inverting circuit, whose first terminal is coupled to the first data transmission line, whose second terminal is coupled to the second data transmission line, and whose third and fourth terminals are coupled to a sensitive amplification module; during the current read buffer operation, the switching circuit responds to the control signal output by the inverting circuit, with its first and third terminals conducting, and its second and fourth terminals conducting, respectively outputting the current voltage on the first and second data transmission lines as the voltage to be identified to the sensitive amplification module.

[0009] The precharge control circuit includes: a first transistor, with its first path terminal coupled to a power supply terminal and its second path terminal coupled to a first data transmission line; a second transistor, with its first path terminal coupled to a power supply terminal and its second path terminal coupled to a second data transmission line; a third transistor, with its first path terminal coupled to the first data transmission line and its second path terminal coupled to the second data transmission line; and control terminals of the first, second, and third transistors for receiving a selection signal. The inverting circuit includes: a fourth transistor, with its first path terminal coupled to a power supply terminal; a fifth transistor, with its first path terminal coupled to the second path terminal of the fourth transistor and its second path terminal coupled to a reference ground; and control terminals of the fourth and fifth transistors for receiving a selection signal. The switching circuit includes: a sixth transistor, with its first path terminal coupled to the first data transmission line and its second path terminal coupled to the first input terminal of the sensitive amplifier module; a seventh transistor, with its first path terminal coupled to the second data transmission line and its second path terminal coupled to the second input terminal of the sensitive amplifier module; and control terminals of the sixth and seventh transistors coupled to the first path terminal of the fifth transistor.

[0010] The sensitive amplification module includes: a comparator, the first input of which is coupled to the first output of the precharge control unit, and the second input of which is coupled to the second output of the precharge control unit; and a latch, the input of which is coupled to the output of the comparator, for latching the output of the comparator; wherein the output of the comparator is used to characterize the data represented by the voltage to be identified stored in the buffer unit.

[0011] The pre-charge control module performs a pre-charge operation on the data transmission lines coupled to all target data terminals before the current read cache operation is the first read cache operation.

[0012] Secondly, this application provides a cache read / write circuit, which includes: a precharge / write control module, whose data transmission line is coupled to several data terminals of the cache; the precharge / write control module, in response to the current cache read operation, reads the voltage to be identified stored in the corresponding cache unit from the target data terminal of the cache through the data transmission line; wherein, the precharge / write control module maintains a precharge operation on the data transmission line coupled to the target data terminal during the previous cache read operation; and a sensitive amplification module, coupled to the data transmission line of the precharge / write control module; the sensitive amplification module, in response to receiving the voltage to be identified sent by the precharge / write control module through the data transmission line, amplifies and reads the voltage to be identified to obtain the data represented by the voltage to be identified; wherein, the precharge / write control module can be multiplexed for writing data to the corresponding cache unit of the cache through the data transmission line.

[0013] The cache read / write circuit also includes a read / write decoding module, which outputs a read cache signal or a write cache signal to the precharge / write control module according to the read cache operation or write cache operation. The precharge / write control module reads the voltage to be identified stored in the corresponding cache unit from the target data terminal of the cache according to the read cache signal, or writes data to the corresponding cache unit of the cache according to the write cache signal.

[0014] Each cache unit corresponds to a data terminal. The precharge / write control module includes several precharge / write control units. The data transmission line of each precharge / write control unit is coupled to the data terminal of a cache unit and a sensitive amplification module.

[0015] Each cache unit includes a first data line and a second data line as its data terminals, which are complementary data lines. Each precharge / write control unit includes a first data line and a second data line as its data transmission lines. The first and second data transmission lines of each precharge / write control unit are respectively coupled to the first and second data lines. In response to the current read cache operation, each precharge / write control unit outputs the current voltage on the first and second data lines (as the voltage to be identified) to the sensitive amplification module via the first and second data lines, respectively. Alternatively, in response to the current write cache operation, each precharge / write control unit inputs the target voltage corresponding to the data to be written to the first and second data lines via the first and second data lines, respectively, so that the corresponding cache unit stores the target voltage.

[0016] Each precharge / write control unit includes: a precharge / write control circuit, which is coupled to the first and second data lines respectively via a first data transmission line and a second data transmission line, for maintaining a precharge operation on the first and second data transmission lines during the previous read cache operation; and a switching circuit, the control terminal of which is coupled to the read / write decoding module, the first terminal of which is coupled to the first data transmission line, the second terminal of which is coupled to the second data transmission line, and the third and fourth terminals of which are coupled to a sensitive amplification module; during the current read cache operation, the switching circuit responds to the read / write decoding module. The first control signal of the code module turns on the first and third terminals of the switching circuit, and turns on the second and fourth terminals of the switching circuit, respectively outputting the current voltage of the voltage to be identified on the first data transmission line and the second data transmission line to the sensitive amplification module; during the current write buffer operation, the switching circuit responds to the first control signal of the read / write decoding module, and the first and third terminals are turned off, and the second and fourth terminals are turned off. The precharge / write control circuit responds to the second control signal of the read / write decoding module, and inputs the target voltage corresponding to the data to be written to the first data transmission line and the second data transmission line, respectively, so that the corresponding buffer unit stores the target voltage.

[0017] The precharge / write control circuit includes: a first transistor, with its first terminal coupled to a power supply and its second terminal coupled to a first data transmission line; a second transistor, with its first terminal coupled to a power supply and its second terminal coupled to a second data transmission line; a third transistor, with its first terminal coupled to the first data transmission line and its second terminal coupled to the second data transmission line; a fourth transistor, with its first terminal coupled to the first terminal of the third transistor and its second terminal coupled to a reference ground; and a fifth transistor, with its first terminal coupled to the third transistor. The second path terminal of the fifth transistor is coupled to a reference ground; wherein, the control terminals of the first, second, third, fourth, and fifth transistors are respectively coupled to the read / write decoding module for receiving corresponding control signals; the switching circuit includes: a sixth transistor, the first path terminal of the sixth transistor is coupled to the first data transmission line, and the second path terminal of the sixth transistor is coupled to the first input terminal of the sensitive amplifier module; a seventh transistor (M6), the first path terminal of the seventh transistor is coupled to the second data transmission line, and the second path terminal of the seventh transistor is coupled to the second input terminal of the sensitive amplifier module; the control terminals of the sixth and seventh transistors are coupled to the read / write decoding module.

[0018] Thirdly, this application provides a non-volatile memory chip, including a cache read circuit as provided in the first aspect, or a cache read / write circuit as provided in the second aspect.

[0019] Fourthly, this application provides a cache reading method applied to a cache reading circuit. The cache reading circuit includes a pre-charge control module and a sensitive amplification module. The cache reading method includes: the pre-charge control module, in response to the current cache read operation, reads the voltage to be identified stored in the corresponding cache unit from the target data terminal of the cache 200 through a data transmission line; wherein, the pre-charge control module maintains a pre-charge operation on the data transmission line coupled to the target data terminal during the previous cache read operation; the sensitive amplification module, in response to receiving the voltage to be identified sent by the pre-charge control module through the data transmission line, amplifies and reads the voltage to be identified to obtain the data represented by the voltage to be identified.

[0020] The beneficial effects of this application are as follows: Unlike the prior art, the cache read circuit and method, cache read / write circuit, and non-volatile memory chip provided in this application, with their pre-charge control module, maintain a pre-charge operation on the data transmission lines coupled to the target data terminals of other cache units each time data is read from the target cache unit. This ensures that when data is read from other cache units in the next read operation, the data transmission lines corresponding to the next cache unit have already been pre-charged during the previous read operation of the target cache unit. Therefore, during the next read operation, the corresponding cache unit can be directly controlled to read data, saving cache read time and thus improving cache read speed. In other words, by adjusting the timing of the separate pre-charge operation required for each read operation cycle of a cache unit in related technologies, the pre-charge operation for the next cache unit to be read is performed within the read operation cycle of the currently read cache unit. This achieves time reuse, shortening the read operation cycle of the cache unit and thus improving cache read speed. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0022] Figure 1 This is a schematic diagram of the structure of an embodiment of the memory provided in this application;

[0023] Figure 2 This is a schematic diagram of an embodiment of reading, programming, and erasing a NAND flash memory provided in this application;

[0024] Figure 3This is a schematic diagram of an embodiment of the cache and cache read module inside the NAND flash memory provided in this application;

[0025] Figure 4 This is a schematic diagram of the structure related to cache reading in the cache unit provided in this application;

[0026] Figure 5 This is a schematic diagram of an embodiment of the cache read method provided in this application;

[0027] Figure 6 This is a schematic diagram of another embodiment of the cache read method provided in this application;

[0028] Figure 7 This application provides Figure 5 and Figure 6 Timing diagram of cache read method;

[0029] Figure 8 This is a schematic diagram of an embodiment of the cache read circuit provided in this application;

[0030] Figure 9 This application provides Figure 8 A schematic diagram of cache read timing;

[0031] Figure 10 This is a schematic diagram of another embodiment of the cache read circuit provided in this application;

[0032] Figure 11 This is a schematic diagram of the structure of an embodiment of the precharge control unit provided in this application;

[0033] Figure 12 This is a schematic diagram of an embodiment of the precharge control circuit provided in this application;

[0034] Figure 13 This is a schematic diagram of the structure of an embodiment of the sensitive amplification module provided in this application;

[0035] Figure 14 This is a schematic diagram of another embodiment of the cache read circuit provided in this application;

[0036] Figure 15 This is a schematic diagram of the structure of an embodiment of the cache read / write circuit provided in this application;

[0037] Figure 16 This is a schematic diagram of the structure of a read / write decoding module in the cache read / write circuit provided in this application;

[0038] Figure 17 This is a schematic diagram of the structure of an embodiment of the precharge / write control unit provided in this application;

[0039] Figure 18This is a schematic diagram of an embodiment of the precharge / write control circuit provided in this application;

[0040] Figure 19 This is a schematic diagram of another embodiment of the cache read / write circuit provided in this application;

[0041] Figure 20 This is the truth value representation of the read / write logic decoding provided in this application;

[0042] Figure 21 This is a flowchart illustrating an embodiment of the cache reading method provided in this application. Detailed Implementation

[0043] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0044] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0045] Memory is widely used for data storage, facilitating data reading and writing. Memory can be non-volatile or volatile. NAND flash memory is a widely used type of memory, characterized by its non-volatile nature, used for data storage such as video, audio, and programs. Based on the number of data bits stored in a single memory cell, NAND flash memory can be categorized into SLC NAND (Single-Level Cell), MLC NAND (Multi-Level Cell), TLC NAND (Triple-Level Cell), and QLC NAND (Quadruple-Level Cell). NAND flash memory communicates with an external controller according to a specific standard or protocol to complete data writing and reading. Common NAND flash memory interface standards include ONFI, Toggle DDR, and SPI.

[0046] The basic structure of NAND flash memory chips is as follows: Figure 1As shown, it includes input / output interfaces, control logic, voltage biasing, cache writing, cache reading, row decoding, column decoding, registers, and a storage array module. The input / output interface module is responsible for interacting with external controllers, including instruction input and decoding, address input, and data input and output. The control logic module is mainly responsible for controlling the internal operation flow, including address control and operating voltage bias. The row and column decoding modules implement row address decoding and column address decoding, respectively. The storage array module is used for data storage and consists of several storage cells, each storing one or more bits of data. Logically, the storage array can be divided into several blocks, each containing multiple pages. The register module is responsible for writing externally input data to the storage array or reading data from the storage array and caching it. The cache writing module is responsible for writing externally input data to the register. The cache reading module is responsible for reading data from the register to the input / output interface.

[0047] The basic operations of NAND flash memory include reading, programming (writing), and erasing, and their operation sequence is as follows: Figure 2 As shown. Read operations are performed page-by-page. Upon receiving a valid read command and address, the NAND flash memory initiates its internal read process, reading the data of the specified page from the storage array into the cache. Finally, the external controller reads the data from the cache to the chip pins. Programming operations are also performed page-by-page. Upon receiving a valid programming command and address, the externally input data is loaded into the cache, and then the internal programming process is initiated to write the cache data to the storage array. Erase operations are performed block-by-block. Upon receiving a valid erase command and address, the NAND flash memory initiates its internal erase process, erasing all data within the specified block.

[0048] A block diagram of the cache and cache read module inside NAND flash memory is shown below. Figure 3 As shown. The cache is physically composed of an array of cache cells, with K rows multiplied by L columns. Here, K represents the number of physically stacked cells (commonly 8, 16, etc.), and L is determined by the page size of the NAND flash memory (common page sizes are 2KB, 4KB, 8KB, 16KB, etc.), hence this cache is also called a page cache. The cache read module consists of N parallel read units (N is usually the number of bits in several bytes, such as 8, 16, 32, etc.), which read data from the cache under the operation of input control signals. The data lines connecting the cache read module to the cache can be single-ended or differential. For example... Figure 3 The differential method used is shown.

[0049] Taking the differential form as an example, for a cache unit, Figure 4This diagram illustrates the structure related to cache readout (differential method). M0 and M1 are P-type MOS transistors (PMOS), and the other devices are N-type MOS transistors (NMOS). Each MOS transistor has four terminals: source, gate, drain, and bulk. Figure 4 All PMOS transistors have their bodies connected to the power supply VDD, and all NMOS transistors have their bodies connected to ground GND. M0's source is connected to the power supply VDD, its gate to node C, and its drain to node Cb; M1's source is connected to the power supply VDD, its gate to node Cb, and its drain to node C; M2's source is connected to ground GND, its gate to node C, and its drain to node Cb; M3's source is connected to ground GND, its gate to node Cb, and its drain to node C; M4's source is connected to the positive data line DL1 (as described in the first data line), its gate to the decoding signal CSL, and its drain to node C; M5's source is connected to the inverting data line DLb1 (as described in the second data line), its gate to the decoding signal CSL, and its drain to node Cb. M0-M3 form a latch, with C and Cb being the positive and negative data storage nodes, respectively. M4-M5 form the latch's decoding switch, controlled by the decoding signal CSL. Logic 0 and logic 1 in the decoding signal CSL represent decoding deselection and decoding selection, respectively.

[0050] For the readout unit, there are two related designs: one is to use a single-stage readout amplifier, such as... Figure 5 As shown, one method directly amplifies and reads the cached data through data lines DL1 / DLb1, i.e., the readout amplifier outputs data DO; another method uses a two-stage readout amplifier, such as... Figure 6 As shown, the first-stage amplifier amplifies the buffered data through local differential data lines LDL1 / LDLb1 and outputs it to data lines DL1 / DLb1. The second-stage amplifier then amplifies and compares the voltage on the differential data lines DL1 / DLb1 and outputs the data DO. The number of first-stage readout amplifiers is the same as the number of local differential data lines LDL1 / LDLb1; the specific number can be one or more, determined according to the actual load and readout speed requirements. Compared to... Figure 5 , Figure 6 Read caching is faster but has a larger area overhead.

[0051] against Figure 5 and Figure 6 The technical solution in the middle, Figure 7 The flowchart illustrating its read cache process is shown. Each two read cache operations are performed serially, and each read cache operation consists of three stages: First, the selected data line is pre-charged for a duration of T. P Then, enable the decoding control for the selected cache unit (see...). Figure 4In the decoding signal CSL, the buffer unit discharges the pre-charged data line and performs data line evaluation. This stage lasts for T seconds. D Finally, the readout amplifier amplifies the discharged data line voltage and outputs logic data, with a duration of T. S .

[0052] As mentioned above, the inventors of this application have found that the read speed of the relevant cache read scheme is not high.

[0053] Based on this, this application proposes to utilize a pre-charge control module to maintain pre-charge operations on the target data ends of other cache units each time data is read from the target cache unit. This ensures that when data is read from the target cache unit again, since the target data end of the current target cache unit has already been pre-charged, data can be read directly, saving cache read time and thus improving cache read speed. Specifically, the timing of the pre-charge operation, which requires separate pre-charge operations within each read cache operation cycle of a cache unit in related technologies, is adjusted so that the pre-charge operation of the next cache unit to be read is performed within the read cache operation cycle of the currently read cache unit. This achieves time reuse by completing the read cache operation of the currently read cache unit and pre-charging the next cache unit to be read within the same time period, shortening the read cache operation cycle of the cache unit and thus improving cache read speed. See any of the following embodiments for details.

[0054] See Figure 8 , Figure 8 This is a schematic diagram of an embodiment of the cache read circuit provided in this application. The cache read circuit 100 includes: a precharge control module 10 and a sensitive amplification module 20.

[0055] The data transmission line of the precharge control module 10 is coupled to several data terminals of the buffer 200. In response to the current read buffer operation, the precharge control module 10 reads the voltage to be identified stored in the corresponding buffer unit from the target data terminal of the buffer 200 through the data transmission line. The precharge control module 10 maintains the precharge operation of the data transmission line coupled to the target data terminal during the previous read buffer operation.

[0056] The sensitive amplification module 20 is coupled to the data transmission line of the precharge control module 10. In response to receiving the voltage to be identified sent by the precharge control module 10 through the data transmission line, the sensitive amplification module 20 amplifies and reads the voltage to be identified to obtain the data represented by the voltage to be identified.

[0057] Combination Figure 9 Explanation: Figure 9 for Figure 8 The read cache operation process corresponding to the cache read circuit 100.

[0058] The read cache operation sequence is as follows:

[0059] Before initiating the read cache operation, the control signal SEL issued by the memory is used to precharge all data terminals of the cache 200 and the data transmission lines of the precharge control module 10 coupled to the data terminals. The precharge duration is T. P .

[0060] When the first cache read begins, the control signal SEL selects a set of LDL / LDLb from the precharge control module 10 to be read (LDL / LDLb are the data transmission lines of the precharge control module 10, used to transmit the voltage on DL1 / DLb1 of the cache unit), and connects the selected LDL / LDLb to DL1 / DLb1 of the cache unit. DL1 / DLb1 of the cache unit constitutes the data terminal of the cache unit, and all other unselected LDL / LDLb are disconnected from DL1 / DLb1. Since the data transmission line of the selected precharge control module 10 has been precharged, the decoding control of the selected cache unit can be directly started (see reference). Figure 4 The decoding signal CSL in the buffer causes the buffer unit to discharge through the data lines DL1 / DLb1, changing the voltage of the data transmission lines LDL / LDLb coupled to the data lines. This stage is called "data line evaluation" and lasts for T. D Then, the sensitive amplification module 20 amplifies the voltage on the data transmission line after discharge and outputs the data. This stage is called "amplification readout" and lasts for T seconds. S This completes one read cache operation. It is important to note that during this read cache operation, all unselected LDL / LDLb in the precharge control module 10 remain in the precharge state.

[0061] Subsequent cache reads follow the same process as the first cache read. Since the data lines of the selected cache unit have already been pre-charged during the previous cache read process, data reading can be completed simply by first "evaluating the data lines" and then "amplifying and reading." Therefore, the time for one cache read is T. D +T S .

[0062] It should be pointed out that, although Figure 9 The example shown is a differential data line method, but this solution is also applicable to single-ended data line methods.

[0063] Regarding the time required for a single cache read, relevant technical solutions (see reference). Figure 7 ) T is needed P +T D +T S This application only requires T D +T SBecause the actual physical traces of LDL / LDLb are usually very long and have large parasitic capacitances, their RC delay is relatively large, resulting in a longer required precharge time T. P The discharge time is relatively long. In contrast, for differential data line methods, it is usually only necessary to determine that the discharge voltage difference between DL1 and DLb1 reaches the level of one hundred millivolts to start amplification and comparison, thus the discharge time T is relatively short. D It doesn't need to be too long. And for T... S If a latching-type sensitive amplification module 20 is used, the amplification and comparison time is also relatively short. Therefore, T P This accounts for a significant portion of the cache read time. In other words, the cache read circuit of this application shows a significant improvement in read speed compared to related technologies.

[0064] In this embodiment, the pre-charge control module 10 maintains a pre-charge operation on the data transmission lines coupled to the target data terminals of other cache units each time data is read from the target cache unit. This ensures that when data is read from other cache units in the next read operation, the data transmission lines corresponding to the next cache unit have already been pre-charged during the previous read operation of the target cache unit. Therefore, during the next read operation, the corresponding cache unit can be directly controlled to read data, saving cache read time and improving cache read speed. In other words, the timing of the separate pre-charge operation required for each read operation cycle of a cache unit in related technologies is adjusted. The pre-charge operation for the next cache unit to be read is performed within the read operation cycle of the currently read cache unit. This achieves time reuse by completing the read operation of the currently read cache unit and pre-charging the data transmission lines corresponding to the next cache unit to be read within the same time period, shortening the read operation cycle of the cache unit and thus improving cache read speed.

[0065] In some embodiments, each cache unit corresponds to a data terminal. The precharge control module 10 includes a plurality of precharge control units, each precharge control unit having its data transmission line coupled to the data terminal of a cache unit and the sensitive amplification module 20. That is, the data input and output of the cache unit can be single data input and output, i.e., data input and output are achieved through a single data line (data terminal). When performing a read operation from the cache unit, the precharge control unit precharges the data terminal of the cache unit to be read in the previous read operation, increasing the voltage of the data terminal. Then the cache unit performs a discharge operation, merging with the voltage on the data terminal. For example, it raises or lowers the voltage on the data terminal, and then outputs the merged voltage to the sensitive amplification module 20.

[0066] In some embodiments, see Figure 10Each cache unit's data terminal includes a first data line DL1 (not shown) and a second data line DLb1 (not shown), wherein the first data line DL1 and the second data line DLb1 are complementary data lines; each precharge control unit's data transmission line includes a first data transmission line LDL and a second data transmission line LDLb. The first data transmission line LDL and the second data transmission line LDLb of each precharge control unit are respectively coupled to the first data line DL1 and the second data line DLb1. In response to the current read cache operation, the precharge control unit outputs the current voltage on the first data line DL1 and the second data line DLb1, which is the voltage to be identified, to the sensitive amplification module 20 through the first data line LDL and the second data line LDLb, respectively. That is, it outputs the current voltage on the first data line DL1 and the second data line DLb1, which is the voltage to be identified, to the sensitive amplification module 20 through data lines DL2 / DLb2.

[0067] When performing a read cache operation on the target cache unit, the first data transmission line LDL and the second data transmission line LDLb of the precharge control unit, which are coupled to the first data line DL1 and the second data line DLb1 of the target cache unit, have already been precharged to the precharge voltage. Based on the selection signal, the corresponding precharge control unit and the target cache unit are selected. The target cache unit discharges the first data line DL1 and the second data line DLb1, causing a change in the precharge voltage on the first data line LDL and the second data line LDLb coupled to the first data line DL1 and the second data line DLb1. In response to the current read cache operation, the precharge control unit outputs the changed voltage on the first data line LDL and the second data line LDLb as the current voltage to the sensitive amplification module 20. The sensitive amplification module 20 detects the input voltage and outputs data that characterizes that voltage. For example, if the cache unit stores voltage characterization data 1, then after the above read cache operation, the sensitive amplification module 20 outputs data 1. If the cache unit stores voltage characterization data 0, then after the above read cache operation, the sensitive amplification module 20 outputs data 0.

[0068] In some embodiments, see Figure 11 The precharge control unit includes: a precharge control circuit 11, an inverting circuit 12, and a switching circuit 13.

[0069] The precharge control circuit 11 is coupled to the first data line DL1 and the second data line DLb1 of the cache unit through the first data transmission line LDL and the second data transmission line LDLb, respectively. It is used to maintain the precharge operation of the first data transmission line LDL and the second data transmission line LDLb during the previous read cache operation, so as to directly control the corresponding cache unit to perform data line discharge operation during the current read cache operation and change the voltage on the first data transmission line LDL and the second data transmission line LDLb.

[0070] The inverter circuit 12 is coupled to the precharge control circuit 11 and is used to output corresponding control signals according to the precharge control circuit 11. The inverter circuit 12 mainly cooperates with the subsequent switching circuit 13. The inverter circuit 12 can output corresponding control signals according to the selection signal mentioned above. For example, when the selection signal is high at the start of reading the buffer, the inverter circuit 12 also outputs a high-level control signal according to the high level of the selection signal to control the switching circuit 13 to turn on. Further, the inverter circuit 12 also outputs a low-level control signal according to the low level of the selection signal to control the switching circuit 13 to turn off. That is, the control signal output by the inverter circuit 12 changes with the selection signal. It can be understood that when the selection signal is low, it indicates that the target buffer unit corresponding to the selection signal has not been selected.

[0071] The control terminal of the switching circuit 13 is coupled to the output terminal of the inverting circuit 12. The first terminal of the switching circuit 13 is coupled to the first data transmission line LDL. The second terminal of the switching circuit 13 is coupled to the second data transmission line LDLb. The third and fourth terminals of the switching circuit 13 are coupled to the sensitive amplification module 20.

[0072] During the current read buffer operation, in response to the control signal output by the inverting circuit 12, the first and third terminals of the switching circuit 13 are turned on, and the second and fourth terminals of the switching circuit 13 are turned on, respectively outputting the current voltage on the first data transmission line LDL and the second data transmission line LDLb as the voltage to be identified to the sensitive amplification module 20.

[0073] It can be understood that the third and fourth terminals of the switching circuit 13 are the output terminals of the switching circuit 13. When the first and third terminals of the switching circuit 13 are turned on, the voltage on the first data transmission line LDL can be output to the sensitive amplifier module 20. When the second and fourth terminals of the switching circuit 13 are turned on, the voltage on the second data transmission line LDLb can be output to the sensitive amplifier module 20.

[0074] In some embodiments, see Figure 12 Taking a single precharge control unit as an example, the precharge control circuit 11 includes: a first transistor M6, a second transistor M7, and a third transistor M8. The inverter circuit 12 includes: a fourth transistor M9 and a fifth transistor M10. The switching circuit 13 includes: a sixth transistor M11 and a seventh transistor M12.

[0075] The first channel terminal of the first transistor M6 is coupled to the power supply terminal, and the second channel terminal of the first transistor M6 is coupled to the first data transmission line LDL.

[0076] The first terminal of the second transistor M7 is coupled to the power supply terminal, and the second terminal of the second transistor M7 is coupled to the second data transmission line LDLb.

[0077] The first path terminal of the third transistor M8 is coupled to the first data transmission line LDL, and the second path terminal of the third transistor M8 is coupled to the second data transmission line LDLb.

[0078] The control terminals of the first transistor M6, the second transistor M7, and the third transistor M8 are used to receive selection signals.

[0079] The first path terminal of the fourth transistor M9 is coupled to the power supply terminal VDD.

[0080] The first terminal of the fifth transistor M10 is coupled to the second terminal of the fourth transistor M9, and the second terminal of the fifth transistor M10 is coupled to the reference ground.

[0081] The control terminals of the fourth transistor M9 and the fifth transistor M10 are used to receive selection signals.

[0082] The first terminal of the sixth transistor M11 is coupled to the first data transmission line LDL, and the second terminal of the sixth transistor M11 is coupled to the first input terminal of the sensitive amplifier module 20. That is, it is coupled to the first input terminal of the sensitive amplifier module 20 through DL2.

[0083] The first terminal of the seventh transistor M12 is coupled to the second data transmission line LDLb, and the second terminal of the seventh transistor M12 is coupled to the second input terminal of the sensitive amplifier module 20. That is, it is coupled to the second input terminal of the sensitive amplifier module 20 through DLb2.

[0084] The control terminals of the sixth transistor M11 and the seventh transistor M12 are coupled to the first pass terminal of the fifth transistor M10.

[0085] In some embodiments, the first transistor M6, the second transistor M7, the third transistor M8, the fourth transistor M9, the sixth transistor M11, and the seventh transistor M12 are PMOS transistors. The fifth transistor M10 is an NMOS transistor.

[0086] In some embodiments, see Figure 13 The aforementioned sensitive amplification module 20 includes a comparator and a latch.

[0087] The first input terminal of the comparator is coupled to the first output terminal of the precharge control unit, and the second input terminal of the comparator is coupled to the second output terminal of the precharge control unit. Corresponding to the above circuit structure, the first output terminal of the precharge control unit is the output terminal DL2 of the first data output line, and the second output terminal of the precharge control unit is the output terminal DLb2 of the second data output line. In some embodiments, the first input terminal of the comparator is a non-inverting input terminal, and the second input terminal of the comparator is an inverting input terminal. SAEN is the read enable signal.

[0088] The input of the latch is coupled to the output of the comparator to latch the comparator's output; the comparator's output is used to characterize the data represented by the voltage to be identified stored in the buffer unit, such as... Figure 13 The latch outputs data DO.

[0089] The pre-charge control module 10 performs a pre-charge operation on all target data terminals before the current read cache operation is the first read cache operation.

[0090] like Figure 14 As shown, the precharge control module 10 consists of M precharge control units. The input terminals LDL[M:1] and LDLb[M:1] of the data transmission line of each precharge control unit are connected to the corresponding cache unit in the buffer 200. The output terminals DL2 / DLb2 of the data transmission lines of all precharge control units are connected together and coupled to the sensitive amplification module 20. The selection signal SEL[M:1] controls whether the corresponding precharge control unit is selected. Each precharge control unit contains 7 MOS transistors, M6-M12, of which M10 is an NMOS and the others are PMOS. The body of all NMOS transistors is connected to ground GND, and the body of all PMOS transistors is connected to the power supply VDD. The source of M6 is connected to the power supply VDD, the gate is connected to the selection signal SEL, and the drain is connected to the data line LDL. The source of M7 is connected to the power supply VDD, the gate is connected to the selection signal SEL, and the drain is connected to the data line LDLb. The source of M8 is connected to the data line LDL, the gate is connected to the selection signal SEL, and the drain is connected to the data line LDLb. M9 has its source connected to power supply VDD, its gate connected to the selection signal SEL, and its drain connected to node SELb. M10 has its source connected to ground GND, its gate connected to the selection signal SEL, and its drain connected to node SELb. M11 has its source connected to data line LDL, its gate connected to node SELb, and its drain connected to data line DL2. M12 has its source connected to data line LDLb, its gate connected to node SELb, and its drain connected to data line DLb2. M6-M8 implement pre-charge control for LDL / LDLb, where M8 is an equalizer; during pre-charge, LDL and LDLb are shorted to ensure their pre-charge voltages are the same. M9-M10 form the aforementioned inverting circuit 12, whose output SELb controls the switching circuit 13 composed of M11-M12.

[0091] The sensitive amplification module 20 consists of a comparator and a latch cascaded together, both controlled by the read enable SAEN. The output terminals DL2 / DLb2 of the data transmission line of the precharge control unit are connected to the comparator to compare the voltages of DL2 and DLb2, and the comparison result is sent to the latch for latching.

[0092] For any set of LDL[i] / LDLb[i], when it is not selected (SEL[i] = 0), the control unit maintains its pre-charge state and disconnects it from DL2 / DLb2; when it is selected (SEL[i] = 1), the pre-charge control unit stops pre-charging it and short-circuits it from DL2 / DLb2. It should be noted that, generally speaking, in actual products, the DL2 / DLb2 traces are short and the parasitic capacitance is small, so no additional pre-charging of DL2 / DLb2 is required. If the parasitic capacitance of DL2 / DLb2 is large, additional pre-charge control for DL2 / DLb2 can be considered.

[0093] During each read cache operation, only one set of LDL / LDLb is selected for decoding. (See reference) Figure 9 The operation process is as follows: When reading from the cache, the data in the cache unit will automatically determine the selected LDL or LDLb to discharge. After the discharge, when the voltage difference between LDL and LDLb exceeds a preset value (e.g., 100 millivolts), the read enable SAEN becomes active, and the comparator in the sensitive amplification module 20 starts working. It compares and amplifies the voltage difference between the two, latches it, and outputs it to the external circuit. This completes one cache read operation.

[0094] In this embodiment, the pre-charge control module 10 maintains a pre-charge operation on the data transmission lines coupled to the target data terminals of other cache units each time data is read from the target cache unit. This ensures that when data is read from other cache units in the next read operation, the data transmission lines corresponding to the next cache unit have already been pre-charged during the previous read operation of the target cache unit. Therefore, during the next read operation, the corresponding cache unit can be directly controlled to read data, saving cache read time and improving cache read speed. In other words, the timing of the separate pre-charge operation required for each read operation cycle of a cache unit in related technologies is adjusted. The pre-charge operation for the next cache unit to be read is performed within the read operation cycle of the currently read cache unit. This achieves time reuse by completing the read operation of the currently read cache unit and pre-charging the data transmission lines corresponding to the next cache unit to be read within the same time period, shortening the read operation cycle of the cache unit and thus improving cache read speed.

[0095] See Figure 15 , Figure 15 This is a schematic diagram of an embodiment of the cache read / write circuit provided in this application. The cache read / write circuit 300 includes: a precharge / write control module 30 and a sensitive amplification module 20.

[0096] The data transmission line of the precharge / write control module 30 is coupled to several data terminals of the buffer 200. In response to the current read buffer operation, the precharge / write control module 30 reads the voltage to be identified stored in the corresponding buffer unit from the target data terminal of the buffer 200 through the data transmission line. During the previous read buffer operation, the precharge / write control module 30 maintains the precharge operation of the data transmission line coupled to the target data terminal.

[0097] The sensitive amplification module 20 is coupled to the data transmission line of the precharge / write control module 30. In response to receiving the voltage to be identified from the precharge / write control module 30 via the data transmission line, the sensitive amplification module 20 amplifies and reads the voltage to be identified, obtaining the data represented by the voltage. The precharge / write control module 30 can be multiplexed to write data to the corresponding cache unit of the cache 200 via the data transmission line.

[0098] That is, when the precharge / write control module 30 performs a read cache operation, it follows the technical solution of any embodiment of this application. When the precharge / write control module 30 performs a write cache operation, it reuses itself, terminates the conduction between the precharge / write control module 30 and the sensitive amplification module 20, and uses only the circuit structure of the precharge / write control module 30 to write data to the corresponding cache unit of the cache 200.

[0099] In this embodiment, the precharge / write control module 30 maintains a precharge operation on the data transmission lines coupled to the target data terminals of other cache units each time data is read from the target cache unit. This ensures that when data is read from other cache units in the next read operation, the data transmission lines corresponding to the next cache unit have already been precharged during the previous read operation of the target cache unit. Therefore, during the next read operation, the corresponding cache unit can be directly controlled to read data, saving cache read time and improving cache read speed. In other words, the timing of the separate precharge operation required for each read operation cycle of a cache unit in related technologies is adjusted. The precharge operation for the next cache unit to be read is performed within the read operation cycle of the currently read cache unit. This achieves time reuse by completing the read operation of the currently read cache unit and precharging the data transmission lines corresponding to the next cache unit to be read within the same time period, shortening the read operation cycle of the cache unit and thus improving cache read speed.

[0100] By utilizing a cache read / write circuit, read / write multiplexing is achieved, which can further reduce the area overhead of electronic components and reduce the overall size of non-volatile memory chips.

[0101] In some embodiments, see Figure 16The aforementioned cache read / write circuit 300 further includes a read / write decoding module 40, which outputs a read cache signal or a write cache signal to the precharge / write control module 30 according to a read cache operation or a write cache operation. The precharge / write control module 30 reads the voltage to be identified stored in the corresponding cache unit from the target data terminal of the cache 200 according to the read cache signal, or the precharge / write control module 30 writes data to the corresponding cache unit of the cache 200 according to the write cache signal.

[0102] The read / write decoding module 40 can be configured with several input and output terminals. For example, the input terminals of the read / write decoding module can include data input terminals, selection signal input terminals, and write enable input terminals. The output terminals of the read / write decoding module can have several output terminals, each of which can control a corresponding sub-circuit in the precharge / write control module 30 to realize the read / write function of the buffer. Figure 16 As shown, the data input terminal can input DI to write data, the selection signal input terminal can input SEL[M:1] to select the signal, and the write enable input terminal can input WDEN to enable the write. Several output terminals can output corresponding control signals, such as signal PD_DL[M:1] to control the fourth transistor M9 in the precharge / write control unit as described below; signal PD_DLb[M:1] to control the fifth transistor M10 in the precharge / write control unit as described below; signal PUb_DL[M:1] to control the first transistor M6 in the precharge / write control unit as described below; signal PUb_DLb[M:1] to control the second transistor M7 in the precharge / write control unit as described below; signal EQb[M:1] to control the third transistor M8 in the precharge / write control unit as described below; and signal SELb[M:1] to control the sixth transistor M11 and the seventh transistor M12 in the precharge / write control unit as described below.

[0103] In some embodiments, each cache unit corresponds to a data terminal, and the precharge / write control module 30 includes: a plurality of precharge / write control units, wherein the data transmission line of each precharge / write control unit is coupled to the data terminal of a cache unit and the sensitive amplification module 20.

[0104] In some embodiments, the data end of each cache unit includes a first data line DL1 (not shown) and a second data line DLb1 (not shown), wherein the first data line DL1 and the second data line DLb1 are complementary data lines; the data transmission lines of each precharge / write control unit include a first data transmission line LDL and a second data transmission line LDLb.

[0105] Each precharge / write control unit has a first data transmission line LDL and a second data transmission line LDLb coupled to a first data line DL1 and a second data line DLb1, respectively.

[0106] In some embodiments, the precharge / write control unit, in response to the current read cache operation, outputs the current voltages on the first data line DL1 and the second data line DLb1, which are the voltages to be identified, to the sensitive amplification module 20 via the first data transmission line LDL and the second data transmission line LDLb, respectively.

[0107] In some embodiments, each precharge / write control unit, in response to the current write cache operation, inputs the target voltage corresponding to the data to be written to the first data line DL1 and the second data line DLb1 through the first data transmission line LDL and the second data transmission line LDLb, respectively, so that the corresponding cache unit stores the target voltage.

[0108] In some embodiments, see Figure 17 Each precharge / write control unit includes a precharge / write control circuit 31 and a switching circuit 32.

[0109] The precharge / write control circuit 31 is coupled to the first data line DL1 and the second data line DLb1 via the first data transmission line LDL and the second data transmission line LDLb, respectively, to maintain the precharge operation of the first data transmission line LDL and the second data transmission line LDLb during the previous read cache operation.

[0110] The control terminal of the switch circuit 32 is coupled to the read / write decoding module, the first terminal of the switch circuit 32 is coupled to the first data transmission line LDL, the second terminal of the switch circuit 32 is coupled to the second data transmission line LDLb, and the third and fourth terminals of the switch circuit 32 are coupled to the sensitive amplification module 20.

[0111] During the current read buffer operation, in response to the first control signal of the read / write decoding module, the first and third terminals of the switch circuit 32 are turned on, and the second and fourth terminals of the switch circuit 32 are turned on, respectively outputting the current voltage on the first data transmission line LDL and the second data transmission line LDLb as the voltage to be identified to the sensitive amplification module 20.

[0112] During the current write cache operation, the switching circuit 32 responds to the first control signal of the read / write decoding module, with the first and third terminals cut off, and the second and fourth terminals cut off. The precharge / write control circuit 31 responds to the second control signal of the read / write decoding module, and inputs the target voltage corresponding to the data to be written to the first data transmission line LDL and the second data transmission line LDLb respectively, so that the corresponding cache unit stores the target voltage.

[0113] In some embodiments, see Figure 18Taking a single precharge / write control unit as an example, the precharge / write control circuit 31 includes: a first transistor M6, a second transistor M7, a third transistor M8, a fourth transistor M9, and a fifth transistor M10. The switching circuit 32 includes: a sixth transistor M11 and a seventh transistor M12. The first transistor M6, second transistor M7, third transistor M8, sixth transistor M11, and seventh transistor M12 are PMOS transistors. The fourth transistor M9 and fifth transistor M10 are NMOS transistors.

[0114] The first channel terminal of the first transistor M6 is coupled to the power supply terminal, and the second channel terminal of the first transistor M6 is coupled to the first data transmission line LDL.

[0115] The first terminal of the second transistor M7 is coupled to the power supply terminal, and the second terminal of the second transistor M7 is coupled to the second data transmission line LDLb.

[0116] The first path terminal of the third transistor M8 is coupled to the first data transmission line LDL, and the second path terminal of the third transistor M8 is coupled to the second data transmission line LDLb.

[0117] The first terminal of the fourth transistor M9 is coupled to the first terminal of the third transistor M8, and the second terminal of the fourth transistor M9 is coupled to the reference ground.

[0118] The first path terminal of the fifth transistor M10 is coupled to the second path terminal of the third transistor M8, and the second path terminal of the fifth transistor M10 is coupled to the reference ground; wherein, the control terminals of the first transistor M6, the second transistor M7, the third transistor M8, the fourth transistor M9 and the fifth transistor M10 are respectively coupled to the read / write decoding module for receiving corresponding control signals.

[0119] The first terminal of the sixth transistor M11 is coupled to the first data transmission line LDL, and the second terminal of the sixth transistor M11 is coupled to the first input terminal of the sensitive amplifier module 20. That is, the second terminal of the sixth transistor M11 is coupled to the first input terminal of the sensitive amplifier module 20 through DL2.

[0120] The first terminal of the seventh transistor M12 is coupled to the second data transmission line LDLb, and the second terminal of the seventh transistor M12 is coupled to the second input terminal of the sensitive amplifier module 20. That is, the second terminal of the seventh transistor M12 is coupled to the second input terminal of the sensitive amplifier module 20 through DLb2.

[0121] The control terminals of the sixth transistor M11 and the seventh transistor M12 are coupled to the read / write decoding module.

[0122] This implementation scheme combines the cache read and cache write circuits together, and reuses some of the MOS transistors in the precharge control module 10 as write drive transistors.

[0123] like Figure 19 As shown, the precharge / write control module 30 consists of M precharge / write control units. The input terminals LDL[M:1] and LDLb[M:1] of the data transmission line of each precharge / write control unit are connected to the corresponding cache unit in the cache 200. The output terminals DL2 / DLb2 of the data transmission lines of all precharge / write control units are connected together and coupled to the sensitive amplification module 20. The selection signal SELb[M:1] controls whether the corresponding precharge / write control unit is selected. The signals PD_DL[M:1], PUb_DL[M:1], PD_DLb[M:1], PUb_DLb[M:1], and EQb[M:1] control the corresponding LDL / LDLb, including precharge during cache read and drive during cache write. Each control unit contains 7 MOS transistors (M6-M12), of which M9 and M10 are NMOS transistors, and the others are PMOS transistors. The body of all NMOS transistors is connected to ground (GND), and the body of all PMOS transistors is connected to the power supply (VDD). M6: Source connected to power supply VDD, gate connected to signal PUB_DL, drain connected to data line LDL. M7: Source connected to power supply VDD, gate connected to signal PUB_DLb, drain connected to data line LDLb. M8: Source connected to data line LDL, gate connected to signal EQb, drain connected to data line LDLb. M9: Source connected to ground GND, gate connected to PD_DL, drain connected to data line LDL. M10: Source connected to ground GND, gate connected to PD_DLb, drain connected to data line LDLb. M11: Source connected to data line LDL, gate connected to node SELb, drain connected to data line DL. M12: Source connected to data line LDLb, gate connected to node SELb, drain connected to data line DLb.

[0124] M6-M10 control the read precharge and write drive of LDL / LDLb, while M11-M12 act as switching transistors to control read amplification. 1) During read precharge, M6-M8 are on and M9-M10 are off, thus achieving balanced precharge of LDL / LDLb; during other read stages, M6-M10 are off. 2) During write drive, M11-M12 are always off. For unselected control units, all M6-M10 are off; for selected control units, M8 is off. The switching status of M6, M7, M9, and M10 is determined by the write data DI.

[0125] The aforementioned PD_DL[M:1], PUb_DL[M:1], PD_DLb[M:1], PUb_DLb[M:1], EQb[M:1], and SELb[M:1] signals are generated by the read / write decoding logic module. The module's inputs include the write enable WDEN, the selection signal SEL[M:1], and the write data DI. The input / output truth table is as follows: Figure 20 As shown.

[0126] The sensitive amplifier module consists of a comparator and a latch cascaded together, both controlled by the read enable SAEN. The input data lines DL2 / DLb2 are connected to the comparator to compare the voltages of DL2 and DLb2, and the comparison result is sent to the latch for storage.

[0127] In some embodiments, combined with Figure 20 The truth table for the read / write logic decoding is explained below:

[0128] like Figure 20 The first line: When SEL[i] is 0 and WDEN is 0, it means that no cache unit is selected, and a precharge operation is required. Therefore, PD_DL[i] and PD_DLb[i] are 0, controlling M9 and M10 to be off; PUb_DL[i], PUb_DLb[i] and EQb[i] are 0, controlling M6, M7 and M8 to be on; SELb[i] is 1, and M11-M12 are off, precharging the data output line of the precharge / write control unit.

[0129] The second line: When SEL[i] is 1 and WDEN is 0, it means that the i-th cache unit is selected. At this time, the i-th cache unit needs to be read from the cache. Therefore, PD_DL[i] and PD_DLb[i] are 0, which controls M9 and M10 to be turned off. PUb_DL[i], PUb_DLb[i] and EQb[i] are 1, which turns off M6, M7 and M8. SELb[i] is 0, which controls M11-M12 to be turned on. The output voltage is sent to the comparator for amplification and reading.

[0130] The third line: When SEL[i] is 0 and WDEN is 1, it means that the i-th cache unit has not yet performed a write cache operation. Therefore, PD_DL[i] and PD_DLb[i] are 0, controlling M9 and M10 to be closed, PUb_DL[i], PUb_DLb[i] and EQb[i] are 1, so that M6, M7 and M8 are closed, and SELb[i] is 1, controlling M11-M12 to be closed, so as to maintain the state of the i-th cache unit.

[0131] The fourth line: When SEL[i] is 1, WDEN is 1, and DI is 0, it indicates that the i-th cache unit is selected, and the i-th cache unit needs to perform a write 0 operation. Therefore, PD_DL[i] is 1 to control M9 to be on, PD_DLb[i] is 0 to control M10 to be off, PUb_DL[i] is 1 to control M6 to be off, PUb_DLb[i] is 0 to control M7 to be on, and EQb[i] is 1 to control M8 to be off. SELb[i] is 1 to control M11-M12 to be off. Thus, the write 0 operation is achieved by pulling down the voltage on the LDL line through M9 and pulling up the voltage on the LDLb line through M7.

[0132] Line 5: When SEL[i] is 1, WDEN is 1, and DI is 1, it means that the i-th cache unit is selected, and the i-th cache unit needs to perform a write 1 operation. Therefore, PD_DL[i] is 0 to control M9 to be off, PD_DLb[i] is 1 to control M10 to be on, PUb_DL[i] is 0 to control M6 to be on, PUb_DLb[i] is 1 to control M7 to be off, and EQb[i] is 1 to control M8 to be off. SELb[i] is 1 to control M11-M12 to be off. Then, the voltage on the LDLb line is pulled down by M10, and the voltage on the LDL line is pulled up by M6 to achieve the write 1 operation.

[0133] See Figure 21 , Figure 21 This is a schematic flowchart of an embodiment of the cache reading method provided in this application. Applied to the aforementioned cache reading circuit 100, which includes a pre-charge control module 10 and a sensitive amplification module 20, the cache reading method includes:

[0134] Step 101: In response to the current read cache operation, the precharge control module reads the voltage to be identified stored in the corresponding cache unit from the target data terminal of the cache through the data transmission line; wherein, the precharge control module maintains the precharge operation of the data transmission line coupled to the target data terminal during the previous read cache operation.

[0135] Step 102: In response to receiving the voltage to be identified sent by the precharge control module through the data transmission line, the voltage to be identified is amplified and read out to obtain the data represented by the voltage to be identified.

[0136] The specific cache reading method in this embodiment can be found in any of the above embodiments, and will not be repeated here.

[0137] In this embodiment, the pre-charge control module maintains a pre-charge operation on the data transmission lines coupled to the target data terminals of other cache units each time data is read from the target cache unit. This ensures that when data is read from other cache units in the next read operation, the data transmission lines corresponding to the next cache unit have already been pre-charged during the previous read operation of the target cache unit. Therefore, the corresponding cache unit can be directly controlled to read data during the next read operation, saving cache read time and improving cache read speed. In other words, the timing of the separate pre-charge operation required for each read operation cycle of a cache unit in related technologies is adjusted. The pre-charge operation for the next cache unit to be read is performed within the read operation cycle of the currently read cache unit. This achieves time reuse by completing the read operation of the currently read cache unit and pre-charging the data transmission lines corresponding to the next cache unit to be read within the same time period, shortening the read operation cycle of the cache unit and thus improving cache read speed.

[0138] Furthermore, by utilizing cache read / write circuitry, read / write multiplexing is achieved, which can further reduce the area overhead of electronic components and reduce the overall size of non-volatile memory chips.

[0139] In this application, a non-volatile memory chip is also provided, including the cache read circuit 100 described above.

[0140] In this application, a non-volatile memory chip is also provided, including the cache read / write circuit 300 described above. In some embodiments, the non-volatile memory chip may be a NAND flash memory.

[0141] In summary, the cache read circuit 100 and method, cache read / write circuit 300, and non-volatile memory chip provided in this application, with the precharge control module 10 maintaining a precharge operation on the data transmission lines coupled to the target data terminals of other cache units each time data is read from the target cache unit. This ensures that when data is read from other cache units in the next read operation, the data transmission lines corresponding to the next cache unit have already been precharged during the previous read operation of the target cache unit. Therefore, during the next read operation, the corresponding cache unit can be directly controlled to read data, saving cache read time and thus improving cache read speed. Specifically, by adjusting the timing of the separate precharge operation required for each read operation cycle of a cache unit in related technologies, the precharge operation for the next cache unit to be read is performed within the read operation cycle of the currently read cache unit. This achieves time reuse by completing the read operation of the currently read cache unit and precharging the data transmission lines corresponding to the next cache unit to be read within the same time period, shortening the read operation cycle of the cache unit and thus improving cache read speed.

[0142] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0143] If the integrated units in the other embodiments described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0144] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A cache read circuit, comprising: The cache reading circuit comprises: a pre-charge control module, a data transmission line of the pre-charge control module is coupled with a plurality of data terminals of a cache, and the pre-charge control module reads out a to-be-identified voltage stored in a corresponding cache unit from a target data terminal of the cache through the data transmission line in response to a current cache reading operation; wherein the pre-charge control module maintains a pre-charge operation on the data transmission line coupled with the target data terminal during a previous cache reading operation; a sensitive amplification module, which is coupled with the data transmission line of the pre-charge control module, and the sensitive amplification module performs an amplification reading operation on the to-be-identified voltage in response to receiving the to-be-identified voltage sent by the pre-charge control module through the data transmission line, and obtains data represented by the to-be-identified voltage.

2. The cache read circuit of claim 1, wherein, Each of the cache units corresponds to a data terminal, and the pre-charge control module comprises a plurality of pre-charge control units, and a data transmission line of each pre-charge control unit is coupled with a data terminal of a cache unit and the sensitive amplification module.

3. The cache read circuit of claim 2, wherein, The data terminal of each of the cache units comprises a first data line and a second data line, wherein the first data line and the second data line are complementary data lines; and the data transmission line of each pre-charge control unit comprises a first data transmission line and a second data transmission line. The first data transmission line and the second data transmission line of each of the pre-charge control units are coupled with the first data line and the second data line respectively, and the pre-charge control unit outputs a current voltage on the first data line and the second data line as the to-be-identified voltage to the sensitive amplification module through the first data transmission line and the second data transmission line respectively in response to a current cache reading operation.

4. The cache read circuit of claim 3, wherein, Each of the pre-charge control units comprises: a pre-charge control circuit, which is coupled with the first data line and the second data line through the first data transmission line and the second data transmission line respectively, and is used for maintaining a pre-charge operation on the first data transmission line and the second data transmission line during a previous cache reading operation; an inverting circuit, which is coupled with the pre-charge control circuit and is used for outputting a corresponding control signal according to the pre-charge control circuit; a switch circuit, a control end of the switch circuit is coupled with an output end of the inverting circuit, a first end of the switch circuit is coupled with the first data transmission line, a second end of the switch circuit is coupled with the second data transmission line, and a third end and a fourth end of the switch circuit are coupled with the sensitive amplification module; During a current cache reading operation, the switch circuit outputs the current voltage on the first data transmission line and the second data transmission line as the to-be-identified voltage to the sensitive amplification module through the first end and the third end and the second end and the fourth end of the switch circuit respectively in response to the control signal output by the inverting circuit.

5. The cache read circuit of any of claims 1-4, wherein, The pre-charge control module performs a pre-charge operation on the data transmission line coupled with all the target data terminals before the current cache reading operation is a first cache reading operation.

6. A cache read-write circuit, comprising: The cache reading and writing circuit comprises: a pre-charge / write control module, a data transmission line of the pre-charge / write control module is coupled with a plurality of data terminals of the buffer, and the pre-charge / write control module reads out a to-be-identified voltage stored in a corresponding buffer cell from a target data terminal of the buffer through the data transmission line in response to a current read buffer operation; a sensitive amplification module, which is coupled with the data transmission line of the pre-charge / write control module, and the sensitive amplification module performs an amplification readout operation on the to-be-identified voltage received from the pre-charge / write control module through the data transmission line to obtain data represented by the to-be-identified voltage; wherein the pre-charge / write control module can be multiplexed to write data to the corresponding buffer cell of the buffer through the data transmission line.

7. The cache read-write circuit of claim 6, wherein, The buffer read-write circuit further comprises: a read-write decoding module, which is configured to output a read buffer signal or a write buffer signal to the pre-charge / write control module according to a read buffer operation or a write buffer operation; the pre-charge / write control module reads out the to-be-identified voltage stored in the corresponding buffer cell from the target data terminal of the buffer according to the read buffer signal, or the pre-charge / write control module writes data to the corresponding buffer cell of the buffer according to the write buffer signal.

8. The cache read-write circuit of claim 7, wherein, Each of the buffer cells corresponds to a data terminal, and the pre-charge / write control module comprises a plurality of pre-charge / write control units, and a data transmission line of each pre-charge / write control unit is coupled with a data terminal of a buffer cell and the sensitive amplification module.

9. The cache read-write circuit of claim 8, wherein, The data terminal of each of the buffer cells comprises a first data line and a second data line, wherein the first data line and the second data line are complementary data lines; and the data transmission line of each pre-charge / write control unit comprises a first data transmission line and a second data transmission line. The first data transmission line and the second data transmission line of each pre-charge / write control unit are coupled with the first data line and the second data line, respectively, and output a current voltage on the first data line and the second data line as the to-be-identified voltage to the sensitive amplification module through the first data transmission line and the second data transmission line, respectively, in response to a current read buffer operation; or, each pre-charge / write control unit inputs a target voltage corresponding to to-be-written data to the first data line and the second data line through the first data transmission line and the second data transmission line, respectively, in response to a current write buffer operation, so that the corresponding buffer cell stores the target voltage.

10. The cache read-write circuit of claim 9, wherein, Each of the pre-charge / write control units comprises: a pre-charge / write control circuit, which is coupled with the first data line and the second data line through the first data transmission line and the second data transmission line, respectively, and is configured to maintain a pre-charge operation on the first data transmission line and the second data transmission line during a last read buffer operation. A switch circuit, a control end of the switch circuit is coupled with the read-write decoding module, a first end of the switch circuit is coupled with the first data transmission line, a second end of the switch circuit is coupled with the second data transmission line, a third end and a fourth end of the switch circuit are coupled with the sensitive amplification module; During the current read cache operation, the switch circuit is responsive to the first control signal of the read-write decoding module, the first end and the third end of the switch circuit are turned on, the second end and the fourth end of the switch circuit are turned on, and the current voltage on the first data transmission line and the second data transmission line as the to-be-identified voltage is respectively output to the sensitive amplification module; During the current write cache operation, the first end and the third end of the switch circuit are turned off in response to the first control signal of the read-write decoding module, the second end and the fourth end of the switch circuit are turned off, and the pre-charge / write-in control circuit is responsive to the second control signal of the read-write decoding module to respectively input the target voltage corresponding to the to-be-written data to the first data transmission line and the second data transmission line, so that the corresponding cache unit stores the target voltage.

11. A nonvolatile memory chip, characterized by comprising: The cache read circuit comprises the cache read circuit according to any one of claims 1-5, or the cache read-write circuit according to any one of claims 6-10.

12. A method of caching a read, the method comprising: The cache read circuit comprises a pre-charge control module and a sensitive amplification module, and the cache read method comprises: The pre-charge control module is responsive to the current read cache operation to read out the to-be-identified voltage stored in the corresponding cache unit from the target data end of the cache through the data transmission line; wherein the pre-charge control module maintains the pre-charge operation on the data transmission line coupled with the target data end during the last read cache operation; The sensitive amplification module is responsive to receiving the to-be-identified voltage sent by the pre-charge control module through the data transmission line to perform amplification readout operation on the to-be-identified voltage, and obtain the data represented by the to-be-identified voltage.

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