Apparatus and method for reference read techniques for threshold selector device memory

Abstract

The invention discloses an apparatus comprising a memory array having a first memory cell comprising a first two-terminal element having first and second threshold voltages, and a second memory cell comprising a second two-terminal element having second and third threshold voltages, a second memory cell including a second two-terminal element having third and fourth threshold voltages; and a control circuit coupled to the memory array. The control circuit is configured to cause the first two-terminal element to have a first threshold voltage and the second two-terminal element to have the third threshold voltage or the fourth threshold voltage, apply a third voltage signal that increases at a first ramp rate to the first memory cell and the second memory cell, it is determined that the first memory cell is switched from a non-conductive state to a conductive state, and the second memory cell is read using the third voltage signal at a first predetermined delay time after the first memory cell is switched from the non-conductive state to the conductive state.

Description

Background Technology

[0001] Memory is widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, non-mobile computing devices, and data servers. Memory can be non-volatile or volatile. Non-volatile memory allows information to be stored and retained even when it is not connected to a power source (e.g., a battery).

[0002] An example of nonvolatile memory is a memory cell that includes a resistive switching memory element (e.g., a magnetic tunnel junction) coupled in series with a threshold selector device (e.g., a bidirectional threshold switch comprising a chalcogenide material or other similar threshold selector device).

[0003] Alternative non-volatile memory technologies eliminate the need for resistor-switched memory elements and use memory cells that include both memory elements and selector devices. For example, the threshold selector device can be programmed with two different resistors (e.g., a high-resistance state and a low-resistance state) to store information.

[0004] Emerging memory technologies also use memory cells that include both threshold selector devices as memory elements and selector devices, but use the threshold voltage difference instead of the resistance difference of the threshold selector device to store the memory state.

[0005] For example, a memory cell that includes a threshold selector device (such as a bidirectional threshold switch or other similar threshold selector device) can be programmed to have two different threshold voltages (e.g., a high threshold voltage and a low threshold voltage) to store information.

[0006] For simplicity, the remaining discussion will use the term "threshold selector memory cell" to describe a memory cell that includes both a threshold selector device as a memory element and a selector device, and uses the threshold voltage difference of the threshold selector device to store data.

[0007] Although memory systems that include threshold selector memory cells are promising, many design and process challenges remain. Attached Figure Description

[0008] Figures 1A to 1H Various implementation schemes of the memory system are described.

[0009] Figure 2A A partial implementation scheme of a three-dimensional memory array is described.

[0010] Figure 2B Depicting Figure 2A An implementation scheme for the memory cells of a three-dimensional memory array.

[0011] Figure 2C Depicting Figure 2B Exemplary current-voltage characteristics of a threshold selector device.

[0012] Figure 3A and Figure 3B An implementation scheme for a crosspoint memory array is described.

[0013] Figure 4A It is a simplified diagram of the threshold voltage relative to time of the threshold selector device, and the read and write voltages applied across the threshold selector memory cell.

[0014] Figure 4B The relative time of the threshold selector memory cell voltage for the boundary read technique is described.

[0015] Figure 4C This is a diagram depicting the example SET and RESET threshold voltage distribution and read voltage distribution for a group of threshold selector memory cells.

[0016] Figure 4D The original SET threshold voltage distribution, the drifted SET threshold voltage distribution, and the driftless RESET threshold voltage distribution of the threshold selector memory cell are depicted.

[0017] Figure 5A This is a flowchart of an implementation scheme for a threshold voltage reference reading technique based on this technology.

[0018] Figure 5B It is a diagram depicting the threshold voltage distribution of the example reference memory cell SET, the threshold voltage distribution of the example data memory cell SET, and the threshold voltage distribution of the example data memory cell RESET.

[0019] Figure 5C Depicting reading voltages with two different ramps. Figure 5B Example threshold voltage distribution.

[0020] Figure 6A This is a simplified diagram of the implementation scheme of the threshold voltage reference reading system.

[0021] Figure 6B It is a description Figure 6A The example threshold voltage reference reading system is illustrated with a diagram of an example signal.

[0022] Figure 6C This is a simplified diagram of an alternative implementation of the threshold voltage reference reading system.

[0023] Figures 6D1 to 6D2 They are Figure 6C The example threshold voltage reference readout system is shown in a simplified diagram of the threshold voltage and readout voltage distribution during both the fast and slow readout processes.

[0024] Figure 7 This is a flowchart of an implementation scheme for a threshold voltage reference reading technique based on this technology. Detailed Implementation

[0025] A fundamental material property of threshold selector devices (such as bidirectional threshold switches) is that the threshold voltage of such devices drifts over time after being written to. Therefore, the memory read window of a threshold selector memory cell is limited by this drift characteristic. Consequently, developing highly reliable and low-latency memory devices using threshold selector memory cells is very challenging.

[0026] A technique for reading a threshold selector memory cell by using a reference memory cell to track and mitigate threshold voltage drift in a corresponding data memory cell is described. In an embodiment, the reference memory cell and the corresponding data memory cell each include a threshold selector device having a first threshold voltage and a second threshold voltage.

[0027] In this implementation, whenever data is written to the corresponding data memory cell, a predetermined value is written to the reference memory cell. After the write operation, the threshold voltages of the reference memory cell and the corresponding data memory cell drift over time. In this implementation, the drifted threshold voltage of the reference memory cell is detected and used to eliminate the drift component of the corresponding data memory cell.

[0028] Figure 1A An embodiment of a memory system 100 and a host 102 is depicted. The memory system 100 may include a non-volatile storage system that is connected to the host 102 (e.g., a mobile computing device or a server) via an interface. In some cases, the memory system 100 may be embedded within the host 102. As an example, the memory system 100 may be a memory card, a solid-state drive (SSD) (such as a high-density MLC SSD (e.g., 2-bit / cell or 3-bit / cell) or a high-performance SLC SSD), or a hybrid HDD / SSD drive.

[0029] As shown in the figure, the memory system 100 includes a memory chip controller 104 and a memory chip 106. The memory chip 106 may include volatile memory and / or non-volatile memory. Although a single memory chip is depicted, the memory system 100 may include more than one memory chip. The memory chip controller 104 may receive data and commands from the host 102 and provide memory chip data to the host 102.

[0030] The memory chip controller 104 may include one or more of the following: control circuitry, a state machine, a page register, an SRAM, a decoder, a sense amplifier, read / write circuitry, and / or a controller, or any combination thereof, for controlling the operation of the memory chip 106. One or more of the control circuitry, state machine, page register, SRAM, decoder, sense amplifier, read / write circuitry, and / or controller used to control the operation of the memory chip may be referred to as management or control circuitry. Management or control circuitry may facilitate operations of one or more memory arrays, including format, erase, program, or read operations.

[0031] In some embodiments, management or control circuitry (or a portion thereof) for facilitating the operation of one or more memory arrays may be integrated within memory chip 106. Memory chip controller 104 and memory chip 106 may be disposed on a single integrated circuit or on a single die. In other embodiments, memory chip controller 104 and memory chip 106 may be disposed on different integrated circuits. In some cases, memory chip controller 104 and memory chip 106 may be integrated on a system board, logic board, or PCB.

[0032] The memory chip 106 includes a memory core control circuit 108 and a memory core 110. The memory core control circuit 108 may include logic for controlling the selection of memory blocks (or arrays) within the memory core 110, controlling the generation of voltage references for biasing a particular memory array to a read or write state, and generating row and column addresses.

[0033] The memory core 110 may include a two-dimensional array of one or more memory cells and / or a three-dimensional array of one or more memory cells. In one embodiment, the memory core may include rewritable memory cells, once-programmable memory cells, and / or multiple-programmable memory cells, or any combination thereof.

[0034] In one embodiment, the memory core control circuit 108 and the memory core 110 may be arranged on a single integrated circuit. In other embodiments, the memory core control circuit 108 (or a portion thereof) and the memory core 110 may be arranged on different integrated circuits.

[0035] A memory operation can be initiated when the host 102 sends an instruction to the memory chip controller 104, indicating that the host 102 wants to read data from the memory system 100 or write data to the memory system 100. In the case of a write (or programming) operation, the host 102 can send a write command and the data to be written to the memory chip controller 104.

[0036] The memory chip controller 104 can cache data to be written and can generate error correction code (ECC) data corresponding to the data to be written. ECC data, which enables the detection and / or correction of data errors occurring during transmission or storage, can be written to the memory core 110 or stored in non-volatile memory within the memory chip controller 104. In one embodiment, ECC data and data error correction are generated by circuitry within the memory chip controller 104.

[0037] The memory chip controller 104 controls the operation of the memory chip 106. In one example, before issuing a write operation to the memory chip 106, the memory chip controller 104 may check the status register to ensure that the memory chip 106 can accept the data to be written.

[0038] In another example, before issuing a read operation to memory chip 106, memory chip controller 104 may pre-read overhead information associated with the data to be read. The overhead information may include ECC data associated with the data to be read or a redirection pointer to a new memory location within memory chip 106 where the requested data is read.

[0039] Once the memory chip controller 104 initiates a read or write operation, the memory core control circuit 108 can generate appropriate bias voltages and / or currents for the word lines and bit lines within the memory core 110, and generate appropriate memory block, row, and column addresses.

[0040] Figure 1B An embodiment of a memory core control circuit 108 is illustrated. In one embodiment, the memory core control circuit 108 includes an address decoder 120, a voltage generator 122 for selecting control lines, and a voltage generator 124 for unselected control lines. Control lines may include word lines, bit lines, or a combination of word lines and bit lines. Selected control lines may include selected word lines or selected bit lines for placing memory cells in a selected state. Unselected control lines may include unselected word lines or unselected bit lines for placing memory cells in an unselected state.

[0041] The voltage generator (or voltage regulator) 122 for selected control lines may include one or more voltage generators for generating voltages for the selected control lines. The voltage generator 124 for unselected control lines may include one or more voltage generators for generating voltages for the unselected control lines. The address decoder 120 can generate memory block addresses, as well as row addresses and column addresses for a specific memory block.

[0042] Figures 1C to 1FOne embodiment of a memory core organization is depicted, comprising a memory core 110 having multiple memory compartments, and each memory compartment having multiple memory blocks. Although one memory core organization is disclosed, wherein a memory compartment comprises a memory block, and a memory block comprises a set of memory cells, other organizations or groupings may also be used with the techniques described herein.

[0043] Figure 1C Depicting Figure 1A An embodiment of memory core 110 is described. As depicted, memory core 110 includes memory compartments 130 and 132. In some embodiments, the number of memory compartments in each memory core may vary for different specific implementations. For example, a memory core may include only a single memory compartment or multiple memory compartments (e.g., 16 memory compartments, 256 memory compartments, etc.).

[0044] Figure 1D Depicting Figure 1C One embodiment of memory compartment 130. As depicted, memory compartment 130 includes memory blocks 140-144 and read / write circuitry 150. In some embodiments, the number of memory blocks in each memory compartment may vary depending on the specific implementation. For example, a memory compartment may include one or more memory blocks (e.g., 32 memory blocks per memory compartment).

[0045] The read / write circuitry 150 includes circuitry for reading and writing memory cells within memory blocks 140-144. As depicted, the read / write circuitry 150 can be shared among multiple memory blocks within a memory compartment. This allows for a reduction in chip area because a single set of read / write circuitry 150 can be used to support multiple memory blocks. However, in some embodiments, only a single memory block can be electrically coupled to the read / write circuitry 150 at a given time to avoid signal interference.

[0046] In some implementations, the read / write circuitry 150 can be used to write one or more pages of data to memory blocks 140-144 (or a subset of the memory blocks). Memory cells within memory blocks 140-144 may allow direct page rewriting (i.e., data representing a page or a portion of a page can be written to memory blocks 140-144 without requiring an erase or reset operation on the memory cell before the data is written).

[0047] Figure 1E Depicting Figure 1DOne embodiment of memory block 140. As depicted, memory block 140 includes memory array 160, row decoder 162, and column decoder 164. Memory array 160 may include contiguous groups of memory cells having continuous word lines and bit lines. Memory array 160 may include one or more layers of memory cells and may include two-dimensional and / or three-dimensional memory arrays.

[0048] Row decoder 162 decodes the row address and selects a specific word line in memory array 160 when appropriate (e.g., when reading or writing a memory cell in memory array 160). Column decoder 164 decodes the column address and selects a specific set of bit lines in memory array 160 to be electrically coupled to read / write circuitry, such as... Figure 1D The read / write circuitry 150. In one embodiment, the number of word lines per memory layer is 4K, the number of bit lines per memory layer is 1K, and the number of memory layers is 4, providing a memory array 160 containing 16M memory cells. Other numbers of word lines per layer, bit lines per layer, and number of layers can be used.

[0049] Figure 1F An embodiment of memory compartment 170 is described. Memory compartment 170 is... Figure 1D Examples of alternative implementations of memory compartment 130. In some implementations, the row decoder, column decoder, and read / write circuitry may be separate or shared between memory arrays. As depicted, row decoder 172 is shared between memory arrays 174 and 176 because row decoder 172 controls word lines in both memory arrays 174 and 176 (i.e., word lines driven by row decoder 172 are shared).

[0050] Row decoders 178 and 172 can be separate, such that even-number bits in memory array 174 are driven by row decoder 178, and odd-number bits in memory array 174 are driven by row decoder 172. Column decoders 180 and 182 can be separate, such that even-number bits in memory array 174 are controlled by column decoder 182, and odd-number bits in memory array 174 are driven by column decoder 180.

[0051] The selection line controlled by column decoder 180 can be electrically coupled to read / write circuit 184. The selection line controlled by column decoder 182 can be electrically coupled to read / write circuit 186. Separating the read / write circuit into read / write circuits 184 and 186 when the column decoder is decoupled allows for a more efficient layout of the memory compartments.

[0052] Row decoders 188 and 172 can be separate, such that even-number bits in memory array 176 are driven by row decoder 188, and odd-number bits in memory array 176 are driven by row decoder 172. Column decoders 190 and 192 can be separate, such that even-number bits in memory array 176 are controlled by column decoder 192, and odd-number bits in memory array 176 are driven by column decoder 190.

[0053] The selection line controlled by column decoder 190 is electrically coupled to read / write circuitry 184. The selection line controlled by column decoder 192 is electrically coupled to read / write circuitry 186. Separating the read / write circuitry into read / write circuitry 184 and 186 when the column decoder is decoupled allows for a more efficient layout of the memory compartments.

[0054] Figure 1G Depicting the corresponding Figure 1F A schematic diagram of an embodiment of memory compartment 170 (including word lines and bit lines) is shown. As depicted, word lines WL1, WL3, and WL5 are shared between memory arrays 174 and 176 and are... Figure 1F The row decoder 172 controls the word lines WL0, WL2, WL4, and WL6, which are driven from the left side of the memory array 174 and controlled by... Figure 1F The row decoder 178 is controlled by [the controller / system]. Word lines WL14, WL16, WL18, and WL20 are driven from the right side of memory array 176 and are [controlled / managed / controlled]. Figure 1F The line decoder 188 is controlled.

[0055] Bit lines BL0, BL2, BL4, and BL6 are driven from the bottom of memory array 174 and are supplied by... Figure 1F The column decoder 182 is controlled. Bit lines BL1, BL3, and BL5 are driven from the top of the memory array 174 and are controlled by... Figure 1F The column decoder 180 is controlled. Bit lines BL7, BL9, BL11, and BL13 are driven from the bottom of the memory array 176 and are controlled by... Figure 1F The column decoder 192 is controlled. Bit lines BL8, BL10, and BL12 are driven from the top of the memory array 176 and are controlled by... Figure 1F The column decoder 190 is controlled.

[0056] In one embodiment, memory arrays 174 and 176 may include memory layers oriented in a plane horizontal to the support substrate. In another embodiment, memory arrays 174 and 176 may include memory layers oriented in a plane vertical to the support substrate (i.e., the vertical plane is substantially perpendicular to the support substrate). In this case, the bit lines of the memory array may include substantially vertical bit lines.

[0057] Figure 1H An embodiment corresponding to a schematic diagram of a memory compartment arrangement (including word lines and bit lines) is depicted, wherein word lines and bit lines are shared between memory blocks, and row decoders and column decoders are separate. Sharing word lines and / or bit lines helps to reduce layout area because two memory arrays can be supported using a single row decoder and / or column decoder.

[0058] As depicted, word lines WL1, WL3, and WL5 are shared between memory arrays 200 and 202. Bit lines BL1, BL3, and BL5 are shared between memory arrays 200 and 204. Word lines WL8, WL10, and WL12 are shared between memory arrays 204 and 206. Bit lines BL8, BL10, and BL12 are shared between memory arrays 202 and 206.

[0059] The line decoders are separate, such that word lines WL0, WL2, WL4, and WL6 are driven from the left side of memory array 200, and word lines WL1, WL3, and WL5 are driven from the right side of memory array 200. Similarly, word lines WL7, WL9, WL11, and WL13 are driven from the left side of memory array 204, and word lines WL8, WL10, and WL12 are driven from the right side of memory array 204.

[0060] The column decoders are separate, such that bit lines BL0, BL2, BL4, and BL6 are driven from the bottom of memory array 200, and bit lines BL1, BL3, and BL5 are driven from the top of memory array 200. Similarly, bit lines BL7, BL9, BL11, and BL13 are driven from the bottom of memory array 202, and bit lines BL8, BL10, and BL12 are driven from the top of memory array 202. Separating the row and / or column decoders also helps alleviate layout constraints (e.g., the column decoder spacing can be reduced by a factor of 2 because the separate column decoders only need to drive every other bit line instead of every single bit line).

[0061] Figure 2A An embodiment of a portion of a monolithic three-dimensional memory array 210 is depicted, comprising a first memory layer 212 and a second memory layer 214 situated above the first memory layer 212. The memory array 210 is... Figure 1E An example of a specific implementation of the memory array 160 is shown. Word lines 216 and 218 are arranged along a first direction, and bit line 220 is arranged along a second direction perpendicular to the first direction. As depicted, the upper conductor of the first memory layer 212 can be used as the lower conductor of the second memory layer 214. In a memory array with additional layers of memory cells, corresponding additional layers for bit lines and word lines will exist.

[0062] Memory array 210 includes memory cells 222. In one embodiment, memory cells 222 may include rewritable memory cells, once-programmable memory cells, and multiple-programmable memory cells. In one embodiment, each memory cell in memory cell 222 is vertically oriented. Memory cells 222 may include non-volatile memory cells or volatile memory cells. Relative to the first memory layer 212, a first portion of memory cell 222 is located between and connected to word line 216 and bit line 220. Relative to the second memory layer 214, a second portion of memory cell 222 is located between and connected to word line 218 and bit line 220.

[0063] In one embodiment, each memory cell 222 includes a threshold selector device, wherein each memory cell 222 represents a data bit. Figure 2B This is a simplified schematic diagram of memory cell 222a, which is Figure 2A An example specific implementation of memory cell 222a. In one embodiment, memory cell 222a includes a selector element S coupled between a first terminal T1 and a second terminal T2. x In one embodiment, memory cell 222a is vertically oriented.

[0064] In one embodiment, memory cell 222a is a threshold selector memory cell—including a threshold selector device (selector element S). x This is a memory cell that functions as both a memory element and a selector device, and uses the threshold voltage difference of the threshold selector device to store data. In one embodiment, memory cell 222a operates as a threshold selector memory cell, wherein the selector element S... x It can be configured to store information using either of two different threshold voltages (e.g., a first threshold voltage and a second threshold voltage). For simplicity, the rest of the discussion will... Figure 2B The memory cell 222a is called the threshold selector memory cell 222a.

[0065] In one implementation, the selector element S x This includes selector materials that provide bidirectional current flow when the current or voltage exceeds a threshold. Selector element S x Therefore, it is also referred to as a "threshold selector device S" in the remaining descriptions. x Therefore, the threshold selector device S x It is a bidirectional device that allows bidirectional current flow when the current or voltage exceeds a threshold and blocks current flow when the current or voltage is below a threshold.

[0066] In one implementation, the threshold selector device Sx This includes a bidirectional threshold switching material that allows current to flow only when the voltage difference across it exceeds a threshold voltage value. In one embodiment, the bidirectional threshold switching material may include a chalcogenide material. The chalcogenide material may include one or more of GeSeAs alloys, GeSeAsTe alloys, GeTeAs alloys, GeSeTe alloys, GeSe alloys, SeAs alloys, AsTe alloys, GeTe alloys, SiTe alloys, SiAsTe alloys, and SiAsSe alloys. The chalcogenide material may be undoped or doped with at least one of N, O, C, P, Ge, As, Te, Se, In, or Si.

[0067] although Figure 2B The threshold selector device S is not shown in the diagram. x It may also include one or more conductive layers and / or barrier layers, such as tungsten, tungsten nitride, tantalum, tantalum nitride, carbon-nitrogen layers, etc. The conductive layers and / or barrier layers may be located above and / or below the bidirectional threshold switching material.

[0068] Figure 2C It describes the threshold selector device S x A graph illustrating exemplary current-voltage (IV) characteristics. Each threshold selector device S... x Initially in a high-resistance (off) state. To enable the threshold selector device S... x As a threshold switching operation, an initial setup operation may be necessary to enable the threshold selector device S x Operates within a current range where switching is possible.

[0069] For example, the forming operation may include feeding the threshold selector device S x Apply one or more voltage pulses, each pulse having a voltage greater than or equal to the forming voltage V. FORM The amplitude. After the formation operation, the threshold selector device S x It can be switched on and off, and can be used as a unipolar threshold selector device or a bipolar threshold selector device. Therefore, the threshold selector device S x It can be referred to as a bipolar threshold selector device.

[0070] exist Figure 2C In the exemplary IV characteristics, for a positive applied voltage, the threshold selector device S x Maintain in a high-resistance state (HRS) (e.g., off) until the voltage on the device meets or exceeds a first threshold voltage V. TP (That is, it has a larger positive value than the first threshold voltage), at which point the threshold selector device S x Switch to low resistance state (LRS) (e.g., ON). Threshold selector device S xKeep it on until the voltage on the device drops to or below the first holding voltage V. HP At this time, the threshold selector device S x disconnect.

[0071] For a negative applied voltage, the threshold selector device S x Remain in the HRS (e.g., disconnected) until the voltage on the device meets or exceeds the second threshold voltage V. TN (i.e., having a smaller negative value than the second threshold voltage), at which point the threshold selector device S x Switch to LRS (e.g., turn on). Threshold selector device S x Keep it on until the voltage on the device increases to or exceeds the second holding voltage V. HN (That is, it has a larger negative value than the second holding voltage), at which point the threshold selector device S x disconnect.

[0072] For simplicity, the remaining description will refer to the threshold selector device S. x The positive threshold voltage. Those skilled in the art will understand that the techniques described below are similarly applicable to threshold selector devices S. x The negative threshold voltage.

[0073] Figure 3A and Figure 3B This is a simplified schematic diagram of an exemplary crosspoint memory array 300, which includes a first memory layer 300a and a second memory layer 300b located above the first memory layer 300a. The crosspoint memory array 300 is... Figure 1E An example of a specific implementation of the memory array 160. The cross-point memory array 300 may include more than two memory layers.

[0074] The cross-point memory array 300 includes word lines WL1a, WL2a, WL3a, WL1b, WL2b, and WL3b, and bit lines BL1, BL2, and BL3. The first memory layer 300a includes memory cells 302 coupled to word lines WL1a, WL2a, and WL3a and bit lines BL1, BL2, and BL3. 11a 302 12a ……302 33a The second memory layer 300b includes memory cells 302 coupled to word lines WL1b, WL2b, WL3b and bit lines BL1, BL2 and BL3. 11b 302 12b ……302 33b In one embodiment, memory cell 302 11a 302 12a ……30233a Each of them is vertically oriented. In one embodiment, memory cell 302 11b 302 12b ……302 33b Each of them is vertically oriented.

[0075] The first memory layer 300a is Figure 2A An example of a specific implementation of the first memory layer 212 of the monolithic three-dimensional memory array 210, and the second memory layer 300b is Figure 2A An example of a specific implementation of the second memory layer 214 of the monolithic three-dimensional memory array 210. In one embodiment, memory cell 302 11a 302 12a ……302 33a 302 11b 302 12b ... 302 33b Each of them is Figure 2B Threshold selector memory unit 222a.

[0076] Those skilled in the art will understand that the cross-point memory array 300 may include more or fewer than six word lines, more or fewer than three bit lines, and more or fewer than eighteen memory cells 302. 11a 302 12a ……302 33a 302 11b 302 12b ……302 33b In some implementations, the crosspoint memory array 300 may include 1000 × 1000 memory cells, although other array sizes may also be used.

[0077] Each memory unit 302 11a 302 12a ……302 33a 302 11b 302 12b ... 302 33b Coupled to a word line in the word lines and a bit line in the bit lines, and each including a corresponding selector element S. 11a、 S 12a ...S 33a S 11b S 12b ...S 33b Above or below. In one embodiment, each memory cell 302 11a 302 12a ...302 33a 302 11b 30212b ... 302 33b It is a threshold selector memory unit 222a, in which the selector element S 11a S 12a ...S 33a S 11b S 12b ... S 33b It can be programmed to two different threshold voltages (e.g., high threshold voltage and low threshold voltage) to store information.

[0078] Each memory unit 302 11a 302 12a ……302 33a Each memory cell 302 has a first terminal coupled to one of bit lines BL1, BL2, BL3 and a second terminal coupled to one of word lines WL1a, WL2a, WL3a. 11b 302 12b ……302 33b It has a first terminal coupled to one of the bit lines BL1, BL2, and BL3, and a second terminal coupled to one of the word lines WL1b, WL2b, and WL3b. For example, memory cell 302 13a Including selector element S 13a It includes a first terminal coupled to bit line BL3 and a second terminal coupled to word line WL1a.

[0079] Similarly, memory cell 302 22b Including selector element S 22b It includes a first terminal coupled to bit line BL2 and a second terminal coupled to word line WL2b. Similarly, memory cell 302 33a Including selector element S 33a It includes a first terminal coupled to bit line BL3 and a second terminal coupled to word line WL3a.

[0080] See again Figure 2B The threshold selector memory unit 222a includes a threshold selector device S. x Such as threshold selector devices comprising bidirectional threshold switching materials, the bidirectional threshold switching material having a structure based on previously used for threshold selector devices S x The threshold voltage varies depending on the polarity of the applied voltage used for writing.

[0081] In one implementation, the threshold selector device S x Having a first (e.g., SET) threshold voltage (referred to herein as "SET threshold voltage V") TSThe second (e.g., RESET) threshold voltage (referred to herein as "RESET threshold voltage V") and the second (e.g., RESET) threshold voltage (referred to herein as "RESET threshold voltage V") TR Therefore, two threshold voltages can be used to represent the stored data, where "memory" is the RESET threshold voltage V. TR With SET threshold voltage V TS The difference between them.

[0082] In one implementation, the threshold selector device S x SET threshold voltage V TS (For example, 3V) represents the first memory state (e.g., SET or "0") of the threshold selector memory cell 222a, and the threshold selector device S x RESET threshold voltage V TR (For example, 4V) represents the second memory state of the threshold selector memory cell 222a (for example, RESET or "1").

[0083] Figure 4A The threshold selector device S is described. x A simplified plot of the threshold voltage relative to time is shown, and the time span across the threshold selector device S is also depicted. x The threshold selector memory cell 222a is subjected to read and write voltages. For simplicity, the following discussion assumes that at time t0, the threshold selector memory cell 222a is in the second memory state (RESET) and the threshold selector device S... x With RESET threshold voltage V TR (4V). In the implementation, the sense amplifier determines the state of the threshold selector memory cell 222a after a sufficient time has been allowed to stabilize following the initial current spike.

[0084] At time t1, a read voltage V is applied to the threshold selector memory cell 222a. RD (For example, 3.5V). Read voltage V RD Less than the RESET threshold voltage V TR (4V), and therefore the threshold selector device S x Without switching or conducting current, the threshold selector memory cell 222a is indicated to be in the second memory state (RESET).

[0085] At time t2, a positive write voltage +V is applied to the threshold selector memory cell 222a. W (e.g., +4.5V). In one implementation, the positive write voltage is +V. W With reading voltage V RD The same polarity makes the threshold selector device S xThe threshold voltage becomes the SET threshold voltage V. TS (3V).

[0086] At time t3, a read voltage V is applied to the threshold selector memory cell 222a. RD (3.5V). Read voltage V RD Above the SET threshold voltage V TS (3V), and therefore the threshold selector device S x And conduct current, thereby indicating that the threshold selector memory cell 222a is in the first memory state (SET).

[0087] At time t4, a negative write voltage -V is applied to the threshold selector memory cell 222a. W (e.g., -4.5V). In one implementation, the negative write voltage is -V W With reading voltage V RD The opposite polarity makes the threshold selector device S x The threshold voltage becomes the RESET threshold voltage V. TR (4V).

[0088] At time t5, a read voltage V is applied to the threshold selector memory cell 222a. RD (3.5V). Read voltage V RD Less than the RESET threshold voltage V TR (4V), and therefore the threshold selector device S x Without switching or conducting current, the threshold selector memory cell 222a is indicated to be in the second memory state (RESET).

[0089] Therefore, as described above and as... Figure 4A The threshold selector device S of the threshold selector memory cell 222a is described. x It has different threshold voltages based on the polarity of the voltage applied when writing to a memory cell. This example read technique is sometimes referred to as a "bounded read," and Figure 4B The voltage-to-time ratio of the threshold selector memory cell 222 for this type of delimited read is depicted.

[0090] Figures 4A to 4B The example uses a threshold selector device S x Described as having a RESET threshold voltage V TR and SET threshold voltage V TS Memory arrays (such as...) Figure 1E The memory array 160 typically includes a number of threshold selector memory cells 222a, each of which includes a corresponding threshold selector device S. x .

[0091] Ideally, the threshold selector device S in the memory array x Having the same RESET threshold voltage V TR and SET threshold voltage V TS However, in reality, the threshold selector device S x The group will have a SET threshold voltage V TS The first distribution of values ​​and the RESET threshold voltage V TR The second distribution of values.

[0092] Therefore, the first selector device S x1 The second selector device S will have a first (SET) threshold voltage and a second (RESET) threshold voltage. x2 It will have a third (SET) threshold voltage and a fourth (RESET) threshold voltage. SET threshold voltage V TS The first distribution of values ​​includes a first (SET) threshold voltage and a third (SET) threshold voltage, and the RESET threshold voltage V TR The second distribution of values ​​includes a second (RESET) threshold voltage and a fourth (RESET) threshold voltage.

[0093] Figure 4C It describes a device S including a threshold selector. x Example SET threshold voltage V of a group of threshold selector memory cells 222a TS Distribution, Example RESET threshold voltage V TR Distribution and example reading voltage V RD The illustration.

[0094] In the implementation, each distribution has a lower tail and an upper tail. SET threshold voltage V TS The upper tail of the distribution and the RESET threshold voltage V TR The difference between the lower tails of the distribution is referred to as the read window margin (RWM) in this paper, and the read voltage V is ideally selected within the read window margin. RD (It has a read voltage V) RD distributed).

[0095] In the implementation scheme, if a read voltage V is applied across the threshold selector memory cell 222a in the first memory state (SET), RD However, the threshold selector device S x No switching and no current conduction, or if a read voltage V is applied across the threshold selector memory cell 222a in the second memory state (RESET). RD However, the threshold selector device S xWhen switching occurs and current is conducted, a read error occurs. The required read reliability, set by the read bit error rate (BER) specification, determines the read window margin requirement for the memory array of threshold selector memory cell 222a.

[0096] Threshold selector device S x One phenomenon (such as threshold selector devices incorporating bidirectional threshold switching materials) is that after a write operation, the SET threshold voltage V... TS and RESET threshold voltage V TR It increases continuously over time at a rate based on material properties. This is referred to as threshold voltage drift in this paper. Threshold voltage drift also exhibits a distribution and is specific to the SET threshold voltage V. TS and RESET threshold voltage V TR They can be different.

[0097] Assuming the maximum SET threshold voltage V TS Drift and zero reset threshold voltage V TR Drift, boundary reads must allow for a reduced read window margin. This is because it is difficult to track how much the threshold voltage of threshold selector memory cell 222a may have drifted. Maximum drift can be defined by “refreshing” threshold selector memory cell 222a at defined time intervals determined based on performance impact. Refreshing involves reading from and subsequently writing to threshold selector memory cell 222a.

[0098] Considering that threshold voltage drift significantly reduces read window margin. Figure 4D The effect of threshold voltage drift on the available read window used for reading BER with target product is shown. Specifically, the figure shows the original SET threshold voltage V. TS Distribution, drifted SET threshold voltage V after time T TS Distributed and drift-free RESET threshold voltage V TR distributed.

[0099] Compare Figure 4C and Figure 4D Threshold voltage drift reduces the read window margin, making cutoff reads very challenging. One approach to address threshold voltage drift is to find a solution with a large nominal read window margin, low drift, and a very tight V0. RD The materials used in distributed circuit design are expensive and may still be insufficient to achieve the necessary product read BER.

[0100] A method is described for reading threshold selector memory cells (such as) by using a "reference memory cell" to track and mitigate threshold voltage drift in a "data memory cell". Figure 2BThe technology of threshold selector memory cell 222a). In one embodiment, the data memory cell and the reference memory cell are each a threshold selector memory cell 222a having the same physical structure and being substantially the same within the limitations of semiconductor manufacturing technology.

[0101] As used herein, the data storage unit is a threshold selector storage unit (such as...) Figure 2B Threshold selector memory cells 222a), each including a RESET threshold voltage V TR (V TRD ) and SET threshold voltage V TS (V TSD Threshold selector device S x And it is used to store data bits.

[0102] As used herein, the reference memory cell is a threshold selector memory cell (such as...) Figure 2B The threshold selector memory unit 222a) includes a threshold voltage V. TS (V TSR ) and RESET threshold voltage V TR (V TRR Threshold selector device S x In the implementation, the reference memory cell is used to store reference bits (e.g., "0" (SET) or "1" (RESET)).

[0103] In one implementation, a reference memory cell is used to track the threshold voltage drift of N corresponding data memory cells, where N = 1, 2, 3, ... In one implementation, N = 128, but other values ​​of N can be used. For simplicity, the following discussion assumes N = 128.

[0104] In one implementation, whenever data is written to a data memory cell, a predetermined value (e.g., 0 or 1) is written to the corresponding reference memory cell. For simplicity, the following discussion assumes that the predetermined value is 0 (i.e., whenever data is written to a data memory cell, the corresponding reference memory cell is written to the SET memory state).

[0105] In one implementation, a SET threshold voltage V is provided. TSR The reference memory cell along with the SET threshold voltage V of N corresponding data memory cells TSD and RESET threshold voltage V TRD The drift occurs over time. In one implementation, it is assumed that the reference memory cell SET threshold voltage V... TSR The drift rate is essentially related to the data memory cell SET threshold voltage V. TSDand data memory cell RESET threshold voltage V TRD Their drift rates are the same.

[0106] In one implementation, when reading a data memory cell, the reference memory cell SET threshold voltage V is used. TSR Detected and used to offset the SET threshold voltage V of the data memory unit TSD and data memory cell RESET threshold voltage V TRD The drift component. In this type of implementation, the cost and power impact of a single reference memory cell on every N data memory cells is minimal. This type of technique is referred to herein as threshold voltage reference readout technique.

[0107] Figure 5A This is a flowchart of an implementation scheme of the threshold voltage reference readout technique according to this technology. In one implementation, the threshold voltage reference readout process 500 is used to read N data memory cells, such as... Figure 2B The threshold selector memory unit 222a. In the example implementation, process 500 is... Figure 1A One or more of the memory chip controller 104 and the memory core control circuit 106 are executed.

[0108] In one implementation, whenever data is written to N data memory cells, the corresponding reference memory cell is written to a first memory state (e.g., 0 or SET). Therefore, at step 502, a write signal writes "0" to the reference memory cell and a programming signal writes data to the N data memory cells. For simplicity, the remainder of process 500 will refer to "data memory cells".

[0109] At step 504, it is determined whether to read the data memory unit. If not, process 500 loops back to step 504 and continues to wait for a request to read the data memory unit.

[0110] In one implementation, a read request can be received at any time after the write operation to the data memory cell and the reference memory cell is performed in step 502. During this time interval, the reference memory cell SET threshold voltage V TSR Distributed data storage unit SET threshold voltage V TSD Distributed and data storage unit RESET threshold voltage V TRD The distribution continues to drift.

[0111] In one implementation, assume the reference memory cell SET threshold voltage V TSR The drift rate of the distribution is essentially related to the data memory cell SET threshold voltage V. TSDDistributed and data storage unit RESET threshold voltage V TRD The distributions have the same drift rate.

[0112] Finally, at some point after the data memory cell is written in step 502, a request to read data from the data memory cell is received. Therefore, at step 504, it is determined that the data memory cell will be read, process 500 proceeds to step 506, and the ramp read voltage V is... RD Word lines applied to the reference memory cell and the data memory cell.

[0113] At step 508, it is determined whether the reference memory cell has been triggered. Specifically, when the ramp read voltage V... RD The reference memory cell SET threshold voltage V is met or exceeded. TSR At that time, the threshold selector device S of the unit x This will trigger and conduct current. Therefore, step 508 determines that the reference memory cell SET threshold voltage V is equal to... TSR The ramp reading voltage V RD The value of .

[0114] As mentioned above, assuming the reference memory cell SET threshold voltage V TSR Distribution with data storage unit SET threshold voltage V TSD Distributed and data storage unit RESET threshold voltage V TRD The drift rates are approximately the same. Therefore, it is assumed that the drifted reference memory cell SET threshold voltage V determined at step 508... TSR The value is the SET threshold voltage V of the data storage unit. TSD Distributed and data storage unit RESET threshold voltage V TRD An indication of the amount of drift in the distribution.

[0115] If it is determined at step 508 that the reference memory cell has not yet been triggered, the process returns to step 506 to continue ramping the voltage V. RD However, if it is determined at step 508 that the reference memory cell has been triggered, then at step 510, process 500 waits for a delay time ΔT. D .

[0116] Specifically, Figure 5B This is an example reference memory cell SET threshold voltage V depicted at the moment the reference memory cell has been triggered. TSR Distribution, and example data storage unit SET threshold voltage V TSD Distributed and data storage unit RESET threshold voltage V TRD Distribution. Therefore. Figure 5BEssentially, it is the SET threshold voltage V of the drifted reference memory cell. TSR Distribution and drifted data memory cell SET threshold voltage V TSD Distributed and data storage unit RESET threshold voltage V TRD A "snapshot" of the distribution.

[0117] Reference memory cell second threshold voltage V TSR The distribution is described as being less than the data memory cell SET threshold voltage V. TSD The distribution is due to the fact that there are more data memory cells than reference memory cells. The SET threshold voltage V for any given reference memory cell... TSR Located at the reference memory cell SET threshold voltage V TSR Somewhere within the distribution, but the exact location of any particular reference memory cell is unknown.

[0118] therefore, Figure 5B The text also describes the ramp read voltage V. RD In the illustrated example, the ramp reads the voltage V. RD At time t L The threshold voltage V across the reference memory cell SET TSR The lower tail of the distribution and at time t U The threshold voltage V across the data memory cell SET TSD The upper tail of the distribution. In one implementation, the data sample delay time ΔT D Set to be equal to the time difference t U -t L .

[0119] In other words, the first predetermined delay time ΔT D Selected to allow ramp reading voltage V RD The data memory cell SET threshold voltage V exceeds the corresponding reference memory cell. TSD The upper tail of the distribution, at the reference memory cell SET threshold voltage V TSR The lower tail of the distribution has a SET threshold voltage. Those skilled in the art will understand that other criteria can be used to specify the first predetermined delay time ΔT. D .

[0120] Refer again Figure 5A After waiting for the first predetermined delay time ΔT D At step 512, stop reading voltage V. RD Slope (e.g., in value V) RDF (location), and will read voltage V RD Fixed at V RDF Place.

[0121] At step 514, the voltage V is read. RD =V RDF Read N data memory units. Without being bound by any particular theory, it is believed that... Figure 5A Example threshold voltage reference read process 500 can reduce threshold voltage drift on data memory units ( Figure 2B The impact of the read window margin of the threshold selector memory cell 222a), each of which includes a data memory cell RESET threshold voltage V for storing data bits. TRD and data memory cell threshold voltage SET V TSD Threshold selector device S x .

[0122] A simple example can be used to illustrate this. Figure 5A An example operation of the threshold voltage reference readout technique 500. In this example, the first memory cell (reference memory cell) includes a first two-terminal element (e.g., a first threshold selector device S) having a first threshold voltage (SET) and a second threshold voltage (RESET). x The second memory cell (data memory cell) includes a second two-terminal element (e.g., a second threshold selector device S) having a third threshold voltage (SET) and a fourth threshold voltage (RESET). x ).

[0123] In one embodiment, a first voltage signal (e.g., a write signal) is applied to a first memory cell to give the first two terminal elements a first threshold voltage (SET), and a second voltage signal (e.g., a programming signal) is applied to a second memory cell to give the second two terminal elements a third threshold voltage (SET) or a fourth threshold voltage (RESET) (step 502).

[0124] The third voltage signal (e.g., reading voltage V) RD A third voltage signal is applied to the first memory cell and the second memory cell, and the third voltage signal increases at a first ramp rate. (Step 506).

[0125] When the third voltage signal meets or exceeds the first threshold voltage, the first memory cell is determined to switch from the non-conductive state to the conductive state (step 508).

[0126] After the first memory cell switches from a non-conductive state to a conductive state, a first predetermined delay time (e.g., the first predetermined delay time ΔT) is applied. D After that, the third voltage signal is used to read the second memory cell (steps 510 and 514).

[0127] exist Figure 5A In the example threshold voltage reference reading process 500, the same ramp reading voltage V is used. RD Word lines are applied to both the reference memory cell and the data memory cell. In another embodiment, the first ramp read voltage V is... RD1 The word line is applied to the reference memory cell, and the second ramp read voltage V is applied. RD2 Word lines applied to data memory cells.

[0128] For example, Figure 5C Depicting Figure 5B Example threshold voltage distribution, where the first ramp reads the voltage V RD1 The word line is applied to the reference memory cell, and the second ramp read voltage V is applied. RD2 Word lines applied to the data memory cell. In one implementation, the first ramp read voltage V RD1 Second slope reading voltage V RD2 Having the same ramp rate, but the second ramp read voltage V RD2 Read voltage V from the first ramp RD1 The voltage offset V was reduced. OFF .

[0129] exist Figure 5C In the example, the SET threshold voltage V of a specific reference memory cell TSR Higher than Figure 5B The SET threshold voltage V described in the figure TSR Therefore, if the same slope reads the voltage V RD1 Word lines applied to both the reference memory cell and the data memory cell, and at a delay time ΔT D Then at time t U The data memory cell is read from the data memory cell, and the read may be disturbed by the RESET threshold voltage V in the data memory cell. TRD The upper tail of the distribution has a RESET threshold voltage V. TRD Some data storage units (in) Figure 5C (The circle is depicted with a dashed line).

[0130] If the voltage V is read from the first ramp instead... RD1 Offset (reduction) of the second ramp read voltage V RD2 It is applied to the data memory cell, and during the delay time ΔT D Then at time t U The data is read from the memory cell, and the read will not interfere with the RESET threshold voltage V of the data memory cell. TRD The upper tail of the distribution has a RESET threshold voltage V. TRD Data storage unit (in) Figure 5C (Depicted as a solid circle in the diagram). Without wishing to be bound by any particular theory, this technique is believed to allow for a delay less than the minimum time ΔT imposed by the circuit. D Used when a limited amount of time is needed to feed the reference bit information back to the data bits.

[0131] Figure 6A It can be used to implement threshold voltage reference readout processes (such as...) Figure 5A A simplified diagram of an embodiment of a threshold voltage reference reading system 600a (example threshold voltage reference reading process 500). In one embodiment, the threshold voltage reference reading system 600a can be... Figure 1A The example memory chip 106 is implemented.

[0132] In one implementation, the threshold voltage reference readout system 600a includes N data modules 6020, 6021, 6022, ..., 602... N-1 and corresponding reference module 602 S Data modules 6020, 6021, 6022, ..., 602 N-1 and corresponding reference module 602 S Each of them is coupled to the corresponding word line decoder WL DEC and the corresponding bit line decoder BL DEC.

[0133] Data modules 6020, 6021, 6022, ..., 602 N-1 and corresponding reference module 602 S Each of them includes an array of threshold selector memory cells 222a, wherein a specific threshold selector memory cell being accessed is selected (referred to herein as “selected threshold selector memory cell”) using word line and bit line addresses WL ADD and BL ADD, respectively.

[0134] Data modules 6020, 6021, 6022, ..., 602 N-1 and corresponding reference module 602 S Each of these is coupled to the sense amplifier circuits 6040, 6041, 6042, ..., 604 via the corresponding bit line decoder BL DEC. N-1 and 604 S Sensing amplifier circuits 6040, 6041, 6042, ..., 604 N-1 Used to determine data modules 6020, 6021, 6022, ..., 602 N-1 The selected data memory cell's memory state is determined and data outputs D0, D1, D2, ..., D are generated respectively. N-1 .

[0135] In one embodiment, the sensing amplifier circuit 604 S A first reference output signal C coupled to the first input terminal of the voltage ramp control circuit 606 S In one implementation, when the word line voltage (WL voltage) generated by the voltage ramp control circuit 606 is less than the reference module 602... S The selected reference memory cell SET threshold voltage V TSR At that time, the first reference output signal C S It has a first value (e.g., LOW), and when the WL voltage is greater than or equal to the reference module 602 S The selected reference memory cell SET threshold voltage V TSR At that time, the first reference output signal has a second value (e.g., HIGH).

[0136] In one implementation, the first reference output signal C S A voltage ramp control circuit 606 is configured to generate a ramp voltage WL applied to the word line of a selected threshold selector memory cell. In one embodiment, the WL voltage is used to drive data modules 6020, 6021, 6022, ..., 602... N-1 The selected threshold selector memory unit and corresponding reference module 602 in S .

[0137] Figure 6B It is a description Figure 6A A diagram illustrating an example signal in an example threshold voltage reference reading system 600a. In one embodiment, for reference module data modules 6020, 6021, 6022, ..., 602... N-1 and corresponding reference module 602 S Controlling the WL voltage ramp, such as Figure 6B shown. Specifically, Figure 6B The threshold voltage V of the data storage unit SET is described. TSD Distribution boundary and data memory cell RESET threshold voltage V TRD The lower tail of the distribution.

[0138] In one implementation, the read window margin is described as the data memory cell RESET threshold voltage V. TRD The lower tail of the distribution and the SET threshold voltage V of the data memory unit TSD The difference between the upper tails of the distribution. Furthermore, Figure 6B The reference cell SET threshold voltage V is described. TSR The distribution boundary.

[0139] exist Figure 6A In the example threshold voltage reference reading system 600a, data is read from N data modules 6020, 6021, 6022, ..., 602... N-1 N data bits are derived, each of which has an array of data memory cells, and a data memory cell is selected from this array for each access. Furthermore, reference module 602... S Provide a corresponding reference bit for each access.

[0140] In one implementation, access involves data from N data modules 6020, 6021, 6022, ..., 602 N-1 Each of them and from reference module 602 S A corresponding reference memory cell is selected and a data memory cell is read. Although not in Figure 6A Described in the text, but the controller (e.g., Figure 1A The memory chip controller 104) coordinates all N data modules 6020, 6021, 6022, ..., 602 N-1 The activities on these data modules are collectively referred to as "libraries" in this article.

[0141] Furthermore, any set of N data bits and its corresponding reference bit is referred to herein as a "line". In the implementation, it is assumed that any line is written first before it can be read.

[0142] In one implementation, a write operation to a line updates the data memory cell based on user data, but always sets the corresponding reference memory cell to the SET memory state. Without wishing to be bound by any particular theory, it is believed that the write operation resets the threshold voltage drift of all bits in the line (e.g., no drift).

[0143] In one implementation, the read operation begins with a fast ramp WL voltage for the data memory cell and the corresponding reference memory cell. This is in Figure 6B The middle is described as a "rapid ramp". In one implementation, during the second predetermined delay time ΔT SR After that, the WL voltage changed to Figure 6B The gentler slope is described as a "slow slope". In one implementation, the second predetermined delay time ΔT SR It is the fast ramp across the reference memory cell SET threshold voltage V TSR The estimated time for the lower tail. Figure 6B (Designated as "early reference unit").

[0144] In one implementation, the WL voltage transitions from a fast ramp to a slow ramp to prevent any data memory cell from hitting the data memory cell RESET threshold voltage V.TRD The lower tail of the distribution interferes with those data storage units.

[0145] In one implementation, when the reference data cell is triggered (e.g., when the WL voltage ramp satisfies or exceeds the reference memory cell SET threshold voltage V),... TSR At that time, the reference data unit sends a signal to the controller. Figure 6B (Described as a "reference trigger signal" in the text). In one implementation, after the controller receives the reference trigger signal, the controller will wait for a first predetermined delay time ΔT. D ( Figure 5A (Step 510) and then stop the WL voltage ramp and sense the data memory cell.

[0146] In one implementation, the first predetermined delay time ΔT D The selection is made so that the reads of the data memory cell are correctly positioned within the read window to achieve the target BER. In one embodiment, the latency is determined by the fast and slow ramp rates of the WL voltage. In one embodiment, the controller stops the WL voltage ramp and senses the data memory cell to prevent a sustained ramp of the WL voltage from exceeding the data memory cell RESET threshold voltage V. TRD The lower tail of the distribution.

[0147] Without wishing to be bound by any particular theory, it is believed Figure 6A Example threshold voltage reference read system 600a can reduce threshold voltage drift on data memory units (such as...) Figure 2B The impact of the read window margin of the threshold selector memory cell 222a), each of which includes a data memory cell RESET threshold voltage V for storing data bits. TRD and data memory cell threshold voltage SET V TSD Threshold selector device S x .

[0148] Example threshold voltage reference reading system 600a for N data modules 6020, 6021, 6022, ..., 602 N-1 Using a single corresponding reference module 602 S . Figure 6C This is an alternative example implementation of a threshold voltage reference readout system 600b that can be used to implement a threshold voltage reference readout process. In one implementation, the threshold voltage reference readout system 600b is similar to... Figure 6A The threshold voltage reference reading system 600a includes an additional corresponding reference module 602. F (also referred to in this document as Quick Reference Module 602) F) and additional sensing amplifier circuit 604 F The threshold voltage reference reading system 600b also includes a reference module 602. S (also referred to in this document as slow reference module 602) S ).

[0149] In one embodiment, the sensing amplifier circuit 604 F The second reference output signal C has a second input terminal coupled to the voltage ramp control circuit 606. F In one implementation, when the WL voltage is less than that of the fast reference module 602 F The selected reference memory cell SET threshold voltage V TSR At that time, the second reference output signal C F It has a first value (e.g., LOW), and when the WL voltage is greater than or equal to the fast reference module 602 F The selected reference memory cell SET threshold voltage V TSR At that time, the second reference output signal has a second value (e.g., HIGH).

[0150] In one implementation, from slow reference module 602 S The first reference output signal C generated S This is referred to in this document as "slow read reference bit", and is from the fast reference module 602. F The generated second reference output signal C F This is referred to herein as a "fast read reference bit". In one implementation, the first reference output signal C S Second reference output signal C F Each is configured to control a voltage ramp control circuit 606, which is configured to generate a ramp voltage WL, which is applied to data modules 6020, 6021, 6022, ..., 602. N-1 and reference module 602 S and 602 F The word line of the selected threshold selector memory cell in the memory.

[0151] In one implementation, write operations to the line will update the data storage unit based on user data, but will always slow down the reference module 602. S and Quick Reference Module 602 FThe corresponding reference memory cell is set to the SET memory state. Compared to the read operation of the threshold voltage reference read system 600a, in one embodiment, the threshold voltage reference read system 600b includes two distinct read operations (referred to herein as "fast read" and "slow read"). In one embodiment, the slow read is invoked only if the fast read has an uncorrectable error (e.g., after ECC application). In one embodiment, only the fast read is performed if the error rate of the fast read after ECC is less than a predetermined threshold (e.g., 1% or some other value).

[0152] In one implementation, fast reads are allowed to achieve a much higher BER relative to the desired BER specification, while slow reads are required to meet the desired BER specification. In one implementation, the higher BER of fast reads results in a sufficiently large read window margin to allow for more aggressive sampling timing of the data bits. However, in another implementation, fast reads are performed such that the read interference error rate is not increased. That is, the data memory cell RESET threshold voltage V is maintained. TRD The required distance for data levels to maintain the specified BER target.

[0153] In one implementation, when a read is performed, only fast reference module 602 is used. F The fast read reference memory unit in the middle, along with data modules 6020, 6021, 6022, ..., 602... N-1 The data bits are triggered together, and the reference module 602 is slowly referenced. S The slow read reference memory cell was not triggered.

[0154] In one implementation, data comes from modules 6020, 6021, 6022, ..., 602... N-1 Data bits used are slower than slow reads at a slower ramp rate (e.g., Figure 6B The fast read rate is much faster than the slow ramp depicted in the diagram. Furthermore, in one embodiment, the fast read uses a first predetermined delay time ΔT. D This is a shorter latency than that used in slow reads. Without wanting to be bound by any particular theory, this is believed to enable low-latency, fast reads, despite a high BER.

[0155] In one implementation, during slow reads, the fast reference module 602 F Fast read reference memory unit and slow reference module 602 SBoth the slow read reference memory cell and the fast read reference memory cell are triggered. The fast read reference memory cell can no longer be used to eliminate the drift of any SET bits that were not triggered during the previous fast read. This is because triggering the fast read reference memory cell during a fast read will reset the drift to zero. Because the slow read reference memory cell was not triggered during a fast read, it continues to drift with the remaining untriggered SET bits in the line. Therefore, the slow read reference memory cell can be used as a way to eliminate the drift components used to read these data bits.

[0156] However, in order to accurately read these remaining data bits, in one implementation, the slow read ramp rate is made slow enough to ensure that the read voltage V is reached. RD It can be correctly positioned to achieve the specified read BER. Without wanting to be bound by any particular theory, it is believed that slow reads will have approximately twice the latency of fast reads. However, because slow reads occur infrequently (e.g., less than 1% of the time), the longer slow read latency has a smaller impact on the average read operation.

[0157] Figures 6D1 to 6D2 They are Figure 6C Example threshold voltage reference reading system 600b: threshold voltage and read voltage V for fast and slow read processes. RD A simplified diagram of the distribution. Two diagrams illustrate the trade-off between speed and BER.

[0158] Without being bound by any particular theory, the threshold voltage reference readout technique described above is believed to provide highly reliable, fast readout operations for OTS memory cells while consuming less power than existing delimited readout techniques.

[0159] Figure 7 A flowchart is shown illustrating an implementation scheme of a threshold voltage reference reading technique 700 based on this technique.

[0160] At step 702, a reference memory cell is written to a first memory state and data is written to a plurality of data memory cells. Each of the reference memory cell and the data memory cells includes a bidirectional threshold switch, which includes a first threshold voltage distribution and a second threshold voltage distribution.

[0161] At step 704, a ramp voltage is applied to the word lines coupled to the reference memory cell and the data memory cell.

[0162] At step 706, it is determined that the reference memory cell has switched from a non-conductive state to a conductive state.

[0163] At step 708, the ramp voltage is stopped after a first predetermined delay time following the switch of the reference memory cell from a non-conductive state to a conductive state.

[0164] At step 710, multiple data memory cells are read with a stopping ramp voltage.

[0165] One embodiment of the disclosed technology includes an apparatus comprising a memory array having: a first memory cell including a first terminal element having a first threshold voltage and a second threshold voltage; a second memory cell including a second terminal element having a third threshold voltage and a fourth threshold voltage; and control circuitry coupled to the memory array. The control circuitry is configured to: apply a first voltage signal to the first memory cell to give the first terminal element the first threshold voltage; apply a second voltage signal to the second memory cell to give the second terminal element the third threshold voltage or the fourth threshold voltage; apply a third voltage signal to the first memory cell and the second memory cell, the third voltage signal increasing at a first ramp rate; determine that the first memory cell switches from a non-conductive state to a conductive state; and use the third voltage signal to read the second memory cell using the third voltage signal after the first memory cell switches from the non-conductive state to the conductive state for a first predetermined delay time.

[0166] One embodiment of the disclosed technology includes a system comprising: a plurality of data modules, each data module including a plurality of data memory units, each data memory unit including a bidirectional threshold switch, the bidirectional threshold switch including a first threshold voltage distribution and a second threshold voltage distribution; a first reference module including a first plurality of first reference memory units, each first reference memory unit including a bidirectional threshold switch, the bidirectional threshold switch including a first reference threshold voltage distribution; a plurality of word lines coupled to the plurality of data memory units and the first plurality of first reference memory units; a voltage ramp control circuit coupled to the plurality of data modules and the first reference module, the voltage ramp control circuit being configured to generate a ramp output voltage; and a control circuit coupled to the plurality of data modules, the first reference module, and the voltage ramp control circuit. The control circuit is configured to: couple the ramp output voltage to a selected data memory cell from each of the plurality of data modules and a selected first reference memory cell from the first reference module; determine that the selected first reference memory cell switches from a non-conductive state to a conductive state; and use the ramp output voltage to read each of the selected data memory cells for a first predetermined delay time after the selected first reference memory cell switches from the non-conductive state to the conductive state.

[0167] One embodiment of the disclosed technology includes a method comprising: writing a reference memory cell to a first memory state and writing data to a plurality of data memory cells, each of the reference memory cell and the data memory cells including a bidirectional threshold switch, the bidirectional threshold switch including a first threshold voltage distribution and a second threshold voltage distribution; applying a ramp voltage to a word line coupled to the reference memory cell and the data memory cells; determining that the reference memory cell has switched from a non-conductive state to a conductive state; stopping the ramp voltage for a first predetermined delay time after the reference memory cell switches from the non-conductive state to the conductive state; and reading the plurality of data memory cells with the stopped ramp voltage.

[0168] For the purposes of this article, if zero or one intermediate layer is between the first and second layers, then the first layer may be above or above the second layer.

[0169] For the purposes of this article, it should be noted that the dimensions of the various features depicted in the accompanying drawings are not necessarily drawn to scale.

[0170] For the purposes of this document, references to “an implementation scheme,” “one implementation scheme,” “some implementation schemes,” or “another implementation scheme” in the specification may be used to describe different implementation schemes and do not necessarily refer to the same implementation scheme.

[0171] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via another part). In some cases, when an element is mentioned as being connected to or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via an intermediary element. When an element is mentioned as being directly connected to another element, there is no intermediary element between the element and the other element.

[0172] For the purposes of this document, the term “based on” may be understood as “at least partially based on”.

[0173] For the purposes of this document, the use of numerical terms such as “first” object, “second” object, and “third” object without additional context may not imply an order of objects, but may be used for identification purposes to distinguish different objects.

[0174] For the purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

[0175] Although the subject matter has been described in language specific to structural features and / or methodological actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms for implementing the claims.

Claims

1. An apparatus comprising: a memory array including a first memory cell and a second memory cell, the first memory cell including a first two-terminal element having a first threshold voltage and a second threshold voltage, the second memory cell including a second two-terminal element having a third threshold voltage and a fourth threshold voltage; and control circuitry coupled to the memory array, the control circuitry configured to: apply a first voltage signal to the first memory cell to cause the first two-terminal element to have the first threshold voltage; apply a second voltage signal to the second memory cell to cause the second two-terminal element to have the third threshold voltage or the fourth threshold voltage; apply a third voltage signal to the first memory cell and the second memory cell, the third voltage signal increasing at a first ramp rate; determine that the first memory cell switches from a non-conductive state to a conductive state; and read the second memory cell using the third voltage signal a first predetermined delay time after the first memory cell switches from the non-conductive state to the conductive state.

2. The apparatus of claim 1, wherein the control circuitry is further configured to cause the third voltage signal to change to a second ramp rate that is lower than the first ramp rate when the first memory cell switches from the non-conductive state to the conductive state.

3. The apparatus of claim 1, wherein the control circuitry is further configured to cause the third voltage signal to stop increasing the first predetermined delay time after the first memory cell switches from the non-conductive state to the conductive state.

4. The apparatus of claim 1, wherein: the first memory cell is configured to read using a read voltage that includes a first polarity; and the first two-terminal element has the first threshold voltage when previously written to using a write signal that includes the first polarity, and the first two-terminal element has the second threshold voltage when previously written to using a write signal that includes a second polarity that is opposite the first polarity.

5. The apparatus of claim 4, wherein: the second memory cell is configured to read using a read voltage that includes the first polarity; and the second two-terminal element has the third threshold voltage when previously written to using a write signal that includes the first polarity, and the second two-terminal element has the fourth threshold voltage when previously written to using a write signal that includes the second polarity.

6. The apparatus of claim 1, wherein: the first threshold voltage and the third threshold voltage include a first threshold voltage distribution; and the second threshold voltage and the fourth threshold voltage include a second threshold voltage distribution.

7. The apparatus of claim 1, wherein: the first threshold voltage is lower than the second threshold voltage; and the third threshold voltage is lower than the fourth threshold voltage. The third threshold voltage is lower than the fourth threshold voltage.

8. The apparatus of claim 1, wherein: the first threshold voltage and the second threshold voltage drift after writing to the first memory cell; and the third threshold voltage and the fourth threshold voltage drift after writing to the second memory cell.

9. The apparatus of claim 8, wherein the first threshold voltage, the second threshold voltage, the third threshold voltage, and the fourth threshold voltage drift at substantially the same rate.

10. The apparatus of claim 1, wherein the first two-terminal element and the second two-terminal element each comprise a selector material that provides bidirectional current flow when the current or voltage exceeds a threshold.

11. The apparatus of claim 1, wherein the first two-terminal element and the second two-terminal element each comprise a chalcogenide material.

12. The apparatus of claim 1, wherein the first two-terminal element and the second two-terminal element each comprise one or more of a GeSeAs alloy, a GeSeAsTe alloy, a GeTeAs alloy, a GeSeTe alloy, a GeSe alloy, a SeAs alloy, an AsTe alloy, a GeTe alloy, a SiTe alloy, a SiAsTe alloy, and a SiAsSe alloy.

13. The apparatus of claim 1, wherein the first two-terminal element and the second two-terminal element each comprise a bidirectional threshold switch.

14. A system comprising: a plurality of data modules, each data module comprising a plurality of data memory cells, each data memory cell comprising a bidirectional threshold switch comprising a first threshold voltage distribution and a second threshold voltage distribution; a first reference module comprising a first plurality of first reference memory cells, each first reference memory cell comprising a bidirectional threshold switch comprising a first reference threshold voltage distribution; a plurality of word lines coupled to the plurality of data memory cells and the first plurality of first reference memory cells; a voltage ramp control circuit coupled to the plurality of data modules and the first reference module, the voltage ramp control circuit configured to generate a ramp output voltage; and a control circuit coupled to the plurality of data modules, the first reference module, and the voltage ramp control circuit, the control circuit configured to: couple the ramp output voltage to selected data memory cells from each of the plurality of data modules and to a selected first reference memory cell from the first reference module; determine that the selected first reference memory cell switches from a non-conductive state to a conductive state; and first read each of the selected data memory cells using the ramp output voltage a first predetermined delay time after the selected first reference memory cell switches from the non-conductive state to the conductive state.

15. The system of claim 14, further comprising: a second reference module comprising a second plurality of second reference memory cells, each second reference memory cell comprising a bidirectional threshold switch comprising a second reference threshold voltage distribution; wherein the control circuit is further configured to: couple the ramp output voltage to a selected second reference memory cell from the second reference module; determine that the selected first reference memory cell switches from a non-conductive state to a conductive state; and second read each of the selected data memory cells using the ramp output voltage a first predetermined delay time after the selected second reference memory cell switches from the non-conductive state to the conductive state.

16. The system of claim 15, wherein the second read occurs before the first read.

17. The system of claim 15, wherein the first read comprises a first error rate and the second read comprises a second error rate higher than the first error rate.

18. The system of claim 14, wherein each bidirectional threshold switch comprises a chalcogenide material.

19. The system of claim 14, wherein each bidirectional threshold switch comprises one or more of a GeSeAs alloy, a GeSeAsTe alloy, a GeTeAs alloy, a GeSeTe alloy, a GeSe alloy, a SeAs alloy, an AsTe alloy, a GeTe alloy, a SiTe alloy, a SiAsTe alloy, and a SiAsSe alloy.

20. A method comprising: writing a reference memory cell to a first memory state and writing data to a plurality of data memory cells, the reference memory cell and the data memory cells each comprising a bidirectional threshold switch comprising a first threshold voltage distribution and a second threshold voltage distribution; applying a ramp voltage to a word line coupled to the reference memory cell and the data memory cells; determining that the reference memory cell has switched from a non-conductive state to a conductive state; stopping the ramp voltage a first predetermined delay time after the reference memory cell switches from the non-conductive state to the conductive state; and reading the plurality of data memory cells with the stopped ramp voltage.

21. The method of claim 20, wherein the first threshold voltage distribution comprises a first threshold voltage and a first threshold voltage distribution width, and the second threshold voltage distribution comprises a second threshold voltage and a second threshold voltage distribution width.

22. The method of claim 20, wherein the first threshold voltage is lower than the second threshold voltage.

23. The method of claim 20, wherein the first threshold voltage distribution width is greater than the second threshold voltage distribution width.

24. The method of claim 20, wherein the first threshold voltage is lower than the second threshold voltage and the first threshold voltage distribution width is greater than the second threshold voltage distribution width.

25. The method of claim 20, wherein the first threshold voltage is lower than the second threshold voltage and the first threshold voltage distribution width is less than the second threshold voltage distribution width.

26. The method of claim 20, wherein the first threshold voltage is greater than the second threshold voltage and the first threshold voltage distribution width is greater than the second threshold voltage distribution width.

27. The method of claim 20, wherein the first threshold voltage is greater than the second threshold voltage and the first threshold voltage distribution width is less than the second threshold voltage distribution width.

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