Shift register realized based on balanced three-valued D flip-flop

Abstract

The invention discloses a shift register realized based on a balanced three-valued D flip-flop, the D flip-flop comprises a standard three-valued inverter STI, two balanced three-valued AND gates TMIN and a balanced three-valued OR gate TMAX, the output ends of the two TMINs are respectively connected to the two input ends of the TMAX, and the output end of the TMAX outputs signals; one input end of the first TMIN is connected with the output end of the TMAX, and the other input end of the first TMIN is connected with the output end of the STI; one input end of the second TMIN is connected with a trigger signal, and the other input end of the second TMIN is connected with an input signal; the STI input end is connected with a trigger signal; the balanced three-valued shift register comprises four D triggers, and the output ends and the input ends of the adjacent D triggers are connected. The shift register disclosed by the invention is simple in structure and easy to realize, can be used for multi-valued digital logic operation, and realizes two modes of serial input-serial output and serial input-parallel output.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of circuit design, and relates to a ternary digital logic circuit structure, in particular to a shift register realized based on a balanced ternary D flip-flop. BACKGROUND

[0002] A traditional digital system is constructed based on binary, and only logic 0 and logic 1 are contained in the logic variable. With the development and attention of multivalued logic, in recent years, research and implementation of ternary logic have become a research hotspot. Ternary can carry more information than binary under the same number of bits, which directly leads to that application of ternary logic can effectively reduce the number of interconnection lines in the circuit, the complexity of circuit design and the chip area.

[0003] With the progress of technology, more and more methods for realizing ternary logic circuits are available. From the 1980s, CMOS technology introduced the first ternary logic gate, to new circuit devices such as FETS used for ternary logic circuit design, various design methods have been gradually proposed, but the defects of complex circuit structure, multiple application devices and high interconnection complexity in the design of ternary logic circuits have not been solved, and the main reason is that switching devices do not have an advantage in the design of ternary logic circuits.

[0004] Memristor has the advantages of non-volatility, nanoscale size and variable resistance, and currently has wide application prospects in the fields of analog circuit design, non-volatile storage, neural networks and digital logic. The memristor with binary variable characteristics has a natural advantage in designing ternary logic circuits. This kind of memristor can switch between two resistance states without additional hardware assistance. At the same time, the memristor is compatible with standard CMOS technology, so the memristor provides a new opportunity for the development and design of new functions of ternary logic circuits.

[0005] The existing ternary D flip-flop is designed on the basis of an SR latch, resulting in too many required components, which is more unfavorable for the design and integration of ternary complex sequential circuits. SUMMARY

[0006] In view of the defects of the prior art, the application provides a shift register realized based on a balanced ternary D flip-flop, which can be used for multivalued digital logic operation, can realize serial input-serial output and serial input-parallel output two modes, and has wide application prospects.

[0007] A balanced ternary D flip-flop comprises a standard ternary inverter STI, two balanced ternary AND gates TMIN and a balanced ternary OR gate TMAX, the outputs of the two balanced ternary AND gates TMIN are connected to the inputs of TMAX, and the output of TMAX outputs a signal Q; the two inputs of one balanced ternary AND gate TMIN are connected to the output of TMAX and the output of STI respectively; the two inputs of the other balanced ternary AND gate TMIN are connected to a trigger signal CP and an input signal D respectively; the input of STI is connected to the trigger signal CP.

[0008] Preferably, the standard ternary inverter STI comprises two memristors M1 and M2, the negative electrode of M1 is connected to a power supply V DD , the positive electrode of M1 is connected to the drain of an NMOS transistor T2, which is the output of STI; the positive electrode of M2 is connected to the drain of an NMOS transistor T1, and the negative electrode of M2 is connected to the positive electrode of M1; the sources of T1 and T2 are connected to a power supply -V DD , and the gates of T1 and T2 are connected, which are the input of STI.

[0009] Preferably, the balanced ternary AND gate TMIN comprises two memristors M3 and M4, the positive electrodes of M3 and M4 are connected and lead to the output of TMIN, and the negative electrodes of M3 and M4 lead to the input of TMIN.

[0010] Preferably, the balanced ternary OR gate TMAX comprises two memristors M7 and M8, the negative electrodes of M7 and M8 are connected and lead to the output of TMAX, and the positive electrodes of M7 and M8 lead to the two inputs of TMAX.

[0011] The application further discloses a balanced ternary shift register based on binary memristors, which comprises four balanced ternary D flip-flops as D1, D2, D3 and D4, the output input terminals of adjacent balanced ternary D flip-flops are connected, the balanced ternary D flip-flops are connected to a trigger signal CP, the total input of the balanced ternary shift register is D in (in other words, the input of flip-flop D1), and the total output of the balanced ternary shift register is D out (in other words, the output of flip-flop D4), which can realize two modes of serial input-serial output and serial input-parallel output.

[0012] The application also discloses a working method of the balanced ternary shift register based on the binary memristor.

[0013] Beneficial effects

[0014] The application discloses a balanced ternary D flip-flop based on a binary memristor and a 4-bit shift register circuit model comprising the flip-flop, which is clear and simple in structure and easy to realize, is inspired from a traditional binary D flip-flop, replaces a complex ternary SR latch with a simple NAND gate, greatly reduces the number of components, and facilitates the design of ternary sequential logic circuits. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 (a) is a memristor-based STI gate circuit schematic diagram of the application;

[0016] Figure 1 (b) is Figure 1 (a) corresponding circuit symbol;

[0017] Figure 2 (a) is a balanced ternary AND gate circuit schematic diagram based on a memristor of the application;

[0018] Figure 2 (b) is Figure 2 (a) corresponding circuit symbol;

[0019] Figure 3 (a) is a balanced ternary OR gate circuit schematic diagram based on a memristor of the application;

[0020] Figure 3 (b) is Figure 3 (a) corresponding circuit symbol;

[0021] Figure 4 (a) is a balanced ternary D flip-flop circuit schematic diagram based on a memristor of the application;

[0022] Figure 4 (b) is a balanced ternary D flip-flop circuit block diagram based on a memristor of the application;

[0023] Figure 4 (c) is Figure 4 (a) the corresponding circuit symbol;

[0024] Figure 5 (a) is the balanced ternary memristor-based 4-bit shift register circuit block diagram of the present application;

[0025] Figure 5 (b) is Figure 5 (a) the corresponding circuit symbol. DETAILED DESCRIPTION

[0026] The technical solutions of the present application will be described in detail below with reference to the accompanying drawings.

[0027] Example 1:

[0028] A D flip-flop, as shown in Figure 4 (b), includes a standard ternary inverter STI, two balanced ternary AND gates TMIN (hereinafter referred to as first TMIN and second TMIN) and a balanced ternary OR gate TMAX. The outputs of the two balanced ternary AND gates TMIN are respectively connected to the two input terminals of TMAX, and the output terminal of TMAX outputs a signal Q; the two input terminals of the first TMIN are respectively connected to the output signal Q of TMAX and the output signal of STI; the two input terminals of the second TMIN are respectively connected to a trigger signal CP and an input signal D; the input terminal of STI is connected to the trigger signal CP.

[0029] The definition voltage V DD is 1V, corresponding to logic 1, and the voltage -V DD is -1V, corresponding to logic -1, and GND is 0V, corresponding to logic 0.

[0030] The standard ternary inverter STI circuit is composed of two memristors M1, M2 and two NMOS tubes T1, T2. As shown in Figure 1 (a), Figure 1 (b), wherein the negative electrode of the memristor M1 is connected to the power supply VDD, the positive electrode of the memristor M1 is connected to the drain of the NMOS tube T2 as an output terminal. The input terminal of the standard ternary inverter is connected to the gate of the NMOS tube T1 and the gate of the NMOS tube T2. The negative electrode of the memristor M2 is connected to the positive electrode of the memristor M1, and the positive electrode of the memristor M2 is connected to the drain of the NMOS tube T1. The sources of the NMOS tubes T1 and T2 are connected to the power supply -V DD . The threshold conduction voltage of the NMOS tube T1 is 0.5V, and the threshold conduction voltage of the NMOS tube T2 is 1.5V. For the standard ternary inverter, the non-logic of 1 is -1, the non-logic of -1 is 1, and the non-logic of 0 is 0.

[0031] The balanced ternary AND gate circuit is composed of two memristors. As shown inFigure 2 (a) Figure 2 As shown in (b), the negative terminal of memristor M3 serves as the first input terminal of the first TMIN. The positive terminal of memristor M3 is connected to the positive terminal of memristor M4, and an output terminal is drawn from it. The negative terminal of memristor M4 serves as the second input terminal of the first TMIN. The negative terminal of memristor M5 serves as the first input terminal of the second TMIN. The positive terminal of memristor M5 is connected to the positive terminal of memristor M6, and an output terminal is drawn from it. The negative terminal of memristor M6 serves as the second input terminal of the second TMIN.

[0032] A balanced ternary OR gate is composed of two memristors. For example... Figure 3 (a) Figure 3 As shown in (b), the positive terminal of memristor M7 is used as the first input terminal of the OR gate, the negative terminal of memristor M8 is connected to the negative terminal of memristor M7 and the output terminal is drawn out from it, and the positive terminal of memristor M8 is used as the second input terminal of the OR gate.

[0033] The output principle of balanced AND gates and OR gates is as follows: the AND gate is a minimum gate (TMIN), and its output is the minimum value of the two inputs; the OR gate is a maximum gate (TMAX), and similarly, its output is the maximum value.

[0034] like Figure 4 As shown in (a), the D flip-flop circuit structure is as follows: the positive terminal of memristor M1 is connected to the negative terminal of memristor M3. The gates of NMOS transistors T1 and T2, and the negative terminal of memristor M5 are connected as the trigger input terminal CP of the balanced ternary D flip-flop. The negative terminal of memristor M6 serves as the signal input terminal D of the balanced ternary D flip-flop. The negative terminals of memristors M7, M8, and M4 are connected as the signal output terminal Q of the balanced ternary D flip-flop. The circuit symbol corresponding to the D flip-flop is shown below. Figure 4 As shown in (c), it has an input terminal D, an output terminal Q, and a trigger terminal CP.

[0035] D flip-flops utilize the switching and memory characteristics of memristors to store and transmit digital signals.

[0036] The truth table for the balanced ternary D flip-flop is shown in Table 1 below:

[0037] Table 1

[0038] CP D Q’ -1 × Q 1 -1 -1 1 0 0 1 1 1

[0039] In the table, Q' is the next state of the flip-flop, representing the state after the flip-flop is triggered. CP and D are the input terminals. According to the truth table of the balanced three-value D flip-flop, it can be seen that when CP = 1, the balanced three-value D flip-flop can accept the input signal and set the output of the circuit to the corresponding state according to the input signal. When CP = -1, the balanced three-value D flip-flop stores the instantaneous state before the trigger signal is -1.

[0040] Example 2:

[0041] A balanced ternary shift register based on a binary memristor includes four D flip-flops as described in Embodiment 1: flip-flop D1, flip-flop D2, flip-flop D3, and flip-flop D4. The internal structure of each D flip-flop is as follows: Figure 4 As shown in (a). Figure 5 As shown in (a), four D flip-flops are connected in sequence. The input terminal of the first flip-flop D1 in the shift register circuit receives the input signal D. in The input of flip-flop D2 is connected to the output signal Q1 of D1. The inputs of the remaining flip-flops are all connected to the output Q of the previous flip-flop. That is, the input of flip-flop D3 is connected to the output Q2 of D2, the input of flip-flop D4 is connected to the output Q3 of D3, and the output of flip-flop D4 is the output signal Q4. out The CP terminals of four D flip-flops are connected together as trigger signal inputs to receive the trigger signal CP. The circuit can implement both serial input-serial output and serial input-parallel output modes. The circuit symbol for the shift register is shown below. Figure 5 As shown in (b).

[0042] Work style:

[0043] From the truth table of the D flip-flop in Example 1, we can obtain:

[0044] When the trigger signal CP of the D flip-flop is -1, the corresponding Figure 4 In (b), the inverter STI outputs 1, the AND gate U2 outputs -1, and the OR gate output depends on the AND gate U1. Since one of the inputs of the AND gate U1 is 1, the actual output depends on the previous state.

[0045] When the trigger signal CP of the D flip-flop is 1, the corresponding Figure 4 In (b), the inverter STI outputs -1 (inverting CP), the AND gate U1 outputs -1, and the OR gate output depends on the AND gate U2. Since one of the inputs of the AND gate U2 is 1, the actual output depends on the other input D of the AND gate U2.

[0046] Taking the input signals 1, 0, -1, 1 sequentially over 4 clock cycles as an example, the initial state of the shift register is (Q1, Q2, Q3, Q4) = (-1, -1, -1, -1). Under the action of the clock pulse, the output result of each D flip-flop after 4 clock cycles is (Q1, Q2, Q3, Q4) = (1, 0, -1, 1). The signal shifting in the shift register is shown in Table 2 below:

[0047] Table 2

[0048] CP D in ]]> Q1 Q2 Q3 Q4 1 1 1 -1 -1 -1 2 0 0 1 -1 -1 3 -1 -1 0 1 -1 4 1 1 -1 0 1

[0049] When the first clock pulse arrives, the initial state of all D flip-flops is "-1". The input terminal D1 of flip-flop D1 is then... in Input the first signal "1", i.e., D in =1. According to the working principle of a balanced ternary D flip-flop, when the clock signal is valid, the output signal of the D flip-flop is equal to the input signal. That is, at this time, flip-flop D1 flips and obtains the output state Q1 = 1. Due to the propagation delay, the input signal of flip-flop D2 still maintains the initial value of Q1, so the output state of flip-flop D2 remains unchanged, that is, Q2 = -1. Similarly, within the current clock pulse, the inputs of the next stage flip-flops D3 and D4 remain unchanged from the previous state, and the output state of both is "-1".

[0050] When the second clock pulse arrives, the second signal "0" is input, at which point flip-flop D1 is activated by D... in =0 control, output state Q1 = 0. Since the output state of flip-flop D1 was "1" in the previous clock cycle, the input signal of flip-flop D2 at the current moment is equal to the output Q1 of D1, which is state "1". Therefore, the output Q2 of flip-flop D2 is 1. The input signals of flip-flops D3 and D4 still maintain the value of Q2 from the previous moment, and the output remains in the "-1" state. Similarly, flip-flop D4 is affected by Q3, and the output remains unchanged.

[0051] When the third clock pulse arrives, the third signal "-1" is input. At this time, flip-flop D1 is affected by D... in =-1 control, output state Q1=-1. Since the output state of flip-flop D1 was "0" in the previous clock cycle, the input signal of flip-flop D2 at the current moment is equal to the output Q1 of D1, which is state "0". Therefore, the output Q2 of flip-flop D2 is 0. The input signal Q2 of flip-flop D3 became "1" in the previous pulse, so the output state Q3=1. The output of flip-flop D4 remains in the "-1" state.

[0052] When the fourth clock pulse arrives, the second signal "1" is input, at which point flip-flop D1 is activated by D... in=1 control, output state Q1=1. The input signal Q1 of flip-flop D2 becomes "-1" in the previous pulse, so the output state Q2=-1. The input signal Q2 of flip-flop D3 becomes "0" in the previous pulse, so the output state Q3=0. The input signal Q3 of flip-flop D4 becomes "1" in the previous pulse, so the output Q4=1. Flip-flop D4 outputs a "1" state.

[0053] Following this pattern, after four CP signals, the four-bit serial input signal (1, 0, -1, 1) is shifted into the shift register, and parallel output signals are obtained at the outputs Q1, Q2, Q3, and Q4 of the four flip-flops. Therefore, the balanced ternary shift register designed above can achieve serial-to-parallel conversion of ternary signals. Similarly, after three more CP signals, the four-bit serial input signal can be output at D... out (Q4) Serial output enables two modes of balanced three-value shift register: serial input-serial output and serial input-parallel output.

[0054] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. For those skilled in the art, various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention, and these variations still fall within the protection scope of the present invention.

Claims

1. A shift register implemented based on balanced ternary D flip-flops, characterized in that, The shift register comprises four balanced ternary D flip-flops D1, D2, D3, D4, the output input terminals of adjacent balanced ternary D flip-flops are connected, the D flip-flops are connected with a trigger signal CP, the total input of the shift register is D in , i.e. the input of the flip-flop D1, the total output is D out , i.e. the output of the flip-flop D4, realizing two modes of serial input-serial output and serial input-parallel output.

2. The shift register implemented based on balanced ternary D flip-flops according to claim 1, wherein, The balanced ternary D flip-flop comprises a standard ternary inverter STI, two balanced ternary AND gates TMIN and a balanced ternary OR gate TMAX. The outputs of the two balanced ternary AND gates TMIN are connected with the inputs of the balanced ternary OR gate TMAX, and the output end of the balanced ternary OR gate TMAX outputs a signal Q; the two input ends of one balanced ternary AND gate TMIN are connected with the output end of the balanced ternary OR gate TMAX and the output end of the standard ternary inverter STI respectively; the two input ends of the other balanced ternary AND gate TMIN are connected with a trigger signal CP and an input signal D respectively; and the input end of the standard ternary inverter STI is connected with the trigger signal CP.

3. The shift register implemented based on balanced ternary D flip-flops according to claim 2, wherein, The standard ternary inverter STI includes two memristors M1 and M2, the negative electrode of M1 is connected with a power supply V DD , the positive electrode of M1 is connected with the drain of NMOS T2 as the output of STI, the positive electrode of M2 is connected with the drain of NMOS T1, and the negative electrode of M2 is connected with the positive electrode of M1 DD , the sources of T1 and T2 are connected with a power supply -V, the gates of T1 and T2 are connected as the input of STI.

4. The shift register implemented based on balanced ternary D flip-flops according to claim 2, wherein, The balanced ternary AND gate TMIN comprises two memristors M3 and M4; the positive poles of the two memristors M3 and M4 are connected and lead to the output end of the balanced ternary AND gate TMIN, and the negative poles of the two memristors M3 and M4 lead to the input end of the balanced ternary AND gate TMIN.

5. The shift register implemented based on balanced ternary D flip-flops according to claim 2, wherein, The balanced ternary OR gate TMAX comprises two memristors M7 and M8; the negative poles of the two memristors M7 and M8 are connected and lead to the output end of the balanced ternary OR gate TMAX, and the positive poles of the two memristors M7 and M8 lead to the two input ends of the balanced ternary OR gate TMAX.

6. The shift register implemented based on balanced ternary D flip-flops according to claim 2, wherein, The shift register realizes the effect of right shifting the code stored in the shift register by one bit after obtaining a clock signal based on the principle of transmission delay of the balanced ternary D flip-flop; the initial state of the shift register (Q1, Q2, Q3, Q4) is (-1, -1, -1, -1), and after four CP signals, the four-bit signal input in series is all moved into the shift register, and the parallel output signal is obtained at the output ends Q1, Q2, Q3 and Q4 of the four balanced ternary D flip-flops.

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