A solid state disk high-write low-read and low-write high-read performance evaluation method

Abstract

The application relates to the technical field of data storage, and discloses a high-write-low-read and low-write-high-read performance evaluation method for a solid state disk, which comprises the following steps: preprocessing the solid state disk, and reading SMART data in the processed solid state disk; in a preset high-temperature environment, writing the SMART data into the preprocessed solid state disk and carrying out high-temperature baking for a preset time, rapidly transferring the solid state disk to a preset low-temperature environment for reading and data integrity checking after the baking time ends; in the preset low-temperature environment, writing the SMART data into the solid state disk after high-temperature testing, rapidly transferring the solid state disk to the preset high-temperature environment for reading and pressure testing, and carrying out bad block checking, SMART log analysis and data integrity checking on the solid state disk after low-temperature testing. The application realizes comprehensive evaluation of the performance of the solid state disk.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and in particular to a method for evaluating the performance of solid-state drives (SSDs) in terms of high write / low read and low write / high read. Background Technology

[0002] With the accelerating pace of informatization, solid-state drives (SSDs), as a high-performance, high-capacity storage medium, have been widely used in personal computers, servers, data centers, and other fields. SSDs offer numerous advantages, such as fast boot times, high file transfer speeds, and good application responsiveness, greatly improving computer performance and user experience. However, SSDs still face some challenges during use, particularly in terms of data retention and read / write stability.

[0003] Currently, solid-state drive (SSD) testing methods mainly focus on simple high and low temperature tests and full-disk write / read operations. These methods cannot effectively identify and filter out weak blocks, making it difficult to guarantee the reliability of products entering the market. Furthermore, existing testing software often only performs basic tests and cannot simulate complex scenarios in real-world applications for automated testing, making it difficult to comprehensively evaluate the performance and stability of SSDs. Summary of the Invention

[0004] This invention provides a method for evaluating the high write-low read and low write-high read performance of solid-state drives (SSDs), which can solve the technical problem that SSD testing methods cannot effectively identify and filter out relatively weak blocks (weak blocks), resulting in the reliability of products entering the market being difficult to guarantee.

[0005] To solve the above-mentioned technical problems, one technical solution adopted by the present invention is: to provide a method for evaluating the high write-low read and low write-high read performance of a solid-state drive, the method comprising:

[0006] Preprocess the solid-state drive and read the SMART data from the processed solid-state drive;

[0007] In a preset high-temperature environment, SMART data is written into the pre-processed solid-state drive and baked at high temperature for a preset time. After the baking time is over, the solid-state drive is quickly transferred to a preset low-temperature environment for reading and data integrity verification.

[0008] In a preset low-temperature environment, SMART data is written to the solid-state drive (SSD) after high-temperature testing. The SSD is then quickly transferred to a preset high-temperature environment for reading and stress testing. Bad block checks, SMART log analysis, and data integrity verification are performed on the SSD after the low-temperature test.

[0009] Based on predictive analysis using machine learning algorithms, the correlation between preprocessed SSD test data and SSD bad blocks and performance degradation after high and low temperature tests is established, and a data analysis platform is built by combining the analysis results.

[0010] The beneficial effects of this invention are as follows: By employing a full-chain verification method encompassing "aging preprocessing - multi-stress coupling - data inspection - deep diagnostics - predictive modeling," it overcomes the limitations of existing technologies in terms of single test scenarios and conditions, achieving a comprehensive evaluation of solid-state drive (SSD) performance. It not only identifies different types of bad blocks but also effectively filters out weak blocks with poor performance, improving the accuracy of product reliability assessment. The combination of enhanced high-write-low-read testing and enhanced low-write-high-read testing overcomes the limitations of traditional testing software that only performs basic tests, enabling automated testing of complex application scenarios. The multi-angle testing strategy allows for a comprehensive evaluation of SSD performance and stability. Through methods such as establishing attenuation baselines, robustness scoring, and predictive analysis, the test results are analyzed in depth and processed intelligently, providing reliable reliability difference assessments for SSDs of different brands and batches. This not only improves the accuracy of test results but also provides users with reliable reference data support. By performing a full-chain verification process including aging preprocessing, multi-stress coupling, data inspection, and deep diagnostics on SSDs, the reliability and lifespan of SSDs are comprehensively evaluated. This series of systematic testing methods effectively improves product quality and reliability, providing users with more comprehensive and reliable test results. By employing various stress coupling strategies during the testing process, such as writing specific data patterns under high-temperature conditions and simulating power instability, different types of error mechanisms can be effectively activated, helping users quickly discover and locate potential faults in solid-state drives, thus improving the comprehensiveness and relevance of the testing. Attached Figure Description

[0011] Figure 1 This is a flowchart illustrating the solid-state drive high write / low read and low write / high read performance evaluation method according to the first embodiment of the present invention.

[0012] Figure 2 yes Figure 1 A flowchart illustrating step 1.

[0013] Figure 3 yes Figure 1 A flowchart illustrating step 2.

[0014] Figure 4 yes Figure 1 A flowchart illustrating step 3.

[0015] Figure 5 yes Figure 1 A flowchart illustrating step 4. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0017] The terms "comprising" and "having," and any variations thereof, used in this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0018] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0019] Figure 1 This is a flowchart illustrating the solid-state drive high-write-low-read and low-write-high-read performance evaluation method according to the first embodiment of the present invention. Figure 1 As shown, the system includes hardware and software components:

[0020] Step 1: Preprocess the solid-state drive and read the SMART data from the processed solid-state drive;

[0021] Step 2: In a preset high-temperature environment, write the SMART data into the pre-processed solid-state drive and bake it at high temperature for a preset time. After the baking time is over, quickly transfer the solid-state drive to a preset low-temperature environment for reading and data integrity verification.

[0022] Step 3: In a preset low-temperature environment, write SMART data into the solid-state drive after the high-temperature test. Then, quickly transfer the solid-state drive to a preset high-temperature environment for reading and stress testing. Perform bad block checks, SMART log analysis, and data integrity verification on the solid-state drive after the low-temperature test.

[0023] Step 4: Based on machine learning algorithms, predictively analyze the correlation between the preprocessed solid-state drive test data and the occurrence of bad blocks and performance degradation in solid-state drives after high-temperature and low-temperature tests, and establish a data analysis platform by combining the analysis results.

[0024] In the SSD preprocessing and SMART data reading stages, to eliminate the interference of abnormal initial SSD conditions on test results, the specific operations can be broken down as follows: First, format the SSD (it is recommended to use the file system corresponding to the target application scenario, such as NTFS, EXT4, etc.), and then perform a full disk read / write erase operation to clear residual factory data and fragmentation information; then check if the SSD has initial bad blocks, and if so, directly discard the sample to avoid affecting the accuracy of the test. In the SMART data reading stage, professional tools (such as CrystalDiskInfo, smartmontools, etc.) can be used to extract key parameters, such as cumulative power-on time, write volume, bad block count, temperature records, flash wear, and other core indicators, as baseline data for subsequent tests.

[0025] In high-temperature baking tests and low-temperature calibrations, the preset high temperature needs to be set according to the actual application scenario of the SSD. For example, industrial-grade SSDs can be set to 70-85℃, and consumer-grade SSDs to 50-65℃. The environment can be built using a constant temperature oven. After writing the SMART data read in step 1 and the supplementary test data package to the SSD, bake it for a preset time (e.g., 2-48 hours, adjusted according to the severity of the test). After baking, it needs to be quickly transferred to a preset low-temperature environment (e.g., -10-0℃ for consumer-grade and -20-40℃ for industrial-grade). This low-temperature environment can be built using a low-temperature test chamber. Immediately read the data in the SSD in the low-temperature environment, and verify whether the data is lost or corrupted by comparing MD5 values ​​and using file integrity verification tools. At the same time, read the SMART data again and record the parameter changes after the high temperature.

[0026] In the low-temperature write and high-temperature stress tests and multi-dimensional verification, the SMART data and test data were first rewritten in the preset low-temperature environment of step 2. Then, the SSD was quickly transferred to the preset high-temperature environment of step 2, and stress tests were initiated, such as performing high IOPS (input / output operations per second) and high-throughput continuous read / write tasks using the FIO tool. After the test, three layers of verification were performed: the SSD detection tool was used to scan for bad blocks and record the number and location of newly added bad blocks; the SMART log was analyzed, focusing on comparing the differences between indicators such as wear and error count and the benchmark data; and finally, the data was verified again using a data verification tool to confirm that the data was not damaged or lost.

[0027] In building the machine learning modeling and data analysis platform, the first step is to organize the dataset, covering baseline data from the SSD preprocessing stage, bad block data after high and low temperature testing, performance parameters (such as read / write speed and latency), and changes in the SMART metric. Labels are also provided indicating whether samples contain bad blocks and the degree of performance degradation. Next, appropriate machine learning algorithms are selected, such as logistic regression and random forests to determine the probability of bad blocks, and linear regression and gradient boosting models to analyze the correlation between SMART data and performance degradation. Training and test sets are then divided, and the models are trained and optimized to improve prediction accuracy. Finally, a data analysis platform is built, integrating data acquisition, model prediction, and result visualization modules to enable real-time test data entry, anomaly alerts, and automatic test report generation.

[0028] It is important to note that temperature fluctuations in high and low temperature environments must be controlled within ±1℃ to avoid instability leading to distorted test results. SSD transfer should be fast to minimize interference from ambient temperature. To ensure the reliability of the machine learning model, SSDs of different brands, capacities, and flash memory types (such as TLC and QLC) need to be tested to accumulate sufficient sample data and avoid overfitting due to a single sample. During high and low temperature testing, SSDs must be protected with anti-static and anti-condensation devices. For example, in low-temperature environments, condensation on the SSD surface should be prevented from damaging components. Test interfaces must use dedicated high / low temperature resistant connectors. The number of high and low temperature cycles (e.g., 10-10000 cycles) can be increased between steps 2 and 3 to simulate long-term SSD usage in fluctuating temperature environments and obtain more comprehensive aging data. In addition to bad blocks and data integrity, tests of detailed performance indicators such as read / write latency fluctuations and IOPS decay curves can be added to make model analysis more detailed. A model iteration module should be added to the data analysis platform to periodically update model parameters as subsequent test data accumulates, improving prediction accuracy and generalization ability.

[0029] Figure 2 yes Figure 1 The flowchart for step 1 is as follows: Figure 2 As shown, step 1 includes: Step 101, performing a light aging process on the solid-state drive (SSD) and conducting a full disk erase / write cycle within a preset number of cycles based on the queue depth and block size for random write and random read operations; Step 102, performing an RDT test on the aged SSD at room temperature and measuring its read and write performance; Step 103, recording the RDT test and read / write performance as baseline performance data for measuring the aged SSD at room temperature, reading SMART data from the aged SSD, and recording the ECC error correction count, average read / write latency, and erase count metrics.

[0030] Step 101: The core of mild aging treatment is to simulate the initial wear and tear of a solid-state drive (SSD) and eliminate the interference of "factory status fluctuations" on the test. The following parameters need to be clearly defined: 1. In the random read / write parameter settings, queue depth (QD): It is recommended to cover actual application scenarios. For example, QD1-QD32 is commonly used in consumer-grade scenarios, while QD64-QD128 can be set for industrial-grade high-concurrency scenarios; block size: use mixed block sizes to simulate real load, such as randomly mixing 4KB (small files), 128KB (medium files), and 1MB (large files) blocks, with a ratio of 7:2:1; - number of full erase / write cycles: adjust according to the SSD type. For consumer-grade TLC / QLC, 3-5 P / E cycles are recommended (to ensure a stable state), while for industrial-grade MLC, 5-10 cycles can be set to avoid excessive aging affecting subsequent tests. Tool selection: It is recommended to use FIO or Iometer to control the "random write → random read → full erase" cycle through scripts, ensuring that each cycle covers 100% of the capacity. 2. Aging process monitoring: During the aging process, the SSD temperature (controlled at room temperature 25±2℃ to avoid self-heating affecting the uniformity of aging) and instantaneous read / write speed fluctuations need to be recorded in real time. If abnormal speed drop or error occurs, the sample should be removed directly to ensure the initial consistency of subsequent test samples.

[0031] Step 102: Technical Details of RDT Testing and Read / Write Performance Measurement RDT (Read Disturbance Test) is crucial for verifying the data stability of an SSD under high-frequency reads. It needs to be combined with regular read / write performance tests to form a complete baseline performance profile: 1. RDT Test Specification - Test Logic: Perform continuous high-frequency reads on the target block (e.g., 1000 times per second) while monitoring the data integrity of adjacent blocks for a preset time (e.g., 2 hours); Judgment Criteria: If data flipping occurs in adjacent blocks (detectable through verification and comparison), record the interference threshold as the baseline for the SSD's resistance to read interference; Tool Support: Can be executed using dedicated testing tools provided by SSD manufacturers (e.g., Intel SSD Toolbox advanced mode) or open-source tools (e.g., the built-in interference test module of nvme-cli). 2. Read / Write Performance Measurement Dimensions: Performance metrics across multiple scenarios must be covered to ensure comprehensive baseline data: Throughput: Maximum throughput (MB / s) for sequential read / write (128KB blocks) and random read / write (4KB blocks); Response Time: Average read / write latency (μs) at different queue depths, 99.9% percentile latency (reflecting performance in extreme scenarios); IOPS: Read / write IOPS values ​​for random 4KB blocks at QD1, QD32, and QD128, reflecting concurrent processing capabilities. Tests should be repeated three times and the average value taken to reduce random errors from a single test.

[0032] Step 103: Core Indicators and Correlation Analysis of Baseline Data Recording: The recorded data needs to serve the subsequent comparative analysis of "performance degradation after high and low temperature testing". Focus on the following indicators and their inherent correlations: 1. SMART Data Core Items: ECC Error Correction Count: including "Raw Read Error Rate" and "Number of Successful ECC Error Correction", reflecting the initial data stability of NAND flash memory; Erase Count: focusing on recording "Total Erase Count" and "Max Erase Count Block", reflecting the wear distribution after aging; Other Key Items: Add "Reserved Block Count" (reflecting initial redundancy capability) and "HostWrites" (calibrating the degree of aging). 2. When recording the correlation between performance metrics and SMART data, a corresponding relationship needs to be established. For example: the correlation between average read / write latency and "erase count" (for the same SSD, a higher number of erases may slightly increase latency); the correlation between ECC error correction count and RDT test results (if there is slight interference in the RDT, it may be accompanied by an increase in the number of ECC error corrections). These correlations will provide the basic logic of "feature-label" for subsequent machine learning models (e.g., whether an SSD with a high ECC count baseline is more prone to bad blocks in high and low temperature tests).

[0033] It is important to note that the entire Step 1 must be conducted in a strictly ambient temperature (25±1℃) environment free from electromagnetic interference to avoid temperature fluctuations affecting the accuracy of performance measurements. Each SSD sample must have an independent file containing the complete chain of "aging parameters → RDT results → performance data → SMART logs," with the recommended naming format being "Brand-Capacity-Model-Aging Cycles-Test Time." If severe interference occurs in the RDT test after aging (e.g., data errors occur before the preset time is reached) or initial warnings appear in the SMART logs (e.g., insufficient spare blocks), the sample must be discarded to ensure the "defect-free" baseline data. Through these detailed steps, Step 1 provides a precise "baseline" for subsequent high and low temperature tests, ensuring that differences in test results are attributable to environmental stress, rather than differences in the initial state of the SSD.

[0034] Figure 3 yes Figure 1 The flowchart for step 2 is as follows: Figure 3As shown, step 2 includes: Step 201, setting test environment parameters, including temperature controller, power supply voltage regulator, and programmable logic device; Step 202, in a preset high-temperature environment, writing SMART data into the pre-processed solid-state drive according to a verifiable pseudo-random data pattern (such as alternating 0x55, 0xAA, and 0xFF), and recording the CRC32 or SHA256 checksum of each logical block address (LBA) in the pre-processed solid-state drive; Step 203, continuously baking the solid-state drive storing SMART data in a preset high-temperature environment for a preset time; Step 204, after the baking time is over, quickly transferring the solid-state drive to a preset low-temperature environment and performing a read test according to the intelligent data inspection mode. The read test includes at least sequential read, random read, and data integrity verification, and records the number of silent errors and uncorrectable errors.

[0035] Step 201: Test Environment Parameter Setting and Equipment Debugging: The core of this step is to build a stable and controllable test environment to avoid equipment fluctuations affecting test results. Specific details are as follows: 1. Temperature Controller and Environment Setup: Select a high-precision programmable constant temperature oven (high temperature end) and a low-temperature test chamber (low temperature end). The temperature controller accuracy must reach ±0.5℃, supporting the setting of fixed temperatures and constant temperature durations. The high-temperature preset must match the SSD type; for consumer-grade SSDs, 55-65℃ is recommended, and for industrial-grade, 75-85℃ is recommended. The low-temperature preset can be set to -10-0℃ for consumer-grade and -30-20℃ for industrial-grade. Simultaneously, the two environments should be placed adjacent to each other to shorten SSD transfer time (recommended transfer time ≤10 seconds) and reduce interference from room temperature exposure. 2. Power Supply Voltage Regulator Configuration: Considering that high-temperature environments may affect power supply stability, a high-precision DC power regulator needs to be connected. The output voltage should match the SSD interface standard (e.g., SATA interface 5V, NVMe interface 12V / 3.3V), with voltage fluctuations controlled within ±0.01V. In addition, overcurrent and overvoltage protection functions must be enabled to prevent SSD damage due to abnormal voltage. Power consumption data throughout the test should also be recorded as an auxiliary analysis indicator. 3. Role and Debugging of Programmable Logic Devices (PLDs): PLDs are used to automate data writing and reading, and to monitor data in real time, improving test efficiency and accuracy. Two configurations need to be completed during debugging: first, write a logic program to control data to be written to the SSD in batches according to a preset pseudo-random mode, and simultaneously record the write timing of each LBA; second, establish a data transmission channel to ensure that the communication latency between the PLD, SSD, and verification module is ≤1ms, avoiding errors in verification value recording due to transmission delays.

[0036] Step 202: Pseudo-random Data Writing and Checksum Recording: The key to this step is to provide a clear basis for subsequent integrity verification through a verifiable data pattern, avoiding data errors and misjudgments. The specific operations are as follows: 1. Execution of the pseudo-random data pattern: An alternating pattern of 0x55, 0xAA, and 0xFF is used, which simulates the randomness of real data while facilitating rapid verification. The data can be written in a cycle of "0x55 (100 LBAs) → 0xAA (100 LBAs) → 0xFF (100 LBAs)" to cover all LBAs of the SSD. The writing tool can be combined with a custom script from the PLD or a professional tool with a custom data pattern (such as the custom write function of HD TunePro). 2. Precise recording of checksums: A CRC32 or SHA256 checksum is calculated separately for each LBA. CRC32 is suitable for scenarios where efficiency is paramount, while SHA256 is suitable for scenarios requiring extremely high verification accuracy. It is recommended to create a two-dimensional data table to record "SSD number - LBA address - write data mode - checksum - write time", and store it as an encrypted CSV file to prevent data tampering and provide corresponding baseline data for subsequent verification.

[0037] Step 203: Continuous High-Temperature Baking Process Control. The core of high-temperature baking is to simulate the long-term storage scenario of SSDs under extreme high temperatures. It is necessary to control the duration and environmental stability. Specific points are as follows: 1. Baking Duration Setting: Adjust according to the test objectives. If testing the short-term effects of high temperatures, set it to 2-8 hours; if simulating long-term high-temperature aging, set it to 24-48 hours. For industrial-grade SSDs, it can be extended to 72 hours to enhance the test's rigor. 2. Baking Process Monitoring: During baking, record the internal temperature in real time using a temperature controller, saving temperature data every 5 minutes. If the temperature fluctuation exceeds ±1℃, the test must be paused and equipment malfunctions investigated. Simultaneously, monitor the SSD's standby current using a PLD or power regulator. If the current abnormally increases, it may indicate overheating of internal components of the SSD, requiring immediate removal and marking as an abnormal sample.

[0038] Step 204: The read test after rapid cooling is crucial for verifying the impact of sudden temperature changes on data and read performance. It needs to comprehensively cover different read scenarios and error types. Specific operations are as follows: 1. Execution of Intelligent Data Inspection Mode: After entering a low-temperature environment, immediately start the read test to prevent the SSD temperature from rising again. Sequential reads read all data on the disk in ascending LBA order to verify continuous read stability; random reads sample 10% of the LBAs and randomly select addresses to read, simulating fragmented read scenarios. During the read process, the read rate is controlled via PLD to match typical usage scenarios (e.g., SATA SSD read rate controlled at around 500MB / s). 2. Data Integrity and Error Count: After reading each LBA, recalculate the checksum and compare it with the baseline value recorded in step 202. If they do not match, it is considered a data error. Simultaneously, distinguish between two types of critical errors: silent errors refer to data errors that the SSD does not actively report, which need to be detected through checksum comparison; uncorrectable errors refer to data errors that the SSD's own ECC error correction mechanism cannot recover from after attempting repair, which can be obtained by reading the "Uncorrectable Error Count" in SMART. Finally, the number of the two types of errors, the corresponding LBA addresses, and the read timing when the errors occurred are summarized to form a complete error report, providing a basis for subsequent correlation analysis.

[0039] Figure 4 yes Figure 1 The flowchart for step 3 is as follows: Figure 4 As shown, step 3 includes: Step 301: In a preset low-temperature environment, SMART data is written to the pre-processed solid-state drive according to a verifiable pseudo-random data pattern (such as alternating 0x55, 0xAA, and 0xFF), and the CRC32 or SHA256 check value of each logical block address (LBA) in the pre-processed solid-state drive is recorded; Step 302: The solid-state drive is quickly transferred to a preset high-temperature environment, and a full disk read is performed in a loop, with small amounts of random data written between each read interval; Step 303: Bad block checks, SMART log analysis, and data integrity verification are performed on the solid-state drive after the low-temperature test.

[0040] Step 3, through the process of "low-temperature writing → high-temperature read / write cycle → multi-dimensional verification," further verifies the stability of the SSD under sudden temperature increases and mixed read / write pressure, serving as a reverse complement and stress reinforcement to Step 2. Step 301: Data Writing and Verification Benchmark Establishment in Low-Temperature Environments. Low-temperature environments affect the charge retention capability of NAND flash memory and the operating efficiency of the controller. This step must ensure the stability of the writing process and establish an accurate benchmark for subsequent verification: 1. Low-Temperature Writing Environment Control - The ambient temperature must be consistent with the preset low temperature in Step 2 (e.g., consumer-grade -10~0℃, industrial-grade -30~-20℃), and the SSD should be placed in only after it has stabilized (it is recommended to start operation after maintaining a constant temperature for 30 minutes) to avoid writing abnormalities caused by temperature fluctuations during the device's cooling process. - Before writing, the low-temperature activation status of the SSD must be detected using PLD or a dedicated tool: Some SSDs may trigger protection mechanisms (such as speed reduction or temporary locking) at low temperatures. It is necessary to confirm that it has entered normal working mode before performing the write operation (this can be confirmed by reading the "Temperature Status" in SMART). 2. Pseudo-random Data Writing and Checksum Recording - The data pattern follows the alternating 0x55, 0xAA, and 0xFF pattern from step 202. However, note that NAND programming speed may decrease at low temperatures (especially QLC / TLC), so the write rate should be appropriately reduced (e.g., controlled at 70% of the room temperature write speed) to avoid write failures due to timeouts. A "write latency" parameter needs to be added to the checksum record: the write time (μs) for each LBA record should be compared with the write latency at room temperature to analyze the immediate impact of low temperature on write performance (e.g., whether the latency doubles or whether there are abnormal fluctuations). The data table format can reuse the structure from step 202, but it needs to be labeled "Low Temperature Write" to distinguish it from high temperature write data.

[0041] Step 302: In the high-temperature environment cyclic read / write stress test, after a sudden transition from low to high temperature, the internal components of the SSD (such as the controller, cache, and NAND) experience drastic temperature changes. The mixed read / write operations at this time can simulate actual loads under extreme scenarios. It is crucial to control the cyclic logic and stress intensity: 1. Transfer and test start timing – The transfer time must be consistent with step 204 (≤10 seconds) to ensure consistency in temperature changes; after entering the high-temperature environment, start the test immediately (delay ≤30 seconds) to prevent the SSD from stabilizing due to being left idle at high temperatures, thus mitigating the impact of the sudden change. The high-temperature environment parameters must be consistent with the preset high temperature in step 2 (e.g., consumer-grade 55~65℃, industrial-grade 75~85℃), and the air circulation function of the environmental chamber must be enabled to prevent localized overheating of the SSD (as the read / write process generates its own heat). 2. Loop Read / Write Operation Design - Loop Logic: A single loop = "Full disk sequential read (1 time) + random small data write (10% capacity)", the number of loops is set according to the test intensity (e.g., 10~50 times, industrial grade can be increased to 100 times). Full disk read: Read completely in LBA order to verify the stability of continuous read under high temperature, and record the average rate and latency fluctuation of each round of read. - Random small data write: Use 4KB blocks, QD16 queue depth, randomly select 10% of LBAs for overwrite writing (using pseudo-random mode) to simulate high-frequency small file write scenarios (e.g., database, log recording), and record the IOPS and failure count (if any) of each round of write. Stress control: Monitor the real-time temperature (if supported) and power consumption of the SSD through PLD. If the temperature exceeds its rated operating limit (e.g., consumer grade 70℃) or the power consumption suddenly increases by more than 30%, pause the current loop and record to avoid permanent hardware damage.

[0042] Step 303: Multi-dimensional Verification and Fault Source Analysis. This step requires a comprehensive evaluation of the SSD's status after the high-temperature stress test through "triple verification" of bad block detection, SMART log parsing, and data integrity verification, providing multi-dimensional features for subsequent machine learning: 1. Bad Block Inspection: Tool Selection: Use vendor-grade tools (such as Samsung Magician's "Full Scan" or Kingston SSD Manager's "Bad Block Detection") or open-source tools (such as the badblocks command) to perform a "read-write verification mode" scan (not a fast scan) to ensure that "newly added recoverable bad blocks" and "unrecoverable bad blocks" can be detected. Recording Dimensions: It is necessary to distinguish between "bad blocks that existed before the high-temperature test" (baseline data from Step 1) and "bad blocks newly added in this test," and to count the number, distribution (whether they are concentrated in a specific LBA range), and type (whether they are contiguous blocks) of newly added bad blocks, and correlate them with whether they were frequently written / read in Step 302, analyzing the correlation between bad block generation and load. 2. SMART Log Analysis: Focus on extracting indicators related to temperature stress and read / write pressure, and compare them with baseline data (step 103) and data after step 204: Error category: Uncorrectable error count (whether it has been added), ECC error correction count (whether the increase exceeds 50% of the baseline), CRC error count (whether interface transmission is affected by high temperature). Wear and health category: Erase count (the amount added in this round of testing), number of spare blocks (whether it has decreased due to the increase of bad blocks), host write volume (whether it matches the design write volume in step 302, verifying whether the controller has abnormal write operations). Temperature category: Maximum operating temperature (whether it has reached the threshold), temperature change rate (whether the controller records abnormally due to sudden changes).

[0043] For the original data written in step 301 (LBAs not overwritten in step 302): recalculate the CRC32 / SHA256 checksum and compare it with the baseline value during low-temperature writing. Count the number and location of silent errors (checksums failing but not reported by the SSD). For the data overwritten in step 302: verify its read consistency during high-temperature cycling, i.e., whether the checksum value read each time is consistent with the value written. If fluctuations occur, record the number of fluctuations and the corresponding cycle number (analyze whether there is a positive correlation with the number of cycles). Finally, output a "Data Error Heatmap": visualize the error distribution by LBA address, and combine the bad block location and block wear data in SMART to determine whether errors are concentrated in high-wear areas or temperature-sensitive areas.

[0044] It is worth noting that the ambient temperature, SSD surface temperature (thermocouples can be attached), and read / write performance parameters must be recorded simultaneously during each round of read / write operations to establish time-series data of "temperature-load-performance degradation," providing dynamic features for machine learning. If the SSD fails to load, cannot be recognized, or experiences three consecutive write failures during the test, the test must be terminated immediately, and the state at termination (such as the number of cycles, current operation, and temperature) must be recorded to avoid data loss. Such samples can be marked as "extreme failure samples" for separate analysis. For each error event (such as bad blocks or verification failures), it is necessary to indicate whether it experienced high-frequency read / write operations in step 302 and whether it was the first operation after a sudden temperature change, providing a basis for subsequent analysis of the synergistic effect of "sudden temperature change + high load." Through the above refinement, step 3 can not only verify the reliability of the SSD under extreme temperature cycling but also provide correlation samples of "environmental parameters-operational load-failure characteristics" for the machine learning model through multi-dimensional data collection, improving the accuracy of subsequent predictive analysis.

[0045] Step 302: After quickly transferring the solid-state drive to a preset high-temperature environment and performing a full disk read cycle with small random data write operations between each read cycle, the method further includes: monitoring the solid-state drive temperature through a temperature sensor; when the solid-state drive temperature exceeds the preset temperature, recording the solid-state drive performance degradation curve and determining whether thermal throttling is caused by overheating.

[0046] Temperature sensor deployment and monitoring range: High-precision thermocouple sensors (such as K-type thermocouples, accuracy ±0.5℃) or digital temperature sensors (such as DS18B20, supporting a range of -55~125℃) should be selected. Avoid using the SSD's built-in temperature sensor (as overheating of the controller may cause reading delays or inaccuracies). Installation locations: ① SSD controller chip surface (apply thermal grease before mounting to monitor core heat sources); ② NAND flash memory chip surface (select chips in the middle position to reflect the storage cell temperature); ③ Near the interface (monitor temperature changes during data transmission). Auxiliary ambient temperature monitoring: Place an independent sensor in the test chamber to record the ambient temperature, eliminating interference from ambient temperature fluctuations on the SSD's own heating. Temperature sampling frequency: Under normal conditions: collect temperature data once per second, recorded as "Time - Controller Temperature - NAND Temperature - Ambient Temperature". Under high-temperature warning conditions: when the SSD temperature approaches a preset threshold (e.g., 5℃ difference from the threshold), increase sampling to once every 100ms to capture sudden temperature increases.

[0047] In the performance data synchronization and curve construction, the data is aligned with the temperature data timestamps to collect key performance indicators and construct a "temperature-performance" correlation curve: 1. Performance Indicator Selection - Throughput: Continuous read / write rate (MB / s), random 4KB read / write IOPS (focusing on performance under high-frequency operations). Latency: Average read / write latency (μs), 99.9th percentile latency (reflecting extreme response times). Operation Status: Whether write cache degradation occurs (e.g., switching from SLC cache to native TLC / QLC), whether garbage collection is triggered (can be determined through "GC count" in SMART or controller logs). 2. Sampling and Curve Plotting - Synchronization Mechanism: The timestamps of temperature sampling and performance testing are bound to each other via PLD or test scripts (error ≤ 10ms) to ensure that each temperature data point corresponds to unique performance data. Curve Construction: With time as the horizontal axis, temperature (controller / NAND) on the left vertical axis, and performance indicators (e.g., IOPS / latency) on the right vertical axis, a superimposed curve is plotted to visually demonstrate the temporal relationship between temperature rise and performance decline. For example: the continuous change curve of IOPS from 300K to 150K during the process of temperature rising from 50℃ to 70℃.

[0048] Thermal throttling is a protective mechanism of SSD controllers that actively reduces performance to prevent overheating damage. It requires a three-step process: "temperature threshold triggering + performance characteristic matching + elimination of other interference." 1. Setting the preset temperature threshold: Base threshold: Refer to the SSD manufacturer's specifications. For example, consumer-grade SSDs typically trigger throttling at 70~85℃, while industrial-grade SSDs trigger it at 85~100℃. Dynamic threshold: Based on the baseline data from step 1, if an SSD experiences performance fluctuations at 60℃ (at room temperature), its threshold can be lowered to 55℃ (adjustment based on individual differences). 2. Characteristic identification of the performance degradation curve: Performance degradation caused by thermal throttling has significant characteristics and needs to be distinguished from other causes (such as bad blocks, cache exhaustion): Suddenness: After the temperature exceeds the threshold, performance drops sharply within 1~3 seconds (e.g., IOPS drops by more than 30%), rather than a slow decay. Reversibility: When the temperature drops below the threshold (e.g., through environmental cooling or load reduction), performance recovers to near the pre-threshold level within a short time (5~10 seconds) (recovery rate ≥80%). Step-by-step performance degradation: If high temperatures persist, multiple rounds of "deceleration-maintenance-deceleration" may occur (the controller throttles in stages). 3. Eliminate other performance degradation factors - bad block impact: Through real-time bad block scanning (e.g., triggering a fast detection every 10 seconds), if no new bad blocks are added when performance degrades, this factor can be ruled out. Cache exhaustion: Monitor SLC cache utilization. If performance degradation occurs even when the cache is not full (e.g., utilization < 90%), and is strongly correlated with temperature rise, it is more likely to be thermal throttling. Power supply fluctuations: Combine with power supply voltage regulator data. If the voltage is stable (fluctuation < ±0.02V), the influence of power supply can be ruled out.

[0049] Data Recording and Analysis Output: 1. When the temperature threshold is triggered, automatically record: Temperature data: Controller / NAND temperature, ambient temperature, and temperature rise rate (°C / s) at the time of triggering. Performance data: Performance curve segments for 30 seconds before and after triggering (including peak, trough, and drop). Controller status: "Thermal Throttle Count" in SMART (supported by some SSDs), and whether there are overheat warning logs. 2. Analysis report output - Thermal throttling determination result: Clearly indicate "whether it is caused by overheating" and attach the determination basis (e.g., "IOPS drops by 40% at 72°C, recovers after cooling to 68°C, no new bad blocks are added, determined to be thermal throttling"). Performance degradation quantification: Calculate the performance loss rate during thermal throttling ((baseline performance - post-throttling performance) / baseline performance × 100%), and the duration. Temperature sensitivity assessment: Through multiple tests, statistically analyze the performance degradation coefficient of the SSD in different temperature ranges (e.g., performance decreases by X% for every 5°C increase from 60~70°C).

[0050] It is important to note that all sensors must be calibrated with a standard thermometer before testing to ensure an error ≤1℃, avoiding misjudgments due to inaccurate readings. During performance testing, the load must be kept constant (e.g., fixed queue depth, block size) to prevent load variations from interfering with the performance curve (this can be achieved through FIO's "Fixed Load Mode"). The same SSD should be tested three times under identical conditions. If the thermal throttling trigger temperature and performance degradation curves show consistent trends, the results are more reliable (excluding accidental factors). This approach accurately captures the dynamic correlation between SSD temperature and performance, clearly distinguishing performance degradation caused by thermal throttling from other factors, providing precise "temperature-performance degradation-failure type" feature data for subsequent machine learning models.

[0051] Figure 5 yes Figure 1 The flowchart for step 4 is as follows: Figure 5 As shown, step 4 includes: step 401, performing predictive analysis based on machine learning algorithms to determine the correlation between preprocessed solid-state drive test data and solid-state drives after high-temperature and low-temperature tests for bad blocks and performance degradation; step 402, classifying and organizing the analysis results, extracting key feature parameters, and constructing feature vectors; step 403, using the training set to iteratively train the model and optimize the prediction accuracy; and step 404, deploying the validated model to the data analysis platform to achieve real-time prediction and evaluation of solid-state drive lifespan and performance trends.

[0052] Step 401: Data Association Analysis and Feature Engineering Fundamentals This step requires data cleaning and association logic mining to provide high-quality input for subsequent modeling: 1. Data Source Integration: Associate all data from Step 1 (baseline data), Step 2 (high temperature test), and Step 3 (low temperature test) by "SSD Sample ID" to form a complete sample set containing "initial state → environmental parameters → operational load → fault results". Typical fields include: Initial characteristics: ECC error correction baseline value, erase count, RDT interference threshold, room temperature read / write latency, etc. (Step 103); Environmental characteristics: high / low temperature values, baking time, number of temperature sudden changes, number of test cycles, etc.; Operational characteristics: write mode (pseudo-random sequence), read / write load (queue depth, block size), cumulative IO volume, etc.; Result labels: number of newly added bad blocks (binary classification: 0 / 1 or multi-class classification: mild / moderate / severe), performance degradation (continuous value: such as throughput decay rate), whether thermal throttling is triggered (0 / 1). Cleaning Rules: 1. Remove abnormal samples due to test interruption (e.g., SSD physical damage); handle missing values ​​(e.g., fill with the mean of samples from the same batch); standardize numerical features (e.g., scale temperature, latency, etc. to the [0,1] range); perform one-hot encoding on categorical features (e.g., flash memory type TLC / QLC). 2. Statistical Analysis: Calculate the correlation between features and labels using Pearson correlation coefficient and chi-square test, such as the correlation coefficient between "initial ECC error correction count" and "number of bad blocks after high-temperature test" (if r>0.7, it indicates a strong correlation); Visualization: Use heatmaps to show the correlation between features (avoid multicollinearity, such as "high temperature value" and "number of thermal throttling times" may be highly correlated, one should be retained); use box plots to observe the feature distribution differences between "samples with bad blocks" and "samples without bad blocks" (e.g., the former has a higher initial erase count); Domain Knowledge Embedding: Combine with SSD principles, prioritize retaining features with clear physical meaning, such as "NAND temperature change rate" which is directly related to "decrease in charge retention capability", and should be included in the analysis.

[0053] Step 402: Key Feature Extraction and Feature Vector Construction: Screening core features from high-dimensional data to reduce model complexity and improve interpretability: 1. Filtering method: Screening based on statistical indicators, such as retaining the top 20 features of mutual information (e.g., "high-temperature baking time", "initial spare block count", "low-temperature write latency"); Packaging method: Through recursive feature elimination (RFE), using a simple model (e.g., logistic regression) to iteratively eliminate features with low contribution to prediction until model performance no longer significantly decreases; Domain-driven screening: Forcefully retaining features strongly related to SSD failure mechanisms, such as: bad block prediction: ECC error correction count change, cumulative erase count, number of silent errors at high temperature; performance degradation prediction: 99.9th percentile latency increase, number of thermal throttling triggers, peak NAND temperature. 2. Structured vector: Each sample is converted into a fixed-length feature vector, such as: [initial ECC value, high temperature value, baking time, low-temperature write latency, number of cycle read / write operations, number of thermal throttling operations,...]. Time-series feature processing: Extract time-series statistics as features from the dynamic data in steps 2 / 3 (such as the temperature-performance curve every 10 seconds), such as "standard deviation of temperature in the high-temperature stage" and "slope of performance degradation curve", and transform the time-series data into a static feature vector.

[0054] Step 403: Model Training and Optimization. Select a suitable algorithm based on the prediction target (classification / regression) and improve generalization ability through iterative optimization: 1. Algorithm Selection - Bad Block Prediction (Classification Task): Prioritize Random Forest (resistant to overfitting, can output feature importance) and Gradient Boosting Tree (XGBoost / LightGBM, strong ability to handle nonlinear associations); Performance Degradation Prediction (Regression Task): Use Gradient Boosting Regression Tree (GBRT) and Neural Network (such as MLP, to handle high-dimensional features); Association Analysis Assistance: Use SHAP values ​​or Partial Dependency Graph (PDP) to interpret the model, for example, "When the temperature exceeds 75℃ and the initial ECC>100, the probability of bad blocks increases to 80%", to enhance the credibility of the results. 2. Training and Optimization Process - Dataset Partitioning: Divide the training and test sets in a 7:3 ratio (ensuring even distribution of SSD samples within the same batch), and use 5-fold cross-validation to evaluate model stability; - Hyperparameter Optimization: Tune using grid search or Bayesian optimization (Optuna tool), such as "number of trees" and "maximum depth" for random forests, and "learning rate" and "subsampling rate" for XGBoost; Performance Metrics: For classification tasks, use precision, recall, and F1-score (avoid inflated precision due to imbalanced samples); For regression tasks, use mean squared error (MSE) and coefficient of determination (R²); Iterative Improvement: If the model has a large prediction error for a certain type of sample (such as QLC flash memory), supplement the test data for that type of sample, or increase the weight of that type of sample and retrain.

[0055] Step 404: Model Deployment and Data Analysis Platform Construction. The validated model is deployed to a usable platform, achieving full automation from data acquisition to prediction output: 1. Model Deployment Methods - Lightweight Deployment: Export the trained model (e.g., XGBoost) to ONNX format and deploy it to edge computing devices (e.g., the industrial control computer built into the test box), supporting local real-time prediction (latency ≤ 1 second); Cloud Integration: If multi-device data aggregation and analysis is required, deploy the model to a cloud server (e.g., encapsulated as an API interface via Flask / FastAPI), receiving test data and returning prediction results. 2. Core Modules of the Data Analysis Platform - Data Acquisition Module: Automatically connects to the testing equipment (temperature sensor, performance tester, SMART reader) from steps 1-3, and stores data in real time to the database (such as PostgreSQL, supporting time-series data indexing) according to sample ID; Feature Engineering Module: Automatically performs data cleaning and feature extraction (reusing the logic of step 402), generating feature vectors that conform to the model input format; Prediction and Early Warning Module: Calls the deployed model and outputs results such as "probability of bad block risk" and "performance degradation rate after the next 300 cycles"; when the risk exceeds the preset threshold (such as bad block probability > 60%), it triggers an audible and visual alarm or email notification; Visualization Module: Displays the following through a dashboard (such as Grafana): single sample full life cycle curve (initial state → high temperature test → low temperature test → prediction trend); group feature analysis (such as average lifespan comparison of different flash memory types, high temperature sensitivity ranking); model interpretation view (such as feature importance ranking, risk contribution factor of a sample); Model Iteration Module: Regularly (such as monthly) adds new test data to the training set, retrains the model and replaces the old version, ensuring that the predictive ability continues to improve with data accumulation.

[0056] It is important to note that model training must cover SSDs of different brands, capacities, flash memory types (MLC / TLC / QLC), and service lives to avoid poor model generalization due to a single sample. Labels such as "bad blocks" and "performance degradation" must be strictly judged according to testing standards (e.g., bad blocks need to be confirmed multiple times by the tool) to avoid incorrect labeling that contaminates the model. Interfaces should be reserved to support new testing dimensions (e.g., humidity and vibration testing), and feature vector design must be compatible with future sensor data (e.g., NAND voltage fluctuations). By implementing step 4, fragmented test data can be transformed into a predictive decision-making tool. This tool can not only provide early warnings of SSD failure risks but also use feature importance analysis to infer key factors affecting SSD reliability (e.g., "high-temperature baking time exceeding 24 hours is the primary cause of bad blocks"), providing data support for SSD design optimization or usage scenario adaptation.

[0057] After step 404, the method further includes: step 405, fitting the indicator data of ECC error correction count, average read / write latency, and erase count with a decay baseline model of each indicator data changing over time based on a multinomial regression model, and setting a dynamic threshold; when the real-time monitoring indicator data deviates from the baseline by more than the threshold range, triggering an early warning mechanism, marking potential fault risks, and dynamically adjusting the threshold parameters in combination with historical data and environmental factors.

[0058] Multinomial regression can effectively capture the non-linear decay trend of indicators over time (or cycle count) (such as the accelerated growth of ECC error correction count and the stepwise increase in latency). Specific models need to be designed for different indicators: 1. Data preparation and time dimension definition - Time-series data acquisition: Using "number of test cycles" (e.g., the number of high / low temperature cycles in steps 2 / 3) or "cumulative running time" as the time axis (t), extract the corresponding indicator values ​​for each time point: ECC error correction count (e(t)): cumulative number of error corrections, reflecting the decay of NAND data stability; Average read / write latency (d(t)): average of random 4KB read / write latency, reflecting performance decay; Erase count (w(t)): cumulative number of erases, reflecting flash memory physical wear. Data grouping: Grouping and modeling by SSD model and flash memory type (TLC / QLC) to avoid baseline distortion caused by mixing samples with different hardware characteristics (e.g., the erase count decay rate of QLC is usually faster than that of TLC). 2. Polynomial Order Selection and Model Training - Order Determination: By visually observing the nonlinearity of the indicator decay curve, an appropriate order is selected: Erase Count (w(t)): Usually grows approximately linearly with time (due to a fixed amount of erasure per cycle), a first-order polynomial (linear regression) is chosen; ECC Error Correction Count (e(t)): Initially grows slowly, then accelerates due to increased wear, a second-order (quadratic function) or third-order polynomial is chosen; Average Delay (d(t)): Affected by garbage collection and bad blocks, it may show a step-like increase, a second-order polynomial (capturing curvature changes) is chosen. Model Formula Example (using a second-order polynomial for ECC Error Correction Count as an example): e(t) = a_0 + a_1 t + a_2 t^2, where a_0, a_1, a_2 are regression coefficients, solved by fitting the training data (time series indices in steps 1-3) using the least squares method. Goodness-of-fit verification: The coefficient of determination R^2 is used to evaluate the fit (R^2 ≥ 0.85 is considered a valid baseline). If the R^2 of a sample is too low (e.g., < 0.7), it is marked as an "abnormal decay pattern," and its cause is analyzed separately (e.g., individual hardware differences).

[0059] The threshold needs to be dynamically adjusted (rather than a fixed value) according to the baseline trend to adapt to the normal decay of the indicator and avoid false alarms or missed alarms: 1. Determining the initial threshold range - based on the statistical distribution of historical data: For SSD samples of the same type, calculate the residual between the actual value of the indicator and the baseline predicted value at each time point t ( = Actual value - Baseline value), take ±3σ (99.7% confidence interval) of the residual as the initial threshold range. For example: when the ECC error correction count is at t=100 cycles, the baseline predicted value is 50, the residual σ=5, then the threshold range is [50-15, 50+15] = [35, 65]. Combined with the hardware specification: if the manufacturer specifies that "the risk increases after the erase count exceeds 1000", the upper limit of the threshold of the baseline model can be linked with this hard index (e.g., upper limit of threshold = baseline value + min(manufacturer threshold - baseline value, 3σ)). 2. Dynamic adjustment mechanism of threshold - adjustment with decay over time: the threshold range needs to change synchronously with the baseline, for example, the upper limit of the threshold of the second-order baseline e(t) is e(t) + k t (where k is a positive coefficient) reflects the characteristic that "the threshold can fluctuate more when decay accelerates in the later stages." Environmental factor weights are introduced: the threshold is dynamically adjusted based on the environmental parameters (high temperature value, number of sudden temperature changes) from steps 2 / 3. For example, in high-temperature environments (>70℃), the threshold range for ECC error correction counting is reduced by 20% (due to accelerated decay at high temperatures, a more sensitive warning is needed); when the number of sudden temperature changes is >50, the delay threshold range is reduced by 15% (because sudden changes easily lead to abnormal delay fluctuations). Based on real-time data feedback: for every 10 new time-series data points, the residual σ is recalculated and the threshold is updated to ensure that the threshold adapts to the individual decay characteristics of the sample (e.g., if the initial residual of a certain SSD is small, the threshold can be appropriately relaxed in the later stages).

[0060] When real-time monitoring data deviates from the baseline by more than the dynamic threshold, a graded warning should be triggered, and the cause of the risk should be identified by combining multi-dimensional information: 1. Deviation Calculation and Warning Level - Deviation D: Quantifies the difference between the actual value and the baseline, the formula is: D = Level classification: Mild warning (1 < D ≤ 1.5): The indicator deviates but does not exceed the expectation severely. It may be accidental fluctuation. Record it and continue to observe. Moderate warning (1.5 < D ≤ 2): The deviation is significant, triggering local alarm (such as the indicator light of the test platform flashing), and generating a temporary report. Severe warning (D > 2): Seriously deviating from the baseline, it is determined as "potential failure risk", immediately push the alarm to the management end, and mark the SSD as the "to be re-inspected" status. 2. After triggering the warning, the following data will be automatically associated to locate the cause: Historical data: Query whether there have been similar warnings for this SSD (such as multiple ECC deviations may indicate NAND degradation), and whether it is in a high wear area (whether the erase count is close to the threshold); Environmental factors: Whether it has experienced extreme temperature recently (such as high temperature > 80°C), and whether the temperature change is frequent (such as ≥ 3 times within 1 hour); Operating load: Whether high-intensity read and write operations have been performed before the warning (such as IOPS > 150% of the baseline), excluding temporary deviations caused by short-term load shocks.

[0061] Time-series data storage: Use time-series databases (such as InfluxDB, TimescaleDB) to store metric data, supporting high write throughput and fast query by time range; Baseline real-time prediction: Pre-store the polynomial regression model parameters (such as coefficients a_0, a_1, a_2) in memory, and directly calculate the baseline value for the real-time incoming time t (avoiding re-training the model every time it is called), ensuring that the prediction latency < 100ms. Regularization processing: Add L2 regularization (Ridge regression) to high-order polynomials (such as 3rd order) to suppress the overfitting of the baseline curve caused by excessive coefficients (such as abnormal fluctuations being misjudged as trends); Continuous trigger mechanism: A mild warning needs to be confirmed only when D > 1 is satisfied at three consecutive time points, avoiding false alarms caused by single measurement errors (such as sensor transient interference). The platform needs to visually display the baseline curve, dynamic threshold range, and real-time data points. For example: With time as the horizontal axis, draw the shaded intervals of "baseline value + upper threshold" and "baseline value - lower threshold", and the real-time data points exceeding the shaded area are marked in red; Use text to explain the adjustment factors of the current threshold (such as "due to high-temperature environment, the threshold is tightened by 20%") to improve the credibility of the warning. Through step 405, the data analysis platform can upgrade from "passive recording" to "active warning": On the one hand, the polynomial regression baseline can accurately describe the attenuation law of SSD indicators, avoiding misjudgment of non-linear attenuation with a fixed threshold; On the other hand, the dynamic threshold combined with environmental and historical data makes the warning more in line with the actual usage scenario, providing an operable decision-making basis for SSD life prediction and fault prevention.

[0062] After the said step 405, the method further includes: Step 406, based on the degree of deviation of each metric data from the attenuation baseline, set weights according to the importance of each metric, and calculate the weights as the total score by means of weighted summation.

[0063] The weights should reflect the priority of different indicators' impact on the SSD's health status, and be determined comprehensively based on SSD failure mechanisms and engineering experience: indicators directly related to "bad block generation" and "data loss" have higher weights. For example: ECC error correction count (especially uncorrectable errors): directly reflects the stability of NAND flash data, with the highest weight (e.g., 0.4); erase count: related to the physical wear and tear life of flash memory, with the next highest weight (e.g., 0.3); average read / write latency: mainly affects performance and indirectly reflects controller or cache efficiency, with a lower weight (e.g., 0.2); other auxiliary indicators (e.g., thermal throttling counts): reflect environmental adaptability, with the lowest weight (e.g., 0.1). Historical data verification: through the correlation analysis in step 401, calculate the correlation coefficient between each indicator and "final failure" (e.g., the correlation coefficient between ECC count and bad blocks r=0.85, and latency and failure r=0.5), and allocate weights according to the proportion of correlation coefficients (e.g., ECC weight = 0.85 / (0.85+0.7+0.5+0.3)=0.38, approximately 0.4). Scenario adaptation adjustment: dynamically fine-tunes the weights for different application scenarios. For example: industrial-grade scenario (data reliability first): ECC weight is increased to 0.5 and latency weight is reduced to 0.1; consumer-grade scenario (performance experience first): latency weight is increased to 0.3 and erase count weight is reduced to 0.25.

[0064] The sum of the weights of all indicators is Furthermore, the weight of a single indicator should not exceed 0.6 (to avoid one indicator dominating the score and ignoring other risks) and should not be lower than 0.05 (to ensure the reference value of auxiliary indicators). The standardized quantification of indicator deviation requires converting the "degree of deviation from the attenuation baseline" of each indicator into a score with a unified dimension (e.g., 0-10 points) to eliminate the influence of differences in the magnitude of the indicators themselves: 1. In the positive processing of deviation, the degree of deviation from the baseline may be "the higher the more dangerous" (e.g., ECC count, erase count) or "the lower the more dangerous" (e.g., spare block quantity, indicators requiring additional supplementation), and is uniformly converted into a positive indicator of "the higher the deviation, the higher the risk": For indicators of "the higher the more dangerous" (e.g., ECC error correction count): Deviation score (A score of 10 is given for scores exceeding the upper limit, representing extremely high risk) - For indicators where "the lower the score, the more dangerous" (such as the number of spare blocks): Deviation score

[0065] If the baseline value of the ECC error correction count is 50, the upper limit of the threshold is 65 (set in step 405), and the actual value at a certain moment is 70: → Take the upper limit of 10 points (exceeding the threshold carries extremely high risk); If the average baseline delay is 100μs, the upper limit of the threshold is 150μs, and the actual value is 120μs: (Medium risk)

[0066] By weighted summing and integrating the scores of each indicator, a total score of 0-10 is generated, which intuitively reflects the overall health status of SSD: Total Score ,in As the indicator weight, This represents the deviation score for the indicator. Example: ECC score 10 (weight 0.4), erase count score 6 (weight 0.3), delay score 4 (weight 0.2), hot throttling score 2 (weight 0.1): S = 10×0.4 + 6×0.3 + 4×0.2 + 2×0.1 = 4 + 1.8 + 0.8 + 0.2 = 6.8 points. The total score is divided into 5 risk levels, corresponding to different handling strategies: 0-2 points: Healthy state, no intervention required, continuous monitoring; 2-4 points: Mild risk, occasional fluctuations may occur, increase sampling frequency; 4-6 points: Moderate risk, multiple indicators deviate from the baseline, generate an early warning report, manual re-inspection recommended; 6-8 points: High risk, core indicators deviate severely, trigger device-level alarms, limit high-load operations; 8-10 points: Emergency risk, high probability of failure, immediately stop use, initiate data migration process.

[0067] For every 100 new fault samples accumulated, the correlation between each indicator and the fault is recalculated (e.g., using the feature importance of random forests), and the weight values ​​are updated (e.g., if "thermal throttling count" is found to be strongly correlated with faults in high-temperature scenarios, its weight can be temporarily increased). If a core indicator (e.g., uncorrectable error count) reaches the manufacturer's specified threshold (e.g., >10), even if the overall score does not reach high risk, it is still directly judged as "emergency risk," avoiding the use of weighted summation to mask fatal problems. The data analysis platform displays: a time series curve of the overall score (for intuitive observation of risk change trends); a pie chart of the score percentage of each indicator (clearly identifying the current main sources of risk, such as "60% of the risk comes from abnormal ECC counts"); and a comparison of historical scores (e.g., "This week's score increased by 2.3 points compared to last week, indicating increased risk"). Through step 406, multi-dimensional indicator deviation information is condensed into a quantifiable and comparable overall score, which not only solves the "multi-indicator warning conflict" (e.g., the decision-making problem when indicator A is normal but indicator B is abnormal), but also provides a unified standard for comparing the health status of different SSDs, making subsequent fault intervention and life assessment more operational.

[0068] Based on the first embodiment, a second embodiment is proposed. In the second embodiment, step 1, solid-state drive (SSD) preprocessing, involves performing a light aging process on the new SSD, specifically including 100-1000 full-disk erase / write cycles. During this process, random write and random read operations are used to simulate normal user scenarios, stabilizing the SSD's performance. RDT testing is performed on the SSD. Under a temperature controller-regulated environment of 25°C, testing software is used to measure the SSD's read and write performance. Specifically, this includes writing 4KB of random data, reading 4KB of random data, repeating 100 times, and recording the average value. Key indicators such as read / write latency and throughput are also recorded. SMART attribute reading is performed. SMART attribute information, including ECC error correction count, average read / write latency, and erase count, is read through the SSD's internal interface and stored as baseline data in the database.

[0069] Step 2, First Stage Test: Setting Test Environment Parameters. The SSD is installed in a temperature-controlled test chamber, with the temperature set to 70℃, and powered by a power supply voltage regulator. Simultaneously, a programmable logic device (PLD) is configured for signal acquisition during data writing and reading. The data writing stage test is performed. Under the 70℃ high-temperature environment, a verifiable pseudo-random data pattern (e.g., alternating 0x55, 0xAA, 0xFF) is used to write data to the SSD. Specifically, a 4KB header information, including the test version number, timestamp, and other metadata, is written first, followed by the actual data. For each logical block address (LBA), its CRC32 or SHA256 checksum is recorded. The high-temperature baking and holding stage is performed. The SSD is kept stationary at 70℃ with continuous power. This stage lasts from 24 to 168 hours (1 week) to accelerate the data charge loss process. The data reading and verification stage is performed. The SSD is rapidly transferred from the 70℃ environment to a 0℃ low-temperature environment, and a "smart data inspection" mode is used for read testing. First, all data is read sequentially, and the throughput and average latency of each read are recorded. Secondly, perform random reads with high queue depths across the entire disk, recording IOPS and latency fluctuations. Finally, using the previously recorded checksums, verify data integrity sector by sector, and count the number of silent errors (data errors that the controller did not report) and uncorrectable errors.

[0070] Step 3, Second Phase Testing: Perform data write phase testing. Under a 0℃ low-temperature environment, employ the same write strategy as in Step 202 to ensure data consistency. Perform the data read and stress test phase. Under a 70℃ high-temperature environment, perform full disk reads 3-5 times in a loop. Between each read, intersperse small data volume (e.g., 1% capacity) random write operations to simulate operating system background activity. Monitor the SSD temperature using a temperature sensor, record the performance degradation curve when overheating occurs, and determine if thermal throttling is caused by overheating. Perform bad block checks, SMART log analysis, and data integrity verification on all test samples. Use a dedicated tool to read the SMART log, obtain information such as ECC error correction count, average read / write latency, and erase count, and compare and analyze this information with baseline data.

[0071] Step 4, Third Stage Analysis: Establish a data analysis platform to achieve unified management and intelligent analysis of test data. This platform supports real-time data acquisition, storage, and display, and possesses data mining and machine learning capabilities. Establish a degradation baseline. For each SSD indicator value, establish its normal degradation baseline model. Specifically, for indicators such as ECC error correction count and read / write latency, a linear regression model is used; for indicators such as bad block rate, a multinomial regression model is used. Calculate a robustness score. Based on the degree to which each indicator deviates from the baseline, calculate a comprehensive "robustness score" for each tested SSD. Specifically, normalize each indicator to the [0, 1] interval, with values ​​closer to 1 indicating better performance. Then, calculate the total score using a weighted summation method, where the weights are set according to the importance of each indicator. Perform predictive analysis. Utilize machine learning algorithms to analyze the correlation between early test data (such as the growth rate of ECC count) and the later occurrence of bad blocks and performance degradation. Specifically, a Long Short-Term Memory (LSTM) network model is used to predict the remaining lifespan and potential failures of the SSD. After training is complete, a web service interface is provided for users to query the prediction results.

[0072] In specific applications: Implementation steps: Step 1, SSD preprocessing: Mild aging process: Install the SSD on the test platform and perform full-disk random read / write operations using the fio (Flexible I / O Tester) tool at room temperature (25℃). Parameter details: A total of 300 full-disk erase / write cycles were performed. The block size (bs) was 4KB, and the random read / write mix ratio (rwmixread) was 50%, simulating typical user load. The entire process lasted approximately 48 hours. RDT testing (obtaining baseline performance): After setting the temperature chamber to 25℃ and stabilizing for 1 hour, performance tests were performed using a test script. Test modes: Sequential read / write: Using a 1MB block size and a queue depth of 32, read and write speeds were tested separately; Random read / write: Using a 4KB block size and a queue depth of 128, random read / write IOPS were tested; Latent test: Using a 4KB block size and a queue depth of 1, read and write latency was tested; Data recording: Record the average values ​​of the three test sets. For example, the measured sequential read speed was 6800 MB / s, the sequential write speed was 5000 MB / s, the random read IOPS was 900K, the random write IOPS was 800K, the read latency was 85μs, and the write latency was 20μs. These data were stored in the database as baseline performance.

[0073] SMART attribute reading operation: Use the command `smartctl -x / dev / nvme0n1` to read the complete SMART information and logs. Key data records: Percentage Used: 1%; Data Units Written: 300 GB; Media and Data Integrity Errors: 0; Error Information Log Entries: 0; Warning CompositeTemperature Time: 0; Critical Composite Temperature Time: 0.

[0074] Step 2, First Stage Test (High Write Low Read Mode): Test Environment Setup: Set the temperature chamber containing the SSD to 70℃ ± 1℃. Set the programmable power supply to 12V with a current limit of 3A. High-Temperature Data Write Operation: In a 70℃ environment, wait for the SSD's internal temperature to stabilize (confirmed by reading the temperature via SMART to reach above 68℃).

[0075] Write strategy: First, a 4KB header containing the test ID, timestamp, firmware version, etc., is written using the `dd` command. Then, a custom data writing program writes 900GB of data (approximately 90% of the user's storage capacity) to the SSD in 128KB blocks at a queue depth of 32. The data pattern is a cyclical fill of 0x55, 0xAA, and 0xFF. After each 128KB block is written, the program calculates the CRC32 checksum of that block and records the Logical Block Address (LBA) and its corresponding CRC32 value in real-time to a separate log file.

[0076] High-temperature baking maintenance: Maintain an ambient temperature and power supply of 70°C for 72 hours. During this period, record the SSD's SMART temperature and power consumption data hourly to monitor its status.

[0077] Low-Temperature Data Reading and Verification Operations: Rapid Transfer: Reduce the oven temperature from 70℃ to 0℃ ± 1℃ within 5 minutes and stabilize for 30 minutes. Sequential Read: Use the fio command to sequentially read the entire disk in 1MB block sizes, recording the average read speed (Example result: speed decreased to 4500 MB / s, a drop compared to baseline performance). Random Read: Use the fio command to perform random reads in 4KB block sizes with a queue depth of 128, recording IOPS and latency (Example result: IOPS decreased to 600K, latency increased to 120μs).

[0078] Data Verification: The data verification program is initiated. This program reads the data in the SSD block by block, recalculates the CRC32 value, and compares it with the log file recorded in step 202. Error Log: Silent Error: CRC32 checksum mismatches were found in 15 data blocks, but the SSD controller did not report any errors. Uncorrectable Error (UNC Error): Two data blocks could not be read, and the SSD controller returned a read error.

[0079] Step 3, Second Stage Test (Low Write High Read Mode): Low Temperature Data Write Operation: In a 0℃ environment, rewrite the data using the exact same program, data mode, and capacity (900GB) as in Step 202, and generate a new CRC32 log. High Temperature Read and Stress Test Operation: Rapidly raise the chamber temperature to 70℃.

[0080] Test mode: Perform four sequential full disk reads in a loop. Between each read, perform a random write operation with a write volume of 10GB (approximately 1% of the capacity) and a block size of 4KB. Monitor the SSD's internal temperature and read speed curves using monitoring software.

[0081] Observation results: During the third read operation, the SSD's internal temperature reached 83°C, triggering thermal throttling. The read speed plummeted from 6000 MB / s to 1500 MB / s and continued to fluctuate. After the temperature decreased, the speed gradually recovered.

[0082] Final check procedure: After the test is completed, read the SMART log again.

[0083] Data logging: Media and Data Integrity Errors increased to 2 (corresponding to UNC errors). ErrorInformation Log Entries increased to 5. Three new reallocated bad blocks were added (Reallocated SectorsCount).

[0084] Step 4, Third Stage Analysis: Data Storage: Store all collected data (performance, SMART, error logs, temperature, power consumption) into an SQL database. Establish a degradation baseline: Based on test data from multiple good-quality hard drives of the same model, establish a baseline model for the "read speed degradation rate after baking at 70℃ for 72 hours". For example, the degradation rate of a good-quality hard drive is usually less than 15%. In this example, the degradation rate of this hard drive is (6800-4500) / 6800 ≈ 33.8%, which significantly deviates from the baseline.

[0085] Robustness score calculation: Indicator normalization: Indicators such as decay rate (33.8%), silent error count (15), and uncorrectable error count (2) are mapped to a score of 0-1 (1 is the best, 0 is the worst). Weighted summation: "Uncorrectable error count" is given the highest weight (0.5), "decay rate" is given a weight of 0.3, and "silent error count" is given a weight of 0.2. Calculation results: The overall robustness score of this disk is only 0.45 (out of 1.0), which is judged as poor reliability.

[0086] Predictive analytics operation: Input the disk's previous data (such as ECC error growth trend and latency change curve) into the pre-trained LSTM model. Output results: The model predicts that the disk has an 85% probability of failing to complete the target number of cycles in subsequent standard durability tests, and its expected lifespan is lower than the average level of similar products.

[0087] Based on the first embodiment, a third embodiment is proposed. In the third embodiment, step 1, solid-state drive preprocessing, involves performing a light aging process on the brand-new solid-state drive, specifically including 500 full-disk erase / write cycles. During this process, fixed-size data blocks (e.g., 4KB) are used to randomly write and read data in different areas of the solid-state drive to ensure uniform data distribution. The solid-state drive undergoes RDT testing. Under a temperature controller-regulated environment of 28°C, testing software is used to measure the read and write performance of the solid-state drive. Specifically, this includes writing 8KB of random data, reading 8KB of random data, repeating this 200 times, and recording the average value. Key indicators such as read / write latency and throughput are also recorded. SMART attribute reading is performed. SMART attribute information, including ECC error correction count, average read / write latency, erase count, and other parameters, is read through the solid-state drive's internal interface and stored as baseline data in the database.

[0088] Step 2, First Stage Test: Setting Test Environment Parameters. The SSD is installed in a temperature-controlled test chamber, with the temperature set to 72℃, and powered by a power supply voltage regulator. Simultaneously, a programmable logic device (PLD) is configured for signal acquisition during data writing and reading. The data writing stage test is performed. Under the 72℃ high-temperature environment, a verifiable pseudo-random data pattern (e.g., alternating 0x55, 0xAA, 0xFF) is used to write data to the SSD. Specifically, an 8KB header information, including the test version number, timestamp, and other metadata, is written first, followed by the actual data. For each logical block address (LBA), its CRC32 checksum is recorded. The high-temperature baking and holding stage is performed. The SSD is kept stationary at 72℃ with continuous power. This stage lasts for 48 hours to accelerate the data charge loss process. The data reading and verification stage is performed. The SSD is rapidly transferred from the 72℃ environment to a 0℃ low-temperature environment, and a "smart data inspection" mode is used for read testing. First, all data is read sequentially, and the throughput and average latency of each read are recorded. Secondly, perform random reads with high queue depths across the entire disk, recording IOPS and latency fluctuations. Finally, using the previously recorded checksums, verify data integrity sector by sector, and count the number of silent errors (data errors that the controller did not report) and uncorrectable errors.

[0089] Step 3, Second Phase Testing: Perform data write phase testing. Under a 0℃ low-temperature environment, use the same write strategy as in Step 202 to ensure data consistency. Perform the data read and stress test phase. Under a 72℃ high-temperature environment, perform four full disk reads in a loop. Between each read, intersperse small data volume (e.g., 2% of capacity) random write operations to simulate operating system background activity. Monitor the SSD temperature using a temperature sensor, record the performance degradation curve when overheating occurs, and determine if thermal throttling is caused by overheating. Perform bad block checks, SMART log analysis, and data integrity verification on all test samples. Use a dedicated tool to read the SMART log, obtain information such as ECC error correction count, average read / write latency, and erase count, and compare and analyze this information with baseline data.

[0090] Step 4, Third Stage Analysis: Establish a data analysis platform to achieve unified management and intelligent analysis of test data. This platform supports real-time data acquisition, storage, and display, and possesses data mining and machine learning capabilities. Establish a degradation baseline. For each SSD indicator value, establish its normal degradation baseline model. Specifically, for indicators such as ECC error correction count and read / write latency, a multinomial regression model is used; for indicators such as bad block rate, an exponential regression model is used. Calculate a robustness score. Based on the degree to which each indicator deviates from the baseline, calculate a comprehensive "robustness score" for each tested SSD. Specifically, normalize each indicator to the [0, 1] interval, with values ​​closer to 1 indicating better performance. Then, calculate the total score using a weighted summation method, where the weights are set according to the importance of each indicator. Perform predictive analysis. Utilize machine learning algorithms to analyze the correlation between early test data (such as the growth rate of ECC count) and the later occurrence of bad blocks and performance degradation. Specifically, a convolutional neural network (CNN) model is used to predict the remaining lifespan and potential failures of the SSD. After training, provide a web service interface for users to query the prediction results.

[0091] A fourth embodiment is proposed based on the first embodiment. In this fourth embodiment, the aim is to test a novel flash memory chip with QLC (four-layer cell) architecture that is more sensitive to charge retention and data stability, thereby demonstrating the universality and scalability of the method of the present invention. Enhanced testing methods for QLC solid-state drives: QLC NAND flash memory faces greater challenges in data retention and read / write interference due to its higher storage density and narrower charge tolerance. This embodiment, based on the method described in Embodiment 1, optimizes parameters and strengthens testing for the characteristics of QLC SSDs. The specific implementation steps are as follows:

[0092] Step 1: SSD Pre-processing: Perform a light aging process on the new QLC architecture SSD. This includes 300 full-disk erase / write cycles (fewer cycles than SLC / MLC / TLC drives because QLC has lower endurance). During this process, 4KB data blocks are used for random writes and reads across the entire disk (queue depth set to 32) to accelerate stabilization and initially screen out extremely fragile storage units. Perform RDT testing on the SSD. Under a temperature controller-regulated environment of 25°C, use testing software to measure the SSD's read and write performance. Pay special attention to recording its out-of-cache write speed, as QLC drives show significant differences in performance in this area. This includes: sequentially writing 100GB of data and recording the entire speed curve; randomly reading 4KB of data 1000 times, recording the average latency and latency distribution. Perform SMART attribute reading. In addition to reading common parameters such as ECC error correction count, average read / write latency, and erase count, specific attributes related to QLC, such as "media wear indicator" and "NAND write volume", are additionally recorded and stored in the database as baseline data.

[0093] Step 2, First Stage Test (High Write Low Read Mode - Enhanced Data Retention Test): Set test environment parameters. Install the QLC SSD in a temperature-controlled test chamber, setting the temperature to 85℃ (higher than the usual 70℃ to accelerate the charge loss process of QLC). Perform the data write stage test. Under the high temperature of 85℃, write to the SSD using a verifiable pseudo-random data mode. This embodiment uses a more stressful data mode: alternating between writing all 0x00 and all 0xFF data blocks. This mode aims to maximize the charge change of the floating gate, intensifying the test stress. The write capacity is 95% of the user's available space (filling most of the capacity to simulate real-world usage). Perform the high-temperature baking retention stage. Keep the SSD idle at 85℃ with continuous power supply. This stage is extended to 336 hours (2 weeks) to fully simulate the data retention capability of the QLC SSD under long-term high-temperature conditions. Perform the data read and verification stage. Quickly transfer the SSD from the 85℃ environment to a 10℃ environment (the temperature difference is still significant, but other physical effects that extreme low temperatures may cause are avoided). The "intelligent data inspection" mode was used for read tests. During verification, in addition to counting the number of silent errors and uncorrectable errors, the UBER (Uncorrectable Bit Error Rate) also needed to be calculated, which is a key reliability indicator for large-capacity storage such as QLC.

[0094] Step 3, Second Phase Testing (Low Write High Read Mode - Enhanced Read Interference and Performance Stability Testing): Perform the data write phase test. Under a low temperature of 10℃, write to the SSD using the same stressful data mode as in Step 202 (alternating between all 0x00 and all 0xFF). Perform the data read and stress test phase. Under a high temperature of 85℃, perform 5 full disk reads in a loop. Between each read, intersperse a larger amount of random write operations (e.g., 5% of capacity), greatly increasing the stress on the flash memory cells from read and programming interference. Monitor the SSD temperature using a temperature sensor and record its performance curves and the trigger point, duration, and performance recovery of thermal throttling in detail. Perform bad block checks, SMART log analysis, and data integrity verification on all test samples. Focus on analyzing newly added bad blocks caused by read and programming interference.

[0095] Step 4, Third Stage Analysis (Targeted Modeling): Establish a data analysis platform (same as Example 1). Establish a degradation baseline. For QLC SSDs, UBER becomes a core degradation indicator, requiring the establishment of an exponential degradation model. Calculate a robustness score. In the scoring model, increase the weight of UBER and read interference-related indicators (such as the number of newly added bad blocks discovered in step 303) to reflect the unique failure modes of QLC drives. Perform predictive analysis. Utilize machine learning algorithms (such as XGBoost) to analyze the correlation between previous test data (such as the growth trend of UBER and the degradation rate of out-of-cache write speed) and the end of the QLC SSD's lifespan, achieving more accurate prediction of remaining lifespan.

[0096] This embodiment overcomes the limitations of existing technologies with their singular test scenarios and conditions through a full-chain verification method encompassing "aging preprocessing - multi-stress coupling - data inspection - deep diagnostics - predictive modeling," achieving a comprehensive evaluation of SSD performance. It not only identifies different types of bad blocks but also effectively filters out weak blocks with poor performance, improving the accuracy of product reliability assessment. By combining enhanced high-write-low-read testing with enhanced low-write-high-read testing, it overcomes the limitations of traditional testing software that only performs basic tests, enabling automated testing of complex application scenarios. The multi-angle testing strategy allows for a comprehensive evaluation of SSD performance and stability. Through methods such as establishing attenuation baselines, robustness scoring, and predictive analysis, the test results are analyzed in depth and intelligently processed, providing reliable reliability difference assessments for SSDs of different brands and batches. This not only improves the accuracy of test results but also provides users with reliable reference data support. Through a full-chain verification process including aging preprocessing, multi-stress coupling, data inspection, and deep diagnostics, the reliability and lifespan of SSDs are comprehensively evaluated. This series of systematic testing methods effectively improves product quality and reliability, providing users with more comprehensive and reliable test results. By employing various stress coupling strategies during the testing process, such as writing specific data patterns under high-temperature conditions and simulating power instability, different types of error mechanisms can be effectively activated, helping users quickly discover and locate potential faults in solid-state drives, thus improving the comprehensiveness and relevance of the testing.

[0097] In the embodiments provided by this invention, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0098] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0099] The above are merely embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for evaluating the high write / low read and low write / high read performance of a solid-state drive, characterized in that, The method includes: Preprocessing the solid-state drive (SSD) includes formatting the SSD, checking for initial bad blocks, removing the SSD with initial bad blocks if found, and reading the SMART data from the processed SSD. In a preset high-temperature environment, SMART data is written into the pre-processed solid-state drive and baked at high temperature for a preset time. After the baking time is over, the solid-state drive is quickly transferred to a preset low-temperature environment for reading and data integrity verification. In a preset low-temperature environment, SMART data is written to the solid-state drive (SSD) after high-temperature testing. The SSD is then quickly transferred to a preset high-temperature environment for reading and stress testing. Bad block checks, SMART log analysis, and data integrity verification are performed on the SSD after the low-temperature test. In this process, all data from the low-temperature test are associated with the SSD sample ID, abnormal samples that interrupt the test are removed, missing values ​​are processed, and numerical features are standardized. Based on predictive analysis using machine learning algorithms, the correlation between preprocessed SSD test data and SSD bad blocks and performance degradation after high and low temperature tests is established, and the analysis results are integrated to build a data analysis platform.

2. The method for evaluating the high write / low read and low write / high read performance of a solid-state drive according to claim 1, characterized in that, The steps of preprocessing the solid-state drive and reading the SMART data from the processed solid-state drive include: The solid-state drive undergoes a light aging process, and a full disk erase / write cycle is performed within a preset number of times based on the queue depth and block size of random write and random read operations. Under normal temperature conditions, RDT tested the aged solid-state drives and measured their read and write performance. Record the baseline performance data of the RDT test and read / write performance of the aged solid-state drive under normal temperature conditions, and read the SMART data of the aged solid-state drive, and record the index data of ECC error correction count, average read / write latency, and erase count.

3. The method for evaluating the high write / low read and low write / high read performance of a solid-state drive according to claim 1, characterized in that, The steps of writing SMART data into a pre-processed solid-state drive in a preset high-temperature environment and subjecting it to high-temperature baking for a preset time, followed by quickly transferring the solid-state drive to a preset low-temperature environment for reading and data integrity verification after the baking time, include: Set the test environment parameters, including temperature controller, power supply voltage regulator and programmable logic device; In a pre-set high-temperature environment, SMART data is written into the pre-processed solid-state drive according to a verifiable pseudo-random data pattern, and the CRC32 or SHA256 check value of each logical block address (LBA) in the pre-processed solid-state drive is recorded. Within a preset time and preset high temperature environment, a solid-state drive storing SMART data is subjected to continuous high-temperature baking. After the baking time is over, the solid-state drive is quickly transferred to a preset low-temperature environment and a read test is performed according to the intelligent data inspection mode. The read test includes at least sequential read, random read, and data integrity verification, and the number of silent errors and uncorrectable errors is recorded.

4. The method for evaluating the high write / low read and low write / high read performance of a solid-state drive according to claim 1, characterized in that, The steps of writing SMART data into a solid-state drive (SSD) after a high-temperature test in a preset low-temperature environment, then quickly transferring the SSD to a preset high-temperature environment for reading and stress testing, and performing bad block checks, SMART log analysis, and data integrity verification on the SSD after the low-temperature test include: In a preset low-temperature environment, SMART data is written into the pre-processed solid-state drive according to a verifiable pseudo-random data pattern, and the CRC32 or SHA256 check value of each logical block address (LBA) in the pre-processed solid-state drive is recorded. The solid-state drive is quickly transferred to a preset high-temperature environment, and a full disk read is performed in a loop, with small amounts of random data written between each read operation. Perform bad block checks, SMART log analysis, and data integrity verification on solid-state drives after low-temperature testing.

5. The method for evaluating the high write / low read and low write / high read performance of a solid-state drive according to claim 4, characterized in that, After the steps of rapidly transferring the solid-state drive to a preset high-temperature environment, performing cyclic full-disk reads, and performing small-scale random write operations between each read interval, the method further includes: The system monitors the temperature of the solid-state drive (SSD) using a temperature sensor. When the SSD temperature exceeds a preset temperature, it records the performance degradation curve of the SSD and determines whether thermal throttling is caused by overheating.

6. The method for evaluating the high write / low read and low write / high read performance of a solid-state drive according to claim 2, characterized in that, The steps for establishing a data analysis platform by integrating the correlation between the preprocessed solid-state drive test data (based on machine learning algorithms for predictive analysis) and the occurrence of bad blocks and performance degradation in solid-state drives after high-temperature and low-temperature tests, include: The correlation between preprocessed SSD test data obtained through predictive analysis based on machine learning algorithms and the occurrence of bad blocks and performance degradation in SSDs after high-temperature and low-temperature tests. The analysis results are categorized and organized, key feature parameters are extracted, and feature vectors are constructed. The model is iteratively trained using the training set to optimize prediction accuracy; The validated model is deployed to a data analysis platform to enable real-time prediction and evaluation of the lifespan and performance trends of solid-state drives.

7. The method for evaluating the high write / low read and low write / high read performance of a solid-state drive according to claim 6, characterized in that, After the step of deploying the validated model to the data analysis platform to achieve real-time prediction and evaluation of the lifespan and performance trends of solid-state drives, the method further includes: Based on the multinomial regression model, the decay baseline model of each indicator data over time is fitted to the index data of ECC error correction count, average read / write latency, and erase count, and a dynamic threshold is set. When real-time monitoring data deviates from the baseline by more than the threshold range, an early warning mechanism is triggered, potential fault risks are marked, and the threshold parameters are dynamically adjusted in combination with historical data and environmental factors.

8. The method for evaluating the high write / low read and low write / high read performance of a solid-state drive according to claim 7, characterized in that, After the steps of triggering an early warning mechanism, marking potential fault risks, and dynamically adjusting the threshold parameters based on historical data and environmental factors when real-time monitoring indicator data deviates from the baseline by more than a threshold range, the method further includes: Based on the degree to which each indicator deviates from the attenuation baseline, weights are assigned according to the importance of each indicator, and the scores of each indicator are integrated by weighted summation to form the total score.

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