Packaging structure and forming method thereof

Abstract

The invention relates to a package structure and a method of forming the same. The embodiment of the invention relates to a method for forming a package structure. The method comprises the following steps: depositing a first layer on the front surface of a wafer and depositing a second layer on the back surface of the wafer; depositing a third layer on the first layer and a fourth layer on the second layer; depositing an etch stop layer on the third layer; depositing a fifth layer on the etch stop layer and a sixth layer on the fourth layer; removing the fifth layer by a first process; and removing the etch stop layer by a second process.

Description

Technical Field

[0001] This disclosure relates to packaging structures and methods for forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured as follows: various insulating or dielectric layers, conductive layers, and semiconductor layers of material are sequentially deposited on a semiconductor substrate, and photolithography is used to pattern the various material layers to form circuit components and elements thereon. The semiconductor devices on the substrate are assembled into individual chips to achieve the designed function. In some cases, two or more substrates with different devices can be bonded together to form a complex substrate, where each individual die includes two or more dies. For example, a substrate with logic devices can be bonded to a substrate with an image sensor, such that the logic devices are connected to the image sensor, and each individual chip may include a logic chip and an image sensor chip. Individual chips are individualized by sawing along the etched lines of an integrated circuit. For example, the individual chips are then individually packaged into multi-chip modules or other types of packages.

[0003] The semiconductor industry is increasing the integration density of various electronic components by continuously shrinking the minimum feature size, which allows more components to be integrated into a given area. In some applications, these smaller electronic components require packaging systems that are smaller and more advanced than those of the past. Furthermore, as more and more metal layers are added to advanced back-end ofline (BEOL) processing, the warpage of System-on-Chip (SoC) substrates is becoming increasingly high, which significantly reduces the chip-on-substrate process window for System-on-Chip (SoIC) and leads to low bonding yields.

[0004] Therefore, an improved packaging structure is needed. Summary of the Invention

[0005] According to one embodiment of the present disclosure, a method for forming a semiconductor structure is provided, comprising: depositing a first layer on the front side of a wafer and depositing a second layer on the back side of the wafer; depositing a third layer on the first layer and depositing a fourth layer on the second layer; depositing an etch stop layer on the third layer; depositing a fifth layer on the etch stop layer and depositing a sixth layer on the fourth layer; removing the fifth layer by a first process; and removing the etch stop layer by a second process.

[0006] According to one embodiment of the present disclosure, a method for forming a semiconductor structure is provided, comprising: providing a first device structure, wherein the first device structure has a first surface and a second surface opposite to the first surface, and the second surface has a first cross-sectional profile; depositing a first structure on the first surface, wherein the first structure causes the second surface to have a second cross-sectional profile different from the first cross-sectional profile; and bonding the first device structure to a second device structure.

[0007] According to one embodiment of this disclosure, a method for forming a semiconductor structure is provided, comprising: bonding an interposer substrate to one or more dies; removing a portion of the interposer substrate to expose one or more vias; depositing a structure on the interposer substrate and the vias, including: depositing a first protective layer on the interposer substrate and the vias; depositing a first buffer layer on the first protective layer; depositing a second protective layer on the first buffer layer; and depositing a second buffer layer on the second protective layer; removing the structure; depositing a dielectric material on the interposer substrate and the vias; and forming one or more electrical connectors in the dielectric material. Attached Figure Description

[0008] A better understanding of the various aspects of this disclosure can be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0009] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E and Figure 1F This is a schematic cross-sectional view of a packaging structure manufactured according to some embodiments.

[0010] Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A and Figure 4B This is a schematic side view of two device structures bonded together according to some embodiments.

[0011] Figure 5A and Figure 5B This is a schematic side view of the rear structure according to some embodiments.

[0012] Figure 6A and Figure 6B This is a schematic side view of a device structure manufactured according to some embodiments.

[0013] Figure 7A , Figure 7B , Figure 7C , Figure 7D and Figure 7E This is a schematic side view of a package structure manufactured according to some embodiments.

[0014] Figure 8A , Figure 8B and Figure 8C The illustration schematically demonstrates warp adjustment according to some embodiments. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature can include embodiments where the first and second features are formed in direct contact, and can also include embodiments where an additional feature can be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, this document may use spatially related terms (e.g., "below," "below," "lower than," "higher than," "above," "above," "top," "upper part," etc.) to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly.

[0017] Embodiments of this disclosure relate to methods for processing and bonding substrates to manufacture integrated circuit chips. The substrate may include semiconductor devices formed on the front side of the substrate and may be referred to as a device substrate. Specifically, embodiments of this disclosure provide a method for depositing a backside structure to protect devices on the substrate and / or adjust substrate warpage during bonding and packaging processes. In some embodiments, the backside structure is deposited in a batch process chamber, wherein layers of the backside structure are formed on both the front and back sides of the substrate. Layers formed on the back side of the substrate can reduce cavity defects.

[0018] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E and Figure 1FThis is a schematic cross-sectional view of a packaging structure 100 manufactured according to an embodiment of the present disclosure. Figure 1A As shown, front and back layers 104F and 104B are deposited on the front and back sides of wafer 102, respectively, and front and back layers 106F and 106B are deposited on the front and back layers 104F and 104B, respectively. In some embodiments, wafer 102 is a blank wafer made of the following: elemental semiconductors, such as crystalline silicon or crystalline germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), combinations thereof, or other suitable materials. In some embodiments, wafer 102 includes multilayer semiconductors and semiconductor-on-insulator (SOI), such as silicon-on-insulator or germanium-on-insulator.

[0019] In some embodiments, the front layer 104F and the back layer 104B are formed simultaneously and have substantially the same properties, such as composition and thickness. For example, the front layer 104F and the back layer 104B are deposited simultaneously in a process chamber, wherein both the front layer 102F and the back layer 102B of wafer 102 are exposed to the processing environment. The front layer and the back layer 104F, 104B can include any suitable dielectric material, such as oxides, such as SiO, SiO2, SiNO, SiONC, etc. In some embodiments, the front layer and the back layer 104F, 104B can include semiconductors, such as SiGe, SiP, etc. In some embodiments, when wafer 102 is a silicon wafer, the front dielectric layer 104F and the back dielectric layer 104B are made of or include silicon oxide. In some embodiments, the front layer and the back layer 104F, 104B can be deposited by any suitable process. In some embodiments, the front layer and the back layer 104F, 104B are formed by incorporating an oxide precursor into the process chamber. In some embodiments, one or more cleaning processes may be performed prior to the formation of the front and back layers 104F, 104B to remove native oxides and / or contaminants from the wafer 102.

[0020] The front layer 104F is sometimes referred to as a backing layer for subsequent patterning processes. In some embodiments, the front layer 104F and the back layer 104B have the same or different thicknesses T1. In some embodiments, the thickness T1 ranges from about 20 angstroms to about 2000 angstroms, for example from about 20 angstroms to about 60 angstroms.

[0021] In some embodiments, the front layer 106F and the back layer 106B are formed simultaneously and have substantially the same properties, such as composition and thickness. For example, the front layer 106F and the back layer 106B are formed simultaneously in a process chamber, wherein both the front dielectric layer 104F and the back dielectric layer 104B are exposed to the processing environment. In some embodiments, dielectric layers 104F, 104B, 106F, and 106B are deposited in the same process chamber.

[0022] The front and back layers 106F and 106B may comprise any suitable dielectric or semiconductor material, such as nitrides like SiN, SiNO, Si3N4, SiNC, SiONC, etc. In some embodiments, the front and back layers 106F and 106B may comprise semiconductors such as SiGe, SiP, etc. The materials of the front and back layers 106F and 106B are different from the materials of the front and back layers 104F and 104B. In some embodiments, the front layer 106F and back layer 106B are made of or comprise nitrides, such as silicon nitride. The front and back layers 106F and 106B can be deposited using any suitable process. In some embodiments, the front and back layers 106F and 106B are formed by flowing a nitrogen-containing precursor and a semiconductor-containing precursor into a process chamber. The front layer 106F and back layer 106B have the same or different thicknesses T2. In some embodiments, the thickness T2 ranges between about 100 angstroms and about 600 angstroms. The front layer 106F can be used as a hard mask layer during subsequent patterning processes. In some embodiments, the thickness T2 of the front layer 106F is greater than the thickness T1 of the front layer 104F. In some embodiments, the ratio R1 of the thickness T1 of the front layer 104F to the thickness T2 of the front layer 106F is between about 1:1 and about 1:18, for example, between about 1:9 and about 1:10.

[0023] While forming the front layer 104F and front layer 106F for subsequent FEOL processes, the back layer 104B and back layer 106B remain on the back side 102B of wafer 102 during wafer processing and can provide protection for wafer 102. However, during certain processes, such as bonding processes and wet cleaning processes, the back layers 104B and 106B, formed simultaneously with the front layers 104F and 106F respectively, cannot provide sufficient protection for wafer 102, resulting in cracks or cavity defects in wafer 102. Embodiments of this disclosure provide an improved back side structure to prevent damage to wafer 102 during wafer processing.

[0024] like Figure 1BAs shown, an etch stop layer 108 is deposited on the front layer 106F. The etch stop layer 108 can be made of or comprise any suitable material having an etch selectivity different from that of the front layer 106F. In some embodiments, the etch stop layer 108 comprises the same material as the front layer 104F. The etch stop layer 108 may have a thickness T3. In some embodiments, the thickness T3 ranges from about 50 angstroms to about 1000 angstroms.

[0025] In some embodiments, an etch stop layer 108 is formed in a process chamber on the back side of the package structure 100 where it is not exposed to the processing environment. Therefore, no material is formed on the back side layer 106B during the formation of the etch stop layer 108. The etch stop layer 108 can be formed by any suitable process, such as atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD).

[0026] like Figure 1C As shown, a front layer 110F and a back layer 110B are formed on the etch stop layer 108 and the back layer 106B, respectively. Similar to the front and back layers 104F, 104B and 106F, 106B, the front layer 110F and the back layer 110B are formed simultaneously and have substantially the same characteristics, such as composition and thickness. The front layer 110F and the back layer 110B are formed simultaneously in a processing chamber where both the etch stop layer 108 and the back layer 106B are exposed to the processing environment.

[0027] Back layer 110B has a thickness T4. In some embodiments, the thickness T4 ranges between about 100 angstroms and about 1600 angstroms. In some embodiments, back layer 110B comprises the same material as back layer 106B, and back layer 110B and back dielectric layer 106B have a combined thickness T5. In some embodiments, the thickness T5 ranges from about 200 angstroms to about 20000 angstroms. Back layers 106B and 110B having a thickness T5 can improve cavity defects during the bonding process. Furthermore, in embodiments where back layers 106B and 110B are made of silicon nitride, silicon nitride can cause greater stress and affect the warpage of package structure 100. In some embodiments, the ratio R2 of the thickness T1 of back layer 104B to the combined thickness T5 of back layers 106F and 110F is between about 1:20 and about 1:60. A smaller ratio R2 compared to ratio R1 (i.e., a larger thickness T5 compared to thickness T2) can improve cavity defects, stress, and warpage adjustment of the package structure 100.

[0028] like Figure 1CAs shown, back layers 110B, 106B, and 104B form a back structure 112. The back structure 112 can be retained on the wafer 102 during wafer processing to protect the back surface 102B of the wafer 102. In some embodiments, the back structure 112 can also serve as a stress adjustment or warpage adjustment structure to achieve a certain degree of warpage within the package structure 100.

[0029] like Figure 1D As shown, the front layer 110F is removed while the back layer 110B is retained. In some embodiments, the package structure 100 is placed in a process chamber where the back layer 110B is not exposed to the processing environment. The process chamber may be a dry etching chamber, such as a plasma etching chamber. In some embodiments, the front layer 110F is removed by a plasma etching process utilizing a plasma source and an etchant. The plasma source may be an inductively coupled plasma (ICP) source, a transformer-coupled plasma (TCP) source, an electron cyclotron resonance (ECR) source, a capacitor-coupled plasma (CCP) source, etc. In some embodiments, the etchant may include tetrafluoromethane (CF4), difluoromethylene (CH2F2), or hexafluoroethane (C2F6), and oxygen and / or nitrogen may be selectively added to control the etching rate and etching selectivity. In some embodiments, the etchant has higher etching selectivity for the front layer 110F relative to the etch stop layer 108. The etch stop layer 108 allows the front layer 110F to be removed without damaging the front layer 106F.

[0030] like Figure 1E As shown, the etch stop layer 108 is removed. The etch stop layer 108 can be removed by any process that substantially does not affect the front layer 106F. In some embodiments, a wet etching process is performed to remove the etch stop layer 108, while the front layer 106F is substantially unaffected by the wet etching process. In some embodiments, the wet etching process includes immersion in diluted HF.

[0031] In some embodiments, the package structure 100 includes a wafer 102, front layers 104F and 106F disposed on the front side 102F of the wafer 102, and back layers 104B, 106B, and 110B disposed on the back side 102B of the wafer 102. In some embodiments, the front layer 104F and the back layer 104B are each composed of silicon oxide, and the front layer 106F and the back layers 106B and 110B are each composed of silicon nitride. The front layers 104F and 106F can be used as mask structures during the patterning process. The back layer 104B can be used as a transition layer because the material of the back layer 104B has better lattice matching with the material of the wafer 102 compared to the material of the back layer 106B. Back layers 106B and 110B can be used as protective layers to protect wafer 102, for example, by preventing cracks or cavities from appearing on the back side 102B of wafer 102 due to the characteristics of back layers 106B and 110B and their combined thickness T5. If back layers 106B and 110B are formed directly on the back side 102B of wafer 102 without back layer 104B, then back layers 106B and 110B may be easily peeled off from the back side 102B of wafer 102.

[0032] After removing the etch stop layer 108, a FEOL process is performed on wafer 102 to form multiple devices (not shown), and a back-end (BEOL) process can be performed to form interconnect structures 120 on wafer 102, such as... Figure 1F As shown. In some embodiments, the multiple devices include multiple application-specific integrated circuit (ASIC) devices. In some embodiments, the multiple devices constitute logic circuits, memory circuits, sensor circuits, etc. In some embodiments, the multiple devices constitute control circuits for sensor circuits. In some embodiments, the multiple devices include transistors, capacitors, diodes, resistors, etc. In some embodiments, the devices are transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, PFETs / NFETs, or other suitable transistors. The transistor can be a planar field-effect transistor (FET), a FinFET, a nanostructure transistor, or other suitable transistor. Nanostructure transistors can include nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor with a gate electrode surrounding a channel.

[0033] The interconnect structure 120 can be formed using BEOL fabrication technology. BEOL includes the formation and patterning of dielectric and conductive metal layers. The interconnect structure 120 includes multiple conductive features 118, such as conductive lines and conductive vias, embedded in the dielectric structure 116.

[0034] like Figure 1F As shown, the package structure 100 also includes a structure 150 bonded to the interconnect structure 120. In some embodiments, the structure 150 includes a CMOS image sensor (CIS) device. In some embodiments, the CIS device is a back-illuminated (BSI) CIS device. For example, in some embodiments, the structure 150 includes an interconnect structure 151 and a wafer 158 disposed on the interconnect structure 151. The interconnect structure 151 includes a dielectric layer 152 and conductive features 154 embedded in the dielectric layer 152. In some embodiments, the top surface of the interconnect structure 120 is configured to be bonded to the top surface of the interconnect structure 151 of the structure 150. A microlens array 156 may be formed on the wafer 158. Thus, in some embodiments, the wafer 102 is a logic circuit wafer including logic circuitry, and the structure 150 is a sensor wafer having a BSI sensing integrated circuit. The logic circuit wafer and the sensor wafer are bonded to form a three-dimensional integrated circuit (3DIC).

[0035] The logic circuit wafer and the sensor wafer are bonded using any suitable process, such as direct bonding, hybrid bonding, etc. Pressure may be applied to the package structure 100 during the bonding process. The back cover structure 112 protects the back cover 102B of the wafer 102 during the bonding process. Furthermore, the back cover structure 112 protects the wafer 102 from damage by processing chemicals during the wet etching process.

[0036] Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A and Figure 4B This is a schematic side view of two device structures 200, 202 bonded together according to some embodiments. Figure 2A As shown, device structures 200 and 202 will be bonded together. In some embodiments, device structures 200 and 202 are wafers having devices and interconnect structures formed thereon. For example, device structure 200 may include... Figure 1F The wafer 102, multiple devices, and interconnect structure 120, the device structure 202 including Figure 1F The interconnect structure 151, wafer 158, and microlens array 156. In some embodiments, device structure 200 is a die, and device structure 202 is a die. Figure 2A As shown, device structure 200 has an adhesive surface 204 that will be bonded to adhesive surface 206 of device structure 200. Adhesive surface 204 may be the top surface of the topmost layer of device structure 200. For example, adhesive surface 204 may be interconnect structure 120. Figure 1FThe bonding surface 206 can be the top surface of the top layer of the device structure 202. For example, the bonding surface 206 can be the top surface of the interconnect structure 151. Figure 1F The top surface of the adhesive surface 204. In some embodiments, the cross-sectional profile of the adhesive surface 204 does not match the cross-sectional profile of the adhesive surface 206. For example, as Figure 2A As shown, the adhesive surface 204 is substantially flat, while the adhesive surface 206 is curved, for example, having a concave cross-sectional profile.

[0037] In some embodiments, in order to change the cross-sectional profile of the adhesive surface 204, a back surface structure 210 is formed on the back surface 208 of the device structure 200, such as... Figure 2B As shown. The back structure 210 includes at least one protective layer 212 and at least one cushioning layer 214. In some embodiments, the protective layer 212 comprises the same material as the back layer 104B, and the cushioning layer 214 comprises the same material as the back layer 106B. In some embodiments, two or more protective layers 212 and two or more cushioning layers 214 are stacked alternately, as shown. Figure 2B As shown. As described above, the materials of the protective layer 212 and the wafer 102 have better lattice matching compared to the materials of the buffer layer 214 and the wafer 102. Furthermore, the protective layer 212 tends to cause concave (smile-shaped) warping, while the buffer layer 214 tends to cause convex (frowning) warping. Therefore, in some embodiments, the thickness of the buffer layer 214 is much greater than the thickness of the protective layer 212 to cause convex warping. For example... Figure 2B As shown, after the back structure 210 is formed on the back surface 208 of the device structure 200, the device structure 200 has a convex warp, and the bonding surface 204 has a convex cross-sectional profile. The convex cross-sectional profile of the bonding surface 204 matches the concave cross-sectional profile of the bonding surface 206. Therefore, the bonding process for bonding the device structure 200 and the device structure 202 is improved.

[0038] In some embodiments, such as Figure 3A As shown, device structure 200 includes a curved (e.g., having a convex cross-sectional profile) adhesive surface 204, and device structure 202 includes a curved (e.g., having a convex cross-sectional profile) adhesive surface 206. In some embodiments, the cross-sectional profile of the adhesive surface 204 is modified by forming a back surface structure 210 on the back surface 208 of device structure 200, such as... Figure 3B As shown. As described above, the back structure 210 includes alternating protective layers 212 and buffer layers 214. In some embodiments, the thickness of the protective layer 212 is greater than the thickness of the buffer layer 214 because the protective layer 212 tends to cause concave warping. Therefore, with the back structure 210 having a thicker protective layer 212, the cross-sectional profile of the adhesive surface 204 changes from convex to concave, as... Figure 3B As shown. The concave profile of the adhesive surface 204 matches the convex profile of the adhesive surface 206, as... Figure 3B As shown.

[0039] In some embodiments, such as Figure 4A As shown, device structure 200 includes a curved (e.g., having a convex cross-sectional profile) adhesive surface 204, and device structure 202 includes a curved (e.g., having a convex cross-sectional profile) adhesive surface 206. In some embodiments, the cross-sectional profiles of both adhesive surfaces 204 and 206 are altered by forming a back surface structure 210 on the back surface 208 of device structure 200 and the back surface 216 of device structure 202, such as... Figure 4B As shown. As described above, the back structure 210 includes alternating protective layers 212 and buffer layers 214. In some embodiments, the thickness of the protective layer 212 is greater than the thickness of the buffer layer 214 because the protective layer 212 tends to cause concave warping. Therefore, with the back structure 210 having a thicker protective layer 212, the cross-sectional profile of the adhesive surface 204 changes from convex to concave, as... Figure 4B As shown. In some embodiments, the convex bonding surface 206 of device structure 202 does not match the concave bonding surface 204 of device structure 200. Therefore, a back structure 210 is formed on the back surface 216 of device structure 202 to change the curvature of the bonding surface 206 of device structure 202. In some embodiments, the bonding surface 206 becomes more convex due to the addition of the back structure 210, and the back structure 210 including a protective layer 212 that is thicker than the buffer layer 214. In some embodiments, the bonding surface 206 becomes less convex due to the addition of the back structure 210, and the back structure 210 including a buffer layer 214 that is thicker than the protective layer 212. By changing the cross-sectional profile of the bonding surface 204 from convex to concave, and by changing the cross-sectional profile of the bonding surface 206 from convex to more convex or less convex, the matching of the bonding surfaces 204 and 206 is improved.

[0040] Figure 2B , Figure 3B and Figure 4B The backside structure 210 shown alters the device structure 200 (and Figure 4B The warping of the device structure 202 in the middle is used to change the bonding surface 204 (and Figure 4B The cross-sectional profile of the bonding surface 206 is such that bonding surfaces 204 and 206 match. Furthermore, the back surface structure 210 protects the back surface 208 of the device structure 200 (and the back surface 216 of the device structure 202) during the bonding process, similar to... Figure 1F The back structure 112 of the protected wafer 102.

[0041] Device structures 200 and 202 can be any suitable structure. In some embodiments, device structure 200 is a logic wafer, device structure 202 is another logic wafer, and the bonding of device structures 200 and 202 is wafer-to-wafer bonding. In some embodiments, device structure 200 is a die, device structure 202 is a die, and the bonding of device structures 200 and 202 is die-to-die bonding. In some embodiments, device structure 200 is a wafer, device structure 202 is a die, and the bonding of device structures 200 and 202 is die-to-wafer bonding. The bonding of device structures 200 and 202 can form other types of packages, such as chip-on-wafer-on-substrate (CoWoS) packages, system-on-chip (SoIC) packages, stacked memory device packages, etc.

[0042] Figure 5A and Figure 5B This is a schematic side view of a back structure 210 according to some embodiments. In some embodiments, the back structure 210 includes alternating protective layers 212 and buffer layers 214, such as... Figure 5A As shown. The number of protective layers 212 can range from 1 to 50, and the number of buffer layers 214 can range from 1 to 50. In some embodiments, the thickness of the protective layer 212 is substantially constant, and the thickness of the buffer layer 214 is substantially constant. In some embodiments, the thickness of the protective layer 212 is substantially the same as the thickness of the buffer layer 214. In some embodiments, the thickness of the protective layer 212 is significantly different from the thickness of the buffer layer 214. As described above, in some embodiments, the thickness of the protective layer 212 is greater than the thickness of the buffer layer 214 to cause concave warping. In some embodiments, the thickness of the buffer layer 214 is greater than the thickness of the protective layer 212 to cause convex warping.

[0043] In some embodiments, the thickness of the buffer layer 214 is not constant, such as... Figure 5BAs shown. For example, the backside structure 210 includes a protective layer 212 and buffer layers 214a-c. Buffer layer 214a is closest to the backside of the wafer (or die) on which the backside structure 210 is formed, and buffer layer 214c is furthest from the backside of the wafer (or die). In some embodiments, the thickness of buffer layers 214a-c increases in the direction away from the wafer. For example, buffer layer 214a has a first thickness, buffer layer 214b has a second thickness greater than the first thickness, and buffer layer 214c has a third thickness greater than the second thickness. As described above, a protective layer 212 is formed between the buffer layer 214 and the wafer due to lattice mismatch between the buffer layer 214 and the wafer. In some embodiments, the thickness of the buffer layer 214 is increased to cause convex warping of the wafer. If the thickness of the buffer layer 214 is greater than a threshold, the buffer layer 214 may be easily peeled off. Therefore, to accommodate a thicker buffer layer 214, an additional protective layer 212 is formed in the backside structure 210 to separate the thicker buffer layer 214. As the buffer layer 214 moves further away from the wafer, the risk of stripping decreases. Therefore, the thickness of the buffer layer 214 increases as it moves further away from the wafer. Although Figure 5B Three protective layers 212 and three buffer layers 214a-c are shown, but other numbers of protective layers 212 and buffer layers 214a-c may also be used. In some embodiments, the backside structure 210 includes alternating protective layers 212 and buffer layers 214, and the thickness of the buffer layers 214 increases in a direction away from the wafer (or die) on which the backside structure 210 is formed. The thickness of the protective layers 212 may remain substantially constant.

[0044] In some embodiments, the thickness of the protective layer 212 increases in the direction away from the wafer, while the thickness of the buffer layer 214 remains constant. In some embodiments, the buffer layer 214 provides protection for the wafer, and the protective layer 212 is softer than the buffer layer 214 and can provide cushioning when the wafer is held by a substrate holder.

[0045] Figure 6A and Figure 6B This is a schematic side view of a device structure 200 manufactured according to some embodiments. In some embodiments, such as Figure 6AAs shown, device structure 200 is placed in a process chamber, with both the front and back sides of device structure 200 exposed to the processing environment. Next, a back structure 210 is formed on the back side of device structure 200, and a front structure 250 is formed on the front side of device structure 200. In some embodiments, the back structure 210 and the front structure 250 are formed simultaneously. The layers of the back structure 210 are formed sequentially, and the layers of the front structure 250 are formed simultaneously with the corresponding layers of the back structure 210. Because the front structure 250 and the back structure 210 are formed simultaneously on device structure 200, warpage of device structure 200 is not affected, as the front structure 250 and the back structure 210 are formed on the front and back sides of device structure 200, respectively.

[0046] Next, as Figure 6B As shown, the front structure 250 is removed. The device structure 200, having the front structure 250 and the back structure 210, can be placed in an etching chamber, wherein the back structure 210 is not exposed to the processing environment. The layers of the front structure 250 can be removed by one or more etching processes. The etching process can be a dry etching process, a wet etching process, or a combination thereof. After removing the front structure 250, the warpage (or lack thereof) of the device structure 200 is adjusted to better match the warpage of another device structure (e.g., device structure 202) to which the device structure 200 will be bonded.

[0047] In some embodiments, device structure 200 is a blank wafer or a blank carrier wafer. Backside structure 210 can adjust the warpage of the blank wafer such that, after the components are formed or bonded to the blank wafer, the warpage can match the warpage of the device of the elements to be bonded to the blank wafer.

[0048] In some embodiments, the backside structure 210 is formed in a process chamber in which the backside of the device structure 200 is exposed to the processing environment, while the frontside of the device structure 200 is not exposed to the processing environment. The backside structure 210 is then formed on the backside of the device structure 200, while the frontside structure 250 is not formed on the frontside of the device structure 200.

[0049] Figure 7A , Figure 7B , Figure 7C , Figure 7D and Figure 7E This is a schematic side view of a package structure 100 manufactured according to some embodiments. In some embodiments, such as Figure 7AAs shown, the package structure 100 is a CoWoS package. The package structure 100 includes a carrier 302, an adhesive layer 304 disposed on the carrier 302, and a plurality of dies 308 disposed on the adhesive layer 304. The dies 308 can be any suitable die, such as an integrated circuit die. The dies 308 can be separated by a dielectric material 306. The dielectric material 306 can be any suitable dielectric material. In some embodiments, the dielectric material 306 is a molding material for encapsulating the dies 308. An interconnect structure 310 is disposed on the dies 308. The interconnect structure 310 includes conductive features 312 formed in one or more dielectric layers. The interconnect structure 310 is bonded to an interconnect structure 314. The interconnect structure 314 may include conductive features electrically connected to the conductive features 312 of the interconnect structure 310. The interconnect structures 310 and 314 can be bonded by any suitable process, such as direct bonding or hybrid bonding. An interposer substrate 320 is disposed on the interconnect structure 314, and a plurality of vias 318 are formed in the interposer substrate 320. In some embodiments, the vias 318 are through-holes through the substrate. The interposer substrate 320 and the interconnect structure 314 may be formed separately from the die 308 and the interconnect structure 310. Similarly, the die 308 and the interconnect structure 310 may be formed on the carrier 302 before being bonded to the interconnect structure 314 and the interposer substrate 320.

[0050] like Figure 7B As shown, the intermediate substrate 320 is thinned to expose the via 318. The intermediate substrate 320 can be thinned by grinding, lapping, etching, polishing, other suitable processes, or combinations thereof. Next, as... Figure 7C As shown, a backside structure 210 is formed on the intermediate substrate 320. The backside structure 210 may include alternating protective layers 212 and buffer layers 214, such as... Figure 7C As shown. In some embodiments, the interposer substrate 320 is a silicon substrate, and a protective layer 212 is formed on the interposer substrate 320 due to better lattice matching. As described above, the thickness of the buffer layer 214 can vary, for example, increasing in a direction away from the interposer substrate 320. In some embodiments, the thickness of the buffer layer 214 is greater than the thickness of the protective layer 212 to cause a convex warping of the interposer substrate 320. In some embodiments, the thickness of the protective layer 212 is greater than the thickness of the buffer layer 214 to cause a concave warping of the interposer substrate 320.

[0051] In some embodiments, such as Figure 7DAs shown, the backside structure 210 is removed, while the interposer substrate 320 retains the warpage resulting from the presence of the backside structure 210. In other words, once the backside structure 210 forms warpage on the interposer substrate 320, removing the backside structure 210 will not affect the warpage. A dielectric material 322 is deposited on the interposer substrate 320, and an electrical connector 324 is formed in the dielectric material 322. The dielectric material 322 may include any suitable dielectric material. In some embodiments, the dielectric material 322 includes a polymer, such as polyimide. The electrical connector 324 is electrically connected to a corresponding via 318. The electrical connector 324 may be a solder ball, metal pillar, controlled collapse chip connection (C4) bump, microbump, bump formed by electroless nickel-palladium-immersion gold (ENEPIG) technology, etc. The electrical connector 324 may be formed by common methods such as vapor deposition, electroplating, printing, solder transfer, balling, etc.

[0052] In some embodiments, the back cover structure 210 is not removed, and an electrical connector 324 is formed in the back cover structure 210. For example, the electrical connector 324 extends through the protective layer 212 and the buffer layer 214 of the back cover structure 210 to electrically connect to the via 318.

[0053] like Figure 7E As shown, the package structure 100 is flipped and attached to the printed circuit board (PCB) 330, and the carrier 302 is removed. The carrier 302 can be removed by any suitable process. In some embodiments, a release film (not shown) is used to remove the carrier 302. In some embodiments, the adhesive layer 304 remains on the die 308, as... Figure 7E As shown. Electrical connector 324 is electrically connected to PCB 330. In some embodiments, the interposer substrate 320 has a concave warp due to a backside structure 210 formed thereon. The concave warp of the interposer substrate 320 improves the contact between the electrical connector 324 and PCB 330.

[0054] Figure 8A , Figure 8B and Figure 8C The illustration schematically demonstrates warp adjustment according to some embodiments. For example... Figure 8A As shown, the first die 402 will be bonded to the second die 410. In some embodiments, each first die 402 includes a circuit layer 404 electrically isolated by an isolation layer 406. In some embodiments, the circuit layer 404 includes a plurality of devices, such as Figure 1F The multiple devices described herein. Isolation layer 406 may include any suitable dielectric material. Multiple electrical connectors 408 are disposed above circuit layer 404, such as... Figure 1FAs shown. The interconnect structure 409 can be disposed below the circuit layer 404 and the isolation layer 406. The interconnect structure 409 is placed on the carrier 411, and the back surface structure 210 is formed on the back surface of the carrier 411, as shown. Figure 8A As shown. The back structure 210 may form a warp in the carrier 411 and the material disposed thereon. In some embodiments, a concave warp is formed, which allows the electrical connector 408 to be better connected to the second die 410.

[0055] like Figure 8A As shown, the second die 410 includes a circuit layer 412 electrically isolated by an isolation layer 414. An interposer substrate 416 is disposed beneath the circuit layer 412 and the isolation layer 414, and a plurality of vias 418 are formed in the interposer substrate 416. The vias 418 can be electrically connected to the respective circuit layer 412. The first die 402 and the second die 410 are bonded together such that an electrical connector 408 is electrically connected to the respective vias 418.

[0056] like Figure 8B As shown, instead of using an electrical connector 408, dielectric layers 452 and 456, each including conductive features 450 and 454, are used to bond the first die 402 to the second die 410. In some embodiments, the dielectric layer 452 is formed on each of the first dies 402, and the conductive feature 450 is formed in the dielectric layer 452. The back surface structure 210 can provide a curved top surface of the dielectric layer 452, allowing the top surface of the dielectric layer 452 to better mate with the bottom surface of the dielectric layer 456. The dielectric layer 456 and the conductive feature 454 are disposed beneath the intermediate substrate 416. In some embodiments, each via 418 is electrically connected to the corresponding conductive feature 454, such as... Figure 8B As shown. The back structure 210 can be used in a manner similar to... Figure 2B and Figure 3B The back structure 210 is described in the text.

[0057] In some embodiments, the cross-sectional profile of the bottom surface of the dielectric layer 456 can be altered by the back structure 210, such as... Figure 8C As shown. In some embodiments, a carrier 460 is formed over the circuit layer 412 and the isolation layer 414, and a back surface structure 210 is formed on the carrier 460. The back surface structure 210 can change the cross-sectional profile of the bottom surface of the dielectric layer 456, such that the bottom surface of the dielectric layer 456 can be aligned with the top surface of the dielectric layer 452 of the first die 402. Figure 8B For better fit. The back structure 210 and carrier 460 can be removed after the first die 402 is bonded to the second die 410. The back structure 210 can be used in a similar manner to Figure 4B The back structure 210 is described in the text.

[0058] Figures 8A to 8C The package shown can be a System-on-a-Chip (SoIC) package. The backside structure 210 forms a warp (or alters the cross-sectional profile of the top and / or bottom surfaces to be bonded) within one or more dies to improve the bonding process and die adhesion. The backside structure 210 can be used for other types of packages.

[0059] This disclosure provides methods for forming a package structure 100 in various embodiments. In some embodiments, the method includes forming a back surface structure 210 on the back surface of the device structure 200. The back surface structure 210 includes alternating protective layers 212 and buffer layers 214. Some embodiments may achieve advantages. For example, the protective layer 212 tends to cause concave warpage on the device structure 200, and the buffer layer 214 tends to cause convex warpage on the device structure 200. By adjusting the warpage of the device structure 200, adhesion between the device structure 200 and another device structure is improved.

[0060] One embodiment is a method. The method includes: depositing a first layer on the front side of a wafer and depositing a second layer on the back side of the wafer; depositing a third layer on the first layer and a fourth layer on the second layer; depositing an etch stop layer on the third layer; depositing a fifth layer on the etch stop layer and a sixth layer on the fourth layer; removing the fifth layer by a first process; and removing the etch stop layer by a second process.

[0061] Another embodiment is a method. The method includes providing a first device structure having a first surface and a second surface opposite to the first surface, the second surface having a first cross-sectional profile. The method further includes depositing a first structure on the first surface, the first structure causing the second surface to have a second cross-sectional profile different from the first cross-sectional profile. The method further includes bonding the first device structure to a second device structure.

[0062] Another embodiment is a method. The method includes: bonding an interposer substrate to one or more dies; removing a portion of the interposer substrate to expose one or more vias; and depositing a structure on the interposer substrate and the vias. Depositing the structure includes: depositing a first protective layer on the interposer substrate and the vias, depositing a first buffer layer on the first protective layer, depositing a second protective layer on the first buffer layer, and depositing a second buffer layer on the second protective layer. The method further includes: removing the structure; depositing a dielectric material on the interposer substrate and the vias; and forming one or more electrical connectors in the dielectric material.

[0063] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0064] Example 1 is a method for forming a semiconductor structure, comprising: depositing a first layer on the front side of a wafer and depositing a second layer on the back side of the wafer; depositing a third layer on the first layer and depositing a fourth layer on the second layer; depositing an etch stop layer on the third layer; depositing a fifth layer on the etch stop layer and depositing a sixth layer on the fourth layer; removing the fifth layer by a first process; and removing the etch stop layer by a second process.

[0065] Example 2 is the method described in Example 1, wherein the first layer and the second layer each comprise oxides, and the third layer and the fourth layer each comprise nitrides.

[0066] Example 3 is the method described in Example 2, wherein the sixth layer comprises the same material as the fourth layer.

[0067] Example 4 is the method described in Example 3, wherein the first layer has a first thickness, the second layer has a second thickness, the third layer has a third thickness, and the fourth layer and the sixth layer together have a fourth thickness.

[0068] Example 5 is the method described in Example 4, wherein the fourth thickness is greater than the second thickness.

[0069] Example 6 is the method described in Example 4, wherein a first ratio of the first thickness to the third thickness is less than a second ratio of the second thickness to the fourth thickness.

[0070] Example 7 is the method described in Example 6, wherein the first ratio is between 1:1 and 1:18, and the second ratio is between 1:20 and 1:60.

[0071] Example 8 is the method described in Example 1, wherein the first process is a dry etching process.

[0072] Example 9 is the method described in Example 8, wherein the second process is a wet etching process.

[0073] Example 10 is a method of forming a semiconductor structure, comprising: providing a first device structure, wherein the first device structure has a first surface and a second surface opposite to the first surface, and the second surface has a first cross-sectional profile; depositing a first structure on the first surface, wherein the first structure causes the second surface to have a second cross-sectional profile different from the first cross-sectional profile; and bonding the first device structure to a second device structure.

[0074] Example 11 is the method described in Example 10, wherein the first structure includes alternating protective layers and buffer layers.

[0075] Example 12 is the method of Example 11, wherein the protective layer comprises an oxide layer and the buffer layer comprises a nitride layer.

[0076] Example 13 is the method described in Example 12, wherein the thickness of the buffer layer increases in a direction away from the first surface.

[0077] Example 14 is the method described in Example 12, wherein the thickness of the buffer layer is greater than the thickness of the protective layer, the first cross-sectional profile is flat, and the second cross-sectional profile is convex.

[0078] Example 15 is the method described in Example 12, wherein the thickness of the buffer layer is less than the thickness of the protective layer, the first cross-sectional profile is convex, and the second cross-sectional profile is concave.

[0079] Example 16 is the method of Example 10, further comprising: depositing a second structure on a surface of the second device structure opposite to the adhesive surface of the second device structure, wherein the cross-sectional profile of the adhesive surface is altered by the second structure.

[0080] Example 17 is a method of forming a semiconductor structure, comprising: bonding an interposer substrate to one or more dies; removing a portion of the interposer substrate to expose one or more vias; depositing a structure on the interposer substrate and the vias, including: depositing a first protective layer on the interposer substrate and the vias; depositing a first buffer layer on the first protective layer; depositing a second protective layer on the first buffer layer; and depositing a second buffer layer on the second protective layer; removing the structure; depositing a dielectric material on the interposer substrate and the vias; and forming one or more electrical connectors in the dielectric material.

[0081] Example 18 is the method described in Example 17, wherein the thickness of the first buffer layer is greater than the thickness of the first protective layer.

[0082] Example 19 is the method described in Example 17, wherein the thickness of the second buffer layer is greater than the thickness of the first buffer layer.

[0083] Example 20 is the method described in Example 19, wherein the thickness of the first protective layer is the same as the thickness of the second protective layer.

Claims

1. A method of forming a semiconductor structure, comprising: depositing a first layer on a front side of a wafer and a second layer on a back side of the wafer; depositing a third layer on the first layer and a fourth layer on the second layer; depositing an etch stop layer on the third layer; depositing a fifth layer on the etch stop layer and a sixth layer on the fourth layer; removing the fifth layer by a first process; and removing the etch stop layer by a second process. the first layer and the second layer each comprise an oxide, and the third layer and the fourth layer each comprise a nitride.

2. The method of claim 1, wherein, the sixth layer comprises the same material as the fourth layer.

3. The method of claim 2, wherein, the first layer has a first thickness, the second layer has a second thickness, the third layer has a third thickness, and the fourth layer and the sixth layer collectively have a fourth thickness.

4. The method of claim 3, wherein, the fourth thickness is greater than the second thickness.

5. The method of claim 4, wherein, a first ratio of the first thickness to the third thickness is less than a second ratio of the second thickness to the fourth thickness.

6. The method of claim 4, wherein, the first ratio is between one to one and one to eighteen, and the second ratio is between one to twenty and one to sixty.

7. The method of claim 6, wherein, the first process is a dry etch process.

8. The method of claim 1, wherein, 9. A method of forming a semiconductor structure, comprising: providing a first device structure, wherein the first device structure has a first surface and a second surface opposite the first surface, and the second surface has a first cross-sectional profile; depositing a first structure on the first surface, wherein the first structure causes the second surface to have a second cross-sectional profile different from the first cross-sectional profile; and bonding the first device structure to a second device structure.

10. A method of forming a semiconductor structure, comprising: bonding an interposer to one or more dies; removing a portion of the interposer to expose one or more vias; depositing a structure on the interposer and the vias, comprising: depositing a first protective layer on the interposer and the vias; depositing a first buffer layer on the first protective layer; depositing a second protective layer on the first buffer layer; and depositing a second buffer layer on the second protective layer; removing the structure; depositing a dielectric material on the interposer and the vias; and forming one or more electrical connectors in the dielectric material. ​

Images