Package structure and manufacturing method thereof

Abstract

The invention provides a packaging structure and a manufacturing method thereof. The package structure includes a three-dimensional carrier and a die. The three-dimensional carrier includes a plurality of conductive circuit layers and a plurality of conductive pads. The plurality of conductive circuit layers are disposed in the three-dimensional carrier. The plurality of conductive pads are arranged on the upper surface, the lower surface and the plurality of side surfaces of the three-dimensional carrier, wherein the plurality of side surfaces are connected between the upper surface and the lower surface. The crystal grains are arranged on at least one of the upper surface and / or the plurality of side surfaces of the three-dimensional carrier.

Description

Technical Field

[0001] This application relates to the structure of an electronic device and a method for manufacturing the same, and more particularly to a packaging structure and a method for manufacturing the same. Background Technology

[0002] With the development of technology, in order to enable chips to have diverse functions within a limited space, multiple chips are generally stacked together. However, each chip generates a lot of heat during operation, and the stacked structure makes heat dissipation difficult for each chip, causing heat to concentrate in the middle of the chip and reducing chip performance and reliability. In addition, if there are defective chips in the stacked package, it is difficult to replace them, leading to increased production costs. Summary of the Invention

[0003] This application relates to a packaging structure and manufacturing method that can improve the heat dissipation efficiency of the packaging structure and thus enhance its performance.

[0004] According to an embodiment of this application, the encapsulation structure includes a three-dimensional carrier and a die. The three-dimensional carrier includes multiple conductive circuit layers and multiple conductive pads. The multiple conductive circuit layers are disposed in the three-dimensional carrier. The multiple conductive pads are disposed on the upper surface, lower surface, and multiple sides of the three-dimensional carrier, wherein the multiple sides are connected between the upper surface and the lower surface. The die is disposed on the upper surface and / or at least one of the multiple sides of the three-dimensional carrier.

[0005] In the packaging structure according to an embodiment of this application, the three-dimensional carrier is formed by stacking multiple glass substrates, wherein multiple conductive line layers are disposed on the upper surface of the multiple glass substrates.

[0006] In the packaging structure according to an embodiment of this application, some of the aforementioned conductive pads are disposed on the sides of a plurality of glass substrates.

[0007] In the packaging structure according to the embodiments of this application, the three-dimensional carrier further includes a plurality of conductive vias connected between adjacent conductive line layers.

[0008] In the packaging structure according to an embodiment of this application, the aforementioned plurality of conductive vias penetrate through the corresponding plurality of glass substrates, so that the lower surfaces of the plurality of glass substrates expose the corresponding plurality of conductive vias.

[0009] In the packaging structure according to an embodiment of this application, the three-dimensional carrier further includes a welding material disposed on a plurality of conductive vias exposed on the lower surfaces of a plurality of glass substrates to bond with the conductive line layers of adjacent plurality of glass substrates.

[0010] In the packaging structure according to an embodiment of this application, the plurality of glass carrier plates mentioned above include a first glass carrier plate and a second glass carrier plate disposed below the first glass carrier plate, wherein the lower surface of the first glass carrier plate faces the upper surface of the second glass carrier plate.

[0011] In the packaging structure according to the embodiments of this application, the above-described packaging structure further includes a substrate, wherein the lower surface of the three-dimensional carrier faces the substrate and is electrically connected to the substrate.

[0012] In the packaging structure according to an embodiment of this application, the aforementioned die corresponds to and contacts multiple conductive pads on multiple sidewalls of a three-dimensional carrier through multiple conductive connectors, so as to electrically connect with the substrate.

[0013] According to embodiments of this application, a method for manufacturing a packaging structure includes the following steps: Providing a plurality of glass substrates, each of which includes a conductive portion; bonding the plurality of glass substrates vertically to form a three-dimensional carrier; bonding the lower surface of the three-dimensional carrier to a substrate; and bonding a die to the upper surface and / or side surface of the three-dimensional carrier, wherein the lower surface of the three-dimensional carrier is opposite to the upper surface, and the side surface of the three-dimensional carrier is connected between the upper and lower surfaces of the three-dimensional carrier.

[0014] In the manufacturing method of the packaging structure according to an embodiment of this application, the manufacturing method of each of the plurality of glass substrates described above includes the following steps: Providing a blank glass substrate. Forming grooves and / or through holes penetrating the blank glass substrate in the upper surface and / or side surface of the blank glass substrate by laser engraving, the grooves and / or through holes corresponding to a preset circuit layout pattern. Forming a conductive material in the grooves and / or through holes to form conductive portions.

[0015] In the manufacturing method of the packaging structure according to the embodiments of this application, the above-mentioned forming of conductive material in the groove and / or through hole includes depositing a conductive material layer on the blank glass substrate and in the groove and / or through hole, and removing excess conductive material layer on the blank glass substrate by a planarization process.

[0016] In the manufacturing method of the packaging structure according to an embodiment of this application, the conductive portion includes a conductive circuit layer, conductive pads, and / or conductive vias. The conductive circuit layer is located in the upper surface of the glass substrate, the conductive pads are located in the side surface of the glass substrate, and the conductive vias penetrate the glass substrate and are exposed on the lower surface of the glass substrate.

[0017] In the manufacturing method of the packaging structure according to an embodiment of this application, the plurality of glass substrates mentioned above include a first glass substrate and a second glass substrate, and the manufacturing method further includes the following steps: Before bonding the plurality of glass substrates together, solder balls are formed on the conductive vias exposed on the lower surface of the first glass substrate. The solder balls on the lower surface of the first glass substrate are bonded to the pad portions of the conductive circuit layer on the upper surface of the second glass substrate.

[0018] In the manufacturing method of the packaging structure according to an embodiment of this application, the method of joining the plurality of glass substrates together includes a laser welding process.

[0019] Based on the above, the packaging structure of this application includes a three-dimensional carrier, and each surface of the three-dimensional carrier can have conductive pads for external connection, so that the die can be disposed on multiple surfaces (e.g., the upper surface and the side surface) of the three-dimensional carrier, thereby dispersing the heat generated by the die, improving the heat dissipation efficiency of the packaging structure and thus enhancing its performance.

[0020] The other effects and embodiments of this application are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1A , Figure 1B , Figure 1C , Figure 2 , Figure 3 and Figure 4 This is a schematic diagram of the manufacturing process of a packaging structure according to an embodiment of this application. Detailed Implementation

[0023] In the embodiments described below, the positional relationships include: up, down, left, and right. Unless otherwise specified, they are all based on the direction shown by the components in the diagram.

[0024] Figure 1A , Figure 1B , Figure 1C , Figure 2 , Figure 3 and Figure 4 This is a schematic diagram of the manufacturing process of a packaging structure 10 according to an embodiment of this application, wherein... Figure 1A and Figure 1B It is a 3D schematic diagram; Figure 1C ,Figure 2 , Figure 3 and Figure 4 This is a cross-sectional view. In some embodiments, Figure 1C It can be Figure 1B A cross-sectional schematic diagram of one embodiment; Figure 2 It can be along Figure 1A A cross-sectional view of section line A-A'.

[0025] Please refer to Figure 1A The system provides a plurality of glass substrates 100a to 100i, each of which may include a conductive portion (e.g., glass substrate 100a may include a conductive portion 110a). Each of the plurality of glass substrates 100a to 100i may be similar to Figure 1B and Figure 1C The glass carrier plate 100 shown below, hereinafter referred to as Figure 1B and Figure 1C The glass carrier 100 shown is used as an example to represent each of the plurality of glass carriers 100a to 100i, and the plurality of glass carriers 100a to 100i may also be collectively referred to as glass carrier 100. In some embodiments, the thickness of the glass carrier 100 may be greater than 0.3 mm. In some embodiments, such as Figure 1B and Figure 1C As shown, the conductive portion 110 may include a conductive wiring layer 112, conductive vias 114, and conductive pads 116. The conductive wiring layer 112 is located in a recess in the upper surface 100T of the glass substrate 100 to provide a horizontal wiring layout. The conductive pads 116 are located in the sides of the glass substrate 100 (e.g., sides 100S1 and 100S2) to provide external connections to external components. The conductive vias 114 penetrate the glass substrate 100 and are exposed on the lower surface 100B of the glass substrate 100 to provide a vertical wiring layout.

[0026] In some embodiments, the conductive circuit layer 112 may include a conductor portion 1121 and a pad portion 1122. The width of the pad portion 1122 may be greater than the line width of the conductor portion 1121, so that the endpoints of the conductive via 114 can be conveniently electrically connected to different glass substrates or other components. In some embodiments, the pad portion 1122 may have a rectangular, circular, or elliptical shape from a top-view perspective, but this application is not limited thereto, and the top-view shape of the pad portion 1122 can be adjusted to any shape according to actual needs.

[0027] In some embodiments, the conductive line layer 112 is located only in the groove on the upper surface 100T of the glass carrier plate 100, and not in the lower surface 100B of the glass carrier plate 100. However, this application is not limited thereto, and in other embodiments, the conductive line layer 112 may also be located in the lower surface 100B of the glass carrier plate 100. In some embodiments, the conductive line layer 112 may also be located in the sides of the glass carrier plate 100 (e.g., sides 100S1-100S4), and this application is not limited thereto.

[0028] It should be understood that Figure 1B and Figure 1C Although the conductive pad 116 is shown located on sides 100S1 and 100S2 of the glass carrier 100, this is not intended to limit the application. The conductive pad 116 may be located on any one or more of the four sides (including sides 100S1, 100S2, 100S3, and 100S4) of the glass carrier 100. Furthermore, Figure 1B and Figure 1C The arrangement of the conductive circuit layer 112, conductive via 114 and conductive pad 116 is only schematically shown and is not intended to limit this application. Each of the plurality of glass substrates 100a-100i may arrange the conductive circuit layer 112, conductive via 114 and conductive pad 116 according to actual needs (such as layout design, design rules, etc.).

[0029] In some embodiments, the method of manufacturing the glass substrate 100 may include the following steps. First, a blank glass substrate 100' is provided. The blank glass substrate 100' may be a quartz glass substrate, a phosphosilicate glass substrate, a borosilicate glass substrate, a fluorosilicate glass substrate, or other suitable glass substrate. Then, by laser engraving, a groove R and / or a through hole TH penetrating the blank glass substrate 100' are formed in the surface (e.g., the upper surface 100T, side surface 100S1, side surface 100S2, side surface 100S3, and / or side surface 100S4). The groove R and / or the through hole TH correspond to a preset circuit layout pattern. That is, the scanning trajectory of the laser engraving is substantially along the preset circuit layout pattern. The position of the groove R may correspond to the subsequently formed conductive circuit layer 112 and conductive pad 116, and the position of the through hole TH corresponds to the subsequently formed conductive via 114. Therefore, the pattern of the groove R and / or the through hole TH is substantially the same as the preset circuit layout pattern. In some embodiments, the formation of the groove R or the through hole TH can be controlled by adjusting the laser power. In some embodiments, the conductive line layer 112, conductive via 114, and conductive pad 116 may be formed in the same process step, but this application is not limited thereto. In other embodiments, the conductive line layer 112, conductive via 114, and conductive pad 116 may be formed in different process steps.

[0030] Subsequently, a conductive material is formed in the groove R and / or through-hole TH to form the conductive portion 110. For example, a conductive material layer (not shown) can be deposited on the blank glass substrate 100' and in the groove R and / or through-hole TH. Then, excess conductive material layer on the blank glass substrate 100' can be removed by a planarization process, for example, by removing the conductive material layer on the upper surface 100T of the blank glass substrate 100' by chemical mechanical polishing. A conductive line layer 112 and conductive pad 116 are then formed in the groove R, and a conductive via 114 is formed in the through-hole TH. Accordingly, a glass substrate 100 including the conductive portion 110 can be obtained.

[0031] In some embodiments, the conductive material layer may be a metallic material, such as copper, aluminum, tungsten, their alloys or other suitable metallic materials, and this application is not limited thereto.

[0032] Please refer to Figure 2 Multiple glass substrates 100a-100i are joined vertically to form a three-dimensional carrier 101. The multiple glass substrates 100a-100i are, for example, joined in the vertical direction N (indicated by...). Figure 4 Multiple glass substrates 100a-100i can be stacked on top of each other. For example, multiple glass substrates 100a-100i can be joined sequentially by laser welding. Specifically, the lower surface of glass substrate 100a (also referred to as the first glass substrate) can be aligned with the upper surface of glass substrate 100b (also referred to as the second glass substrate), and then the lower surface of glass substrate 100a can be joined with the upper surface of glass substrate 100b by laser welding; subsequently, the lower surface of glass substrate 100b can be aligned with the upper surface of glass substrate 100c, and then the lower surface of glass substrate 100b can be joined with the upper surface of glass substrate 100c by laser welding. In this way, multiple glass substrates 100a-100i can be joined sequentially to form a three-dimensional carrier 101.

[0033] In some embodiments, before bonding multiple glass substrates together, solder balls (not shown) may be formed on the exposed conductive vias 114a on the lower surface of the glass substrate (i.e., glass substrate 100a) overlying the adjacent glass substrates (e.g., glass substrate 100a and glass substrate 100b). Then, the solder balls on the lower surface of the glass substrate (i.e., glass substrate 100a) overlying the adjacent glass substrates (e.g., glass substrate 100a and glass substrate 100b) are bonded to the pad portion of the conductive line layer 112b on the upper surface of the glass substrate (i.e., glass substrate 100b) overlying the adjacent glass substrates (e.g., glass substrate 100a and glass substrate 100b).

[0034] In some embodiments, an annealing process may also be performed to strengthen the bond between the solder balls and the adjacent glass substrate. The annealing temperature may be selected based on the composition of the solder balls, and this application is not limited thereto.

[0035] In some embodiments, the lower surface of the upper glass carrier (e.g., glass carrier 100a) and the upper surface of the lower glass carrier (e.g., glass carrier 100b) are in direct contact with each other.

[0036] exist Figure 2 The three-dimensional carrier 101 is schematically illustrated and includes nine glass substrates, but this is not intended to limit the scope of this application. The number of glass substrates stacked can be adjusted according to actual needs.

[0037] exist Figure 2 In the three-dimensional carrier 101, there is an upper surface T, a lower surface B opposite to the upper surface T, and four side surfaces S1, S2 (e.g., ...) connecting the upper surface T and the lower surface B of the three-dimensional carrier 101. Figure 1A (as indicated), S3, S4 (such as) Figure 1A (As indicated). In this embodiment, the upper surface T of the three-dimensional carrier 101 is the upper surface of the glass carrier 100a, the lower surface B of the three-dimensional carrier 101 is the lower surface of the glass carrier 100i, and the sides S1, S2, S3, and S4 of the three-dimensional carrier 101 are composed of the sides 100S1-100S4 of multiple glass carriers 100a-100i.

[0038] In some embodiments, the upper surface T of the three-dimensional carrier 101 may expose the conductive circuit layer 112a of the glass substrate 100a. The lower surface B of the three-dimensional carrier 101 may expose the conductive vias 114i of the glass substrate 100i. The sides S1, S2, S3, and S4 of the three-dimensional carrier 101 may expose multiple conductive pads of the glass substrates. For example, side S1 of the three-dimensional carrier 101 may expose conductive pads 116b-116d of the glass substrates 100b-100d and conductive pads 116f-116h of the glass substrates 100f-100h, and side S3 of the three-dimensional carrier 101 may expose conductive pads 116d-116f of the glass substrates 100d-100f (labeled as follows). Figure 3 ) and the conductive pad 116i of the glass substrate 100i (marked in Figure 3 ). Figure 2 Although not shown in the drawings, it should be understood that the sides S2 and S4 of the three-dimensional carrier 101 can also expose corresponding conductive pads as needed, and this application is not limited thereto. In some embodiments, the pad portion of the conductive circuit layer 112a in the upper surface of the uppermost glass carrier plate (i.e., glass carrier plate 100a) of the three-dimensional carrier 101 (e.g., Figure 1BThe pad portion 1122 shown can be used as a conductive pad 116a for external connection of the three-dimensional carrier 101. That is, from another perspective, the conductive pad (e.g., conductive pad 116a) of the three-dimensional carrier 101 can also be located in a groove on the upper surface T of the three-dimensional carrier 101, and the conductive pad 116a can be exposed on the upper surface T of the three-dimensional carrier 101.

[0039] In some embodiments, the conductive vias of adjacent glass substrates can be connected to each other, allowing the conductive line layer of one of the multiple glass substrates to be connected across the multiple glass substrates to the conductive line layer of another of the multiple glass substrates. For example, the conductive line layer 112e of glass substrate 100e can be connected to the conductive line layer 112h of glass substrate 100h through conductive vias 114e, 114f, and 114g.

[0040] Please refer to Figure 3 Dies 120 (e.g., dies 120a, 120b, 120c, or 120d) are bonded to the upper surface T and / or sides (e.g., sides S1, S2, S3, S4) of the three-dimensional carrier 101. For example, die 120a can be bonded to the conductive pad 116a exposed on the upper surface T of the three-dimensional carrier 101 via conductive connector 122a. Dies 120b can be bonded to the conductive pads 116d-116f exposed on the side S3 of the three-dimensional carrier 101 via conductive connector 122b. Dies 120c and 120d can be bonded to the conductive pads 116b-116d, 116f-116h exposed on the side S1 of the three-dimensional carrier 101 via conductive connectors 122c and 122d, respectively. Since the grains 120 are bonded to the upper surface T and / or sides (e.g., sides S1, S2, S3, S4) of the three-dimensional carrier 101, if a defective grain is found among the bonded grains 120, it can be simply replaced while other good grains 120 are retained.

[0041] In some embodiments, conductive connectors 122a-122d (collectively referred to as conductive connectors 122) may be, for example, solder balls, conductive bumps, conductive posts or other suitable conductive connectors, but this application is not limited thereto.

[0042] Figure 3 The diagram only schematically illustrates four grains 120 bonded to the upper surface T and sides S1 and S3 of the three-dimensional carrier 101, but it is not intended to limit this application. The number of grains and their bonding positions with the three-dimensional carrier can be adjusted according to actual needs.

[0043] Please refer to Figure 4The lower surface B of the three-dimensional carrier 101 is bonded to the substrate 140. For example, a conductive connector 130 can be formed on the conductive via 114i exposed on the lower surface B of the three-dimensional carrier 101, and then the three-dimensional carrier 101 can be bonded to the substrate 140 through the conductive connector 130. A conductive terminal 150 can be formed on the other surface of the substrate 140 opposite to the surface where the three-dimensional carrier 101 is located to provide external connectivity.

[0044] In some embodiments, a portion of the conductive pads (e.g., conductive pad 116i) located on the side (e.g., side S3) of the three-dimensional carrier 101 can be electrically connected to the corresponding pads (not shown) on the substrate 140 by wire bonding.

[0045] In some embodiments, substrate 140 may include a plurality of alternately stacked dielectric layers (not shown), conductive layers (not shown), and vias (not shown). In some embodiments, substrate 140 may be a printed circuit board or other suitable circuit substrate.

[0046] In some embodiments, the conductive connector 130 and the conductive terminal 150 may respectively include, for example, solder balls, conductive bumps, conductive posts or other suitable conductive connectors, and this application is not limited thereto.

[0047] After the above process, the packaging structure 10 can be roughly completed.

[0048] Please refer to Figure 4 The encapsulation structure 10 includes a three-dimensional carrier 101 and a die 120. The three-dimensional carrier 101 includes multiple conductive line layers 112 and multiple conductive pads 116. The multiple conductive line layers 112 are disposed in the three-dimensional carrier 101, and the multiple conductive pads 116 are disposed on the upper surface T and multiple side surfaces S1-S4 of the three-dimensional carrier 101, wherein the multiple side surfaces S1-S4 connect between the upper surface T and the lower surface B. The die 120 is disposed on the upper surface T and / or at least one of the multiple side surfaces S1-S4 of the three-dimensional carrier 101. In some embodiments, the encapsulation structure 10 further includes a substrate 140, with the lower surface B of the three-dimensional carrier 101 facing the substrate 140 and electrically connected to the substrate 140. Since the three-dimensional carrier 101 can provide up to five surfaces for bonding with the die 120, the bonding area of ​​the three-dimensional carrier 101 is increased, which can disperse the heat generated by the die, thereby improving heat dissipation efficiency.

[0049] In some embodiments, the three-dimensional carrier 101 is formed by stacking a plurality of glass substrates 100 (including glass substrates 100a-100h), and a plurality of conductive line layers 112 are embedded in the upper surface of each of the plurality of glass substrates 100, such that adjacent conductive line layers 112 are separated by the glass substrates 100 in the vertical direction N. In this document, the upper surface of the glass substrate 100 refers to the surface facing away from the substrate 140, and the lower surface of the glass substrate 100 refers to the surface facing the substrate 140. Since the three-dimensional carrier 101 is composed of a plurality of glass substrates 100, its coefficient of thermal expansion can be matched with the grain size, thus reducing the occurrence of warpage.

[0050] In some embodiments, the conductive line layer 112 is not disposed in the lower surface of the glass substrate 100, but this application is not limited thereto. In other embodiments, the conductive line layer 112 may also be disposed in the lower surface of the glass substrate 100, so that both the upper and lower surfaces of the glass substrate can have horizontal line layouts.

[0051] In some embodiments, some conductive pads 116 are embedded in the side surface of the glass carrier 100 so that the side surfaces S1-S4 of the three-dimensional carrier 101 can bond with the grains. In some embodiments, the surface of some conductive pads 116 may be flush with the side surface of the three-dimensional carrier 101. For example, the exposed surfaces of some conductive pads 116b-116d and conductive pads 116f-116h are flush with the side surface S1 of the three-dimensional carrier 101; the exposed surfaces of some conductive pads 116d-116f are flush with the side surface S3 of the three-dimensional carrier 101.

[0052] In some embodiments, the three-dimensional carrier 101 further includes a plurality of conductive vias 114 connected between adjacent conductive line layers 112. The conductive vias 114, for example, penetrate the glass substrate 100 to expose the corresponding conductive vias 114 on the lower surface of the glass substrate 100, thereby electrically connecting adjacent conductive line layers 112 in the vertical direction N.

[0053] In some embodiments, the conductive circuit layer 112, the conductive via 114, and the conductive pad 116 may be made of metallic materials, such as copper, aluminum, tungsten, their alloys, or other suitable metallic materials, and this application is not limited thereto.

[0054] In some embodiments, the three-dimensional carrier 101 further includes a welding material disposed on the exposed conductive vias 114 on the lower surface of the glass carrier 100 to bond with the conductive line layer 112 of the adjacent glass carrier 100.

[0055] In some embodiments, the die 120 may correspond to and contact with a plurality of conductive pads 116 on the sidewalls S1-S4 of the three-dimensional carrier 101 via a plurality of conductive connectors 122, so as to be electrically connected to the substrate 140.

[0056] In summary, the packaging structure of this application includes a three-dimensional carrier, and each surface of the three-dimensional carrier can have conductive pads for external connection, so that the die can be disposed on multiple surfaces (e.g., the upper surface and the side surface) of the three-dimensional carrier, thereby dispersing the heat generated by the die, improving the heat dissipation efficiency of the packaging structure and thus enhancing its performance.

[0057] The embodiments and / or implementation methods described above are merely preferred embodiments and / or implementation methods for implementing the technology of this application, and are not intended to limit the implementation methods of the technology of this application in any way. Any person skilled in the art may make some modifications or alterations to other equivalent embodiments without departing from the scope of the technical means disclosed in this application, but these should still be regarded as the technology or embodiments that are substantially the same as those of this application.

Claims

1. A package structure, characterized by, The package structure comprises: a three-dimensional carrier comprising: a plurality of conductive routing layers disposed in the three-dimensional carrier; and a plurality of conductive pads disposed on an upper surface and a plurality of side surfaces of the three-dimensional carrier, wherein the plurality of side surfaces are connected between the upper surface and a lower surface of the three-dimensional carrier; a die disposed on at least one of the upper surface and / or the plurality of side surfaces of the three-dimensional carrier.

2. The package structure of claim 1, wherein, The three-dimensional carrier is stacked by a plurality of glass carrier plates, wherein the plurality of conductive routing layers are disposed in upper surfaces of the plurality of glass carrier plates.

3. The package structure of claim 1, wherein, Some of the plurality of conductive pads are disposed on side surfaces of the plurality of glass carrier plates.

4. The package structure of claim 2, wherein, The three-dimensional carrier further comprises a plurality of conductive vias connected between adjacent ones of the plurality of conductive routing layers.

5. The package structure of claim 4, wherein, The plurality of conductive vias penetrate through corresponding ones of the plurality of glass carrier plates to expose lower surfaces of the plurality of glass carrier plates to the plurality of conductive vias.

6. The package structure of claim 5, wherein, The three-dimensional carrier further comprises a solder material disposed on the plurality of conductive vias exposed by the lower surfaces of the plurality of glass carrier plates to engage with the conductive routing layers of adjacent ones of the plurality of glass carrier plates.

7. The package structure of claim 2, wherein, The plurality of glass carrier plates comprise a first glass carrier plate and a second glass carrier plate disposed below the first glass carrier plate, wherein a lower surface of the first glass carrier plate faces an upper surface of the second glass carrier plate.

8. The package structure of claim 1, wherein, A substrate is further included, wherein the lower surface of the three-dimensional carrier faces and is electrically connected to the substrate.

9. The package structure of claim 8, wherein, The die is electrically connected to the substrate by a plurality of conductive connections corresponding to and contacting the plurality of conductive pads on the plurality of side surfaces of the three-dimensional carrier.

10. A method of manufacturing a package structure, characterized by, The manufacturing method comprises: providing a plurality of glass carrier plates, wherein each of the plurality of glass carrier plates comprises a conductive portion; engaging the plurality of glass carrier plates on top of one another to form a three-dimensional carrier; engaging a lower surface of the three-dimensional carrier to a substrate; and engaging a die to an upper surface and / or a side surface of the three-dimensional carrier, wherein the lower surface of the three-dimensional carrier is opposite to the upper surface, and the side surface of the three-dimensional carrier is connected between the upper surface and the lower surface of the three-dimensional carrier.

11. The method of manufacturing a package structure according to claim 10, wherein The manufacturing method of each of the plurality of glass carrier plates comprises: providing a blank glass substrate; forming a recess and / or a through hole penetrating through the blank glass substrate in an upper surface and / or a side surface of the blank glass substrate by laser engraving, the recess and / or the through hole corresponding to a pre-determined routing layout pattern; and forming a conductive material in the recess and / or the through hole to form the conductive portion.

12. The method of manufacturing a package structure according to claim 11, wherein The forming of the conductive material in the recess and / or the through hole comprises: depositing a layer of the conductive material on the blank glass substrate and in the recess and / or the through hole; and removing excess of the layer of the conductive material on the blank glass substrate by a planarization process.

13. The method of manufacturing a package structure according to claim 10, wherein The conductive portion comprises: a conductive routing layer in an upper surface of the glass carrier plate; and / or a conductive pad in a side surface of the glass carrier plate; and / or a conductive via penetrating through the glass carrier plate to be exposed to a lower surface of the glass carrier plate.

14. The method of manufacturing a package structure according to claim 13, wherein The plurality of glass carriers includes a first glass carrier and a second glass carrier, and the manufacturing method further includes: forming solder balls on the conductive vias exposed on the lower surface of the first glass carrier before the plurality of glass carriers are joined together; joining the solder balls on the lower surface of the first glass carrier to a conductive routing layer on an upper surface of the second glass carrier.

15. The method of manufacturing a package structure according to claim 10, wherein The method of joining the plurality of glass carriers together includes a laser welding process.

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