Semiconductor package assembly and method of forming same

Abstract

The invention provides a semiconductor package assembly and a method of forming the same. The assembly includes: a first semiconductor package including a first substrate and a first electronic component mounted on a front surface of the first substrate; a cooling device including a cooling duct mounted on the first semiconductor package such that a lower surface of the cooling duct is thermally coupled to the first electronic component; a second semiconductor package including a second substrate and a second electronic component mounted on a front surface of the second substrate, the second semiconductor package mounted on the cooling duct such that the second electronic component is thermally coupled to an upper surface of the cooling duct; and a sealant formed between the front surface of the first substrate and the front surface of the second substrate to seal the first electronic component, the second electronic component, and a portion of the cooling duct.

Description

Technical Field

[0001] This application generally relates to semiconductor technology, and more specifically, to semiconductor package assemblies and methods of forming thereof. Background Technology

[0002] The semiconductor industry has faced complex integration challenges as consumers demand smaller, faster, and higher-performing electronic devices and increasingly package more functionality into single devices. Today, package-in-package (PiP) or package-on-package (PoP) technologies have been introduced. In a typical PiP or PoP device, one or more pre-molded semiconductor packages can be mounted onto another semiconductor package. However, when the device is in operation, the multiple electronic modules contained within it can generate heat, especially high-performance logic and memory chips such as central processing units (CPUs), graphics processing units (GPUs), and high-bandwidth memory (HBM). In these situations, the generated heat must be dissipated promptly to ensure the proper functionality of the electronic modules. Typically, heat sinks are attached to these electronic modules to facilitate heat dissipation. However, the efficiency of existing heat dissipation methods may still be limited, especially for devices that include high-performance chips with stacked structures.

[0003] Therefore, a semiconductor package assembly with improved heat dissipation capabilities is needed. Summary of the Invention

[0004] The objective of this application is to provide a semiconductor package assembly with improved heat dissipation capabilities.

[0005] According to one aspect of this application, a semiconductor package assembly is provided. The semiconductor package assembly may include: a first semiconductor package including a first substrate and at least one first electronic component mounted on a front surface of the first substrate; a cooling device including a cooling conduit, wherein the cooling conduit is mounted on the first semiconductor package such that a lower surface of the cooling conduit is thermally coupled to the first electronic component; a second semiconductor package including a second substrate and at least one second electronic component mounted on a front surface of the second substrate, wherein the second semiconductor package is mounted on the cooling conduit such that the second electronic component is thermally coupled to an upper surface of the cooling conduit; and a sealant formed between the front surfaces of the first substrate and the second substrate to seal at least a portion of the first electronic component, the second electronic component, and the cooling conduit.

[0006] According to another aspect of this application, a method for forming a semiconductor package assembly is provided. The method may include: providing a first semiconductor package, wherein the first semiconductor package includes a first substrate and at least one first electronic component mounted on a front surface of the first substrate; mounting a cooling conduit of a cooling device on the first semiconductor package, the lower surface of the cooling conduit being thermally coupled to the first electronic component; mounting a second semiconductor package on the cooling conduit, wherein the second semiconductor package includes a second substrate and at least one second electronic component mounted on a front surface of the second substrate, and the second electronic component being thermally coupled to an upper surface of the cooling conduit; and forming a sealant between the front surface of the first substrate and the front surface of the second substrate to seal at least a portion of the first electronic component, the second electronic component, and the cooling conduit.

[0007] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory and do not limit the invention. Furthermore, the accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. Attached Figure Description

[0008] The accompanying drawings referenced herein form part of this specification. The features shown in the drawings are merely illustrative of some embodiments of this application, and not all embodiments of this application, unless the detailed description clearly indicates otherwise, and the reader of this specification should not infer the contrary.

[0009] Figure 1A This is a cross-sectional view showing a semiconductor package assembly according to an embodiment of this application.

[0010] Figure 1B It is shown Figure 1A The top view of the first base shown in the figure.

[0011] Figure 1C It is shown Figure 1A The bottom view of the second base shown in the figure.

[0012] Figure 1D It is shown Figure 1A The image shows a top view of the cooling pipes.

[0013] Figure 1E It is shown Figure 1A A perspective view of the cooling pipes shown in the image.

[0014] Figure 2 This is a cross-sectional view of a semiconductor package assembly according to another embodiment of this application.

[0015] Figure 3 This is a cross-sectional view of a semiconductor package assembly according to another embodiment of this application.

[0016] Figure 4A to 4G This is a cross-sectional view illustrating the various steps of a method for forming a semiconductor package assembly according to an embodiment of this application.

[0017] Use the same reference numerals to refer to the same or similar parts in a continuous diagram. Detailed Implementation

[0018] The following detailed description of exemplary embodiments of this application takes into account the accompanying drawings, which form a part of the description. The drawings illustrate specific exemplary embodiments in which this application may be practiced. The detailed description, including the drawings, describes these embodiments in sufficient detail to enable those skilled in the art to practice this application. Those skilled in the art can further utilize other embodiments of this application and make logical, mechanical, and other changes without departing from the spirit or scope of this application. Therefore, the reader of the following detailed description should not interpret it in a limiting sense, and only the appended claims define the scope of the embodiments of this application.

[0019] In this application, unless otherwise specified, the use of the singular includes the plural. In this application, unless otherwise specified, the use of “or” means “and / or”. Furthermore, the use of the term “comprising” and other forms such as “including” and “containing” is not restrictive. Additionally, unless otherwise specified, terms such as “element” or “component” cover elements and components comprising one unit, as well as elements and components comprising more than one sub-unit. Furthermore, the section headings used herein are for organizational purposes only and should not be construed as limiting the subject matter described.

[0020] In this document, spatially relative terms such as “below,” “under,” “above,” “on top,” “upper,” “upper part,” “lower part,” “left side,” “right side,” “vertical,” “horizontal,” and “side” may be used for ease of description to describe the relationship between one element or feature as shown in the accompanying drawings and one or more other elements or features. Apart from the orientations depicted in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or there may be an intermediate element present.

[0021] To address the heat dissipation problem mentioned above, a novel semiconductor package assembly with a cooling system is provided. In this assembly, two semiconductor packages are attached face-to-face to opposite sides of a cooling channel. Because the cooling channel is sandwiched between the two semiconductor packages, the electronic components (especially high-performance logic chips that generate significant heat) of the two packages can directly contact the cooling channel, thus effectively dissipating the heat generated within the semiconductor package assembly.

[0022] Figure 1A This is a cross-sectional view showing a semiconductor package assembly 100 according to an embodiment of the present application. The semiconductor package assembly 100 may include a first semiconductor package, a second semiconductor package, and a cooling conduit 130 sandwiched between the first semiconductor package and the second semiconductor package.

[0023] like Figure 1A As shown, a first semiconductor package includes a first substrate 110 and a plurality of first electronic components 120 mounted on the first substrate 110. The first substrate 110 has a front surface 110a and a back surface 110b opposite to each other, and the first electronic components 120 are mounted on the front surface 110a of the first substrate 110. The first substrate 110 may provide support and connectivity for electronic components and devices mounted thereon. For example, the first substrate 110 may include a printed circuit board (PCB), a carrier substrate, a semiconductor substrate with electrical interconnects, a ceramic substrate, a laminated interposer, a strip interposer, a lead frame, or other suitable substrate. The first substrate 110 may include a structure capable of fabricating an integrated circuit system thereon or any of the structures thereon. In some examples, the first substrate 110 may include a redistribution structure having one or more dielectric layers and one or more conductive layers between and through the dielectric layers. The conductive layers may define pads, traces, and plugs through which electrical signals or voltages may be distributed horizontally and vertically across the redistribution structure.

[0024] The first electronic component 120 may include any of a variety of types of semiconductor dies, semiconductor packages, or discrete devices. For example, the first electronic component 120 may include logic chips such as central processing units (CPUs) or graphics processing units (GPUs), memory devices such as high-bandwidth memory (HBM), digital signal processors (DSPs), radio frequency (RF) circuits, wireless baseband system-on-chip (SoC) processors, sensors, application-specific integrated circuits (ASICs), etc. The first electronic component 120 may be a passive component, such as a resistor, capacitor, inductor, switch, or any other suitable electronic device. The first electronic component 120 may be mounted on the front surface 110a of the first substrate 110 via solder bumps or a similar structure.

[0025] refer to Figure 1B The embodiment provides a top view of a first substrate 110. A plurality of electronic components 120a, 120b, 120c, 120d, and 120e are mounted on the front surface 110a of the first substrate 110. Electronic component 120a may be a high-performance logic chip such as a CPU or GPU, which may have high power consumption and generate a large amount of heat during operation, and electronic components 120b, 120c, 120d, and 120e may be HBMs. In one example, electronic components 120a, 120b, 120c, 120d, and 120e may have the same height, such that they are all comparable to... Figure 1A The lower surface 130a of the cooling conduit 130 shown in the figure is in thermal contact.

[0026] refer to Figure 1A The second semiconductor package includes a second substrate 150 and a plurality of second electronic components 160 mounted on the second substrate 150. The second substrate 150 has a front surface 150a and a back surface 150b opposite to the front surface 150a, and the second electronic components 160 are mounted on the front surface 150a of the second substrate 150. The second electronic components 160 may include any of a variety of semiconductor dies, semiconductor packages, or discrete devices, and may be mounted on the front surface 150a of the second substrate 150 via solder bumps or similar structures. The second substrate 150 may be similar to the first substrate 110, and will not be described in detail herein. In one example, the difference between the second substrate 150 and the first substrate 110 is that the second substrate 150 includes a first via 152a and a second via 152b. The first via 152a and the second via 152b may be formed in a peripheral region of the second substrate 150 and extend through the second substrate 150. The first through-hole 152a and the second through-hole 152b provide pathways for the cooling conduit 130 to enter or exit the semiconductor package assembly 100, which will be discussed in detail below.

[0027] refer to Figure 1CThe embodiment provides a bottom view of a second substrate 150 according to an exemplary embodiment. A plurality of electronic components 160a, 160b, 160c, 160d, and 160e are mounted on the front surface 150a of the second substrate 150. Electronic component 160a may be a high-performance logic chip such as a CPU or GPU, and electronic components 160b, 160c, 160d, and 160e may be HBMs. Electronic components 160a, 160b, 160c, 160d, and 160e may have the same height, such that they are all comparable to... Figure 1A The upper surface 130b of the cooling pipe 130 shown in the figure is in thermal contact.

[0028] Understandable. Figure 1B and 1C The types and layouts of electronic components shown are merely exemplary and can be varied according to actual needs.

[0029] In some embodiments, such as Figure 1A As shown, a first thermal interface material (TIM) layer 182 is formed between the first electronic component 120 and the lower surface 130a of the cooling conduit 130, and a second TIM layer 184 is formed between the second electronic component 160 and the upper surface 130b of the cooling conduit 130. That is, the first electronic component 120 and the second electronic component 160 are thermally coupled to the cooling conduit 130 via the first TIM layer 182 and the second TIM layer 184, respectively. The first TIM layer 182 and / or the second TIM layer 184 may include solder, indium, silver, indium / silver alloy, or other suitable materials with high thermal conductivity. However, this application is not limited to the above embodiments. In some other embodiments, the first electronic component 120 and the second electronic component 160 are directly coupled to the cooling conduit 130, i.e., the first TIM layer 182 and the second TIM layer 184 may be omitted.

[0030] The cooling conduit 130 is hollow and thus forms a coolant fluid path between the first electronic component 120 and the second electronic component 160, through which the coolant fluid flows to the external environment. Because the cooling conduit 130 is in thermal contact with the first electronic component 120 and the second electronic component 160, the heat generated by the first electronic component 120 and the second electronic component 160 can be dissipated to the external environment through the flowing coolant fluid. In some embodiments, the cooling conduit 130 may be made of a material including or composed of copper, and the coolant fluid may include water. However, this application is not limited thereto. In some other embodiments, the cooling conduit 130 may include stainless steel, an alloy, or other similar materials having high thermal conductivity and sufficient strength, and the coolant fluid may include a liquid flow, a gas flow such as an air flow, or a mixture of gas and liquid such as a liquid nitrogen flow. The cooling conduit 130 prevents coolant fluid leakage and improves the electrical reliability and safety of the semiconductor package assembly 100.

[0031] refer to Figure 1D and 1E ,exist Figure 1D The document provides a top view showing the cooling pipe 130, and in Figure 1E A perspective view showing the cooling pipe 130 is provided. Figure 1D and 1E As shown, the cooling pipe 130 includes a horizontal portion 130-1, a first vertical portion 130-2, and a second vertical portion 130-3.

[0032] The horizontal portion 130-1 may have a rectangular layout corresponding to the layout of the first electronic component 120 and the second electronic component 160. Therefore, the first electronic component 120 and the second electronic component 160 may be thermally coupled to the lower and upper surfaces of the horizontal portion 130-1 of the cooling conduit, respectively. The first vertical portion 130-2 and the second vertical portion 130-3 are in fluid communication with the horizontal portion 130-1 and extend upwards. The first vertical portion 130-2 and the second vertical portion 130-3 may be similar in cross-sectional shape to and aligned with the first through-hole 152a and the second through-hole 152b formed in the second substrate 150, such that the first vertical portion 130-2 and the second vertical portion 130-3 may extend through the first through-hole 152a and the second through-hole 152b, respectively. The first vertical portion 130-2 can serve as the outlet of the cooling pipe 130 to discharge coolant fluid from the horizontal portion 130-1 to dissipate heat to the outside, for example, to a coolant pool or tank; and the second vertical portion 130-3 can serve as the inlet of the cooling pipe 130 to receive the cooled coolant fluid.

[0033] However, cooling pipe 130 is not limited to Figure 1D and 1EThe structure and configuration are shown in the figure. In some other embodiments, the horizontal portion 130-1 may include multiple branches extending between the first vertical portion 130-2 and the second vertical portion 130-3, or have a zigzag shape that meanders between the first vertical portion 130-2 and the second vertical portion 130-3. Additionally, the outlet portion 130-2 and the inlet portion 130-3 may extend downward and through two through-holes formed in the first substrate 110, or extend horizontally through two opposing side surfaces of the semiconductor package assembly 100. It is understood that the cooling conduit 130 may take other suitable shapes to increase its contact area with the first electronic component 120 and the second electronic component 160.

[0034] Continue to refer to Figure 1A The cooling conduit 130 is part of a cooling device that further includes a pump 136 and a radiator 138. Figure 1A As shown, pipe 134a is used to cool the outlet of pipe 130 (i.e., Figure 1D and 1E The first vertical portion 130-2 shown in the diagram is coupled to the pump 136, and another conduit 134b is used to connect the inlet of the cooling conduit 130 (i.e., Figure 1D and 1E The second vertical portion 130-3 shown is coupled to the pump 136. Depending on the configuration of the pump 136, conduit 134b carries coolant fluid into the cooling conduit 130, and conduit 134a carries coolant fluid out of the cooling conduit 130, thus circulating the coolant fluid within conduits 134a and 134b and within the cooling conduit 130. Conduits 134a and 134b may include polyvinyl chloride (PVC), polyurethane (PU), polyethylene terephthalate (PETG), metals such as copper or aluminum, etc. Furthermore, two valves 132 may be provided at the inlet and outlet of the cooling conduit 130 to regulate the flow rate of the coolant fluid within the cooling conduit 130. For example, when the semiconductor package assembly 100 operates at high power, i.e., when more heat may be generated during operation, valve 132 may be adjusted to accelerate the flow rate of the coolant fluid. Figure 1A As shown, a radiant radiator 138 is coupled to a pump 136 to cool the coolant fluid as it enters the pump 136. The radiant radiator 138 can be a passive or active radiant radiator, capable of cooling the coolant fluid to a lower temperature. Therefore, the coolant fluid in the cooling conduit 130 can be effectively circulated (by the pump 136 and the radiant radiator 138) through the pump 136. Figure 1A (The arrow in the image indicates) and cooling.

[0035] In some embodiments, reference Figure 1AMultiple first contact pads are formed on the peripheral area of ​​the front surface 110a of the first substrate 110 where the first electronic component 120 is not mounted. Correspondingly, multiple second contact pads are formed on the peripheral area of ​​the front surface 150a of the second substrate 150 where the second electronic component 160 is not mounted. For example, the first and second contact pads are formed by redistribution structures formed in the first substrate 110 and the second substrate 150, respectively. Furthermore, multiple interconnect structures 170 are electrically connected between the first and second contact pads to form an electrical connection therebetween, and further form an electrical connection between the first substrate 110 and the second substrate 150. For example, solder bumps may be formed on the first and second contact pads to attach the interconnect structures 170 therebetween. In this way, the first semiconductor package and the second semiconductor package can be interconnected to form an integrated circuit system.

[0036] exist Figure 1A In this embodiment, the interconnect structure 170 is an e-bar module. The e-bar modules are pre-formed, and each e-bar module includes at least one conductive post (e.g., a copper post) surrounded by a dielectric layer such as an insulating polymer material or composite. However, this application is not limited to... Figure 1A As shown in the example, and in some other embodiments, the interconnect structure 170 may include metal pillars, bonding wires, or similar conductive elements.

[0037] In some embodiments, reference Figure 1A A sealant 140 is formed between the front surface 110a of the first substrate 110 and the front surface 150a of the second substrate 150. The sealant 140 seals at least a portion of the first electronic component 120, the second electronic component 160, the interconnect structure 170, and the cooling conduit 130 to protect them from external environmental factors and damage. In one example, the sealant 140 at least seals the portion of the cooling conduit 130 exposed from the front surface 150a of the second substrate 150. In another example, the sealant 140 further fills gaps in through-holes in the second substrate 150 to secure the cooling conduit 130. The sealant 140 may comprise a polymer composite material, such as epoxy resin, epoxy resin with filler, epoxy acrylate with filler, or a polymer with suitable filler, but the scope of this application is not limited thereto.

[0038] In some embodiments, reference Figure 1A Multiple conductive bumps 190 are formed on the back surface 110b of the first substrate 110. Figure 1AIn the example shown, the conductive bump 190 is depicted as a solder bump, but this application is not limited thereto. In some other embodiments, the conductive bump 190 may include conductive pillars, copper balls, etc. When the semiconductor package assembly 100 is mounted on an external device or substrate such as a printed circuit board (PCB), the conductive bump 190 may be used to electrically connect the semiconductor package assembly 100 to the external device or substrate.

[0039] Figure 2 This is a cross-sectional view of a semiconductor package assembly 200 according to another embodiment of this application. The semiconductor package assembly 200 may have some features similar to... Figure 1A The semiconductor package assembly 100 shown has a similar structure and configuration. Similar or identical portions of the semiconductor package assembly 200 to the semiconductor package assembly 100 will not be repeated here.

[0040] Specifically, such as Figure 2 As shown, the semiconductor package assembly 200 includes a first semiconductor package, a second semiconductor package, and a cooling conduit 230 sandwiched between the first semiconductor package and the second semiconductor package. The first semiconductor package includes a first substrate 210 and at least one first electronic component 220 mounted on the front surface 210a of the first substrate 210. The second semiconductor package includes a second substrate 250 and at least one second electronic component 260 mounted on the front surface 250a of the second substrate 250.

[0041] Unlike Figure 1A The semiconductor package assembly 100 shown in the figure, Figure 2 The semiconductor package assembly 200 further includes a first heat sink 225 and a second heat sink 265. The first heat sink 225 is disposed between the lower surface of the first electronic component 220 and the cooling conduit 230, and the second heat sink 265 is disposed between the upper surface of the second electronic component 260 and the cooling conduit 230. The heat sinks 225 and 265 may include metal caps made of copper, aluminum, nickel-plated copper, nickel-plated aluminum, or other materials with high thermal conductivity. To further improve thermal conductivity, a first TIM layer 282 is formed between the first electronic component 220 and the first heat sink 225, and a second TIM layer 284 is formed between the second electronic component 260 and the second heat sink 265. In addition, a sealant 240 is formed between the front surface 210a of the first substrate 210 and the front surface 250a of the second substrate 250 to seal at least a portion of the first electronic component 220, the second electronic component 260, and the cooling conduit 230.

[0042] The heat sinks 225 and 265, which are thermally coupled to electronic components 220 and 260, can be further improved. Figure 2 The heat dissipation capability of the semiconductor package assembly 200.

[0043] Figure 3 This is a cross-sectional view of a semiconductor package assembly 300 according to another embodiment of this application. The semiconductor package assembly 300 may have some features similar to... Figure 1A The semiconductor package assembly 100 shown has a similar structure and configuration. Similar or identical parts between the semiconductor package assembly 300 and the semiconductor package assembly 100 will not be repeated here.

[0044] Specifically, such as Figure 3 As shown, the semiconductor package assembly 300 includes a first semiconductor package, a second semiconductor package, and a cooling conduit 330 sandwiched between the first semiconductor package and the second semiconductor package. The first semiconductor package includes a first substrate 310 and at least one first electronic component 320 mounted on a front surface 310a of the first substrate 310. The second semiconductor package includes a second substrate 350 and at least one second electronic component 360 mounted on a front surface 350a of the second substrate 350. Furthermore, a sealant 340 is formed between the front surfaces 310a and 350a of the first and second substrates 350 to seal at least a portion of the first electronic component 320, the second electronic component 360, and the cooling conduit 330.

[0045] Unlike Figure 1A The semiconductor package assembly 100 shown in the figure has a plurality of third electronic components 392 mounted on the back surface 350b of a second substrate 350. The third electronic components 392 can include any of a variety of types of semiconductor dies, semiconductor packages, or discrete devices. For example, the third electronic components 392 can be mounted on the back surface 350b of the second substrate 350 via solder bumps or similar structures. Furthermore, an underfill sealant 394 can be formed between the third electronic components 392 and the back surface 350b of the second substrate 350. The underfill sealant 394 can fill any gap between the third electronic components 392 and the second substrate 350, and optionally cover the side surfaces of the third electronic components 392. The underfill sealant 394 can include polymer composite materials, such as epoxy resin, epoxy acrylate, or polymers with or without fillers. The underfill sealant 394 can provide mechanical support for the interconnection between the third electronic components 392 and the second substrate 350. Additionally, a heat sink 396 is thermally coupled to the third electronic components 392. Figure 3 As shown, a heat sink 396 is attached to the top surface of the third electronic component 392. The heat sink 396 at least partially surrounds the third electronic component 392 mounted on the back surface 350b of the second substrate 350 in order to dissipate heat from the third electronic component 392.

[0046] Figure 3The semiconductor package assembly 300 shown is a 3-layer package that increases the package density and incorporates cooling channels 330 and heat sinks 396 to improve its heat dissipation capabilities.

[0047] refer to Figure 4A to 4G This illustrates the various steps of a method for forming a semiconductor package assembly according to embodiments of this application. For example, the method can be used to form... Figure 1A The semiconductor package assembly 100 shown is illustrated below. Reference will be made to it in the following text. Figures 4A to 4G The method will be described in more detail below.

[0048] refer to Figure 4A A first semiconductor package 401 is provided. The first semiconductor package 401 includes a first substrate 410 and a plurality of first electronic components 420 mounted on the first substrate 410. The first substrate 410 has a front surface 410a and a back surface 410b opposite to each other, and the first electronic components 420 are mounted on the front surface 410a of the first substrate 410. The first substrate 410 may include a redistribution structure having one or more dielectric layers and one or more conductive layers between and through the dielectric layers. The conductive layers may define pads, traces, and plugs through which electrical signals or voltages may be distributed horizontally and vertically across the redistribution structure. The first electronic components 420 may include any of a variety of types of semiconductor dies, semiconductor packages, or discrete devices. For example, the first electronic components 420 may include logic chips such as CPUs or GPUs, memory devices such as HBMs, etc. The first electronic components 420 may be mounted on the front surface 410a of the first substrate 410 via solder bumps or similar structures.

[0049] refer to Figure 4B A first TIM layer 482 is formed on the first electronic component 420, and then the lower surface of the cooling conduit 430 is attached to and thermally coupled to the first electronic component 420 via the first TIM layer 482. In some embodiments, the first TIM layer 482 may include solder, indium, silver, indium / silver alloy, or other suitable materials. In some embodiments, the first TIM layer 482 may be formed by spraying, electroplating, sputtering, or any other suitable metal deposition process. Figure 4B In the example shown, the cooling conduit 430 includes a horizontal portion, a first vertical portion, and a second vertical portion. The lower surface of the horizontal portion of the cooling conduit 430 is attached to the first electronic component 420 via a first TIM layer 482. The first and second vertical portions are in fluid communication with the horizontal portion and extend upward.

[0050] refer to Figure 4CA second TIM layer 484 is formed on the upper surface of the cooling conduit 430, specifically on the upper surface of the horizontal portion of the cooling conduit 430. The second TIM layer 484 can be formed similarly to the first TIM layer 482 and using a similar process. In some embodiments, a plurality of first contact pads are formed on the peripheral region of the front surface 410a of the first substrate 410 where the first electronic component 420 is not mounted. For example, the first contact pads can be formed using a redistribution structure formed in the first substrate 410. Subsequently, a plurality of interconnect bumps 472, such as solder material, are formed on the first contact pads.

[0051] Next, refer to Figure 4D A second semiconductor package 405 is provided. The second semiconductor package 405 includes a second substrate 450 and a plurality of second electronic components 460 mounted on the second substrate 450. The second substrate 450 has a front surface 450a and a back surface 450b opposite to each other, and the second electronic components 460 are mounted on the front surface 450a of the second substrate 450. For example, the second electronic components 460 may be mounted on the front surface 450a of the second substrate 450 via solder bumps or similar structures. In some embodiments, a plurality of second contact pads are formed on the peripheral area of ​​the front surface 450a of the second substrate 450 where the second electronic components 460 are not mounted. Subsequently, a plurality of interconnect structures 470 are attached to the second contact pads via interconnect bumps 474 such as solder material. The interconnect structures 470 may be electrically functional pillar modules, metal pillars, or similar conductive elements. In addition, a first via 452a and a second via 452b may be formed in the second substrate 450. The first through-hole 452a and the second through-hole 452b can be formed using laser drilling, mechanical drilling, or other suitable processes. The first through-hole 452a and the second through-hole 452b provide paths for the cooling conduit 430 to enter or exit the semiconductor package assembly to be formed.

[0052] Next, refer to Figure 4E and Figure 4F The second semiconductor package 405 is mounted on the first semiconductor package 401 via a cooling conduit 430. Specifically, the second electronic component 460 is thermally coupled to the upper surface of the cooling conduit 430 via a second TIM layer 484, and the interconnect structure 470 is mounted on the front surface 410a of the first substrate 410 via interconnect bumps 472. Therefore, the electrical connection between the first substrate 410 and the second substrate 450 can be formed by the interconnect structure 470.

[0053] As described above, in some embodiments, the cooling conduit 430 may include an upwardly extending first vertical portion and a second vertical portion. Therefore, when the second semiconductor package 405 is mounted on the first semiconductor package 401, the first vertical portion and the second vertical portion of the cooling conduit 430 are aligned with the first through-hole 452a and the second through-hole 452b of the second substrate 450, respectively, and then the second semiconductor package 405 is moved downward to allow the first vertical portion and the second vertical portion of the cooling conduit 430 to pass through the first through-hole and the second through-hole of the second substrate 450, respectively.

[0054] Continue to refer to Figure 4F A sealant 440 is formed between the front surface 410a of the first substrate 410 and the front surface 450a of the second substrate 450 to seal at least a portion of the first electronic component 420, the second electronic component 460, the interconnect structure 470, and the cooling conduit 430. The sealant 440 may comprise a polymer composite material, such as epoxy resin, filled epoxy resin, filled epoxy acrylate, or a polymer with suitable fillers, but the scope of this application is not limited thereto. The sealant 440 can be formed using molding processes such as injection molding. However, this application is not limited thereto. In some other embodiments, the sealant 440 can be formed using various other molding techniques, including transfer molding, compression molding, film-assisted molding (FAM), etc.

[0055] Next, refer to Figure 4G Multiple conductive bumps 490 are formed on the back surface 410b of the first substrate 410. For example, solder material can be printed or deposited onto conductive pads exposed from the back surface 410b of the first substrate 410, and then the solder material can be reflowed by heating the material above its melting point to form the conductive bumps 490. In some other embodiments, the conductive bumps 490 can be compression-bonded or thermocompressively bonded to contact pads exposed from the back surface 410b of the first substrate 410. Figure 4G In the example shown, the conductive bump 490 is depicted as a solder bump, but this application is not limited thereto. In some other embodiments, the conductive bump 490 may include conductive pillars, copper balls, microbumps, etc.

[0056] In some embodiments, a pump may be coupled to cooling conduit 430 to circulate coolant fluid within cooling conduit 430, and a radiant radiator may be further coupled to the pump to cool the coolant fluid, which will not be described in detail here.

[0057] Although Figure 4A to 4G The steps shown only depict a single unit of the semiconductor package assembly, but can be used... Figure 4A to 4GThe process shown creates strip-type semiconductor package assemblies, that is, multiple semiconductor package assemblies formed in the form of package strips. Subsequently, a separate step can be performed to separate the package strips into individual semiconductor package assemblies.

[0058] Although combined with the corresponding Figure 4A to 4G The method for manufacturing a semiconductor package assembly described in this application is illustrated, but those skilled in the art will understand that modifications and adaptations can be made to the process without departing from the scope of the invention.

[0059] In one example, in such Figure 4B Before the cooling conduit 430 is mounted on the first semiconductor package, as shown, the first heat sink can be attached to the first electronic component 420 via the first TIM layer 482, and in accordance with... Figure 4C As shown, before forming the second TIM layer on the upper surface of the cooling pipe 430, and in the manner described... Figure 4E As shown, before mounting the second semiconductor package 405 on the cooling conduit 430, a second heat sink can be attached to the upper surface of the cooling conduit 130. Thus, the method described above can be used to form... Figure 2 The semiconductor package assembly 200 shown is illustrated.

[0060] In another example, as Figure 4G Before forming the plurality of conductive bumps 490 on the back surface 410b of the first substrate 410, at least one third electronic component can be mounted on the back surface 450b of the second substrate 450, and then a third heat sink can be attached to the third electronic component. Thus, the method described above can be used to form... Figure 3 The semiconductor package assembly 300 shown.

[0061] The discussion herein includes numerous illustrative figures illustrating various portions of a semiconductor package assembly and methods for fabricating such assemblies. For clarity, such figures do not show all aspects of every exemplary semiconductor package assembly. Any example assembly and / or method provided herein may share any or all of its characteristics with any or all other assemblies and / or methods provided herein.

[0062] Various embodiments have been described herein with reference to the accompanying drawings. However, it will be apparent that various modifications and changes can be made thereto, and other embodiments can be practiced, without departing from the broad scope of the invention as set forth in the appended claims. Furthermore, other embodiments will be apparent to those skilled in the art upon consideration of the description and practice of one or more embodiments of the invention disclosed herein. Therefore, it is intended that this application and the examples herein be considered exemplary only, and the true scope and spirit of the invention are indicated by the list of exemplary claims appended.

Claims

1. A semiconductor package assembly, characterized in that, The semiconductor package assembly includes: A first semiconductor package, the first semiconductor package including a first substrate and at least one first electronic component mounted on the front surface of the first substrate; A cooling device, the cooling device including a cooling pipe, wherein the cooling pipe is mounted on the first semiconductor package such that the lower surface of the cooling pipe is thermally coupled to the first electronic component; A second semiconductor package, the second semiconductor package including a second substrate and at least one second electronic component mounted on a front surface of the second substrate, wherein the second semiconductor package is mounted on the cooling channel such that the second electronic component is thermally coupled to the upper surface of the cooling channel; and A sealant formed between the front surface of the first substrate and the front surface of the second substrate to seal at least a portion of the first electronic component, the second electronic component, and the cooling conduit.

2. The semiconductor packaging assembly according to claim 1, characterized in that, The cooling pipe includes a horizontal section, a first vertical section, and a second vertical section. The first electronic component and the second electronic component are thermally coupled to the lower and upper surfaces of the horizontal section of the cooling pipe, respectively. The first vertical section and the second vertical section are in fluid communication with the horizontal section and extend upward.

3. The semiconductor packaging assembly according to claim 2, characterized in that, The second substrate includes a first through hole and a second through hole, and the first vertical portion and the second vertical portion of the cooling pipe extend through the first through hole and the second through hole of the second substrate, respectively.

4. The semiconductor packaging assembly according to claim 2, characterized in that, The semiconductor package assembly further includes: A first thermal interface material (TIM) layer is formed between the lower surface of the first electronic component and the horizontal portion of the cooling pipe; and A second TIM layer is formed between the second electronic component and the upper surface of the horizontal portion of the cooling pipe.

5. The semiconductor packaging assembly according to claim 1, characterized in that, The cooling device further includes: A pump, which is in fluid communication with the cooling conduit to circulate coolant fluid within the cooling conduit; and A radiant heat sink, which is in fluid communication with the pump to cool the coolant fluid.

6. The semiconductor package assembly according to claim 5, characterized in that, The cooling pipes comprise copper, and the coolant fluid comprises water.

7. The semiconductor package assembly according to claim 1, characterized in that, The semiconductor package assembly further includes: At least one first contact pad is formed in a peripheral region of the front surface of the first substrate; At least one second contact pad, said at least one second contact pad being formed in a peripheral region of the front surface of the second substrate; and At least one interconnect structure is disposed between the first contact pad and the second contact pad to form an electrical connection therebetween.

8. The semiconductor package assembly according to claim 7, characterized in that, The interconnection structure includes electrical functional column modules or metal columns.

9. The semiconductor package assembly according to claim 1, characterized in that, The semiconductor package assembly further includes: Multiple conductive bumps are formed on the back surface of the first substrate.

10. The semiconductor package assembly according to claim 1, characterized in that, The semiconductor package assembly further includes: A first heat sink is disposed between the first electronic component and the lower surface of the cooling pipe; and The second heat sink is disposed between the second electronic component and the upper surface of the cooling pipe.

11. The semiconductor package assembly according to claim 1, characterized in that, The semiconductor package assembly further includes: At least one third electronic component, said at least one third electronic component being mounted on the back surface of the second substrate; and A third heat sink is attached to the third electronic component.

12. A method for forming a semiconductor package assembly, characterized in that, The method includes: A first semiconductor package is provided, wherein the first semiconductor package includes a first substrate and at least one first electronic component mounted on the front surface of the first substrate; A cooling conduit for a cooling device is mounted on the first semiconductor package, wherein the lower surface of the cooling conduit is thermally coupled to the first electronic component; A second semiconductor package is mounted on the cooling conduit, wherein the second semiconductor package includes a second substrate and at least one second electronic component mounted on the front surface of the second substrate, and the second electronic component is thermally coupled to the upper surface of the cooling conduit; and A sealant is formed between the front surface of the first substrate and the front surface of the second substrate to seal at least a portion of the first electronic component, the second electronic component, and the cooling conduit.

13. The method according to claim 12, characterized in that, The cooling pipe includes a horizontal section, a first vertical section, and a second vertical section, and the first vertical section and the second vertical section are in fluid communication with the horizontal section and extend upward. and The cooling conduit on which the cooling device is mounted on the first semiconductor package includes: attaching the lower surface of the horizontal portion of the cooling conduit to the first electronic component; and Installing the second semiconductor package on the cooling pipe includes attaching the second electronic component to the upper surface of the horizontal portion of the cooling pipe.

14. The method according to claim 12, characterized in that, The second substrate includes a first through hole and a second through hole, and The mounting of the second semiconductor package on the cooling pipe further includes: Align the first vertical portion and the second vertical portion of the cooling pipe with the first through hole and the second through hole of the second base, respectively; and The second semiconductor package is moved downward to allow the first vertical portion and the second vertical portion of the cooling conduit to pass through the first through-hole and the second through-hole of the second substrate, respectively.

15. The method according to claim 12, characterized in that, The method further includes: A first thermal interface material (TIM) layer is formed on the first electronic component before mounting the cooling conduit of the cooling device on the first semiconductor package; and A second TIM layer is formed on the upper surface of the cooling pipe before the second semiconductor package is mounted on the cooling pipe.

16. The method according to claim 12, characterized in that, The method further includes: Couple the pump to the cooling pipe to circulate coolant fluid within the cooling pipe; and The radiant radiator is coupled to the pump to cool the coolant fluid.

17. The method according to claim 12, characterized in that, The first semiconductor package further includes at least one first contact pad formed at a peripheral region of the front surface of the first substrate, and the second semiconductor package further includes at least one second contact pad formed at a peripheral region of the front surface of the second substrate; and The method further includes: At least one interconnect structure is attached between the first contact pad and the second contact pad to form an electrical connection therebetween.

18. The method according to claim 12, characterized in that, The method further includes: Multiple conductive bumps are formed on the back surface of the first substrate.

19. The method according to claim 12, characterized in that, The method further includes: A first heat sink is attached to the first electronic component before the cooling conduit of the cooling device is mounted on the first semiconductor package; and A second heat sink is attached to the upper surface of the cooling pipe before the second semiconductor package is mounted on the cooling pipe.

20. The method according to claim 12, characterized in that, The method further includes: At least one third electronic component is mounted on the back surface of the second substrate; and A third heat sink is attached to the third electronic component.

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