Shifting register unit and driving method thereof, gate driving circuit and display device

Abstract

The invention discloses a shift register unit and a driving method thereof, a gate driving circuit and a display device, and belongs to the technical field of display. In the shift register unit, an input control circuit (01) can control the on-off of an input signal end (INn) and an input node (Qn) under the control of a clock signal provided by a first clock end (CKn) and a clock signal provided by a second clock end (CB). And the output control circuit (02) can output a gate driving signal to the pixel through the output signal end (OUTn) based on the potential of the input node (Qn) and an enabling control signal provided by the enabling control end (GEN) so as to drive the pixel to emit light. By flexibly setting a clock signal and an enable control signal, a shift register unit outputs a gate driving signal matched with a P-type transistor and / or an N-type transistor in a pixel to an output signal end (OUTn), and selectively controls the shift register unit to output or not to output in different time periods, so that the pixel is locally refreshed, and the pixel refreshing efficiency is improved. And the gate driving signal is reliably reset, so that the driving flexibility is better, and the driving modes are abundant.

Description

Shift register unit and driving method thereof, gate driving circuit and display device

[0001] The present application claims priority to the Chinese patent application No. 202410544894.4, filed on April 30, 2024, and entitled "Shift register unit and driving method thereof, gate driving circuit and display device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a shift register unit and driving method thereof, a gate driving circuit and a display device. BACKGROUND

[0003] With the progress of display technology, a gate driving circuit is usually arranged on a display panel by using a gate driver on array (GOA) technology to facilitate a narrow frame design.

[0004] In the related art, a gate driving circuit usually includes a plurality of GOA units connected in cascade, and the plurality of GOA units are connected one-to-one with a plurality of rows of pixels on a display panel and are used to transmit a gate driving signal to the plurality of rows of pixels row by row to light up the pixels row by row, i.e., to realize row-by-row scanning and refreshing, so that the display panel can display a picture.

[0005] However, the current driving mode of the gate driving circuit is relatively single, such as being unable to locally refresh pixels. SUMMARY

[0006] A shift register unit and driving method thereof, a gate driving circuit and a display device are provided. The technical solutions are as follows:

[0007] In one aspect, a shift register unit is provided, which includes:

[0008] An input control circuit is connected with a first clock terminal, a second clock terminal, an input signal terminal and an input node respectively, and is used to control the on-off of the input signal terminal and the input node in response to a first clock signal provided by the first clock terminal and a second clock signal provided by the second clock terminal;

[0009] An output control circuit is connected with the input node, an enable control terminal and an output signal terminal respectively, and is used to control the potential of the output signal terminal based on the potential of the input node and an enable control signal provided by the enable control terminal, so as to output a gate driving signal to a connected pixel through the output signal terminal to drive the pixel to emit light.

[0010] Optionally, the output control circuit includes:

[0011] The first output control sub-circuit is connected with the input node and the first intermediate node respectively, and is configured to control the potential of the first intermediate node based on the potential of the input node.

[0012] The second output control sub-circuit is connected with the first intermediate node, the enable control terminal and the output signal terminal respectively, and is configured to control the potential of the output signal terminal based on the potential of the first intermediate node and the enable control signal.

[0013] Optionally, the second output control sub-circuit comprises:

[0014] The first output control unit is connected with the first intermediate node, the enable control terminal and the second intermediate node respectively, and is configured to control the potential of the second intermediate node based on the potential of the first intermediate node and the enable control signal.

[0015] The second output control unit is connected with the second intermediate node and the output signal terminal respectively, and is configured to control the potential of the output signal terminal based on the potential of the second intermediate node.

[0016] Optionally, the second output control sub-circuit comprises:

[0017] The first output control unit is connected with the first intermediate node and the second intermediate node respectively, and is configured to control the potential of the second intermediate node based on the potential of the first intermediate node.

[0018] The second output control unit is connected with the second intermediate node, the enable control terminal and the output signal terminal respectively, and is configured to control the potential of the output signal terminal based on the potential of the second intermediate node and the enable control signal.

[0019] Optionally, the first output control unit is further connected with a reset control terminal, and is further configured to control the potential of the second intermediate node based on a reset control signal provided by the reset control terminal.

[0020] Optionally, the first output control unit is further connected with a reset control terminal, and is further configured to control the potential of the second intermediate node based on a reset control signal provided by the reset control terminal.

[0021] Or, the second output control unit is further connected with the reset control terminal, and is further configured to control the potential of the output signal terminal based on the reset control signal.

[0022] Optionally, the first output control sub-circuit is further connected with a reset control terminal, and is configured to control the potential of the first intermediate node based on the potential of the input node and a reset control signal provided by the reset control terminal.

[0023] Optionally, the shift register unit further comprises:

[0024] a switch circuit, connected between the enable control terminal and the second output control sub-circuit, and further connected with the first control terminal and the second control terminal respectively, and used for controlling the on-off of the enable control terminal and the second output control sub-circuit in response to a first control signal provided by the first control terminal and a second control signal provided by the second control terminal.

[0025] Optionally, in the case that neither the first output control sub-circuit nor the second output control sub-circuit is connected with the reset control terminal, the first control terminal is connected with a first intermediate node of a previous shift register unit cascaded with the shift register unit, and the second control terminal is connected with a second intermediate node of the previous shift register unit.

[0026] in the case that the second output control sub-circuit of the first output control sub-circuit and the second output control sub-circuit is further connected with the reset control terminal, the first control terminal is connected with a first intermediate node of a previous shift register unit cascaded with the shift register unit, and the second control terminal is connected with a second intermediate node of the previous shift register unit.

[0027] in the case that the first output control sub-circuit of the first output control sub-circuit and the second output control sub-circuit is further connected with the reset control terminal, the first control terminal is connected with a first intermediate node of a previous shift register unit cascaded with the shift register unit, and the second control terminal is connected with a second intermediate node of the previous shift register unit.

[0028] Optionally, the shift register unit further comprises:

[0029] a latch circuit, connected with a third clock terminal, a fourth clock terminal, the first intermediate node and the input node respectively, and used for controlling the on-off of the first intermediate node and the input node in response to a third clock signal provided by the third clock terminal and a fourth clock signal provided by the fourth clock terminal, and outputting the potential of the first intermediate node to the input node after being inverted.

[0030] Optionally, the first clock terminal and the third clock terminal are shared, and the second clock terminal and the fourth clock terminal are shared.

[0031] Optionally, the latch circuit comprises: a first NOT gate and a first transmission gate connected in series between the first intermediate node and the input node, and the first transmission gate is further connected with the third clock terminal and the fourth clock terminal respectively.

[0032] Optionally, the circuit connected with the reset control terminal or the enable control terminal in the first output control sub-circuit and the second output control sub-circuit comprises an NAND gate or an NOR gate, and the circuit not connected with the reset control terminal and the enable control terminal comprises an NAND gate.

[0033] In the case that the first output control sub-circuit is connected with the reset control terminal and the second output control sub-circuit is not connected with the reset control terminal, the first NAND gate comprised by the latch circuit and the second NAND gate comprised by the second output control sub-circuit are shared.

[0034] Optionally, the second output control sub-circuit is further connected with a first power terminal and is configured to control the on-off of the first power terminal and the output signal terminal and the on-off of the enable control terminal and the output signal terminal in response to the potential of the first intermediate node, so as to control the potential of the output signal terminal and output the gate drive signal through the output signal terminal.

[0035] The gate drive signal comprises a power signal provided by the first power terminal or the enable control signal.

[0036] The enable control signal is a potential change signal comprising an effective potential and an ineffective potential, so that the gate drive signal is a pulse width adjustable signal; the effective potential refers to a signal for driving a transistor in the pixel to turn on, and the ineffective potential refers to a signal for driving the transistor in the pixel to turn off.

[0037] Optionally, in the case that the output signal terminal is used to connect a P-type transistor in the pixel, the effective potential of the enable control signal is less than the potential of the power signal provided by the first power terminal.

[0038] In the case that the output signal terminal is used to connect an N-type transistor in the pixel, the effective potential of the enable control signal is greater than the potential of the power signal provided by the first power terminal.

[0039] Optionally, the pixel is located in a display area, and the display area comprises a first display area and a second display area, and the refresh frequency of the first display area is greater than the refresh frequency of the second display area.

[0040] In the first display area, the enable control signal is the potential change signal, and in the second display area, the potential of the enable control signal is kept as a constant ineffective potential.

[0041] Optionally, the enable control terminal of the shift register unit is different from the enable control terminal of another stage shift register unit connected in cascade with the shift register unit.

[0042] Optionally, the number of the second output control sub-circuits is at least two.

[0043] Further, the at least two second output control sub-circuits are connected to the at least two output signal terminals one by one, and the at least two second output control sub-circuits are connected to the at least two enable control terminals one by one, the at least two output signal terminals being used for connecting different pixels.

[0044] Optionally, the second output control sub-circuit comprises a third NAND gate connected between the first intermediate node and the output signal terminal.

[0045] Optionally, the input control circuit comprises a second transmission gate.

[0046] The second transmission gate is connected between the input signal terminal and the input node, and is further connected to the first clock terminal and the second clock terminal respectively.

[0047] Optionally, the shift register unit further comprises:

[0048] A driving enhancement circuit connected between the output control circuit and the output signal terminal, and used for performing at least one inversion processing on the potential of the output signal of the output control circuit and then outputting the output signal to the output signal terminal.

[0049] Optionally, the driving enhancement circuit comprises at least one fourth NAND gate connected between the output control circuit and the output signal terminal, and in the case that the driving enhancement circuit comprises a plurality of fourth NAND gates, the plurality of fourth NAND gates are connected in series between the output control circuit and the output signal terminal.

[0050] The power supply terminal of each fourth NAND gate in the plurality of fourth NAND gates is further connected to a second power supply terminal and a third power supply terminal respectively, and is used for working based on the power supply signal provided by the second power supply terminal and the power supply signal provided by the third power supply terminal, wherein the potential of the power supply signal provided by the second power supply terminal is greater than the potential of the power supply signal provided by the third power supply terminal.

[0051] Optionally, in the plurality of fourth NAND gates, the potential of the power supply signal provided by the second power supply terminal connected to the last fourth NAND gate is greater than or equal to the potential of the power supply signal provided by the second power supply terminal connected to other fourth NAND gates except the last fourth NAND gate; wherein the last fourth NAND gate is the fourth NAND gate directly connected to the output signal terminal.

[0052] Optionally, in the plurality of fourth NOT gates, a third power supply end connected to a last fourth NOT gate provides a power supply signal with a potential less than or equal to a potential of a power supply signal provided by a third power supply end connected to another fourth NOT gate other than the last fourth NOT gate; wherein the last fourth NOT gate is a fourth NOT gate directly connected to the output signal end.

[0053] Optionally, the output signal end comprises: a first output end for connection with an N-type transistor in a pixel, and a second output end for connection with a P-type transistor in the pixel; and the driving enhancement circuit comprises:

[0054] a first driving enhancement sub-circuit connected between the output control circuit and the first output end, and configured to output the potential of the output signal of the output control circuit after an even number of inversion processes.

[0055] a second driving enhancement sub-circuit connected between the output control circuit and the second output end, and configured to output the potential of the output signal of the output control circuit after an odd number of inversion processes.

[0056] Optionally, the first driving enhancement sub-circuit comprises an even number of fourth NOT gates connected in series, the second driving enhancement sub-circuit comprises an odd number of fourth NOT gates connected in series, and the first driving enhancement sub-circuit and the second driving enhancement sub-circuit share at least one fourth NOT gate.

[0057] Optionally, in the case that the output control circuit is further connected to a first power supply end, and the output signal end is configured to connect to a P-type transistor in a pixel, the first power supply end is shared with the second power supply end.

[0058] In the case that the output control circuit is further connected to a first power supply end, and the output signal end is configured to connect to an N-type transistor in a pixel, the first power supply end is shared with the third power supply end.

[0059] Optionally, the output signal end of the shift register unit is configured to connect to an N-type data writing transistor in the pixel, and configured to output a gate driving signal to the N-type data writing transistor through the output signal end.

[0060] and / or,

[0061] The output signal end of the shift register unit is configured to connect to a P-type data writing transistor in the pixel, and configured to output a gate driving signal to the P-type data writing transistor through the output signal end.

[0062] Optionally, the input control circuit comprises a second transmission gate; the output control circuit comprises a first output control sub-circuit and a second output control sub-circuit, and the second output control sub-circuit comprises a first output control unit and a second output control unit, and the first output control sub-circuit and the second output control unit each comprise an NOR gate, the first output control unit comprises a second NOR gate; the shift register unit further comprises a switching circuit, a latching circuit and a driving enhancement circuit, and the switching circuit comprises a third transmission gate, the latching circuit comprises a first NOR gate and a first transmission gate, and the driving enhancement circuit comprises three fourth NOR gates; and the first NOR gate and the second NOR gate are shared.

[0063] The second transmission gate is connected between an input end of the shift register unit and the input node, and is further connected with the first clock end and the second clock end respectively.

[0064] In the first output control sub-circuit, two input ends of the NOR gate are connected with the input node and a reset control end respectively, and an output end of the NOR gate is connected with a first intermediate node.

[0065] An input end of the second NOR gate is connected with the first intermediate node, and an output end of the second NOR gate is connected with a second intermediate node.

[0066] In the second output control unit, one input end of the NOR gate is connected with the second intermediate node, another input end of the NOR gate is connected with the enable control end through the third transmission gate, and an output end of the NOR gate is connected with the output signal end through the three fourth NOR gates in sequence, and the third transmission gate is further connected with the first intermediate node and the second intermediate node respectively, and the three fourth NOR gates are connected in series.

[0067] An input end of the first NOR gate is connected with the first intermediate node, and an output end of the first NOR gate is connected with the input node through the first transmission gate, and the first transmission gate is further connected with a third clock end and a fourth clock end respectively.

[0068] The output signal end is used for being connected with the P-type transistor in the pixel.

[0069] Optionally, the output control circuit comprises a first output control sub-circuit and a second output control sub-circuit; the shift register unit further comprises a latching circuit and a driving enhancement circuit; the input control circuit comprises a second transmission gate; the first output control sub-circuit comprises an NOR gate; the second output control sub-circuit comprises a third NOR gate; the latching circuit comprises a first NOR gate and a first transmission gate; the driving enhancement circuit comprises two fourth NOR gates connected in series.

[0070] The first transmission gate is connected to the input signal end and the input node connection, and is also connected to the first clock end and the second clock end, respectively;

[0071] The two input ends of the NAND gate are connected to the input node and the reset control end, respectively, and the output end of the NAND gate is connected to the first intermediate node;

[0072] The input end of the third NAND gate is connected to the first intermediate node, the output end of the third NAND gate is connected to the output signal end through the two fourth NAND gates in series, and the third NAND gate is also connected to the first power supply end and the enable control end, respectively, and each fourth NAND gate is also connected to the second power supply end and the third power supply end, respectively;

[0073] The input end of the first NAND gate is connected to the first intermediate node, and the output end of the first NAND gate is connected to the input node through the first transmission gate, and the first transmission gate is also connected to the third clock end and the fourth clock end, respectively.

[0074] In another aspect, a driving method of a shift register unit is provided for driving the shift register unit as described in the above aspect; the method comprises:

[0075] In response to a first scan instruction, a first clock signal is provided to the first clock end, a second clock signal is provided to the second clock end, and an enable control signal identical to the first clock signal or the second clock signal is provided to the enable control end, and the first clock signal and the second clock signal provided have opposite potentials in the same period;

[0076] In response to a second scan instruction, a first clock signal is provided to the first clock end, a second clock signal is provided to the second clock end, and an enable control signal of a constant potential is provided to the enable control end;

[0077] The first clock signal and the second clock signal are used to drive the input control circuit to control the on-off of the input end and the first intermediate node, and to control the potential of the first intermediate node based on the input signal provided by the input signal end; the enable control signal is used to drive the output control circuit to control the potential of the output signal end based on the potential of the first intermediate node and the enable control signal, so as to output a gate drive signal to the pixel through the output signal end to drive the pixel to emit light;

[0078] And the refresh frequency indicated by the first scan instruction is greater than the refresh frequency indicated by the second scan instruction.

[0079] In yet another aspect, a gate drive circuit is provided, which comprises a plurality of shift register units as described in the above aspect connected in cascade.

[0080] Optionally, the plurality of shift register units in cascade comprises a plurality of groups of shift register units, each group of shift register units comprising at least two shift register units in cascade;

[0081] The first clock end and the second clock end connected by the at least two shift register units are respectively and correspondingly staggered connected with different at least two clock lines, and the enable control ends connected by the at least two shift register units are respectively and correspondingly connected with different at least two enable control lines; and the plurality of groups of shift register units share the at least two clock lines and share the at least two enable control lines.

[0082] Optionally, each group of shift register units comprises two adjacent shift register units in cascade.

[0083] In still another aspect, a display device is provided, comprising a display panel and the gate drive circuit as described in the above-mentioned still another aspect.

[0084] The display panel comprises a plurality of pixels, and the gate drive circuit is connected with the plurality of pixels and is configured to transmit a gate drive signal to the plurality of pixels to drive the plurality of pixels to emit light. BRIEF DESCRIPTION OF DRAWINGS

[0085] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0086] FIG. 1 is a structural schematic diagram of a shift register unit provided by an embodiment of the present application;

[0087] FIG. 2 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present application;

[0088] FIG. 3 is a driving timing schematic diagram of a pixel circuit provided by an embodiment of the present application;

[0089] FIG. 4 is a structural schematic diagram of another shift register unit provided by an embodiment of the present application;

[0090] FIG. 5 is a structural schematic diagram of still another shift register unit provided by an embodiment of the present application;

[0091] FIG. 6 is a structural schematic diagram of yet another shift register unit provided by an embodiment of the present application;

[0092] FIG. 7 is a structural schematic diagram of still another shift register unit provided by an embodiment of the present application;

[0093] Fig. 8 is a structural schematic diagram of still another shift register unit provided by an embodiment of the present application;

[0094] Fig. 9 is a structural schematic diagram of still another shift register unit provided by an embodiment of the present application;

[0095] Fig. 10 is a structural schematic diagram of still another shift register unit provided by an embodiment of the present application;

[0096] Fig. 11 is a structural schematic diagram of still another shift register unit provided by an embodiment of the present application;

[0097] Fig. 12 is a structural schematic diagram of still another shift register unit provided by an embodiment of the present application;

[0098] Fig. 13 is a timing schematic diagram of an enable control signal in different regions provided by an embodiment of the present application;

[0099] Fig. 14 is a structural schematic diagram of still another shift register unit provided by an embodiment of the present application;

[0100] Fig. 15 is a structural schematic diagram of still another shift register unit provided by an embodiment of the present application;

[0101] Fig. 16 is a structural schematic diagram of still another shift register unit provided by an embodiment of the present application;

[0102] Fig. 17 is a structural schematic diagram of still another shift register unit provided by an embodiment of the present application;

[0103] Fig. 18 is a circuit structural schematic diagram of a shift register unit provided by an embodiment of the present application;

[0104] Fig. 19 is a circuit structural schematic diagram of another shift register unit provided by an embodiment of the present application;

[0105] Fig. 20 is a circuit structural schematic diagram of still another shift register unit provided by an embodiment of the present application;

[0106] Fig. 21 is a circuit structural schematic diagram of still another shift register unit provided by an embodiment of the present application;

[0107] Fig. 22 is a circuit structural schematic diagram of still another shift register unit provided by an embodiment of the present application;

[0108] Fig. 23 is a circuit structural schematic diagram of still another shift register unit provided by an embodiment of the present application;

[0109] Fig. 24 is a circuit structural schematic diagram of still another shift register unit provided by an embodiment of the present application;

[0110] FIG. 25 is a schematic circuit structure diagram of another shift register unit according to an embodiment of the present application;

[0111] FIG. 26 is a schematic circuit structure diagram of another shift register unit according to an embodiment of the present application;

[0112] FIG. 27 is a schematic circuit structure diagram of another shift register unit according to an embodiment of the present application;

[0113] FIG. 28 is a schematic circuit structure diagram of another shift register unit according to an embodiment of the present application;

[0114] FIG. 29 is a schematic circuit structure diagram of another shift register unit according to an embodiment of the present application;

[0115] FIG. 30 is a schematic circuit structure diagram of another shift register unit according to an embodiment of the present application;

[0116] FIG. 31 is a schematic circuit structure diagram of another shift register unit according to an embodiment of the present application;

[0117] FIG. 32 is a schematic circuit structure diagram of another shift register unit according to an embodiment of the present application;

[0118] FIG. 33 is a schematic transistor structure diagram of a shift register unit according to an embodiment of the present application;

[0119] FIG. 34 is a schematic transistor structure diagram of another shift register unit according to an embodiment of the present application;

[0120] FIG. 35 is a schematic transistor structure diagram of another shift register unit according to an embodiment of the present application;

[0121] FIG. 36 is a schematic transistor structure diagram of another shift register unit according to an embodiment of the present application;

[0122] FIG. 37 is a schematic transistor structure diagram of another shift register unit according to an embodiment of the present application;

[0123] FIG. 38 is a schematic transistor structure diagram of another shift register unit according to an embodiment of the present application;

[0124] FIG. 39 is a schematic transistor structure diagram of another shift register unit according to an embodiment of the present application;

[0125] FIG. 40 is a schematic module equivalent diagram of a shift register unit according to an embodiment of the present application;

[0126] FIG. 41 is a schematic module equivalent diagram of another shift register unit according to an embodiment of the present application;

[0127] Figure 42 is a flow chart illustrating a driving method of a shift register unit according to an embodiment of the present application;

[0128] Figure 43 is a timing diagram illustrating a driving method of a shift register unit according to an embodiment of the present application;

[0129] Figure 44 is a timing diagram illustrating a driving method of a shift register unit according to an embodiment of the present application;

[0130] Figure 45 is a timing diagram illustrating a driving method of a shift register unit according to an embodiment of the present application;

[0131] Figure 46 is a timing diagram illustrating a driving method of a shift register unit according to an embodiment of the present application;

[0132] Figure 47 is a timing diagram illustrating a driving method of a shift register unit according to an embodiment of the present application;

[0133] Figure 48 is a timing diagram illustrating a driving method of a shift register unit according to an embodiment of the present application;

[0134] Figure 49 is a timing diagram illustrating a driving method of a shift register unit according to an embodiment of the present application;

[0135] Figure 50 is a timing diagram illustrating a driving method of a shift register unit according to an embodiment of the present application;

[0136] Figure 51 is a timing diagram illustrating a driving method of a shift register unit according to an embodiment of the present application;

[0137] Figure 52 is a timing diagram illustrating a driving method of a shift register unit according to an embodiment of the present application;

[0138] Figure 53 is a timing diagram illustrating a driving method of a shift register unit according to an embodiment of the present application;

[0139] Figure 54 is a timing diagram illustrating a driving method of a shift register unit according to an embodiment of the present application;

[0140] Figure 55 is a structural diagram illustrating a gate driving circuit according to an embodiment of the present application;

[0141] Figure 56 is a structural diagram illustrating a gate driving circuit according to an embodiment of the present application;

[0142] Figure 57 is a structural diagram illustrating a gate driving circuit according to an embodiment of the present application;

[0143] Figure 58 is a structural diagram illustrating a gate driving circuit according to an embodiment of the present application;

[0144] FIG. 59 is a structural schematic diagram of another gate driving circuit according to an embodiment of the present application;

[0145] FIG. 60 is a structural schematic diagram of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0146] For the purpose, technical solutions and advantages of the present application to be clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0147] It can be understood that the transistors used in the embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics, and the transistors used in the embodiments of the present application are mainly switching transistors according to the role in the circuit. Since the source and the drain of the switching transistor used here are symmetrical, the source and the drain can be interchangeable. In the embodiments of the present application, the source is referred to as the first pole and the drain is referred to as the second pole. According to the mode in the drawings, the middle end of the transistor is defined as the control pole, which can also be referred to as the gate, the signal input signal end is defined as the source, and the signal output signal end is defined as the drain. In addition, the switching transistor used in the embodiments of the present application can include any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low potential and is turned off when the gate is at a high potential, and the N-type switching transistor is turned on when the gate is at a high potential and is turned off when the gate is at a low potential. In addition, a plurality of signals in each embodiment of the present application correspond to a first potential and a second potential. The first potential and the second potential only represent that the potential of the signal has two state quantities, and do not represent that the first potential or the second potential has a specific value throughout the text.

[0148] The embodiments of the present application provide a shift register unit, which can not only better match the timing requirements of N-type transistors and / or P-type transistors in pixels, but also can realize local refresh of pixels, reliably reset the output signal, have good driving flexibility, rich driving modes, and good driving effect. As shown in FIG. 1, the shift register unit includes an input control circuit 01 and an output control circuit 02.

[0149] The input control circuit 01 is connected with a first clock end CKn, a second clock end CB, an input signal end IN_n and an input node Q_n respectively, and is configured to control the on-off of the input signal end IN_n and the input node Q_n in response to a first clock signal provided by the first clock end CKn and a second clock signal provided by the second clock end CB.

[0150] For example, the input control circuit 01 can control the input signal terminal IN_n to be connected to the input node Q_n when the first clock signal has the first potential and the second clock signal has the first potential, so that the input signal provided by the input signal terminal IN_n is output to the input node Q_n, thereby controlling the potential of the input node Q_n to be the potential of the input signal; and the input control circuit 01 can control the input signal terminal IN_n to be disconnected from the input node Q_n when the first clock signal has the second potential or the second clock signal has the second potential.

[0151] It can be understood that "n" represents that the shift register unit is an nth shift register unit, and correspondingly, "n-1" represents a previous shift register unit connected in cascade with the shift register unit, and "n+1" represents a next shift register unit connected in cascade with the shift register unit, and n can be an integer greater than 1. Generally, a plurality of shift register units can be connected in one-to-one correspondence with a plurality of rows of pixels, and of course, are not limited to one-to-one correspondence. For example, each shift register unit can be connected with at least two rows of pixels.

[0152] Optionally, in the embodiment of the present application, the first potential can be a valid potential, and the second potential can be an invalid potential. For the P-type transistor in the pixel, the first potential can be a low potential (low, L) relative to the second potential. For the N-type transistor in the pixel, the first potential can be a high potential (high, H) relative to the second potential. It can be known accordingly that the reset output to the signal of the P-type transistor means that the potential of the signal output to the P-type transistor is high H; and the reset output to the signal of the N-type transistor means that the potential of the signal output to the N-type transistor is low L. In addition, the high potential can be represented by binary "1", and the low potential can be represented by binary "0".

[0153] With reference still to FIG. 1, the output control circuit 02 is connected with the input node Q_n, the enable control terminal GEN and the output signal terminal OUT_n respectively, and is configured to control the potential of the output signal terminal OUT_n based on the potential of the input node Q_n and the enable control signal provided by the enable control terminal GEN, so as to output the gate driving signal to the connected pixel through the output signal terminal OUT_n to drive the pixel to emit light. For example, the output control circuit 02 can be connected with the data writing transistor in the pixel through the output signal terminal OUT_n, so as to output the gate driving signal to the data writing transistor.

[0154] For example, the output control circuit 02 can control the potential of the output signal end OUT_n to be low potential 0 when the potential of the input node Q_n is high potential 1 and / or the potential of the enable control signal is high potential 1, and the output control circuit 02 can control the potential of the output signal end OUT_n to be high potential 1 when the potential of the input node Q_n is low potential 0 and the potential of the enable control signal is low potential 0. In this way, the gate drive signal including high potential 1 and low potential 0 (i.e., including the first potential and the second potential) can be output through the output signal end OUT_n, and the pulse (such as a phase with a pulse width of 1H) with a required timing can be output to the P-type transistor and / or the N-type transistor in the pixel, so as to meet the driving requirements of the PMOS switch type pixel, or meet the driving requirements of the NMOS switch type pixel, or meet the driving requirements of the CMOS switch type pixel. The "H" can refer to a row period, and can be flexibly adjusted according to the number of cascaded groups of the shift register unit.

[0155] In addition, the enable control signal provided by the enable control end GEN can be flexibly set to control the shift register unit to output or not to output. For example, during the blanking time (i.e., the porch period) of each frame, the potential of the enable control signal can be set to high potential, so that the shift register unit controls the potential of the output signal end OUT_n to be an invalid potential, i.e., the shift register unit continuously outputs the gate drive signal with the invalid potential to the pixel through the output signal end OUT_n, and at this time, the shift register unit is considered not to output, so as to realize local refresh of the pixel. In addition, during power-on / power-off of the display panel, the potential of the enable control signal can be set to control the potential of the output signal end OUT_n to be an invalid potential, so as to reset the gate drive signal output to the pixel, and ensure good on / off reliability.

[0156] For example, for the N-type transistor in the pixel connected to the output signal end OUT_n, during the porch period (or during power-on / power-off of the display panel), the potential of the enable control signal provided by the enable control end GEN can be set to high potential 1, i.e., the enable control signal is high, so that the output control circuit 02 controls the potential of the output signal end OUT_n to be low potential 0, so as to reset the display drive signal output to the N-type transistor. The P-type transistor is the same, and will not be described again. During the normal output period, the enable control signal provided by the enable control end GEN can be set to have the same timing as the timing of the first clock signal or the timing of the second clock signal, so that the output control circuit 02 can normally output the gate drive signal including high potential 1 and low potential 0.

[0157] It can be understood that the PMOS switch type pixel refers to a pixel in which the pixel circuit includes a plurality of P-type transistors; the NMOS switch type pixel refers to a pixel in which the pixel circuit includes a plurality of N-type transistors; and the CMOS switch type pixel refers to a pixel in which the pixel circuit includes at least one P-type transistor and at least one N-type transistor. MOS is an abbreviation of metal-oxide-semiconductor, that is, the transistors in the pixel circuit can be MOS transistors. In addition, the transistors can also be thin film transistors (TFTs). That is, the transistors in the pixel circuit can be MOS TFTs, the P-type transistors can be referred to as PMOS TFTs, and the N-type transistors can be referred to as NMOS TFTs. Of course, this is only illustrative.

[0158] Optionally, taking the CMOS switch type pixel as an example, FIG. 2 shows a circuit structure schematic diagram of a pixel provided in an embodiment of the present application. As shown in FIG. 2, the pixel can include a pixel circuit and a light emitting element L1. The pixel circuit can include 8 transistors T1 to T8 and 1 capacitor Cst, that is, a circuit of 8T1C structure. The light emitting element L1 can be an organic light-emitting diode (OLED). The connection modes of the parts are as shown in FIG. 2, and will not be described again. In addition, the signal ends connected by the pixel include a gate signal end Gate, reset signal ends Reset1, Reset2 and Reset3, a data signal end Vdata, reset power supply ends V1, V2 and V3, a light emitting control end EM, a pull-up power supply end EVDD, and a pull-down power supply end ELVSS. Of course, in some other embodiments, the pixel circuit can also be of other structures, such as a 8T2C structure. The light emitting element L1 can also be of other types. For example, a micro light-emitting diode (Micro-LED), also referred to as MLED. Embodiments of the present application do not limit this.

[0159] For the PMOS switch type pixel, the 8 transistors T1 to T8 can all be PMOS TFTs; for the NMOS switch type pixel, the 8 transistors T1 to T8 can all be NMOS TFTs; and for the CMOS switch type pixel, as shown in FIG. 2, T2 and T3 can be NMOS TFTs, and the other transistors except T2 and T3 can be PMOS TFTs. Correspondingly, taking the gate signal end Gate as an example, the gate signal end Gate connected by the transistor T2 is identified as Gate_N, and the gate signal end Gate connected by the transistor T1 is identified as Gate_P. “N” represents the relevant signal end connected by the NMOS TFT, “P” represents the relevant signal end connected by the PMOS TFT, and the identification of the other signal ends can be the same.

[0160] For the PMOS switch type pixel, since the transistors T1 and T2 receiving the gate driving signal are both PMOS TFTs, the same or similar P-type gate driving signal can be used to drive the transistors T1 and T2 to work. For the NMOS switch type pixel, since the transistors T1 and T2 receiving the gate driving signal are both NMOS TFTs, the same or similar N-type gate driving signal can be used to drive the transistors T1 and T2 to work. For the CMOS switch type pixel shown in FIG. 2, since the transistor T1 receiving the gate driving signal is a PMOS TFT and the transistor T2 is an NMOS TFT, the opposite P-type gate driving signal and N-type gate driving signal are needed to drive the transistors T1 and T2 to work, respectively. As described above, the P-type gate driving signal refers to the gate driving signal with the first potential being the low potential 0 and the second potential being the high potential 1, and the N-type control signal refers to the gate driving signal with the first potential being the high potential 1 and the second potential being the low potential 0.

[0161] Optionally, taking the pixel circuit shown in FIG. 2 as an example, FIG. 3 shows a driving timing diagram of the pixel circuit. As shown in FIG. 3, the driving timing can include stages t1 to t5 executed in sequence.

[0162] In stage t1, the potential of the light emitting control signal provided by the light emitting control end EM can be the high potential. Correspondingly, the transistors T4 and T5 can be both turned off or turned off. Further, the pull-up power supply end EVDD and the pull-down power supply end EVSS can be disconnected, so that the light emission of the light emitting element L1 is turned off.

[0163] In stage t2, the potential of the reset signal provided by the reset signal end Reset1 is the high potential, and the potential of the reset signal provided by the reset signal end Reset3 is the low potential. Correspondingly, the transistors T3 and T6 can be both turned on. Further, the reset power supply end V2 can output the reset power supply signal to the node P1 through the turned-on transistor T3 to reset the node P1 to the potential V20 of the reset power supply signal provided by the reset power supply end V2, so that the potential of the node P2 gradually becomes V20-Vth_Td, Vth_Td being the threshold voltage of the transistor T8 (also referred to as the driving transistor Td). In addition, the reset power supply end V1 can output the reset power supply signal to the node P4 (i.e., the anode of the OLED) through the turned-on transistor T6 to reset the node P4 to the potential of the reset power supply signal provided by the reset power supply end V1.

[0164] At stage t3, the potential of the reset signal provided by the reset signal terminal Reset1 becomes low, the potential of the reset signal provided by the reset signal terminal Reset3 becomes high, the potential of the gate drive signal provided by the gate signal terminal Gate_P is low, and the potential of the gate drive signal provided by the gate signal terminal Gate_N is high. Correspondingly, the transistors T3 and T6 are both turned off, and the transistors T1, T2 and T8 are all turned on. Further, the data signal terminal Vdata transmits the data signal to the node P2 through the turned-on transistor T1, so as to charge the potential of the node P2 to the potential Vdata0 of the data signal, and the potentials of the node P3 and the node P1 are charged to Vdata0+Vth_Td.

[0165] At stage t4, the potential of the gate drive signal provided by the gate signal terminal Gate_N becomes low, the potential of the gate drive signal provided by the gate signal terminal Gate_P becomes high, and the potential of the reset signal provided by the reset signal terminal Reset2 is low. Correspondingly, the transistors T1 and T2 are both turned off, and the transistor T7 is turned on. Further, the reset power terminal V3 outputs the reset power signal to the node P2 through the turned-on transistor T7, so as to reset the node P2 to the potential V30 of the reset power signal provided by the reset power terminal V3. If V30>Vdata0, the potential of the node P3 can become V30+Vth_Td, otherwise, the potential of the node P3 can remain Vdata0+Vth_Td.

[0166] At stage t5, the potential of the reset signal provided by the reset signal terminal Reset2 becomes high, and the potential of the light-emitting control signal provided by the light-emitting control terminal EM becomes low. Correspondingly, the transistor T7 is turned off, and the transistors T4, T5 and T8 are turned on. Further, a path is formed between the pull-up power terminal EVDD and the pull-down power terminal EVSS, so that the light-emitting element L1 can emit light. The light-emitting current Id positively correlated with the light-emitting brightness can be determined by the potential of the node P1 and the potential of the node P2. The potential of the node P1 is Vdata0+Vth_Td, and the potential of the node P2 is the potential EVDD0 of the pull-up power signal provided by the pull-up power terminal EVDD. Correspondingly, based on the current calculation formula, Id=K(Vdata0-EVDD0) 2 . K is determined by the aspect ratio W / L, the capacitance Cox, the mobility μ and other inherent characteristics of the transistor T8. That is, the light-emitting current transmitted to the light-emitting element L1 by the pixel circuit can be independent of the threshold voltage Vth_Td of the driving transistor, and further, the drift of the threshold voltage Vth_Td of the transistor T8 will not affect the light-emitting brightness of the light-emitting element L1, so as to ensure that the light-emitting effect of the light-emitting element L1 is better.

[0167] It can be understood that, on the basis of the above driving principle introduction, the transistors T1 and T2 can be referred to as data writing transistors, the transistors T3, T6 and T7 can be referred to as reset transistors, the transistors T4 and T5 can be referred to as light emitting control transistors, and the transistor T8 can be referred to as a driving transistor.

[0168] Optionally, the output signal end OUT_n of the shift register unit can be connected with the gate signal end (for example, the Gate_N and / or Gate_P shown in FIG. 2) of the pixel circuit, and is used to provide the required gate driving signal to the gate signal end. For example, the inverted P-type gate driving signal and N-type gate driving signal shown in FIG. 3 are provided to drive the transistors T1 and T2 in FIG. 2 to work reliably. Of course, in some other embodiments, the output signal end OUT_n of the shift register unit can also be connected with other signal ends (for example, a reset signal end) of the pixel circuit, and is used to provide a signal to the other signal ends.

[0169] In summary, the embodiment of the present application provides a shift register unit. The shift register unit includes an input control circuit and an output control circuit. The input control circuit can control the on-off of the input signal end and the input node under the control of the clock signal provided by the first clock end and the clock signal provided by the second clock end. The output control circuit can output the gate driving signal to the pixel through the output signal end based on the potential of the input node and the enable control signal provided by the enable control end to drive the pixel to emit light. In this way, the clock signal and the enable control signal can be flexibly set, so that the shift register unit outputs the gate driving signal matching the P-type transistor and / or the N-type transistor in the pixel to the output signal end, and can also selectively control the shift register unit to output or not to output at different time periods, to realize local refresh of the pixel, reliably reset the gate driving signal, ensure good driving flexibility, and rich driving mode.

[0170] Optionally, as described above, the output signal end OUT_n of the shift register unit can be used to connect with the N-type data writing transistor in the pixel, and is used to output the gate driving signal to the N-type data writing transistor through the output signal end OUT_n. For example, in combination with FIG. 2, the output signal end OUT_n of the shift register unit can be connected with the gate signal end Gate_N of the N-type data writing transistor T2 in the pixel, and output the required N-type gate driving signal to the gate signal end Gate_N.

[0171] and / or,

[0172] The output signal terminal OUT_n of the shift register unit can be used to connect with the P-type data write transistor in the pixel, and is used to output the gate driving signal to the P-type data write transistor through the output signal terminal OUT_n. For example, in combination with FIG. 2, the output signal terminal OUT_n of the shift register unit can be connected with the gate signal terminal Gate_P of the P-type data write transistor T1 in the pixel, and outputs the required P-type gate driving signal to the gate signal terminal Gate_P.

[0173] Optionally, FIG. 4 shows a structural schematic diagram of another shift register unit provided by the embodiment of the present application. As shown in FIG. 4, the output control circuit 02 includes a first output control sub-circuit 021 and a second output control sub-circuit 022.

[0174] The first output control sub-circuit 021 can be connected with the input node Q_n and the first intermediate node Q1_n respectively, and can be used to control the potential of the first intermediate node Q1_n based on the potential of the input node Q_n.

[0175] For example, the first output control sub-circuit 021 can output the potential of the input node Q_n after inverting processing to the first intermediate node Q1_n, that is, can control the potential of the first intermediate node Q1_n to be opposite to the potential of the input node Q_n.

[0176] The second output control sub-circuit 022 can be connected with the first intermediate node Q1_n, the enable control terminal GEN and the output signal terminal OUT_n respectively, and can be used to control the potential of the output signal terminal OUT_n based on the potential of the first intermediate node Q1_n and the enable control signal.

[0177] For example, the second output control sub-circuit 022 can control the potential of the output signal terminal OUT_n to be low potential 0 when the potential of the first intermediate node Q1_n is high potential 1 and / or the potential of the enable control signal is high potential 1; and the second output control sub-circuit 022 can control the potential of the output signal terminal OUT_n to be high potential 1 when the potential of the first intermediate node Q1_n is low potential 0 and the potential of the enable control signal is low potential 0.

[0178] Optionally, based on FIG. 4, as a first optional implementation manner, as shown in FIG. 5, the second output control sub-circuit 022 can include a first output control unit 0221 and a second output control unit 0222.

[0179] The first output control unit 0221 can be connected with the first intermediate node Q1_n, the enable control terminal GEN and the second intermediate node Q2_n respectively, and can be used to control the potential of the second intermediate node Q2_n based on the potential of the first intermediate node Q1_n and the enable control signal.

[0180] For example, the first output control unit 0221 can control the potential of the second intermediate node Q2_n to be low potential 0 when the potential of the first intermediate node Q1_n is high potential 1 and / or the potential of the enable control signal is high potential 1; and the first output control unit 0221 can control the potential of the second intermediate node Q2_n to be high potential 1 when the potential of the first intermediate node Q1_n is low potential 0 and the potential of the enable control signal is low potential 0.

[0181] The second output control unit 0222 can be connected with the second intermediate node Q2_n and the output signal terminal OUT_n respectively, and can be used to control the potential of the output signal terminal OUT_n based on the potential of the second intermediate node Q2_n.

[0182] For example, the second output control unit 0222 can output the potential of the second intermediate node Q2_n after inverting processing to the output signal terminal OUT_n, that is, can control the potential of the output signal terminal OUT_n to be opposite to the potential of the second intermediate node Q2_n.

[0183] Optionally, based on FIG. 4, as a second optional implementation manner, as shown in FIG. 6, the second output control sub-circuit 022 can include the first output control unit 0221 and the second output control unit 0222.

[0184] The first output control unit 0221 can be connected with the first intermediate node Q1_n and the second intermediate node Q2_n respectively, and can be used to control the potential of the second intermediate node Q2_n based on the potential of the first intermediate node Q1_n.

[0185] For example, the first output control unit 0221 can output the potential of the first intermediate node Q1_n after inverting processing to the second intermediate node Q2_n, that is, can control the potential of the second intermediate node Q2_n to be opposite to the potential of the first intermediate node Q1_n.

[0186] The second output control unit 0222 can be connected with the second intermediate node Q2_n, the enable control terminal GEN and the output signal terminal OUT_n respectively, and can be used to control the potential of the output signal terminal OUT_n based on the potential of the second intermediate node Q2_n and the enable control signal.

[0187] For example, the second output control unit 0222 can control the potential of the output signal terminal OUT_n to be low potential 0 when the potential of the second intermediate node Q2_n is high potential 1 and / or the potential of the enable control signal is high potential 1; and the second output control unit 0222 can control the potential of the output signal terminal OUT_n to be high potential 1 when the potential of the second intermediate node Q2_n is low potential 0 and the potential of the enable control signal is low potential 0.

[0188] That is, in the first alternative implementation, the first output control unit 0221 included in the second output control sub-circuit 022 can further be connected with the enable control terminal GEN and can further control the potential of the second intermediate node Q2_n based on the enable control signal provided by the enable control terminal GEN. In the second alternative implementation, the second output control unit 0222 included in the second output control sub-circuit 022 can further be connected with the enable control terminal GEN and can further control the potential of the output signal terminal OUT_n based on the enable control signal provided by the enable control terminal GEN.

[0189] Optionally, based on the first alternative implementation shown in FIG. 5, as an alternative embodiment, as shown in FIG. 7, the first output control unit 0221 can further be connected with the reset control terminal Trst and can further be used to control the potential of the second intermediate node Q2_n based on the reset signal provided by the reset control terminal Trst.

[0190] Optionally, based on the second alternative implementation shown in FIG. 6, as another alternative embodiment, as shown in FIG. 8, the first output control unit 0221 can further be connected with the reset control terminal Trst and can further be used to control the potential of the second intermediate node Q2_n based on the reset signal provided by the reset control terminal Trst. Alternatively, as still another alternative embodiment, as shown in FIG. 9, the second output control unit 0222 can further be connected with the reset control terminal Trst and can further be used to control the potential of the output signal terminal OUT_n based on the reset signal.

[0191] Optionally, in combination with FIGS. 4 to 6, as still another alternative embodiment, as shown in FIG. 10, the first output control sub-circuit 021 can further be connected with the reset control terminal Trst and can further be used to control the potential of the first intermediate node Q1_n based on the reset signal provided by the reset control terminal Trst. It can be understood that FIG. 10 is a structural schematic diagram of still another shift register unit based on the structure shown in FIG. 4.

[0192] That is, in the embodiment, the first output control sub-circuit 021 or the second output control sub-circuit 022 in the output control circuit 02 can also be connected with the reset control terminal Trst, and can also control the output potential based on the reset signal provided by the reset control terminal Trst. For the second output control sub-circuit 022, the first output control unit 0221 can also be connected with the reset control terminal Trst, or the second output control unit 0222 can also be connected with the reset control terminal Trst.

[0193] It can be understood that, in addition to the enable control terminal GEN, the reset control terminal Trst is also provided, and the potential of the output signal terminal OUT_n can be controlled to be an invalid potential by flexibly setting the reset signal provided by the reset control terminal Trst when the display panel is powered on or powered off or in a porch period, that is, the gate drive signal output by the reset output, so as to improve the reliability of power-on and power-off. In this way, the driving abnormality during switching between low brushing and high brushing in the local refresh scene can also be avoided, and the driving power consumption of the shift register unit can be reduced.

[0194] Optionally, in some embodiments, as shown in FIG. 11, the second output control sub-circuit 022 can also be connected with the first power supply terminal V1, and can be used to control the connection and disconnection of the first power supply terminal V1 and the output signal terminal OUT_n, and the connection and disconnection of the enable control terminal GEN and the output signal terminal OUT_n in response to the potential of the first intermediate node Q1_n, so as to control the potential of the output signal terminal OUT_n and output the gate drive signal through the output signal terminal OUT_n.

[0195] For example, taking the first potential as a high potential 1 and the second potential as a low potential 0 as an example, when the potential of the first intermediate node Q1_n is a high potential 1, the second output control sub-circuit 022 can control the enable control terminal GEN and the output signal terminal OUT_n to be conductive, and control the first power supply terminal V1 and the output signal terminal OUT_n to be disconnected, so that the enable control signal provided by the enable control terminal GEN is output as a gate drive signal through the output signal terminal OUT_n; when the potential of the first intermediate node Q1_n is a low potential 0, the second output control sub-circuit 022 can control the first power supply terminal V1 and the output signal terminal OUT_n to be conductive, and control the enable control terminal GEN and the output signal terminal OUT_n to be disconnected, so that the power supply signal provided by the first power supply terminal V1 is output as a gate drive signal through the output signal terminal OUT_n. That is, in this embodiment, the gate drive signal output through the output signal terminal OUT_n can include the power supply signal or the enable control signal provided by the first power supply terminal V1.

[0196] And, the enable control signal can be a potential change signal including an effective potential and an ineffective potential, so that the gate drive signal is a pulse width adjustable signal. That is, the pulse width of the gate drive signal output through the output signal terminal OUT_n can be adjusted by flexibly setting the pulse width of the enable control signal to match the pixel charging requirement. As described above, the effective potential can refer to a signal for driving the transistor in the pixel to turn on, and the ineffective potential can refer to a signal for driving the transistor in the pixel to turn off. On the basis of the transistor turning on, the pixel can be refreshed and lit. In the case of the transistor turning off, the pixel can stop being refreshed and lit.

[0197] As can be seen, in combination with FIG. 11, in the case where the output signal terminal OUT_n is used to connect the P-type transistor in the pixel, the output signal terminal OUT_n connecting the P-type transistor is identified as GP_n in the figure. Since for the P-type transistor, the low potential turns on and the high potential turns off, the effective potential of the enable control signal can be less than the potential of the power signal provided by the first power terminal V1. For example, the first power terminal V1 can be a pull-up power terminal VGH, and the enable control terminal GEN can be a potential adjustable pull-down power terminal VGL.

[0198] In combination with FIG. 12, in the case where the output signal terminal OUT_n is used to connect the N-type transistor in the pixel, the output signal terminal OUT_n connecting the N-type transistor is identified as GN_n in the figure. Since for the N-type transistor, the high potential turns on and the low potential turns off, the effective potential of the enable control signal can be greater than the potential of the power signal provided by the first power terminal V1. For example, the first power terminal V1 can be a pull-down power terminal VGL, and the enable control terminal GEN can be a potential adjustable pull-up power terminal VGH.

[0199] Optionally, referring to FIG. 13, the pixel can be located in a display area AA, and the display area AA can include a first display area AA1 and a second display area AA2. The refresh frequency of the first display area AA1 can be greater than the refresh frequency of the second display area AA2. That is, the first display area AA1 can be a high refresh area, and the second display area AA2 can be a low refresh area. For example, the refresh frequency of the first display area AA1 can be 120 hz, and the refresh frequency of the second display area AA2 can be 1 hz.

[0200] Correspondingly, in the first display area AA1, the enable control signal can be the potential change signal as described above, and in the second display area AA2, the potential of the enable control signal can be kept as a constant invalid potential. In this way, only the pixels in the high-brushing area are refreshed and lighted, and the pixels in the low-brushing area are not refreshed and lighted, thereby realizing the local brushing effect. For example, for the structure in which the output signal end OUT_n is connected to the terminal GP_n of the P-type transistor, in the low-brushing area, the potential of the enable control signal can be kept as a constant high potential. For the structure in which the output signal end OUT_n is connected to the terminal GN_n of the N-type transistor, in the low-brushing area, the potential of the enable control signal can be kept as a constant low potential.

[0201] Alternatively, the enable control end GEN connected by the shift register unit and the enable control end GEN connected by the other stage shift register unit cascaded by the shift register unit can be different. That is, the two adjacent stages of the cascaded shift register units can be connected to different enable control ends GEN. Of course, it should be noted here that the first clock end CKn and the second clock end CB of the two adjacent stages of the cascaded shift register units can be alternately connected to two clock lines, and the gate driving circuit including the multi-stage shift register unit shares the two clock lines, that is, it can be considered that the gate driving circuit adopts 2-phase clock. In this way, for the pixels connected by the two adjacent stages of the cascaded shift register units (for example, two adjacent rows of pixels), the light emission thereof can be driven separately, such as time-division lighting of the two adjacent rows of pixels. If the gate driving circuit adopts 3-phase clock, then the three adjacent stages of the cascaded shift register units can be connected to different enable control ends GEN, and the same applies to the subsequent stages, which will not be described one by one. The multi-stage shift register units can share the different enable control ends GEN.

[0202] For example, referring to FIG. 14, the nth stage of the shift register unit and the n+1 stage of the shift register unit are cascaded, the nth stage of the shift register unit is connected to the enable control end GEN-1, and the n+1 stage of the shift register unit is connected to the enable control end GEN-2. The multi-stage shift register units in the gate driving circuit can share the two enable control ends GEN-1 and GEN-2. This belongs to the design mode of 2GEN.

[0203] Alternatively, based on FIG. 11, the number of the second output control sub-circuits 022 can be at least two. That is, the shift register unit can include two or more second output control sub-circuits 022.

[0204] And, the at least two second output control sub-circuits 022 can be connected with the at least two output signal terminals OUT_n one by one, and the at least two second output control sub-circuits 022 can be connected with the at least two enable control terminals GEN one by one, and the at least two output signal terminals OUT_n are used for connecting different pixels. In this way, the enable control signals can be flexibly set, so that different pixels can be refreshed and lightened by one shift register unit, thereby the structure of the gate drive circuit can be simplified, and the narrow frame design is facilitated.

[0205] For example, referring to FIG. 15, the shift register unit shown therein includes two second output control sub-circuits 022-1 and 022-2, which are connected with two output signal terminals OUT_n and OUT_n+1 one by one respectively, and are connected with two enable control terminals GEN1 and GEN2 respectively, and the two output signal terminals OUT_n and OUT_n+1 are used for connecting two adjacent rows of pixels respectively. In this way, the enable control signals provided by the enable control terminals GEN1 and GEN2 can be flexibly set, so that the two adjacent rows of pixels can be separately lightened respectively, and the row-by-row scanning drive is also achieved.

[0206] It can be understood that, based on FIG. 14 and combined with FIG. 15, the shift register unit cascaded by two adjacent stages can be connected with four different enable control terminals GEN, and the multiple shift register units in the gate drive circuit can share the four different enable control terminals GEN. This belongs to the design mode of 4GEN.

[0207] Of course, in some other embodiments, the at least two enable control terminals GEN connected by the at least two second output control sub-circuits 022 can also be shared. In this way, the simultaneous drive of different pixels (such as two adjacent rows of pixels) connected to the shift register unit can be achieved, that is, the different pixels are lightened at the same time.

[0208] Optionally, it can also be seen from FIGS. 4 to 15 that the shift register unit described in the embodiments of the present application can further include a latch circuit 03.

[0209] And, the latch circuit 03 can be connected with a third clock terminal CBn, a fourth clock terminal CK, a first intermediate node Q1_n and an input node Q_n respectively, and can be used for controlling the on-off of the first intermediate node Q1_n and the input node Q_n in response to a third clock signal provided by the third clock terminal CBn and a fourth clock signal provided by the fourth clock terminal CK, and outputting the potential of the first intermediate node Q1_n to the input node Q_n after the potential of the first intermediate node Q1_n is inverted.

[0210] In an example, the latch circuit 03 can control the first intermediate node Q1_n and the input node Q_n to be conductive when the third clock signal has the first potential and the fourth clock signal has the first potential, and output the potential of the first intermediate node Q1_n to the input node Q_n after being inverted; and the latch circuit 03 can control the first intermediate node Q1_n and the input node Q_n to be disconnected when the third clock signal has the second potential or the fourth clock signal has the second potential. In this way, the potential of the input node Q_n can be the same as the potential of the first intermediate node Q1_n, so as to latch the potential of the input node Q_n, or the latch circuit 03 can also be called as storing the potential of the input node Q_n, so as to avoid the potential of the input node Q_n from being leaked.

[0211] Optionally, based on FIG. 6, FIG. 16 shows a structural schematic diagram of another shift register unit. As shown in FIG. 16, the first clock end CKn and the fourth clock end CK can be shared, and the second clock end CB and the third clock end CBn can be shared. For example, the first clock end CKn and the fourth clock end CK can both be the fourth clock end CK, and the second clock end CB and the third clock end CBn can both be the second clock end CB.

[0212] That is, in an optional implementation, as shown in FIG. 16, each shift register unit can be connected to two clock ends (i.e., two groups of clock signals), CK and CB, which belongs to a 2CK design mode. Alternatively, in another optional implementation, as shown in FIGS. 4 to 15, each shift register unit can be connected to four clock ends (i.e., four groups of clock signals), CKn, CK, CBn and CB, which belongs to a 4CK design mode.

[0213] Optionally, the period of the four groups of clock signals can be 2H, the clock signal provided by the clock end CK and the clock signal provided by the clock end CB can be different by 1H, the clock signal provided by the clock end CKn and the clock signal provided by the clock end CB can be inverse signals, and the clock signal provided by the clock end CBn and the clock signal provided by the clock end CK can be inverse signals. In addition, the pulse width of the low potential 0 of the clock signal provided by the clock end CK and the clock signal provided by the clock end CB is generally smaller than 0 to 2 microseconds (μs) or so, and can be selected according to the load resistance RC, so as to eliminate the influence of clock delay, and avoid the input control circuit 01 and the latch circuit 03 from being simultaneously controlled to be conductive at the same time, thereby causing the risk of competition between different circuits during state switching.

[0214] Optionally, as can be further seen from FIGS. 4 to 15, the shift register unit can further include a driving enhancement circuit 04.

[0215] And the driving enhancement circuit 04 can be connected between the output control circuit 02 and the output signal terminal OUT_n, and can be used to output the potential of the output signal of the output control circuit 02 to the output signal terminal OUT_n after at least one inversion processing. In this way, the purpose of enhancing the driving capability of the shift register unit can be achieved.

[0216] Optionally, in some embodiments, continuing to refer to FIG. 16, the output signal terminal OUT_n can include: a first output terminal OUTN_n and a second output terminal OUTP_n, the first output terminal OUTN_n can be used to be connected with the N-type transistor in the pixel, and the second output terminal OUTP_n can be used to be connected with the P-type transistor in the pixel. For example, in combination with FIG. 2, the first output terminal OUTN_n can be connected with the gate signal terminal Gate_N, that is, can be connected with the N-type transistor T2; and the second output terminal OUTP_n can be connected with the gate signal terminal Gate_P, that is, can be connected with the P-type transistor T1. On this basis, the driving enhancement circuit 04 can include: a first driving enhancement sub-circuit 041 and a second driving enhancement sub-circuit 042.

[0217] The first driving enhancement sub-circuit 041 can be connected between the output control circuit 02 and the first output terminal OUTN_n, and can be used to output the potential of the output signal of the output control circuit 02 to the first output terminal OUTN_n after even times of inversion processing. That is, the potential of the first output terminal OUTN_n is the same as the potential of the output signal of the output control circuit 02.

[0218] The second driving enhancement sub-circuit 042 can be connected between the output control circuit 02 and the second output terminal OUTP_n, and can be used to output the potential of the output signal of the output control circuit 02 to the second output terminal OUTP_n after odd times of inversion processing. That is, the potential of the second output terminal OUTP_n is opposite to the potential of the output signal of the output control circuit 02.

[0219] Correspondingly, it can be understood that the output signal terminal OUT_n shown in FIGS. 4 to 15 can be the first output terminal OUTN_n or the second output terminal OUTP_n. In other words, the driving enhancement circuit 04 shown in FIGS. 4 to 15 can be the first driving enhancement sub-circuit 041 or the second driving enhancement sub-circuit 042.

[0220] Optionally, on the basis of FIG. 11, FIG. 17 shows another structure of a shift register unit provided by the embodiments of the present application. As shown in FIG. 17, the shift register unit can further include: a switch circuit 05.

[0221] And the switch circuit 05 can be connected between the enable control terminal GEN and the output control circuit 02, and can also be connected with the first control terminal Con1 and the second control terminal Con2 respectively, and can be used to control the connection between the enable control terminal GEN and the output control circuit 02 in response to the first control signal provided by the first control terminal Con1 and the second control signal provided by the second control terminal Con2. That is, in the embodiment of the present application, the output control circuit 02 and the enable control terminal GEN can be indirectly connected through the switch circuit 05.

[0222] For example, the switch circuit 05 can control the enable control terminal GEN and the output control circuit 02 to be connected when the potential of the first control signal is the first potential and the potential of the second control signal is the first potential, so that the enable control signal provided by the enable control terminal GEN is transmitted to the output control circuit 02. And the switch circuit 05 can control the enable control terminal GEN and the output control circuit 02 to be disconnected when the potential of the first control signal is the second potential or the potential of the second control signal is the second potential.

[0223] And in the case that neither the first output control sub-circuit 021 nor the second output control sub-circuit 022 is connected with the reset control terminal Trst, that is, on the basis of the structures shown in FIGS. 4 to 6, the first control terminal Con1 can be connected with the first intermediate node Q1_n-1 of the previous stage shift register unit in the cascade connection of the shift register units, and the second control terminal Con2 can be connected with the second intermediate node Q2_n-1 of the previous stage shift register unit. In the case that the second output control sub-circuit 022 of the first output control sub-circuit 021 and the second output control sub-circuit 022 is connected with the reset control terminal Trst, that is, on the basis of the structures shown in FIGS. 7 to 9, the first control terminal Con1 can be connected with the first intermediate node Q1_n-1 of the previous stage shift register unit in the cascade connection of the shift register units, and the second control terminal Con2 can be connected with the second intermediate node Q2_n-1 of the previous stage shift register unit. In the case that the first output control sub-circuit 021 of the first output control sub-circuit 021 and the second output control sub-circuit 022 is connected with the reset control terminal Trst, that is, on the basis of the structure shown in FIG. 10, the first control terminal Con1 can be connected with the first intermediate node Q1_n of the shift register unit, and the second control terminal Con2 can be connected with the second intermediate node Q2_n of the shift register unit.

[0224] Optionally, on the basis of the different embodiments described above, FIGS. 18 to 32 respectively show a plurality of circuit structure schematic diagrams of the shift register unit.

[0225] For the structures shown in FIGS. 4-10 and FIGS. 16 and 17, in the scenario that the output signal terminal OUT_n is connected to the gate signal terminal Gate and the gate driving signal is provided to the gate signal terminal Gate, for the nth shift register unit, the first output terminal OUTN_n can also be denoted as GN_n, the second output terminal OUTP_n can also be denoted as GP_n, the first intermediate node Q1_n can be denoted as GNc_n, and the second intermediate node Q2_n can be denoted as GPc_n. The first intermediate node Q1_n of the previous stage shift register unit can be denoted as GNc_n-1, and the second intermediate node Q2_n of the previous stage shift register unit can be denoted as GPc_n-1. In addition, the input signal terminal IN_n can be connected to the second intermediate node GPc_n-1 of the previous stage shift register unit in cascade, and of course the input signal terminal IN_n of the first stage shift register unit needs to be connected to the start signal terminal STV to receive the start signal from the start signal terminal STV. Therefore, it can also be known that GPc_n-1 and GNc_1 can be referred to as stage transmission nodes for transmitting signals. In addition, GN_n can also refer to a terminal connected to an N-type transistor in a pixel, and GP_n can also refer to a terminal connected to a P-type transistor in a pixel.

[0226] For the structures shown in FIGS. 11-15, in the scenario that the output signal terminal OUT_n is connected to the P-type transistor and the gate signal terminal Gate, for the nth shift register unit, the output signal terminal OUT_n can also be denoted as GP_n, the input signal terminal IN_n can also be denoted as GPc_n-1, the first intermediate node Q1_n can also be denoted as GNc_n, and the stage transmission node can also be denoted as GPc_n. In the scenario that the output signal terminal OUT_n is connected to the N-type transistor and the gate signal terminal Gate, for the nth shift register unit, the output signal terminal OUT_n can also be denoted as GN_n, the input signal terminal IN_n can also be denoted as GNc_n-1, the first intermediate node Q1_n can also be denoted as GPc_n, and the stage transmission node can also be denoted as GNc_n. That is, it can be understood that the input signal terminal IN_n of the nth shift register unit can be connected to the stage transmission node GPc_n-1 or GNc_n-1 in the previous stage shift register unit in cascade.

[0227] Optionally, referring to FIGS. 18-32, the latch circuit 03 can include a first inverter INV1 and a first transmission gate Tg1 connected in series between the first intermediate node Q1_n and the input node Q_n, and the first transmission gate Tg1 can be further connected to the third clock terminal CBn and the fourth clock terminal CK, respectively. That is, the input terminal of the first inverter INV1 can be connected to the first intermediate node Q1_n, the output terminal of the first inverter INV1 can be connected to one end of the first transmission gate Tg1, and the other end of the first transmission gate Tg1 can be connected to the input node Q_n. It can be understood that the inverter can also be referred to as an inverter, and the transmission gate can also be referred to as a transmission switch. For the structure shown in FIGS. 11-17, the stage transmission node can be the connection node of the first inverter INV1 and the first transmission gate Tg1.

[0228] Optionally, continuing to refer to FIGS. 18-32, the input control circuit 01 can include a second transmission gate Tg2 connected between the input signal terminal IN_n and the input node Q_n, and further connected to the first clock terminal CKn and the second clock terminal CB, respectively.

[0229] In the circuit structures shown in FIGS. 18-25 and 28-32, the first clock terminal CKn and the fourth clock terminal CK are shared, both being the fourth clock terminal CK; the second clock terminal CB and the third clock terminal CBn are shared, both being the second clock terminal CB. In the structures shown in FIGS. 26 and 27, the first clock terminal CKn, the second clock terminal CB, the third clock terminal CBn and the fourth clock terminal CK are independent of each other.

[0230] Optionally, continuing to refer to FIGS. 18-27, the circuit connected to the reset control terminal Trst or the enable control terminal GEN in the first output control sub-circuit 021 and the second output control sub-circuit 022 can include a NOR gate or a NAND gate, and the circuit not connected to the reset control terminal Trst and not connected to the enable control terminal GEN can include a second inverter INV2.

[0231] Optionally, referring to FIG. 27, in the case that the first output control sub-circuit 021 is connected to the reset control terminal Trst and the second output control sub-circuit 022 is not connected to the reset control terminal Trst, the first inverter INV1 included in the latch circuit 03 and the second inverter INV2 included in the second output control sub-circuit 022 can be shared. In this way, the structure can be simplified and the cost can be saved.

[0232] Optionally, as shown in FIGS. 28-32, the second output control sub-circuit 022 can include a third inverter INV3 connected between the first intermediate node Q1_n and the output signal terminal OUT_n. Based on this structure, the first output control sub-circuit 021 can include a NOR gate or a NAND gate.

[0233] It can be understood that the logic operation principle of the NOR gate is that all 0s output 1 and all 1s output 0; that is, when the potentials of all the received signals are low potentials 0, the potential of the output signal can be controlled to be a high potential 1; otherwise, as long as the potential of a received signal is a high potential 1, the potential of the output signal is controlled to be a low potential 0. The logic operation principle of the NAND gate is that all 1s output 0 and all 0s output 1; that is, when the potentials of all the received signals are high potentials 1, the potential of the output signal can be controlled to be a low potential 0; otherwise, as long as the potential of a received signal is a low potential 0, the potential of the output signal is controlled to be a high potential 1. Different gate circuits correspond to different control modes, and the above-mentioned embodiments are all described by taking the NOR gate as an example.

[0234] For example, as shown in FIG. 18, the first output control sub-circuit 021 includes a second inverter INV2-1, the second output control unit 0222 in the second output control sub-circuit 022 includes another second inverter INV2-2, the first output control unit 0221 includes a NOR gate, and the NOR gate is a two-input NOR gate. The input signal terminal of the second inverter INV2-1 is connected with the input node Q_n, and the output terminal of the second inverter INV2-1 is connected with the first intermediate node Q1_n. The two input terminals of the NOR gate are respectively connected with the first intermediate node Q1_n and the enable control terminal GEN, and the NOR gate is directly connected with the enable control terminal GEN. The output terminal of the NOR gate is connected with the second intermediate node Q2_n. The input terminal of the second inverter INV2-2 is connected with the second intermediate node Q2_n, the output terminal of the second inverter INV2-2 is indirectly connected with the first output terminal OUTN_n through the first drive enhancement circuit 041, and is indirectly connected with the second output terminal OUTP_n through the second drive enhancement circuit 042.

[0235] For example, referring to FIG. 19 and FIG. 20, it can be seen that the first output control sub-circuit 021 shown therein includes a second NOT gate INV2-1, the first output control unit 0221 in the second output control sub-circuit 022 includes another second NOT gate INV2-2, and the second output control unit 0222 includes a NOR gate. The difference is that the NOR gate in FIG. 14 is a two-input NOR gate, and the NOR gate in FIG. 15 is a three-input NOR gate. In this embodiment, the input signal end of the second NOT gate INV2-1 is connected with the input node Q_n, and the output end of the second NOT gate INV2-1 is connected with the first intermediate node Q1_n. The input end of the second NOT gate INV2-2 is connected with the first intermediate node Q1_n, and the output end of the second NOT gate INV2-2 is connected with the second intermediate node Q2_n. In FIG. 19, the two input ends of the NOR gate are respectively connected with the second intermediate node Q2_n and the enable control end GEN. In FIG. 20, the three input ends of the NOR gate are respectively connected with the second intermediate node Q2_n, the enable control end GEN and the reset control end Trst. In addition, the output end of the NOR gate in FIG. 19 and FIG. 20 is indirectly connected with the first output end OUTN_n through the first drive enhancement circuit 041, and is indirectly connected with the second output end OUTP_n through the second drive enhancement circuit 042.

[0236] For example, referring to FIG. 21, it can be seen that the first output control sub-circuit 021 shown therein includes a second NOT gate INV2-1, the first output control unit 0221 in the second output control sub-circuit 022 includes another second NOT gate INV2-2, and the second output control unit 0222 includes a NAND gate, which is a three-input NAND gate. In this embodiment, the input signal end of the second NOT gate INV2-1 is connected with the input node Q_n, and the output end of the second NOT gate INV2-1 is connected with the first intermediate node Q1_n. The input end of the second NOT gate INV2-2 is connected with the first intermediate node Q1_n, and the output end of the second NOT gate INV2-2 is connected with the second intermediate node Q2_n. The three input ends of the NAND gate are respectively connected with the second intermediate node Q2_n, the enable control end GEN and the reset control end Trst, and the NAND gate is indirectly connected with the enable control end GEN through the switch circuit 05. The output end of the NAND gate is indirectly connected with the first output end OUTN_n through the first drive enhancement circuit 041, and is indirectly connected with the second output end OUTP_n through the second drive enhancement circuit 042.

[0237] For example, referring to FIG. 22 and FIG. 23, it can be seen that the first output control sub-circuit 021 shown therein includes a second inverter INV2, the first output control unit 0221 in the second output control sub-circuit 022 includes a NOR gate, the second output control unit 0222 includes a NAND gate, and the NOR gate is a two-input NOR gate and the NAND gate is a two-input NAND gate. The input signal terminal of the second inverter INV2 is connected to the input node Q_n, and the output terminal of the second inverter INV2 is connected to the first intermediate node Q1_n. The two input terminals of the NOR gate are respectively connected to the first intermediate node Q1_n and the reset control terminal Trst, and the output terminal of the NOR gate is connected to the second intermediate node Q2_n. The two input terminals of the NAND gate are respectively connected to the second intermediate node Q2_n and the enable control terminal GEN, the output terminal of the NAND gate is indirectly connected to the first output terminal OUTN_n through the first drive enhancement circuit 041, and is indirectly connected to the second output terminal OUTP_n through the second drive enhancement circuit 042. The difference is that in FIG. 22, the NAND gate is directly connected to the enable control terminal GEN. In FIG. 23, the NAND gate is indirectly connected to the enable control terminal GEN through the switch circuit 05.

[0238] For example, referring to FIG. 24 and FIG. 25, it can be seen that the first output control sub-circuit 021 shown therein includes a second inverter INV2, the first output control unit 0221 in the second output control sub-circuit 022 includes a NAND gate, the second output control unit 0222 includes a NOR gate, and the NAND gate is a two-input NAND gate and the NOR gate is a two-input NOR gate. The input signal terminal of the second inverter INV2 is connected to the input node Q_n, and the output terminal of the second inverter INV2 is connected to the first intermediate node Q1_n. The two input terminals of the NAND gate are respectively connected to the first intermediate node Q1_n and the reset control terminal Trst, and the output terminal of the NAND gate is connected to the second intermediate node Q2_n. The two input terminals of the NOR gate are respectively connected to the second intermediate node Q2_n and the enable control terminal GEN, the output terminal of the NOR gate is indirectly connected to the first output terminal OUTN_n through the first drive enhancement circuit 041, and is indirectly connected to the second output terminal OUTP_n through the second drive enhancement circuit 042. The difference is that in FIG. 24, the NOR gate is directly connected to the enable control terminal GEN. In FIG. 25, the NOR gate is indirectly connected to the enable control terminal GEN through the switch circuit 05.

[0239] For example, referring to FIG. 26 and FIG. 27, it can be seen that the first output control sub-circuit 021 shown therein includes one NOR-1, the first output control unit 0221 in the second output control sub-circuit 022 includes one second inverter INV2, the second output control unit 0222 includes another NOR-2, and the NOR-1 is a two-input NOR-1, and the NOR-2 is also a two-input NOR-2. The two inputs of the NOR-1 are connected to the input node Q_n and the reset control terminal Trst, respectively, and the output of the NOR-1 is connected to the first intermediate node Q1_n. The input of the second inverter INV2 is connected to the first intermediate node Q1_n, and the output of the second inverter INV2 is connected to the second intermediate node Q2_n. The two inputs of the NOR-2 are connected to the second intermediate node Q2_n and the enable control terminal GEN, respectively. The difference lies in that, in FIG. 26, the output of the NOR-2 is connected to the first output terminal OUTN_n through the drive enhancement circuit 04. In FIG. 27, the output of the NOR-2 is connected to the second output terminal OUTP_n through the drive enhancement circuit 04. In addition, in FIG. 26, the second inverter INV2 and the first inverter INV1 are independent of each other. In FIG. 27, the second inverter INV2 and the first inverter INV1 are shared.

[0240] For example, referring to FIG. 28 to FIG. 30, it can be seen that the first output control sub-circuit 021 shown therein includes one NOR-1, and the second output control sub-circuit 022 includes one third inverter INV3. The NOR-1 is a two-input NOR-1. The two inputs of the NOR-1 are connected to the input node Q_n and the reset control terminal Trst, respectively, and the output of the NOR-1 is connected to the first intermediate node Q1_n. The input of the third inverter INV3 is connected to the first intermediate node Q1_n, and the output of the third inverter INV3 is connected to the output signal terminal OUT_n through the drive enhancement circuit 04.

[0241] For example, referring to FIG. 31 and FIG. 32, it can be seen that the first output control sub-circuit 021 shown therein includes one NAND-1, and the second output control sub-circuit 022 includes one third inverter INV3. The NAND-1 is a two-input NAND-1. The two inputs of the NAND-1 are connected to the input node Q_n and the reset control terminal Trst, respectively, and the output of the NAND-1 is connected to the first intermediate node Q1_n. The input of the third inverter INV3 is connected to the first intermediate node Q1_n, and the output of the third inverter INV3 is connected to the output signal terminal OUT_n through the drive enhancement circuit 04.

[0242] It can be understood that Fig. 28 shows a structural schematic diagram of the n-th stage shift register unit connected with P-type transistors. Fig. 29 shows a structural schematic diagram of the n-th stage and the n+1-th stage shift register units connected with P-type transistors, and the third inverter INV3 in the two-stage shift register unit of the cascade is connected with different enable control terminals GEN-1 and GEN-2. Fig. 30 shows a structural schematic diagram of the n-th stage and the n+1-th stage shift register units connected with P-type transistors, and each stage of the shift register unit includes two second output control sub-circuits 022 (i.e., includes two third inverters INV3), and the two second output control sub-circuits 022 are connected with different enable control terminals GEN1 and GEN2. Fig. 31 shows a structural schematic diagram of the n-th stage and the n+1-th stage shift register units connected with N-type transistors based on Fig. 29. Fig. 32 shows a structural schematic diagram of the n-th stage and the n+1-th stage shift register units connected with N-type transistors based on Fig. 30. Here, no longer introduced one by one.

[0243] Optionally, with continuous reference to Figs. 18 to 32, it can be seen that the driving enhancement circuit 04 can include at least one fourth inverter INV4 connected between the output control circuit 02 and the output signal terminal OUT_n, and in the case that the driving enhancement circuit 04 includes multiple fourth inverters INV4, the multiple fourth inverters INV4 can be connected in series between the output control circuit 02 and the output signal terminal OUT_n in turn. That is, the input terminal of the first fourth inverter INV4 can be connected with the output control circuit 02, the input terminal of the other fourth inverters INV4 can be connected with the output terminal of the previous fourth inverter INV4 in series, and the output terminal of the last fourth inverter INV4 is connected with the output signal terminal OUT_n.

[0244] For example, taking the structure shown in Figs. 16 and 17 as an example, with reference to Fig. 18, it can be seen that the first driving enhancement sub-circuit 041 connected with the first output terminal OUTN_n can include an even number of fourth inverters INV4 connected in series for performing even times of inverting processing on the potential of the output signal of the output control circuit 02 and then outputting to the first output terminal OUTN_n. And the second driving enhancement sub-circuit 042 connected with the second output terminal OUTP_n can include an odd number of fourth inverters INV4 connected in series for performing odd times of inverting processing on the potential of the output signal of the output control circuit 02 and then outputting to the second output terminal OUTP_n.

[0245] Optionally, in some embodiments, the even number of fourth inverters INV4 included in the first driving enhancement sub-circuit 041 and the odd number of fourth inverters INV4 included in the second driving enhancement sub-circuit 042 can share at least one fourth inverter INV4, so as to simplify the structure and save the cost.

[0246] For example, referring to FIG. 18, it can be seen that the first driving enhancement sub-circuit 041 each includes two fourth inverters INV4-1 and INV4-2, and the second driving enhancement sub-circuit 042 each includes three fourth inverters INV4-1, INV4-3 and INV4-4, that is, the first driving enhancement sub-circuit 041 and the second driving enhancement sub-circuit 042 share the fourth inverter INV4-1.

[0247] It can be understood that by setting the driving enhancement circuit 04 to include a plurality of fourth inverters INV4 connected in series, the driving capability of the output signal outputted from the output signal terminal OUT_n can be amplified step by step, and the driving capability can be better enhanced.

[0248] Optionally, referring to FIG. 19, it can be seen that the switch circuit 05 can include a third transmission gate Tg3, and the third transmission gate Tg3 can be connected between the enable control terminal GEN and the output control circuit 02, and can also be connected with the first control terminal Con1 and the second control terminal Con2 respectively.

[0249] Optionally, in combination with FIG. 27, on the basis of setting the pulse width of the low potential 0 of the clock signal provided by the clock terminal CK and the clock signal provided by the clock terminal CB to be smaller than 1H by about 0 to 2 μs, the risk of the first transmission gate Tg1 and the second transmission gate Tg2 being opened at the same time when the input state is switched, such as when the potential of the input signal provided by the input signal terminal IN_n changes, and the gate circuit (that is, the NOR-1) in the first output control sub-circuit 021 and the first inverter INV1 in the latch circuit 03 competing with each other can be avoided.

[0250] That is, the embodiment of the present application can provide the following various embodiments of the shift register unit:

[0251] In the embodiment 1, as shown in FIG. 18, the shift register unit can include two transmission gates (i.e., a first transmission gate Tg1 and a second transmission gate Tg2), one NOR gate, and seven inverters (i.e., a first inverter INV1, two second inverters INV2-1 and INV2-2, and four fourth inverters INV4-1, INV4-2, INV4-3, and INV4-4), which are totally ten gate circuits. Among them, the fourth inverters INV4-1 and INV4-2 belong to the first driving enhancement sub-circuit 041 and are connected to the first output end OUTN_n (GN_n); the fourth inverters INV4-1, INV4-3, and INV4-4 belong to the second driving enhancement sub-circuit 042 and are connected to the second output end OUTP_n (GP_n). That is, the output signal end OUT_n can include the first output end OUTN_n and the second output end OUTP_n, the shift register unit can output the required N-type gate driving signal to the NMOS TFT in the pixel circuit through the first output end OUTN_n, and can output the required P-type gate driving signal to the PMOS TFT in the pixel circuit through the second output signal end OUT_n OUTP_n. In other words, the shift register unit shown in FIG. 18 is suitable for the driving of PMOS+NMOS transistors.

[0252] The shift register unit can output a single-pulse gate driving signal. In normal output, the phase of the enable control signal provided by the enable control end GEN of the shift register unit connected to the odd-numbered row of pixels can be set to be the same as the phase of the clock signal provided by the clock end CK; the phase of the enable control signal provided by the enable control end GEN of the shift register unit connected to the even-numbered row of pixels can be set to be the same as the phase of the clock signal provided by the clock end CB. When the display panel is powered on or off or in the porch period, the potential of the enable control signal can be set to be a high potential 1, i.e., the potential of the enable control signal is set to be high H, so that the potential of the second intermediate node Q2_n (i.e., the potential of the stage transfer signal), the potential of the first output end OUTN_n, and the potential of the second output end OUTP_n controlled by the shift register unit are all invalid potentials, realizing output reset and stage transfer reset.

[0253] It can be understood that the setting of the enable control signal matching the clock signal provided by the clock ends CK and CB is an example with 2H as a period. In some other embodiments, in other period scenarios, the enable control signal can match the clock signal provided by more clock ends.

[0254] In the embodiment 2, referring to FIG. 19, the shift register unit can include three transmission gates (i.e., a first transmission gate Tg1, a second transmission gate Tg2, and a third transmission gate Tg3), a NOR gate, and seven inverters (i.e., a first inverter INV1, two second inverters INV2-1 and INV2-2, and four fourth inverters INV4-1, INV4-2, INV4-3, and INV4-4), totally 11 gate circuits. The difference from the embodiment 1 shown in FIG. 18 is that the third transmission gate Tg3 is added to control the connection between the enable control terminal GEN and the NOR gate under the control of a stage transfer signal provided by the shift register unit.

[0255] For example, the stage transfer signal can be a signal transmitted by the first intermediate node Q1_n-1 (i.e., GNc_n-1) and the second intermediate node Q2_n-1 (i.e., GPc_n-1) of the previous stage shift register unit. In this way, the enable control terminal GEN can be controlled to be turned on to the output control circuit 02 only when the potential of the node GNc_n-1 is high and the potential of the node GPc_n-1 is low, so that the enable control signal is transmitted to the output control circuit 02 to control the operation of the shift register unit. That is, the enable control signal provided by the enable control terminal GEN can be used to control the operation of the shift register unit with the potential of the node GNc_n-1 being high and the potential of the node GPc_n-1 being low, instead of controlling the operation of all shift register units. In this way, the load can be reduced, thereby reducing the operating power consumption of the shift register unit, and the impact on the voltage provided by the power supply terminal can be reduced, thereby improving the output stability of the shift register unit. Here, the power supply terminal can be a power supply terminal connected to the shift register unit to drive the shift register unit to operate normally.

[0256] In the embodiment 3, referring to FIG. 20, the shift register unit can include three transmission gates (i.e., a first transmission gate Tg1, a second transmission gate Tg2, and a third transmission gate Tg3), a NOR gate, and seven inverters (i.e., a first inverter INV1, two second inverters INV2-1 and INV2-2, and four fourth inverters INV4-1, INV4-2, INV4-3, and INV4-4), totally 11 gate circuits. The difference from the embodiment 2 shown in FIG. 19 is that the reset control terminal Trst is added, and the NOR gate is changed from the two-input NOR gate shown in FIG. 19 to a three-input NOR gate.

[0257] It can be understood that, based on the foregoing structure, the potential of the reset control signal provided by the reset control end Trst can be set to a high potential to control the potentials of the first output end OUTN_n and the second output end OUTP_n to be invalid potentials to realize output reset during the power-on or power-off or porch period of the display panel. Here, all the shift register units can perform global reset on the output signals. In this way, the reliability of power-on and power-off can be improved.

[0258] In embodiment 4, as shown in FIG. 21, the shift register unit can include three transmission gates (i.e., a first transmission gate Tg1, a second transmission gate Tg2, and a third transmission gate Tg3), one NAND gate, and seven NOT gates (i.e., a first NOT gate INV1, two second NOT gates INV2-1 and INV2-2, and four fourth NOT gates INV4-1, INV4-2, INV4-3, and INV4-4), a total of 11 gate circuits. The difference from embodiment 3 shown in FIG. 20 is that the three-input NOR gate is changed to a three-input NAND gate. Correspondingly, based on the logic operation principle of the NAND gate, the difference from embodiment 3 is that, during the power-on or power-off or porch period of the display panel, the potential of the reset control signal provided by the reset control end Trst can be set to a low potential to control the potentials of the first output end OUTN_n and the second output end OUTP_n to be invalid potentials to realize output reset, thereby improving the reliability of power-on and power-off.

[0259] In embodiment 5, as shown in FIG. 22, the shift register unit can include two transmission gates (i.e., a first transmission gate Tg1 and a second transmission gate Tg2), one NAND gate, one NOR gate, and six NOT gates (i.e., a first NOT gate INV1, a second NOT gate INV2, and four fourth NOT gates INV4-1, INV4-2, INV4-3, and INV4-4), a total of 10 gate circuits. The difference from embodiment 1 shown in FIG. 18 is that the second NOT gate INV2-2 is replaced by a two-input NAND gate, the NAND gate is connected with the enable control end GEN, and the reset control end Trst is connected with the NOR gate.

[0260] Based on the foregoing structure, the potential of the reset control signal provided by the reset control end Trst can be set to a high potential to reset all outputs during the power-on or power-off or porch period of the display panel, thereby improving the reliability of power-on and power-off. In addition, the enable control signal provided by the enable control end GEN can be flexibly set to realize local refresh.

[0261] Optionally, for the structure shown in Fig. 22, at local refresh, for the low brushing area, the potential of the enable control signal provided by the enable control terminal GEN can be set as low potential 0, so that the shift register unit only controls the potential of the first output terminal OUTN_n and the potential of the second output terminal OUTP_n to be invalid potential, and does not control the potential of the second intermediate node Q2_n to be invalid potential, that is, only output reset is realized, and the stage transfer signal is not reset, so that the shift register unit can pass the signal to the input signal terminal IN_n+1 of the next stage shift register unit, and maintain the ability to restart the output. For the high brushing area, the enable control signal provided by the enable control terminal GEN can be normally provided, for example, the enable control signal provided by the enable control terminal GEN of the shift register unit connected to the odd row pixels can be set to have the same phase as the clock signal provided by the clock terminal CK; the enable control signal provided by the enable control terminal GEN of the shift register unit connected to the even row pixels can be set to have the same phase as the clock signal provided by the clock terminal CB. That is, by flexibly setting the enable control signal provided by the enable control terminal GEN, local refresh can be realized, and only the shift register unit that has not completed the shift is reset. In this way, the display abnormality caused by the slow shift due to the frequency reduction can be avoided.

[0262] In embodiment 6, referring to Fig. 23, the shift register unit can include three transfer gates (i.e., a first transfer gate Tg1, a second transfer gate Tg2, and a third transfer gate Tg3), a NAND gate, a NOR gate, and six NOT gates (i.e., a first NOT gate INV1, a second NOT gate INV2, and four fourth NOT gates INV4-1, INV4-2, INV4-3, and INV4-4), a total of 11 gate circuits. The difference from embodiment 5 of Fig. 22 is that a third transfer gate Tg3 is added to control the on-off of the enable control terminal GEN and the NOR gate under the control of the stage transfer signal provided by the shift register unit.

[0263] It can be understood that, as in embodiment 2, the structure shown in Fig. 23 can also reduce the discharge load, thereby reducing the working power consumption of the shift register unit, and at the same time, can also reduce the impact on the voltage provided by the power supply terminal, and improve the output stability of the shift register unit.

[0264] In Embodiment 7, referring to FIG. 24, the shift register unit can include two transmission gates (i.e., a first transmission gate Tg1 and a second transmission gate Tg2), a NAND gate, a NOR gate, and six inverters (i.e., a first inverter INV1, a second inverter INV2, and four fourth inverters INV4-1, INV4-2, INV4-3, and INV4-4), totaling 10 gate circuits. The difference from Embodiment 5 of FIG. 22 is that the NOR gate and the NAND gate are exchanged. Accordingly, based on the logic operation principle of the NAND gate and the NOR gate, the difference from Embodiment 5 is that, during the power-on or power-off period or the porch period of the display panel, the potential of the reset control signal provided by the reset control terminal Trst can be set to a low potential to achieve global output reset and improve the power-on or power-off reliability. In addition, during local refresh, for the low refresh area, the potential of the enable control signal provided by the enable control terminal GEN can be set to a high potential to cause the shift register unit to only achieve output reset and not reset the stage transmission signal.

[0265] In Embodiment 8, referring to FIG. 25, the shift register unit can include three transmission gates (i.e., a first transmission gate Tg1, a second transmission gate Tg2, and a third transmission gate Tg3), a NAND gate, a NOR gate, and six inverters (i.e., a first inverter INV1, a second inverter INV2, and four fourth inverters INV4-1, INV4-2, INV4-3, and INV4-4), totaling 11 gate circuits. The difference from Embodiment 7 of FIG. 24 is that the third transmission gate Tg3 is added to control the enable control terminal GEN and the NOR gate under the control of the stage transmission signal provided by the shift register unit.

[0266] It can be understood that, as in Embodiment 2, the structure shown in FIG. 25 can also reduce the discharge load, thereby reducing the working power consumption of the shift register unit, and also reducing the impact on the voltage provided by the power supply terminal and improving the output stability of the shift register unit.

[0267] Embodiment 9, referring to Fig. 26, the shift register unit can include three transmission gates (i.e., a first transmission gate Tgl, a second transmission gate Tg2, and a third transmission gate Tg3), two NOR gates NOR-1 and NOR-2, and four inverters (i.e., a first inverter INV1, a second inverter INV2, and two fourth inverters INV4-1 and INV4-2) for a total of nine gate circuits. The difference from Embodiment 2 of Fig. 19 is that the second inverter INV2-1 is changed to a NOR gate NOR-1. Accordingly, as previously described, referring to Fig. 26, the first control terminal Conl can be connected to the first intermediate node Ql_n of the current stage shift register unit, and the second control terminal Con2 can be connected to the second intermediate node Q2_n of the current stage shift register unit. That is, the third transmission gate Tg3 can control the enablement of the control terminal GEN and the output control circuit 02 under the stage signal control of the current stage shift register unit. Of course, in some embodiments, for this embodiment, the first control terminal Conl can also be connected to the first intermediate node Ql_n-1 of the previous stage shift register unit in the cascade, and the second control terminal Con2 can also be connected to the second intermediate node Q2_n-1 of the previous stage shift register unit in the cascade. It is only necessary to synchronize the matching of the enablement control signal. In addition, in this embodiment, a 4-phase clock can be used to drive the shift register unit to work.

[0268] Embodiment 10, referring to Fig. 27, the shift register unit can include three transmission gates (i.e., a first transmission gate Tgl, a second transmission gate Tg2, and a third transmission gate Tg3), two NOR gates NOR-1 and NOR-2, and four inverters (i.e., a first inverter INV1 and three fourth inverters INV4-1, INV4-2, and INV4-3) for a total of nine gate circuits. The difference from Embodiment 9 of Fig. 26 is that the second inverter INV2 and the first inverter INV1 can be shared as the same inverter.

[0269] Embodiment 11, referring to FIG. 28, the shift register unit can include two transmission gates (i.e., a first transmission gate Tg1 and a second transmission gate Tg2), one NOR gate NOR-1, and four inverters (i.e., a first inverter INV1, a third inverter INV3, and two fourth inverters INV4-1, INV4-2, and INV4-3) in total 7 gate circuits. The start signal is the signal outputted by the stage pass node GPc_n-1 in the previous stage shift register unit in the cascade. The clock signals provided by the clock terminals CK and CB can be signals with opposite phases and a duty cycle of 50%. The reset control terminal Trst provides a reset control signal for resetting the high potential of the output signal at the output signal terminal OUT_n. The enable control terminal GEN is connected to the third inverter INV3 as a pull-down power terminal VGL for controlling the pulse width of the output signal. Of course, if it is a local brush driving, the enable control signal provided by the enable control terminal GEN in the low brush area can be high potential. In addition, it can also be understood that if there is no need for reset, the NOR gate NOR-1 can be replaced by an inverter, and the reset control terminal Trst can be omitted.

[0270] Embodiment 12, referring to FIG. 29, the structure of the two-stage shift register unit in the cascade is shown, and the structure of each stage of the shift register unit can be as shown in FIG. 28, and the third inverter INV3 in the two-stage shift register unit in the cascade is connected to different enable control terminals GEN. It belongs to the design mode of 2CK+2GEN.

[0271] Embodiment 13, referring to FIG. 30, the structure of the two-stage shift register unit in the cascade is shown, and each stage of the shift register unit can include two third inverters INV3, and two fourth inverters INV4-1 and INV4-2 connected to each third inverter INV3. That is, each stage of the shift register unit shown in FIG. 13 includes two transmission gates (i.e., a first transmission gate Tg1 and a second transmission gate Tg2), one NOR gate NOR-1, and seven inverters (i.e., a first inverter INV1, two third inverters INV3, and four fourth inverters INV4-1, INV4-2, and INV4-3) in total 10 gate circuits. In this way, each stage of the shift register unit can drive two different pixels (such as two adjacent rows of pixels), which is beneficial to reduce the area of the shift register unit, thereby facilitating the design of narrow frame. It belongs to the design mode of 2CK+4GEN.

[0272] Embodiment 14, referring to Fig. 31, shows a structure diagram of a shift register unit connected with N-type transistors based on the structure of Fig. 29 shown in Embodiment 12. The structure of each shift register unit is the same as shown in Fig. 29. Referring to Fig. 32, shows a structure diagram of a shift register unit connected with N-type transistors based on the structure of Fig. 30 shown in Embodiment 13. The structure of each shift register unit is the same as shown in Fig. 30. The difference is that the output signal and the stage transmission signal are N-type signals, or the NOR-1 is replaced by NAND-1, and the enable control end GEN is connected to the third inverter INV3 as the pull-up power end VGH, for controlling the width of the high level of the output signal. Of course, if it is a local brush driving, the enable control signal provided by the enable control end GEN in the low brush area can be low. In addition, it can also be understood that if there is no need for reset, the NAND-1 can also be replaced by an inverter, and the reset control end Trst can be omitted.

[0273] It can be understood that the above description of the embodiments is only illustrative, and any gate circuit combination that meets the above control mode can be applied to the embodiments of the present application. For example, the input signal end IN_n can also be connected to the first intermediate node Q1_n (i.e., GNc_n-1) of the previous stage shift register unit. For another example, in Figs. 22-25, the NOR can also be moved to the second inverter INV2.

[0274] Alternatively, in an implementation manner, the shift register unit provided by the embodiments of the present application can be the structure shown in Fig. 27. That is, the input control circuit 01 can include: a second transmission gate; the output control circuit 02 can include: a first output control sub-circuit 021 and a second output control sub-circuit 022, and the second output control sub-circuit 022 can include: a first output control unit 0221 and a second output control unit 0222, and the first output control sub-circuit 021 and the second output control unit 0222 can each include: a two-input NOR gate, and the two-input NOR gate included in the first output control sub-circuit 021 is denoted as NOR-1, and the two-input NOR gate included in the second output control unit 0222 is denoted as NOR-2, the first output control unit 0221 can include: a second inverter INV2; and the shift register unit can further include: a switching circuit 05, a latch circuit 03 and a driving enhancement circuit 04, and the switching circuit 05 can include: a third transmission gate Tg3, the latch circuit 03 can include: a first inverter INV1 and a first transmission gate Tg1, the driving enhancement circuit 04 can include: three fourth inverters INV4-1, INV4-2 and INV4-3; and the first inverter INV1 can be shared with the second inverter INV2.

[0275] The second transmission gate Tg2 is connected between the input signal end IN_n of the shift register unit and the input node Q_n, and is also connected with the first clock end CKn and the second clock end CB respectively.

[0276] In the first output control sub-circuit 021, two input ends of the two-input NOR gate NOR-1 are connected with the input node Q_n and the reset control end Trst respectively, and an output end of the two-input NOR gate NOR-1 is connected with the first intermediate node Q1_n.

[0277] An input end of the second inverter INV2 is connected with the first intermediate node Q1_n, and an output end of the second inverter INV2 is connected with the second intermediate node Q2_n.

[0278] In the second output control unit 0222, one input end of the two-input NOR gate NOR-2 is connected with the second intermediate node Q2_n, and the other input end of the two-input NOR gate NOR-2 is connected with the enable control end GEN through the third transmission gate Tg3, and an output end of the two-input NOR gate NOR-2 is connected with the output signal end OUT_n of the shift register unit through three fourth inverters INV4-1, INV4-2 and INV4-3, and the third transmission gate Tg3 is also connected with the first intermediate node Q1_n and the second intermediate node Q2_n respectively, and the three fourth inverters INV4-1, INV4-2 and INV4-3 are connected in series.

[0279] An input end of the first inverter INV1 is connected with the first intermediate node Q1_n, and an output end of the first inverter INV1 is connected with the input node Q_n through the first transmission gate Tg1, and the first transmission gate Tg1 is also connected with the third clock end CBn and the fourth clock end CK respectively.

[0280] Further, the output signal end OUT_n of the shift register unit can be used to connect with the P-type transistor in the pixel. That is, the output signal end OUT_n can be OUTP_n. For example, in combination with FIG. 2, the output signal end OUT_nP_n of the shift register unit can be connected with the gate signal end Gate_P of the P-type transistor T1.

[0281] Optionally, in another implementation manner, the shift register unit provided by the embodiment of the present application can be the structure shown in FIG. 28. That is, the output control circuit 02 can include a first output control sub-circuit 021 and a second output control sub-circuit 022. The shift register unit can further include a latch circuit 03 and a driving enhancement circuit 04. The input control circuit 01 can include a second transmission gate Tg2. The first output control sub-circuit 021 can include a NOR gate NOR-1. The second output control sub-circuit 022 can include a third inverter INV3. The latch circuit 03 can include a first inverter INV1 and a first transmission gate Tg1. The driving enhancement circuit 04 can include two fourth inverters INV4-1 and INV4-2 connected in series.

[0282] The first transmission gate Tg1 is connected between the input signal end IN_n and the input node Q_n, and is further connected to the first clock end CKn and the second clock end CB respectively.

[0283] The two input ends of the NOR gate NOR-1 are connected to the input node Q_n and the reset control end Trst respectively, and the output end of the NOR gate NOR-1 is connected to the first intermediate node Q1_n.

[0284] The input end of the third inverter INV3 is connected to the first intermediate node Q1_n, the output end of the third inverter INV3 is connected to the output signal end OUT_n through the two fourth inverters INV4 connected in series, and the third inverter INV3 is further connected to the first power supply end V1 and the enable control end GEN respectively. Each fourth inverter INV4 is further connected to the second power supply end V2 and the third power supply end V3 respectively.

[0285] The input end of the first inverter INV1 is connected to the first intermediate node Q1_n, the output end of the first inverter INV1 is connected to the input node Q_n through the first transmission gate Tg1, and the first transmission gate Tg1 is further connected to the third clock end CBn and the fourth clock end CK respectively.

[0286] Optionally, based on FIG. 25 and FIG. 27, FIG. 33 and FIG. 34 also respectively show a transistor TFT structure schematic diagram of a shift register unit. Based on FIG. 28, taking the P-type transistor in the pixel connected to the output signal end OUT_n as an example, FIG. 35, FIG. 37 and FIG. 38 respectively show another transistor TFT structure schematic diagram of a shift register unit. Based on FIG. 28, taking the N-type transistor in the pixel connected to the output signal end OUT_n as an example, FIG. 36 shows still another transistor TFT structure schematic diagram of a shift register unit. Based on FIG. 30, FIG. 39 shows yet another transistor TFT structure schematic diagram of a shift register unit. Taking the structure of FIG. 25 as an example, referring to FIG. 33, the circuit structure shown in FIG. 25 can include 10 PMOS TFTs and 10 NMOS TFTs, i.e. 20 TFTs, and the connection relationship can refer to FIG. 25, which will not be described herein. The circuit structures of other shift register units can be evolved from the above, and can be formed by deleting the basic modules, which will not be described herein.

[0287] As can be seen from FIG. 33 to FIG. 39, each fourth inverter INV4 can also be connected to the second power supply end V2 and the third power supply end V3, and can be used to work based on the power supply signal provided by the second power supply end V2 and the power supply signal provided by the third power supply end V3. The potential of the power supply signal provided by the second power supply end V2 can be greater than the power supply signal provided by the third power supply end V3. That is, the second power supply end V2 can be the pull-up power supply end as described above, and the third power supply end V3 can be the pull-down power supply end as described above.

[0288] In addition, among the plurality of fourth inverters INV4, the potential of the power supply signal provided by the second power supply end V2 connected to the last fourth inverter INV4 can be greater than or equal to the potential of the power supply signal provided by the second power supply end V2 connected to other fourth inverters INV4.

[0289] And / or the potential of the power supply signal provided by the third power supply end V3 connected to the last fourth inverter INV4 can be less than or equal to the potential of the power supply signal provided by the third power supply end V3 connected to other fourth inverters INV4.

[0290] Among them, the last fourth inverter INV4 is the fourth inverter INV4 directly connected to the output signal end OUT_n among the plurality of fourth inverters INV4.

[0291] For distinction, the second power supply end V2 connected to the last fourth inverter INV4 is marked as VGH2, and the second power supply end V2 connected to other fourth inverters INV4 is marked as VGH1. Similarly, the third power supply end V3 connected to the last fourth inverter INV4 is marked as VGL2, and the third power supply end V3 connected to other fourth inverters INV4 is marked as VGL1.

[0292] Optionally, in the case that the output control circuit 02 is also connected with the first power supply terminal V1 and the output signal terminal OUT_n is used to connect the P-type transistor in the pixel, the first power supply terminal V1 can be shared with the second power supply terminal V2; in the case that the output control circuit 02 is also connected with the first power supply terminal V1 and the output signal terminal OUT_n is used to connect the N-type transistor in the pixel, the first power supply terminal V1 can be shared with the third power supply terminal V3.

[0293] In addition, in the shift register unit, the power supply terminals of the gate circuits included in the other circuits except the output control circuit 01 and the driving enhancement circuit 04 can also be respectively connected with the pull-up power supply terminal and the pull-down power supply terminal, and are used to work based on the power supply signals respectively provided by the pull-up power supply terminal and the pull-down power supply terminal, and the potential of the power supply signal provided by the pull-up power supply terminal is greater than the potential of the power supply signal provided by the pull-down power supply terminal. Optionally, the pull-up power supply terminal here can be shared with the second power supply terminal V2, and / or the pull-down power supply terminal here can be shared with the third power supply terminal V3.

[0294] That is, for each shift register unit, in one embodiment, double VGH and double VGL power supply can be used. Alternatively, in another embodiment, single VGH and single VGL power supply can also be used, that is, any NOT gate in the shift register unit is connected with the same VGH and VGL.

[0295] For example, in the structure shown in FIG. 33, generally, the greater the channel width of the transistor, the closer the threshold voltage Vth of the transistor to 0. Thus, for the last fourth NOT gate INV4 directly connected with the output signal terminal OUT_n, such as the fourth NOT gate INV4-4 connected with the second output terminal OUTP_n, taking VGL2 as an example:

[0296] If the potential of the second output terminal OUTP_n needs to be controlled to be high, the PMOS TFT in the fourth inverter INV4-4 needs to be controlled to be turned on and the NMOS TFT needs to be controlled to be turned off, so that the VGH2 connected to the fourth inverter INV4-4 and the second output terminal OUTP_n are turned on, and a high potential power supply signal is output to the second output terminal OUTP_n. If the PMOS TFT in the fourth inverter INV4-4 needs to be turned on, the power supply terminal VGL1 connected to the fourth inverter INV4-4 needs to be controlled to be turned on to the fourth inverter INV4-4, so as to output a low potential power supply signal to the fourth inverter INV4-4. If the power supply terminal VGL1 connected to the fourth inverter INV4-4 needs to be controlled to be turned on, it can be known that the NMOS TFT in the fourth inverter INV4-3 needs to be controlled to be turned on and the PMOS TFT in the fourth inverter INV4-3 needs to be controlled to be turned off. Therefore, for the NMOS TFT in the fourth inverter INV4-4, the gate-source voltage difference Vgs should be equal to the difference between the potential Vgl1 of the power supply signal provided by the power supply terminal VGL1 and the potential Vgl2 of the power supply signal provided by the power supply terminal VGL2. That is, Vgs = Vgl1-Vgl2. Moreover, if the NMOS TFT in the fourth inverter INV4-4 needs to be reliably turned off, the gate-source voltage difference Vgs of the NMOS TFT needs to be controlled to be less than the threshold voltage Vth, that is, Vgs < Vth needs to be met. Since Vgs = Vgl1-Vgl2, it can be known that Vgl1-Vgl2 < Vth needs to be met. Based on this, when dual-VGL power supply is adopted, Vgl1-Vgl2 < Vth can be met by adjusting the potential Vgl2 of the power supply signal provided by the power supply terminal VGL2 to be lower or adjusting the potential Vgl1 of the power supply signal provided by the power supply terminal VGL1 to be higher, so as to ensure that the NMOS TFT in the fourth inverter INV4-4 can be completely turned off, and the shift register unit can reliably control the potential of the second output terminal OUTP_n to be high. That is, the absolute value of the potential Vgl2 of the power supply signal provided by the power supply terminal VGL2 can be set to be smaller than the absolute value of the potential Vgl1 of the power supply signal provided by the power supply terminal VGL1. For example, the potential of the power supply signal Vgl2 provided by the power supply terminal VGL2 can be -5V, and the potential of the power supply signal Vgl1 provided by the power supply terminal VGL1 can be -7V.

[0297] The same applies to the VGH. For example, still taking the fourth inverter INV4-4 connected to the second output terminal OUTP_n in FIG. 33 as an example, when dual-VGL power supply is adopted, the potential Vgh1 of the power supply signal provided by the power supply terminal VGH1 can be lowered, or the potential Vgh2 of the power supply signal provided by the power supply terminal VGH2 can be raised, so that Vgh1-Vgh2Vth, and thus the PMOS TFT in the fourth inverter INV4-4 can be completely turned off, only the NMOS TFT is turned on, so that the power supply terminal VGL2 and the second output terminal OUTP_n are turned on, and a low-potential power supply signal is output to the second output terminal OUTP_n. That is, the shift register unit can reliably control the potential of the second output terminal OUTP_n to be low.

[0298] In addition, by adopting dual-VGH and dual-VGL power supply, the charging and discharging speed of the fourth inverter INV4 directly connected to the output terminal OUT_n can be accelerated, thereby further improving the driving capability of the shift register unit, and reducing the leakage current and saving power consumption.

[0299] Of course, in some other embodiments, it is not limited to dual-VGH and dual-VGL power supply. For example, still referring to FIG. 33, the fourth inverter INV4-2 connected to the first output terminal OUTN_n can also be connected to the power supply terminal VGH3 and the power supply terminal VGL3 respectively, that is, triple-VGH and triple-VGL power supply can be adopted.

[0300] In addition, the potential of the power supply signal provided by the power supply terminal VGH3 can be the same as the potential of the power supply signal provided by the power supply terminal VGH2 or the power supply terminal VGH1; or the potential of the power supply signal provided by the power supply terminal VGH3 can be different from the potential of the power supply signal provided by the power supply terminal VGH2 and the power supply terminal VGH1, that is, the power supply terminals VGH3, VGH2 and VGH1 can be independent of each other. The same applies to the power supply terminal VGL3, that is, the potential of the power supply signal provided by the power supply terminal VGL3 can be the same as the potential of the power supply signal provided by the power supply terminal VGL2 or the power supply terminal VGL1; or the potential of the power supply signal provided by the power supply terminal VGL3 can be different from the potential of the power supply signal provided by the power supply terminal VGL2 and the power supply terminal VGL1, that is, the power supply terminals VGL3, VGL2 and VGL1 can be independent of each other.

[0301] It can also be understood that, by comparing Figure 35 and Figure 36, it can be further seen that, in the scenario of connecting the P-type transistor in the pixel to the output signal end OUT_n, the enable control end GEN can serve as the pull-down power end VGL; in the scenario of connecting the N-type transistor in the pixel to the output signal end OUT_n, the enable control end GEN can serve as the pull-up power end VGH. Moreover, the structures shown in Figure 35 and Figure 36 are both connected to 2 clock ends CK and CB, and are both connected to 1 power end VGH1 and 1 power end VGL1. Figure 35 and Figure 36 both belong to the design of 2CK+2GEN+VGH / VGL. By comparing Figure 35 and Figure 37, it can be seen that the structure shown in Figure 35 is connected to 1 power end VGH1 and 1 power end VGL1. The structure shown in Figure 37 is connected to 2 power ends VGH1 and VGH2, and 2 power ends VGL2 and VGL2. Figure 37 belongs to the design of 2CK+2GEN+2VGH / VGL. By comparing Figure 37 and Figure 38, it can be seen that the structure shown in Figure 37 is connected to 2 clock ends CK and CB, while the structure shown in Figure 38 is connected to 4 clock ends CKn, CB, CBn and CK. Figure 38 belongs to the design of 4CK+2GEN+2VGH / VGL. By comparing Figure 39 and Figure 38, it can be seen that the structure shown in Figure 37 includes 1 third inverter INV3 and 2 fourth inverters INV4, while the structure shown in Figure 39 includes 2 third inverters INV3 and 4 fourth inverters INV4. Figure 39 belongs to the design of 4CK+4GEN+2VGH / VGL. Of course, here only some circuit structures are shown schematically, and for the scenario of connecting the N-type transistor, the above different circuit structures can be obtained by corresponding combination, which will not be elaborated one by one.

[0302] Optionally, on the basis of the foregoing, it can be known that, in some embodiments, in combination with Figure 40, it can be seen that the shift register unit provided by the embodiments of the present application can actually be divided into three modules: an input shift module, a transmission and control module, and a driving enhancement module.

[0303] For example, taking the structure shown in Figure 4 as an example, the input shift module can refer to a module composed of a circuit for controlling the potential of the first intermediate node Q1_n based on the input signal provided by the input signal end IN_n; the transmission and control module can refer to a module composed of a circuit for controlling the potential received by one end of the driving enhancement circuit 04 based on the potential of the first intermediate node Q1_n; and the driving enhancement module can refer to the driving enhancement circuit 04. Moreover, the shift register unit can be connected to at least the following multiple signal ends: VGH, VGL, CK, CB, Trst, GEN, GPc_n-1, OUTN_n (i.e., GN_n), OUTP_n (i.e., GP_n), and GPc_n. The connection mode is referred to Figure 40, which will not be elaborated here.

[0304] Optionally, based on the foregoing, it can be known that in some embodiments, as shown in FIG. 41, the shift register unit provided by the embodiments of the present application can actually be divided into three modules: a shift control module, an output pulse width control module, and an output driving module.

[0305] For example, in the structure shown in FIG. 11, the shift control module can refer to a module including the input control circuit 01, the first output control sub-circuit 02, and the latch circuit 03, the output pulse width control module can refer to a module including the second output control sub-circuit 022, and the output driving module can refer to a module including the driving enhancement circuit 04. In addition, the shift register unit can be connected to at least the following signal terminals: IN_n / STV, clock (for example, CK and CB), power supply 1 (for example, VGH1), GEN, power supply 2 (for example, VGH2 and VGL2), and OUT_n. The connection mode is described with reference to FIG. 41, which will not be described here again. The power supply 1 and the power supply 2 can use the same or different power supplies.

[0306] In summary, the embodiments of the present application provide a shift register unit. The shift register unit includes an input control circuit and an output control circuit. The input control circuit can control the on-off of the input signal terminal and the input node under the control of the clock signal provided by the first clock terminal and the clock signal provided by the second clock terminal. The output control circuit can output a gate driving signal to a pixel through an output terminal based on the potential of the input node and the enable control signal provided by the enable control terminal to drive the pixel to emit light. In this way, the clock signal and the enable control signal can be flexibly set, so that the shift register unit outputs a gate driving signal matching the P-type transistor and / or the N-type transistor in the pixel to the output terminal, and the shift register unit can be selectively controlled to output or not to output at different time periods, to locally refresh the pixel and reliably reset the gate driving signal, to ensure good driving flexibility and rich driving modes.

[0307] The embodiments of the present application also provide a driving method of a shift register unit. The method can be used to drive the shift register unit as described above. As shown in FIG. 42, the method includes the following steps.

[0308] In step 4201, in response to a first scan instruction, a first clock signal is provided to a first clock terminal, a second clock signal is provided to a second clock terminal, and an enable control signal same as the first clock signal or the second clock signal is provided to an enable control terminal, and the potentials of the first clock signal and the second clock signal in the same time period are opposite.

[0309] In step 4202, in response to a second scan instruction, a first clock signal is provided to a first clock terminal, a second clock signal is provided to a second clock terminal, and an enable control signal with a constant potential is provided to an enable control terminal.

[0310] The first clock signal and the second clock signal are used to drive the input control circuit to control the on-off of the input signal end and the first intermediate node, and control the potential of the first intermediate node based on the input signal provided by the input signal end; the enable control signal is used to drive the output control circuit to control the potential of the output end based on the potential of the first intermediate node and the enable control signal, so as to output the gate drive signal to the data writing transistor in the pixel through the output end, and drive the pixel to emit light; and the refresh frequency indicated by the first scan instruction is greater than the refresh frequency indicated by the second scan instruction. That is, the refresh area indicated by the first scan instruction can be a high refresh area, and the refresh area indicated by the second scan instruction can be a low refresh area. That is, for the low refresh area, the enable control signal with a high potential or a low potential can be provided to realize output reset.

[0311] Optionally, taking the structure shown in FIGS. 18 to 25 as an example, FIG. 43 shows a driving timing diagram of a shift register unit. In addition, based on the structure shown in FIG. 27, FIG. 44 schematically shows a signal simulation diagram of a shift register unit. Wherein, FIG. 43 shows the signal timing of the signal ends CK, CB, GEN, GPc_n-1, GPc_n, GP_n and GN_n, and the timing relationship is shown in FIG. 43, which is not introduced one by one here. FIG. 44 shows the signal timing of the signal ends CK, CBn, CB, CKn, Trst, GEN, GPc_n-1, GPc_n, GNc_n and GP_n, and the timing relationship is shown in FIG. 44, which is not introduced one by one here.

[0312] GEN includes GEN1 and GEN2, GEN1 can refer to the enable control end connected to the shift register unit connected to the odd row pixels, and GEN2 can refer to the enable control end connected to the shift register unit connected to the even row pixels. The signal provided by GPc_n-1 is the input signal received by the input signal end IN_n of the nth stage shift register unit, and the low potential pulse width in the signal provided by GPc_n-1 can be an integer multiple of the clock signal period provided by the clock end CK, thereby ensuring complete output of the display driving signal, and a non-integer multiple will generally be reduced to an integer multiple of the pulse width. The pulse width and phase of the input signal received by the input signal end IN_n of the first stage shift register unit can correspond to the low potential of the clock signal provided by the clock end CB, and of course it can also be multiple periods, and the shift register unit can output multiple pulses accordingly. In addition, as described above, for the NOR gate example, the potential of the reset control signal can be set high during power-on or power-off (or during the porch period), which is used for global reset and improves the on-off reliability, that is, the power-on and power-off reliability; the potential of the reset control signal can be set low at other times. It can be understood that the driving timing of other structures can be derived from Figure 44, and will not be described here.

[0313] Optionally, taking the circuit structure shown in Figures 18 to 20 and 24 to 25, that is, the NOR gate connected to the enable control end GEN, as an example, Figure 45 shows a local brush driving timing diagram of a shift register unit. Taking the circuit structure shown in Figures 21 to 23, that is, the NAND gate connected to the enable control end GEN, as an example, Figure 46 shows another local brush driving timing diagram of a shift register unit. Moreover, Figures 45 and 46 each schematically show two low brush areas 1 and 2, and one high brush area.

[0314] As can be seen from FIGS. 45 and 46, on the basis of setting the NOR gate connected with the enable control terminal GEN, in combination with the simulation diagram shown in FIG. 44, in the low brush area, the enable control signal provided by setting the enable control terminal GEN high, i.e. controlling the potential of the enable control signal to be high, can be used to realize output reset. In the low brush area, on the basis of setting the NAND gate connected with the enable control terminal GEN, the enable control signal provided by setting the enable control terminals GEN1 and GEN2 low, i.e. controlling the potential of the enable control signal to be low, can be used to realize output reset. In addition, as can be seen from the simulation diagram shown in FIG. 44, and FIGS. 45 and 46, in the high brush area, the phase of the enable control signal provided by the enable control terminal GEN1 connected with the shift register unit of the odd row pixel can be set to be the same as the phase of the clock signal provided by the clock terminal CK; the phase of the enable control signal provided by the enable control terminal GEN2 connected with the shift register unit of the even row pixel can be set to be the same as the phase of the clock signal provided by the clock terminal CB. Of course, the enable control signal provided by the enable control terminal GEN1 and the enable control signal provided by the enable control terminal GEN2 can also be interchanged. That is, the phase of the enable control signal provided by the enable control terminal GEN1 connected with the shift register unit of the odd row pixel can be set to be the same as the phase of the clock signal provided by the clock terminal CB; the phase of the enable control signal provided by the enable control terminal GEN2 connected with the shift register unit of the even row pixel can be set to be the same as the phase of the clock signal provided by the clock terminal CK.

[0315] Optionally, taking the circuit structure shown in FIGS. 26 and 27 as an example, FIG. 47 shows another local brush driving timing diagram of a shift register unit, including timing of A. high brush area and B. low brush area. As can be seen from FIG. 47, it shows 4 groups of clock signals, each of which can meet the description recorded in the foregoing, which will not be repeated here. As can be seen from FIG. 47, in the display panel power-on or power-off or in the porch period, the reset control signal provided by setting the reset control terminal Trst high, i.e. controlling the potential of the reset control signal to be high, can be used to realize output reset. In A. high brush area, it can be set as in FIGS. 45 and 46; in B. low brush area, the enable control signal provided by setting the enable control terminal GEN high, i.e. controlling the potential of the enable control signal to be high, can be used to realize output reset.

[0316] Taking the structure shown in FIG. 34 as an example, continuing to refer to FIG. 47, the driving principle of the shift register unit is described as follows:

[0317] Firstly, in the first stage t01, a high potential first clock signal can be provided to the first clock end CKn, and a low potential second clock signal can be provided to the second clock end CB, so that the second transmission gate Tg2 is opened. Then the input signal end IN_n and the input node Q_n are conducted, and the input signal end IN_n (i.e., GPc_n-1) can output an input signal to the input node Q_n, and the potential of the output input signal can be high potential. In addition, a high potential reset control signal can be provided to the reset control end Trst, and then the potential of the node GNc_n can be controlled to be low potential after the NOR-1, and the potential of the node GPc_n can be controlled to be high potential after the second inverter INV2. Because the potential of the node GNc_n is low potential and the potential of the node GPc_n is high potential, the third transmission gate Tg3 can be turned off, and the NOR-2 can output a low potential signal, and the low potential signal can make the potential of the output end GP_n high potential after passing through an odd number of fourth inverters INV4. In addition, in the first stage t01, a low potential third clock signal can be provided to the third clock end CBn, and a high potential fourth clock signal can be provided to the fourth clock end CK, so that the first transmission gate Tg1 is turned off, and then the node GPc_n and the input node Q_n are disconnected.

[0318] It can be understood that, as shown in FIG. 47, the pulse width of the low potential of the clock signal provided by the clock end CK and the clock signal provided by the clock end CB is less than the pulse width of the high potential, generally about 0 to 2 μs less than 1H, which can be flexibly selected according to the load RC. On the basis of the setting, as recorded in the foregoing, the influence of clock delay can be eliminated, and the risk of competition between the NOR-1 in the first output control sub-circuit 021 and the first inverter INV1 in the latch circuit 03 caused by the simultaneous opening of the first transmission gate Tg1 and the second transmission gate Tg2 when the input state is switched can be avoided.

[0319] Secondly, in the second stage t02, the first clock signal with low potential can be provided to the first clock terminal CKn, and the second clock signal with high potential can be provided to the second clock terminal CB, so that the second transmission gate Tg2 is turned off, and then the input signal terminal IN_n is disconnected from the input node Q_n. The third clock signal with high potential can be provided to the third clock terminal CBn, and the fourth clock signal with low potential can be provided to the fourth clock terminal CK, so that the first transmission gate Tg1 is turned on, and then the node GPc_n is connected to the input node Q_n, so that the potential of the input node Q_n is latched as the high potential of the node GPc_n. In addition, the reset control signal with low potential can be provided to the reset control terminal Trst, so that the potential of the node GNc_n is controlled as low potential after the NOR-1, and then the potential of the node GPc_n is controlled as high potential after the second inverter INV2. Since the potential of the node GNc_n is low, and the potential of the node GPc_n is high, the third transmission gate Tg3 is turned off, and the NOR-2 outputs a signal with low potential, which is outputted to the output terminal GP_n after passing through an odd number of fourth inverters INV4.

[0320] In the third stage t03, the first clock signal with high potential can be provided to the first clock terminal CKn, and the second clock signal with low potential can be provided to the second clock terminal CB, so that the second transmission gate Tg2 is turned on, and then the input signal terminal IN_n is connected to the input node Q_n, and the input signal terminal IN_n can output the input signal to the input node Q_n, and the potential of the input signal can be low. In addition, the reset control signal with low potential can be provided to the reset control terminal Trst, and then the potential of the node GNc_n is controlled as high potential after the NOR-1, and then the potential of the node GPc_n is controlled as low potential after the second inverter INV2. Since the potential of the node GNc_n is high, and the potential of the node GPc_n is low, the third transmission gate Tg3 is turned on, and the enable control signal provided by the enable control terminal GEN is transmitted to the NOR-2. At this time, the potential of the enable control signal can be high. Thus, the NOR-2 outputs a signal with low potential, which is outputted to the output terminal GP_n after passing through an odd number of fourth inverters INV4. In addition, in the third stage t03, the third clock signal with low potential can be provided to the third clock terminal CBn, and the fourth clock signal with high potential can be provided to the fourth clock terminal CK, so that the first transmission gate Tg1 is turned off, and then the node GPc_n is disconnected from the input node Q_n.

[0321] In the fourth stage t04, the first clock signal with low potential can be provided to the first clock terminal CKn, and the second clock signal with high potential can be provided to the second clock terminal CB, so that the second transmission gate Tg2 is turned off, and the input signal terminal IN_n is disconnected from the input node Q_n. The third clock signal with high potential can be provided to the third clock terminal CBn, and the fourth clock signal with low potential can be provided to the fourth clock terminal CK, so that the first transmission gate Tg1 is turned on, and the node GPc_n is connected to the input node Q_n, thereby latching the potential of the input node Q_n as the low potential of the node GPc_n. In addition, the reset control signal with low potential can be provided to the reset control terminal Trst, so that the potential of the node GNc_n is controlled as high potential after the NOR-1, and the potential of the node GPc_n is controlled as low potential after the second inverter INV2. Since the potential of the node GNc_n is high and the potential of the node GPc_n is low, the third transmission gate Tg3 is turned on, so that the enable control signal provided by the enable control terminal GEN is transmitted to the NOR-2. At this time, the potential of the enable control signal can be low. Thus, the high potential signal can be output after the NOR-2, and the low potential can be output at the output terminal GP_n after the odd number of fourth inverters INV4.

[0322] The working principles of other stages are not repeated here in detail in combination with the timing shown in FIG. 47. Alternatively, the shift register unit can also be connected with a display driver IC (DIC), and be used to receive the signals such as clock signals provided by the DIC. That is, the DIC can provide the required signals to each signal terminal of the shift register unit, so that the shift register unit outputs the required display driving signals to the pixels.

[0323] Alternatively, in the structure shown in FIGS. 28 and 29, and as an example of distinguishing the high brush area and the low brush area as shown in FIG. 13, that is, as an example of 2CK+2GEN design, FIG. 48 shows another driving timing diagram of a shift register unit, which includes the timing of the clock signals provided by a group of clock terminals CK and CB, the timing of the input signal (also referred to as the start signal) provided by the input signal terminal GPc_n-1, the timing of the stage transmission signal provided by the stage transmission node GPc_n, the timing of the signal output by the output signal terminal GP_n, the timing of the enable control signals provided by the enable control terminals GEN-1 and GEN-2, and the timing of the reset control signal provided by the reset control terminal Trst. The timing relationship is shown in FIG. 48. Two clock signals are used, and the phase relationship is shown in the figure, with a period of 4H, in which CK and CB are different by 2H (2 rows of periods, which can be adjusted according to the number of GOA groups), and the duty cycle is 50%.

[0324] As can be seen in combination with FIG. 48, first, in the A. high brush area, the pixel can be normally charged, which is divided into the following four stages:

[0325] In the first stage t01, the potential of the clock signal provided by the clock terminal CK is a low potential, the potential of the clock signal provided by the clock terminal CB is a high potential, the potential of the input signal provided by the input signal terminal GPc_n-1 is a low potential, and the potential of the reset control signal provided by the reset control terminal Trst is a low potential. In this way, the first transfer gate Tg1 can be opened, and the second transfer gate Tg2 can be turned off. Further, the input signal terminal GPc_n-1 can be disconnected from the input node Q_n, and the stage transfer node GPc_n can be connected to the input node Q_n. The potential of the first intermediate node Q1_n (i.e., GNc_n) can remain at the low potential of the previous stage. After the first inverter INV1, the potential of the stage transfer node GPc_n can remain at the high potential of the previous stage. After the opened first transfer gate Tg1, the potential of the control input node Q_n can also remain at the high potential of the previous stage. Therefore, in combination with FIG. 35, in the first stage t01, the P-type transistor in the third inverter INV3 can be turned on, the N-type transistor can be turned off, the power supply terminal VGH1 can be connected to the drive enhancement circuit 04, and the enable control terminal GEN-1 can be disconnected from the drive enhancement circuit 04. Further, the high potential power supply signal provided by the power supply terminal VGH1 can be transmitted to the drive enhancement circuit 04. Then, after the two fourth inverters INV4-1 and INV4-2 in the drive enhancement circuit 04, the high potential gate drive signal can be output through the output signal terminal GP_n. Accordingly, the first stage t01 can also be referred to as the start-up stage.

[0326] In the second stage t02, the potential of the clock signal provided by the clock terminal CK becomes high, the potential of the clock signal provided by the clock terminal CB becomes low, the potential of the input signal provided by the input signal terminal GPc_n-1 is low, and the potential of the reset control signal provided by the reset control terminal Trst is low. In this way, the first transmission gate Tg1 is turned off, and the second transmission gate Tg2 is turned on. Then, the input signal terminal GPc_n-1 is connected to the input node Q_n, and the stage transmission node GPc_n is disconnected from the input node Q_n. At this time, the low potential input signal can be transmitted to the input node Q_n, and the potential of the input node Q_n is controlled to be low. Because the potential of the reset control signal is low, the first intermediate node Q1_n (i.e., GNc_n) can be controlled to be high by the NOR gate NOR-1. After the first inverter INV1, the potential of the stage transmission node GPc_n becomes low. Therefore, in the second stage t02, the P-type transistor in the third inverter INV3 can be turned off, the N-type transistor can be turned on, the power terminal VGH1 can be disconnected from the driving enhancement circuit 04, and the enable control terminal GEN-1 can be connected to the driving enhancement circuit 04. Then, the enable control signal provided by the enable control terminal GEN-1 can be transmitted to the driving enhancement circuit 04. Because the potential of the enable control signal provided by the enable control terminal GEN-1 is high in the second stage t02, it can be known that the high potential gate drive signal can still be output through the output signal terminal GP_n after the two fourth inverters INV4-1 and INV4-2 in the driving enhancement circuit 04. Correspondingly, the second stage t02 can also be called a shift output stage.

[0327] In the third stage t03, the potential of the clock signal provided by the clock terminal CK becomes low, the potential of the clock signal provided by the clock terminal CB becomes high, the potential of the input signal provided by the input signal terminal GPc_n-1 becomes high, and the potential of the reset control signal provided by the reset control terminal Trst is low. In this way, the first transmission gate Tg1 is turned on, and the second transmission gate Tg2 is turned off. Then, the input signal terminal GPc_n-1 is disconnected from the input node Q_n, and the stage transfer node GPc_n is connected to the input node Q_n. The potential of the first intermediate node Q1_n (i.e., GNc_n) can remain high as in the previous stage (i.e., the second stage t02). After the first inverter INV1, the potential of the stage transfer node GPc_n remains low as in the previous stage. After the first transmission gate Tg1 is turned on, the potential of the control input node Q_n also remains low as in the previous stage. Therefore, in the third stage t03, the P-type transistor in the third inverter INV3 is turned off, the N-type transistor is turned on, the power terminal VGH1 is disconnected from the driving enhancement circuit 04, and the enable control terminal GEN-1 is still connected to the driving enhancement circuit 04. Then, the enable control signal provided by the enable control terminal GEN-1 is transmitted to the driving enhancement circuit 04. Since the potential of the enable control signal provided by the enable control terminal GEN-1 becomes low in the third stage t04, it can be known that after the two fourth inverters INV4-1 and INV4-2 in the driving enhancement circuit 04, a low potential gate drive signal can be output through the output signal terminal GP_n. Moreover, the low potential pulse width of the gate drive signal can be determined by the low potential pulse width of the enable control signal provided by the enable control terminal GEN-1, for example, the low potential pulse width of the gate drive signal can be consistent with the low potential pulse width of the enable control signal provided by the enable control terminal GEN-1. Accordingly, the third stage t03 can also be referred to as the output stage.

[0328] In the fourth stage t04, the potential of the clock signal provided by the clock terminal CK becomes high again, the potential of the clock signal provided by the clock terminal CB becomes low again, the potential of the input signal provided by the input signal terminal GPc_n-1 is high, and the potential of the reset control signal provided by the reset control terminal Trst is low. In this way, the first transfer gate Tg1 is turned off, and the second transfer gate Tg2 is turned on. Then, the input signal terminal GPc_n-1 is connected to the input node Q_n, and the stage transfer node GPc_n is disconnected from the input node Q_n. At this time, the high input signal can be transmitted to the input node Q_n, and the potential of the input node Q_n is high. Because the potential of the reset control signal is low, the first intermediate node Q1_n (i.e., GNc_n) can be controlled by the NOR gate NOR-1 to be low. After the first inverter INV1, the potential of the stage transfer node GPc_n becomes high, and the node is reset. Correspondingly, the fourth stage t04 can also be called the reset stage.

[0329] Secondly, in the B. low brush area, compared with the A. high brush area, the difference is that the enable control signals provided by the enable control terminals GEN-1 and GEN-2 can all be kept high. In this way, the potential of the first intermediate node Q1_n is high or high, that is, in combination with FIG. 35, whether the P-type transistor or the N-type transistor in the third inverter INV3 is turned on, the high signal can be output to the driving enhancement circuit 04 through the third inverter INV3. In this way, after passing through the two fourth inverters INV4-1 and INV4-2 in the driving enhancement circuit 04, the high gate drive signal can always be output through the output signal terminal GP_n, so as to realize the purpose of not refreshing the pixels in the low brush area, and realize the local brush display, that is, the local refresh display. In addition, in the low brush area, the potential of the stage transfer node GPc_n can be normally controlled to be high or low, and the normal stage transfer is realized.

[0330] In addition, it can also be seen from FIG. 48 that before the first stage t01, the reset control end Trst can provide a high potential reset control signal, so that the potential of the first intermediate node Q1_n (i.e., GNc_n) controlled by the NOR gate NOR-1 is low, and the potential of the stage transfer node GPc_n controlled by the first inverter INV1 is high. Moreover, in the case that the potential of the first intermediate node Q1_n (i.e., GNc_n) is low, as described above in the first stage t01, a high potential signal can be output as a gate drive signal through the output signal end GP_n. Thus, the reset of the stage transfer node and the output signal can be realized. Alternatively, as described above, the potential of the reset control signal can be controlled to be high for a short time at power-on or power-off, or at the blanking time of each frame, or at the blanking time of the local brush mode, or after the end of the last high brush area of the local brush mode, to realize the reset function.

[0331] Alternatively, with the timing diagram shown in FIG. 48, and taking the scanning of the first row of pixels as an example, FIG. 49 also schematically shows a timing simulation structure diagram in the normal refresh mode, and FIG. 50 also schematically shows a timing simulation structure diagram in the local brush mode. The normal refresh mode is also referred to as the refresh mode without distinguishing the high brush area and the low brush area; and the local brush mode is also referred to as the refresh mode with distinguishing the high brush area and the low brush area.

[0332] Optionally, taking the structure shown in FIG. 38 as an example, i.e., taking the 4CK+2GEN design as an example, FIG. 51 shows the driving timing diagram of another shift register unit, which includes the timing of the clock signal provided by a group of clock terminals CK and CB, the timing of the clock signal provided by another group of clock terminals CKn and CBn, the timing of the input signal (also referred to as the start signal) provided by the input signal terminal GPc_n-1, the timing of the stage transmission signal provided by the stage transmission node GPc_n, the timing of the output signal output by the output signal terminal GP_n, the timing of the enable control signal provided by the enable control terminals GEN-1 and GEN-2, and the timing of the reset control signal provided by the reset control terminal Trst. The timing relationship is shown in FIG. 51 and will not be described in detail. The difference from FIG. 48 is that this structure can use 4 clock signals with a period of 2H. As described above, the clock signal provided by the clock terminal CK and the clock signal provided by the clock terminal CB can be different by 1H, the clock signal provided by the clock terminal CKn and the clock signal provided by the clock terminal CB can be inverse signals, and the clock signal provided by the clock terminal CBn and the clock signal provided by the clock terminal CK can be inverse signals. In addition, the pulse width of the low level 0 of the clock signal provided by the clock terminal CK and the clock signal provided by the clock terminal CB is generally smaller than 1H by about 0 to 2μs, and can be selected according to the load, in order to eliminate the influence of clock delay and avoid the risk of competition between different circuits caused by the simultaneous control of the input control circuit 01 and the latch circuit 03. The driving principle is the same as that of FIG. 48, which will not be described here.

[0333] Optionally, taking the structure shown in FIG. 30 as an example, i.e., taking the 2CK+4GEN design as an example, FIG. 52 shows the driving timing diagram of another shift register unit, which includes the timing of the clock signal provided by a group of clock terminals CK and CB, the timing of the input signal (also referred to as the start signal) provided by the input signal terminal GPc_n-1, the timing of the stage transmission signal provided by the stage transmission node GPc_n, the timing of the output signal output by the output signal terminal GP_n, the timing of the enable control signal provided by the enable control terminals GEN1-1, GEN2-1, GEN1-2 and GEN2-2, and the timing of the reset control signal provided by the reset control terminal Trst. The timing relationship is shown in FIG. 53 and will not be described in detail. The difference from FIG. 48 is that this structure can use 4 enable control terminals GEN, and the period of the enable control signal can be 4H and the pulse width can be less than 1H, which can be set according to the pixel charging time. In addition, the phase difference of the enable control signals provided by the 4 enable control terminals GEN can be 1H in turn. The driving principle is the same as that of FIG. 48, which will not be described here, and the difference is that the period of the output signal is longer.

[0334] Optionally, taking the structure shown in FIG. 31 as an example, i.e., taking the 2CK+2GEN design as an example, FIG. 53 shows a driving timing diagram of another shift register unit, which includes the timing of the clock signals provided by the clock terminals CK and CB, the timing of the input signals (also referred to as start signals) provided by the input signal terminals GNc_n-1, the timing of the stage transmission signals provided by the stage transmission nodes GNc_n, the timing of the output signals output by the output signal terminals GN_n, the timing of the enable control signals provided by the enable control terminals GEN-1 and GEN-2, and the timing of the reset control signals provided by the reset control terminal Trst. The timing relationship is shown in FIG. 53 and will not be described again. The difference from the timing shown in FIG. 48 is that, since the structure shown in FIG. 28 is a P-type transistor in the driving pixel, and the structure shown in FIG. 31 is an N-type transistor in the driving pixel, the low and high potentials of the signals are reversed.

[0335] Optionally, taking the structure shown in FIG. 32 as an example, i.e., taking the 2CK+2GEN design as an example, FIG. 54 shows a driving timing diagram of another shift register unit, which includes the timing of the clock signals provided by the clock terminals CK and CB, the timing of the input signals (also referred to as start signals) provided by the input signal terminals GNc_n-1, the timing of the stage transmission signals provided by the stage transmission nodes GNc_n, the timing of the output signals output by the output signal terminals GN_n, the timing of the enable control signals provided by the enable control terminals GEN1-1, GEN2-1, GEN1-2 and GEN2-2, and the timing of the reset control signals provided by the reset control terminal Trst. The timing relationship is shown in FIG. 54 and will not be described again. The difference from the timing shown in FIG. 52 is that, since the structure shown in FIG. 30 is a P-type transistor in the driving pixel, and the structure shown in FIG. 32 is a P-type transistor in the driving pixel, the low and high potentials of the signals are reversed.

[0336] It can be understood that the driving methods of shift register units of other structures are the same, and will not be described again. In addition, since the driving method of the shift register unit can have substantially the same technical effects as the shift register units described in the foregoing embodiments, for the purpose of brevity, the technical effects of the driving method of the shift register unit will not be described again.

[0337] The embodiments of the present application also provide a gate driving circuit. As shown in FIG. 55, the gate driving circuit includes at least two shift register units GOA (also referred to as Gate GOA) connected in cascade, which are as described above. Correspondingly, as shown in FIG. 55, the output signal terminals of the shift register units can be connected with the gate signal terminals Gate to provide gate driving signals to the gate signal terminals Gate.

[0338] In addition, as shown in FIG. 55, the gate driving circuit includes a plurality of stages of shift register units connected with P-type transistors, denoted as P-GOA. The gate driving circuit is powered by two groups of clock signals (including CK and CB) and double VGH and double VGL (including the second power supply terminal V2 and VGH2, and the third power supply terminal V3 and VGL2). The cascading manner is that the input signal terminal IN_1 of the first stage of shift register units P-GOA is connected with the start signal terminal STV, and the input signal terminals (such as IN_2, IN_n-1 and IN_n) of the other stages of shift register units P-GOA are connected with the second intermediate node Q2_n (i.e., the node GPc_n) of the previous stage of shift register units P-GOA. For other structural designs, reference can be made to the related descriptions of the shift register units, which will not be repeated here.

[0339] Alternatively, as shown in FIG. 28 and FIG. 29, FIG. 56 shows another structural schematic diagram of a gate driving circuit. As shown in FIG. 56, the gate driving circuit includes a plurality of stages of shift register units connected with P-type transistors, denoted as P-GOA. The gate driving circuit is powered by two groups of clock signals (including CK and CB), single VGH and single VGL (including the power supply terminal VGH1 and VGL1), one reset control terminal Trst, and two enable control terminals GEN-1 and GEN-2. The cascading manner is that the input signal terminal GPc_i of the first stage of shift register units P-GOA is connected with the start signal terminal STV, and the input signal terminals GPc_i of the other stages of shift register units P-GOA are connected with the stage transmission node GPc_o of the previous stage of shift register units P-GOA. CK and CB are alternately connected, two rows for one period. GEN-1 and GEN-2 are alternately connected, two rows for one period.

[0340] Alternatively, as shown in FIG. 37, FIG. 57 shows another structural schematic diagram of a gate driving circuit. As shown in FIG. 57, the gate driving circuit includes a plurality of stages of shift register units connected with P-type transistors, denoted as P-GOA. The gate driving circuit is powered by two groups of clock signals (including CK and CB), double VGH and double VGL (including the power supply terminal VGH1, VGH2 and VGL1, VGL2), one reset control terminal Trst, and two enable control terminals GEN-1 and GEN-2. The cascading manner is that the input signal terminal GPc_i of the first stage of shift register units P-GOA is connected with the start signal terminal STV, and the input signal terminals GPc_i of the other stages of shift register units P-GOA are connected with the stage transmission node GPc_o of the previous stage of shift register units P-GOA. CK and CB are alternately connected, two rows for one period. GEN-1 and GEN-2 are alternately connected, two rows for one period. That is, the difference between FIG. 57 and FIG. 56 is that FIG. 57 is powered by double VGH / double VGL.

[0341] Optionally, taking the structure shown in FIG. 38 as an example, FIG. 58 shows a structural schematic diagram of another gate drive circuit. As shown in FIG. 58, the gate drive circuit includes a plurality of stages of shift register units connected by P-type transistors, denoted as P-GOA. Four groups of clock signals (including CK, CB, CKn and CBn) are used, double VGH and double VGL (including power terminals VGH1, VGH2 and VGL1, VGL2) are used for power supply, one reset control terminal Trst is used, and two enable control terminals GEN-1 and GEN-2 are used. The cascading mode shown is that the input signal terminal GPc_i of the first stage of shift register units P-GOA is connected with the start signal terminal STV, and the input signal terminal GPc_i of the other stages of shift register units P-GOA is connected with the stage transmission node GPc_o of the previous stage of shift register units P-GOA. That is, the difference between FIG. 58 and FIG. 57 is that four groups of clock signals are used in FIG. 58.

[0342] Optionally, taking the structure shown in FIG. 39 as an example, FIG. 59 shows a structural schematic diagram of another gate drive circuit. As shown in FIG. 59, the gate drive circuit includes a plurality of stages of shift register units connected by P-type transistors, denoted as P-GOA. Four groups of clock signals (including CK, CB, CKn and CBn) are used, double VGH and double VGL (including power terminals VGH1, VGH2 and VGL1, VGL2) are used for power supply, one reset control terminal Trst is used, and four enable control terminals GEN1-1, GEN2-1, G2N1-2 and GEN2-2 are used. The cascading mode shown is that the input signal terminal GPc_i of the first stage of shift register units P-GOA is connected with the start signal terminal STV, and the input signal terminal GPc_i of the other stages of shift register units P-GOA is connected with the stage transmission node GPc_o of the previous stage of shift register units P-GOA. That is, the difference between FIG. 59 and FIG. 58 is that four enable control terminals are used in FIG. 59.

[0343] Based on the foregoing description, it can be known that, in the embodiments of the present application, the plurality of stages of shift register units in cascade can include a plurality of groups of shift register units, each group of shift register units can include at least two stages of shift register units in cascade. The first clock terminal and the second clock terminal connected by the at least two stages of shift register units are respectively and correspondingly staggered connected with different at least two clock lines, and the enable control terminals connected by the at least two stages of shift register units are respectively and correspondingly connected with different at least two enable control lines; and the plurality of groups of shift register units share the at least two clock lines and the at least two enable control lines.

[0344] For example, referring to FIG. 56, each group of shift register units can include two adjacent shift register units in cascade. In this way, each shift register unit can be connected to two clock lines (also identified as CK and CB in the figure), and the shift register units at each level are connected to CK and CB alternately, 2 rows per cycle. Similarly, the two adjacent shift register units can be connected to two enable control lines (also identified as GEN-1 and GEN-2 in the figure) alternately, 2 rows per cycle.

[0345] Alternatively, since the structure shown in FIGS. 55-59 can realize local brush driving, the gate on array substrate driving circuit can also be referred to as a hybrid refresh display gate on array (HRD).

[0346] Alternatively, in some embodiments, dummy shift register units, i.e., dummy GOA, can also be added at the first row or the last row to meet the required timing requirements or driving load.

[0347] It can be understood that since the gate on array substrate driving circuit can have substantially the same technical effects as the shift register units described in each of the foregoing embodiments, for the purpose of brevity, the technical effects of the gate on array substrate driving circuit are not described again here.

[0348] The embodiments of the present application also provide a display device. As shown in FIG. 60, the display device includes a display panel 10 and a gate on array substrate driving circuit 00 as shown in any one of FIGS. 55-59.

[0349] In combination with FIG. 2, the display panel 10 includes a plurality of pixels (not shown in FIG. 60), and the gate on array substrate driving circuit 00 is connected to the plurality of pixels, such as the gate signal end Gate of the pixels, and is used to transmit gate signals to the plurality of pixels to drive the plurality of pixels to emit light.

[0350] It can be understood that since the display device can have substantially the same technical effects as the shift register units described in each of the foregoing embodiments, for the purpose of brevity, the technical effects of the display device are not described again here.

[0351] Alternatively, the display device can be an OLED display device, an active-matrix OLED (AMOLED) display device, or any product or component having a display function. In addition, the display device can also be any appropriate display device, including but not limited to a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and an e-book.

[0352] It can be understood that the terms used in the embodiments of the present application are only used to explain the embodiments, and are not intended to limit the present application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be understood as the common meanings of the technical terms or scientific terms understood by those skilled in the art.

[0353] As used in the present patent application specification and claims, the terms "first", "second", or "third" and similar terms, do not denote any order, quantity, or importance, but are used to distinguish different components. "Connected" or "coupled" means electrical connection.

[0354] Similarly, "one" or "a" and similar terms do not denote a quantity restriction, but denote the existence of at least one.

[0355] "Include" or "contain" and similar terms mean that the elements or objects appearing before "include" or "contain" cover the elements or objects listed after "include" or "contain" and their equivalents, and do not exclude other elements or objects.

[0356] "Up", "down", "left" or "right" and the like are only used to represent relative positional relationships, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0357] The above is only an optional embodiment of the present application, and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A shift register unit, comprising: an input control circuit connected with a first clock terminal, a second clock terminal, an input signal terminal and an input node respectively, and configured to control the on-off of the input signal terminal and the input node in response to a first clock signal provided by the first clock terminal and a second clock signal provided by the second clock terminal; an output control circuit connected with the input node, an enable control terminal and an output signal terminal respectively, and configured to control the potential of the output signal terminal based on the potential of the input node and an enable control signal provided by the enable control terminal, so as to output a gate drive signal to a connected pixel through the output signal terminal to drive the pixel to emit light.

2. The shift register cell of claim 1, wherein, The output control circuit comprises: a first output control sub-circuit connected with the input node and a first intermediate node respectively, and configured to control the potential of the first intermediate node based on the potential of the input node; a second output control sub-circuit connected with the first intermediate node, the enable control terminal and the output signal terminal respectively, and configured to control the potential of the output signal terminal based on the potential of the first intermediate node and the enable control signal.

3. The shift register cell of claim 2, wherein, The second output control sub-circuit comprises: a first output control unit connected with the first intermediate node, the enable control terminal and a second intermediate node respectively, and configured to control the potential of the second intermediate node based on the potential of the first intermediate node and the enable control signal; a second output control unit connected with the second intermediate node and the output signal terminal respectively, and configured to control the potential of the output signal terminal based on the potential of the second intermediate node.

4. The shift register cell of claim 2, wherein, The second output control sub-circuit comprises: a first output control unit connected with the first intermediate node and a second intermediate node respectively, and configured to control the potential of the second intermediate node based on the potential of the first intermediate node; a second output control unit connected with the second intermediate node, the enable control terminal and the output signal terminal respectively, and configured to control the potential of the output signal terminal based on the potential of the second intermediate node and the enable control signal.

5. The shift register cell of claim 3, wherein, The first output control unit is further connected with a reset control terminal, and is further configured to control the potential of the second intermediate node based on a reset control signal provided by the reset control terminal.

6. The shift register cell of claim 4, wherein, The first output control unit is further connected with a reset control terminal, and is further configured to control the potential of the second intermediate node based on a reset control signal provided by the reset control terminal. Or, the second output control unit is further connected with the reset control terminal, and is further configured to control the potential of the output signal terminal based on the reset control signal.

7. The shift register cell of claim 2, wherein, The first output control sub-circuit is further connected with a reset control terminal, and is configured to control the potential of the first intermediate node based on the potential of the input node and a reset control signal provided by the reset control terminal.

8. The shift register cell of claim 3, wherein, The shift register unit further comprises: A switch circuit is connected between the enable control terminal and the second output control sub-circuit, and is also connected with the first control terminal and the second control terminal respectively, and is used for controlling the on-off of the enable control terminal and the second output control sub-circuit in response to the first control signal provided by the first control terminal and the second control signal provided by the second control terminal.

9. The shift register cell of claim 8, wherein, In the case that neither the first output control sub-circuit nor the second output control sub-circuit is connected with the reset control terminal, the first control terminal is connected with a first intermediate node of a previous stage shift register unit cascaded with the shift register unit, and the second control terminal is connected with a second intermediate node of the previous stage shift register unit. In the case that the second output control sub-circuit of the first output control sub-circuit and the second output control sub-circuit is also connected with the reset control terminal, the first control terminal is connected with a first intermediate node of a previous stage shift register unit cascaded with the shift register unit, and the second control terminal is connected with a second intermediate node of the previous stage shift register unit. In the case that the first output control sub-circuit of the first output control sub-circuit and the second output control sub-circuit is also connected with the reset control terminal, the first control terminal is connected with a first intermediate node of a previous stage shift register unit cascaded with the shift register unit, and the second control terminal is connected with a second intermediate node of the previous stage shift register unit.

10. The shift register cell of claim 2, wherein, The shift register unit further comprises: A latch circuit is connected with the third clock terminal, the fourth clock terminal, the first intermediate node and the input node respectively, and is used for controlling the on-off of the first intermediate node and the input node in response to the third clock signal provided by the third clock terminal and the fourth clock signal provided by the fourth clock terminal, and outputs the potential of the first intermediate node to the input node after being inverted.

11. The shift register cell of claim 10, wherein, The first clock terminal and the third clock terminal are shared, and the second clock terminal and the fourth clock terminal are shared.

12. The shift register cell of claim 11, wherein, The latch circuit comprises a first NOT gate and a first transmission gate connected in series between the first intermediate node and the input node, and the first transmission gate is also connected with the third clock terminal and the fourth clock terminal respectively.

13. The shift register cell of claim 12, wherein, The circuit connected with the reset control terminal or the enable control terminal in the first output control sub-circuit and the second output control sub-circuit comprises a NOR gate or a NAND gate, and the circuit not connected with the reset control terminal and the enable control terminal comprises a NOT gate. In the case that the first output control sub-circuit is connected with the reset control terminal and the second output control sub-circuit is not connected with the reset control terminal, the first NOT gate of the latch circuit is shared with a second NOT gate of the second output control sub-circuit.

14. The shift register cell of claim 2, wherein, The second output control sub-circuit is also connected with a first power supply terminal, and is used for controlling the on-off of the first power supply terminal and the output signal terminal in response to the potential of the first intermediate node, and controlling the on-off of the enable control terminal and the output signal terminal, so as to control the potential of the output signal terminal and output the gate drive signal through the output signal terminal. The gate drive signal comprises a power signal provided by the first power supply end or the enable control signal. The enable control signal is a potential change signal comprising an effective potential and an ineffective potential, and the gate drive signal is a pulse width adjustable signal. The effective potential refers to a signal for turning on a transistor in a pixel, and the ineffective potential refers to a signal for turning off the transistor in the pixel.

15. The shift register cell of claim 14, wherein, In the case where the output signal end is used for connecting a P-type transistor in a pixel, the effective potential of the enable control signal is less than the potential of the power signal provided by the first power supply end. In the case where the output signal end is used for connecting an N-type transistor in a pixel, the effective potential of the enable control signal is greater than the potential of the power signal provided by the first power supply end.

16. The shift register cell of claim 14, wherein, The pixel is located in a display area, and the display area comprises a first display area and a second display area. The refresh frequency of the first display area is greater than the refresh frequency of the second display area. In the first display area, the enable control signal is the potential change signal, and in the second display area, the potential of the enable control signal remains constant as an ineffective potential.

17. The shift register cell of claim 14, wherein, The enable control end connected to the shift register unit is different from the enable control end connected to other stage shift register units cascaded with the shift register unit.

18. The shift register cell of claim 14, wherein, The number of the second output control sub-circuits is at least two. At least two of the second output control sub-circuits are connected to at least two output signal ends one by one, and at least two of the second output control sub-circuits are connected to at least two enable control ends one by one. The at least two output signal ends are used for connecting different pixels.

19. The shift register cell of claim 14, wherein, The second output control sub-circuit comprises a third NOT gate connected between the first intermediate node and the output signal end.

20. The shift register cell of any one of claims 1 to 19, wherein, The input control circuit comprises a second transmission gate. The second transmission gate is connected between the input signal end and the input node, and is further connected to the first clock end and the second clock end respectively.

21. The shift register cell of any one of claims 1 to 20, wherein, The shift register unit further comprises: A driving enhancement circuit connected between the output control circuit and the output signal end, and configured to perform at least one inversion processing on the potential of the output signal of the output control circuit and then output the output signal to the output signal end.

22. The shift register cell of claim 21, wherein, The driving enhancement circuit comprises at least one fourth NOT gate connected between the output control circuit and the output signal end. In the case where the driving enhancement circuit comprises a plurality of fourth NOT gates, the plurality of fourth NOT gates are connected in series between the output control circuit and the output signal end. The power supply end of each fourth NOT gate in the plurality of fourth NOT gates is further connected to a second power supply end and a third power supply end respectively, and is configured to work based on a power signal provided by the second power supply end and a power signal provided by the third power supply end. The potential of the power signal provided by the second power supply end is greater than the potential of the power signal provided by the third power supply end.

23. The shift register cell of claim 22, wherein, Among the plurality of fourth NAND gates, a second power supply end connected to a last fourth NAND gate provides a power supply signal with a potential greater than or equal to a potential of a power supply signal provided by a second power supply end connected to other fourth NAND gates except the last fourth NAND gate; and the last fourth NAND gate is a fourth NAND gate directly connected to the output signal end.

24. The shift register cell of claim 22, wherein, Among the plurality of fourth NAND gates, a third power supply end connected to a last fourth NAND gate provides a power supply signal with a potential less than or equal to a potential of a power supply signal provided by a third power supply end connected to other fourth NAND gates except the last fourth NAND gate; and the last fourth NAND gate is a fourth NAND gate directly connected to the output signal end.

25. The shift register cell of claim 22, wherein, The output signal end includes a first output end and a second output end, the first output end is used to be connected with an N-type transistor in a pixel, and the second output end is used to be connected with a P-type transistor in the pixel; and the driving enhancement circuit includes: a first driving enhancement sub-circuit connected between the output control circuit and the first output end and used to output the potential of the output signal of the output control circuit after an even number of inversion processes; a second driving enhancement sub-circuit connected between the output control circuit and the second output end and used to output the potential of the output signal of the output control circuit after an odd number of inversion processes.

26. The shift register cell of claim 25, wherein, The first driving enhancement sub-circuit includes an even number of fourth NAND gates connected in series, the second driving enhancement sub-circuit includes an odd number of fourth NAND gates connected in series, and the first driving enhancement sub-circuit and the second driving enhancement sub-circuit share at least one fourth NAND gate.

27. The shift register cell of claim 22, wherein, In a case where the output control circuit is further connected with a first power supply end and the output signal end is used to be connected with a P-type transistor in a pixel, the first power supply end is shared with the second power supply end; In a case where the output control circuit is further connected with a first power supply end and the output signal end is used to be connected with an N-type transistor in a pixel, the first power supply end is shared with the third power supply end.

28. The shift register cell of any one of claims 1 to 27, wherein, The output signal end of the shift register unit is used to be connected with an N-type data writing transistor in the pixel and is used to output a gate driving signal to the N-type data writing transistor through the output signal end; and / or, The output signal end of the shift register unit is used to be connected with a P-type data writing transistor in the pixel and is used to output a gate driving signal to the P-type data writing transistor through the output signal end.

29. The shift register cell of any one of claims 1 to 7, wherein, The input control circuit comprises a second transmission gate; the output control circuit comprises a first output control sub-circuit and a second output control sub-circuit, and the second output control sub-circuit comprises a first output control unit and a second output control unit, and the first output control sub-circuit and the second output control unit each comprise an NOR gate, the first output control unit comprises a second NOR gate; the shift register unit further comprises a switching circuit, a latch circuit and a driving enhancement circuit, and the switching circuit comprises a third transmission gate, the latch circuit comprises a first NOR gate and a first transmission gate, the driving enhancement circuit comprises three fourth NOR gates; and the first NOR gate and the second NOR gate are shared; The second transmission gate is connected between an input signal end of the shift register unit and the input node, and is further connected with the first clock end and the second clock end respectively; In the first output control sub-circuit, two input ends of the NOR gate are connected with the input node and a reset control end respectively, and an output end of the NOR gate is connected with a first intermediate node; An input end of the second NOR gate is connected with the first intermediate node, and an output end of the second NOR gate is connected with a second intermediate node; In the second output control unit, one input end of the NOR gate is connected with the second intermediate node, another input end of the NOR gate is connected with the enable control end through the third transmission gate, and an output end of the NOR gate is connected with the output signal end through the three fourth NOR gates, and the third transmission gate is further connected with the first intermediate node and the second intermediate node respectively, and the three fourth NOR gates are connected in series; An input end of the first NOR gate is connected with the first intermediate node, and an output end of the first NOR gate is connected with the input node through the first transmission gate, and the first transmission gate is further connected with a third clock end and a fourth clock end respectively; And the output signal end is used for being connected with a P-type transistor in the pixel.

30. The shift register cell of any of claims 14 to 19, wherein, The output control circuit comprises a first output control sub-circuit and a second output control sub-circuit; the shift register unit further comprises a latch circuit and a driving enhancement circuit; the input control circuit comprises a second transmission gate; the first output control sub-circuit comprises an NOR gate; the second output control sub-circuit comprises a third NOR gate; the latch circuit comprises a first NOR gate and a first transmission gate; the driving enhancement circuit comprises two fourth NOR gates connected in series; The first transmission gate is connected between the input signal end and the input node, and is further connected with the first clock end and the second clock end respectively; Two input ends of the NOR gate are connected with the input node and a reset control end respectively, and an output end of the NOR gate is connected with a first intermediate node; An input end of the third NOR gate is connected with the first intermediate node, and an output end of the third NOR gate is connected with the output signal end through the two fourth NOR gates connected in series, and the third NOR gate is further connected with a first power supply end and the enable control end respectively, and each fourth NOR gate is further connected with a second power supply end and a third power supply end respectively; An input terminal of the first NOT gate is connected to the first intermediate node, an output terminal of the first NOT gate is connected to the input node through the first transmission gate, and the first transmission gate is further connected to a third clock terminal and a fourth clock terminal.

31. A driving method of a shift register unit, for driving the shift register unit according to any one of claims 1 to 30; the method comprising: in response to a first scan instruction, providing a first clock signal to the first clock terminal, providing a second clock signal to the second clock terminal, and providing a same enable control signal as the first clock signal or the second clock signal to the enable control terminal, and the first clock signal and the second clock signal provided have opposite potentials in the same time period; in response to a second scan instruction, providing a first clock signal to the first clock terminal, providing a second clock signal to the second clock terminal, and providing an enable control signal with a constant potential to the enable control terminal; wherein the first clock signal and the second clock signal are used to drive the input control circuit to control the on-off of the input terminal and the first intermediate node, and to control the potential of the first intermediate node based on the input signal provided by the input signal terminal; the enable control signal is used to drive the output control circuit to control the potential of the output signal terminal based on the potential of the first intermediate node and the enable control signal, so as to output a gate drive signal to the pixel through the output signal terminal, to drive the pixel to emit light; and the refresh frequency indicated by the first scan instruction is greater than the refresh frequency indicated by the second scan instruction.

32. A gate drive circuit, the gate drive circuit comprising: A plurality of shift register units according to any one of claims 1 to 30 are cascaded.

33. The gate drive circuit of claim 32, wherein, The plurality of shift register units include a plurality of groups of shift register units, each group of shift register units including at least two shift register units cascaded; the first clock terminal and the second clock terminal connected by the at least two shift register units are respectively connected to different at least two clock lines in a staggered manner one by one, and the enable control terminals connected by the at least two shift register units are respectively connected to different at least two enable control lines one by one; and the plurality of groups of shift register units share the at least two clock lines and the at least two enable control lines.

34. The gate drive circuit of claim 33, wherein, Each group of shift register units includes two adjacent shift register units cascaded.

35. A display device comprising: A display panel, and a gate drive circuit according to any one of claims 32 to 34; the display panel includes a plurality of pixels, and the gate drive circuit is connected to the plurality of pixels and is used to transmit a gate drive signal to the plurality of pixels, to drive the plurality of pixels to emit light.

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