Shift register unit and driving method thereof, display driver and display device

Abstract

The invention provides a shift register unit and a driving method thereof, a display driver and a display device, and belongs to the technical field of display. Wherein the input control circuit can control the on-off of the input end and the input node under the control of a clock signal. And the output control circuit can output a display driving signal to the pixel based on the potential of the input node and an enable signal provided by the enable end. And the switch control circuit can control the on-off of the enabling end and the output control circuit under the control of the control signal. Therefore, the enabling end can be selected to be connected to or not connected to the output control circuit by flexibly setting the control signal, so that the output control circuit outputs the required driving signal to the pixel to drive the pixel to emit light. On the basis, the shift register unit can output a signal matched with a P-type transistor and / or an N-type transistor in a pixel by flexibly setting an enable signal and a clock signal. The shift register unit is rich in driving mode and low in working power consumption.

Description

Shift register unit and driving method thereof, display driver and display device TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a shift register unit and driving method thereof, a display driver and a display device. BACKGROUND

[0002] A display device generally comprises a display driver and a display panel. The display driver can transmit display driving signals including gate driving signals, reset control signals and light emitting control signals to multiple rows of pixels on the display panel to drive the multiple pixels to emit light. In view of the narrow frame design, the gate driver on array (GOA) technology is currently used to integrate the display driver on the display panel.

[0003] In the related art, the display driver configured by using the GOA technology generally comprises multiple GOA units connected in cascade. The multiple GOA units can be connected in one-to-one correspondence with multiple rows of pixels on the display panel through multiple signal lines and are used to transmit the gate driving signals to the multiple rows of pixels row by row to light up the pixels row by row, so as to realize row-by-row scanning and refreshing and enable the display panel to display a picture.

[0004] However, due to the cascade of the multiple GOA units, the driving mode of the GOA units in the current display driver is fixed and single, and the working power consumption is large.

[0005] SUMMARY

[0006] A shift register unit and driving method thereof, a display driver and a display device are provided. The technical solutions are as follows:

[0007] In one aspect, a shift register unit is provided, which comprises:

[0008] an input control circuit connected with a first clock terminal, a second clock terminal, an input terminal and an input node respectively, and configured to control the on-off of the input terminal and the input node in response to a first clock signal provided by the first clock terminal and a second clock signal provided by the second clock terminal;

[0009] an output control circuit connected with the input node, an enable terminal and an output terminal respectively, and configured to control the potential of the output terminal based on the potential of the input node and an enable signal provided by the enable terminal, so as to output a gate driving signal to a data writing transistor in a pixel or output a reset signal to a reset transistor in the pixel through the output terminal, to drive the pixel to emit light;

[0010] A switch control circuit is connected between the enable terminal and the output control circuit, and is further connected with the at least two first control terminals and the at least two second control terminals respectively, and is configured to control the enable terminal and the output control circuit to be turned on or turned off in response to a first control signal provided by each of the first control terminals and a second control signal provided by each of the second control terminals.

[0011] Optionally, the output control circuit comprises:

[0012] A first output control sub-circuit is connected with the input node and a first intermediate node respectively, and is configured to control a potential of the first intermediate node based on a potential of the input node.

[0013] A second output control sub-circuit is connected with the first intermediate node, the enable terminal and the output terminal respectively, and is configured to control a potential of the output terminal based on a potential of the first intermediate node and the enable signal.

[0014] Optionally, the second output control sub-circuit comprises:

[0015] A first output control unit is connected with the first intermediate node and a second intermediate node respectively, and is configured to control a potential of the second intermediate node based on a potential of the first intermediate node.

[0016] A second output control unit is connected with the second intermediate node, the enable terminal and the output terminal respectively, and is configured to control a potential of the output terminal based on a potential of the second intermediate node and the enable signal.

[0017] Optionally, the first output control unit in the second output control sub-circuit is further connected with a reset control terminal, and is further configured to control the potential of the second intermediate node based on a reset control signal provided by the reset control terminal.

[0018] Optionally, the second output control unit in the second output control sub-circuit is further connected with a reset control terminal, and is further configured to control the potential of the output terminal based on a reset control signal provided by the reset control terminal.

[0019] Optionally, the first output control sub-circuit is further connected with a reset control terminal, and is further configured to control the potential of the first intermediate node based on a reset control signal provided by the reset control terminal.

[0020] Optionally, the switch control circuit is connected with two first control terminals and two second control terminals respectively, and the two first control terminals and the two second control terminals correspond to each other one by one.

[0021] And, one first control end and one second control end corresponding to each other are connected with the second intermediate node and the first intermediate node of the previous stage shift register unit cascaded with the shift register unit respectively.

[0022] Optionally, the shift register unit further comprises:

[0023] A latch circuit connected with the third clock end, the fourth clock end, the first intermediate node and the input node respectively, and configured to control the on-off of the first intermediate node and the input node in response to a third clock signal provided by the third clock end and a fourth clock signal provided by the fourth clock end, and output the potential of the first intermediate node to the input node after being inverted.

[0024] Optionally, the first clock end and the third clock end are shared, and the second clock end and the fourth clock end are shared.

[0025] Optionally, the latch circuit comprises a first NAND gate and a first transmission gate connected in series between the first intermediate node and the input node, and the first transmission gate is further connected with the third clock end and the fourth clock end respectively.

[0026] Optionally, the circuits connected with the enable end or the reset control end in the first output control sub-circuit and the second output control sub-circuit comprise NAND gates or NOR gates, and the circuits not connected with the enable end and not connected with the reset control end comprise a second NAND gate.

[0027] And, in the case that the first output control sub-circuit is connected with the reset control end and the second output control sub-circuit is not connected with the reset control end, the first NAND gate included in the latch circuit is shared with the second NAND gate included in the second output control sub-circuit.

[0028] Optionally, the shift register unit further comprises:

[0029] A driving enhancement circuit connected between the output control circuit and the output end, and configured to output the potential of the output signal of the output control circuit to the output end after at least one inversion.

[0030] Optionally, the driving enhancement circuit comprises at least one third NAND gate connected in series between the output control circuit and the output end, and in the case that the driving enhancement circuit comprises a plurality of third NAND gates, the plurality of third NAND gates are connected in series between the output control circuit and the output end.

[0031] Each of the third NAND gates is also connected with the first power supply end and the second power supply end respectively, and is used to work based on a first power supply signal provided by the first power supply end and a second power supply signal provided by the second power supply end, wherein the potential of the first power supply signal is greater than the potential of the second power supply signal.

[0032] Optionally, in the plurality of third NAND gates, the first power supply signal provided by the first power supply end connected with the last third NAND gate is greater than or equal to the first power supply signal provided by the first power supply end connected with other third NAND gates, and the last third NAND gate is the third NAND gate connected with the output end in the plurality of third NAND gates.

[0033] Optionally, in the plurality of third NAND gates, the second power supply signal provided by the second power supply end connected with the last third NAND gate is less than or equal to the second power supply signal provided by the second power supply end connected with other third NAND gates, and the last third NAND gate is the third NAND gate connected with the output end in the plurality of third NAND gates.

[0034] Optionally, the output end includes a first output end and a second output end, and the potential of the first output end is opposite to the potential of the second output end in the same period; the driving enhancement circuit includes:

[0035] a first driving enhancement sub-circuit connected between the output control circuit and the first output end, and used to output the potential of the output signal of the output control circuit after even times of inversion processing;

[0036] a second driving enhancement sub-circuit connected between the output control circuit and the second output end, and used to output the potential of the output signal of the output control circuit after odd times of inversion processing.

[0037] Optionally, the first driving enhancement sub-circuit includes an even number of third NAND gates connected in series, the second driving enhancement sub-circuit includes an odd number of third NAND gates connected in series, and the first driving enhancement sub-circuit and the second driving enhancement sub-circuit share at least one third NAND gate.

[0038] Optionally, the input control circuit includes a second transmission gate;

[0039] The second transmission gate is connected between the input end and the input node, and is also connected with the first clock end and the second clock end respectively.

[0040] Optionally, the switch control circuit includes at least two third transmission gates;

[0041] The at least two third transmission gates are connected in series between the enable terminal and the output control circuit, and are respectively connected with the at least two first control terminals and the at least two second control terminals one by one, and each of the third transmission gates is connected with a corresponding first control terminal and a corresponding second control terminal.

[0042] Optionally, in the case that the shift register unit is configured to output a gate drive signal to a data write-in transistor in a pixel through the output terminal:

[0043] The output terminal of the shift register unit is configured to be connected with an N-type data write-in transistor in the pixel, and is configured to output a gate drive signal to the N-type data write-in transistor through the output terminal.

[0044] And / or,

[0045] The output terminal of the shift register unit is configured to be connected with a P-type data write-in transistor in the pixel, and is configured to output a gate drive signal to the P-type data write-in transistor through the output terminal.

[0046] Optionally, in the case that the shift register unit is configured to output a reset signal to a reset transistor in a pixel through the output terminal:

[0047] The output terminal of the shift register unit is configured to be connected with an N-type reset transistor in the pixel, and is configured to output a reset signal to the N-type reset transistor through the output terminal.

[0048] And / or,

[0049] The output terminal of the shift register unit is configured to be connected with a P-type reset transistor in the pixel, and is configured to output a reset signal to the P-type reset transistor through the output terminal.

[0050] Optionally, the input control circuit comprises a second transmission gate; the output control circuit comprises a first output control sub-circuit and a second output control sub-circuit, and the first output control sub-circuit comprises a two-input NOR gate, and the second output control sub-circuit comprises a two-input NAND gate; the switch control circuit comprises two third transmission gates; the shift register unit further comprises a latch circuit and a driving enhancement circuit, and the latch circuit comprises a first NAND gate and a first transmission gate, and the driving enhancement circuit comprises three third NAND gates.

[0051] The second transmission gate is connected between the input terminal of the shift register unit and the input node, and is further connected with the first clock terminal and the second clock terminal respectively.

[0052] The two inputs of the two-input NOR gate are connected with the input node and the reset control terminal respectively, and the output of the two-input NOR gate is connected with the first intermediate node;

[0053] One input of the two-input NAND gate is connected with the first intermediate node, and the other input of the two-input NAND gate is connected with the enable terminal through the two third transmission gates, the output of the two-input NAND gate is connected with the output of the shift register unit through the three third NAND gates, and the two third transmission gates are connected in series, the three third NAND gates are connected in series, one of the two third transmission gates is also connected with the second intermediate node and the first intermediate node of the previous shift register unit in the cascade connection of the shift register unit respectively, and the other third transmission gate is also connected with the first intermediate node and the second intermediate node of the shift register unit respectively;

[0054] The input of the first NAND gate is connected with the first intermediate node of the shift register unit, the output of the first NAND gate is connected with the input node through the first transmission gate, and the first transmission gate is also connected with the third clock terminal and the fourth clock terminal respectively;

[0055] And the output of the shift register unit is connected with the N-type transistor in the pixel.

[0056] In another aspect, a driving method of a shift register unit is provided, which is used to drive the shift register unit as described in the above aspect; the method comprises:

[0057] In response to a first scanning instruction, a first clock signal is provided to the first clock terminal, a second clock signal is provided to the second clock terminal, and an enable signal of a first potential is provided to the enable terminal;

[0058] In response to a second scanning instruction, a first clock signal is provided to the first clock terminal, a second clock signal is provided to the second clock terminal, and an enable signal of a second potential is provided to the enable terminal;

[0059] The first clock signal and the second clock signal are used to drive the input control circuit to control the on-off of the input terminal and the input node; the enable signal is used to drive the output control circuit to control the potential of the output terminal based on the potential of the input node and the enable signal, so as to output a gate drive signal to the data writing transistor in the pixel through the output terminal or output a reset signal to the reset transistor in the pixel, so as to drive the pixel to emit light; and the refresh frequency indicated by the first scanning instruction is greater than the refresh frequency indicated by the second scanning instruction.

[0060] In yet another aspect, a display driver is provided, comprising: at least two shift register units as described in any of the above aspects, cascaded.

[0061] In yet another aspect, a display device is provided, comprising: a display panel, and a display driver as described in the yet another aspect above.

[0062] The display panel comprises a plurality of pixels, and the display driver is connected to the plurality of pixels and configured to transmit a gate driving signal or a reset signal to the plurality of pixels to drive the plurality of pixels to emit light. BRIEF DESCRIPTION OF DRAWINGS

[0063] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0064] FIG. 1 is a structural schematic diagram of a shift register unit provided by an embodiment of the present application;

[0065] FIG. 2 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present application;

[0066] FIG. 3 is a driving timing schematic diagram of a pixel circuit provided by an embodiment of the present application;

[0067] FIG. 4 is a driving timing schematic diagram of another pixel circuit provided by an embodiment of the present application;

[0068] FIG. 5 is a structural schematic diagram of another shift register unit provided by an embodiment of the present application;

[0069] FIG. 6 is a structural schematic diagram of another shift register unit provided by an embodiment of the present application;

[0070] FIG. 7 is a structural schematic diagram of another shift register unit provided by an embodiment of the present application;

[0071] FIG. 8 is a structural schematic diagram of another shift register unit provided by an embodiment of the present application;

[0072] FIG. 9 is a structural schematic diagram of another shift register unit provided by an embodiment of the present application;

[0073] FIG. 10 is a structural schematic diagram of another shift register unit provided by an embodiment of the present application;

[0074] FIG. 11 is a structural schematic diagram of another shift register unit provided by an embodiment of the present application;

[0075] Figure 12 is a schematic diagram of a circuit structure of a shift register unit according to an embodiment of the present application;

[0076] Figure 13 is a schematic diagram of a circuit structure of another shift register unit according to an embodiment of the present application;

[0077] Figure 14 is a schematic diagram of a circuit structure of yet another shift register unit according to an embodiment of the present application;

[0078] Figure 15 is a schematic diagram of a circuit structure of still another shift register unit according to an embodiment of the present application;

[0079] Figure 16 is a schematic diagram of a circuit structure of still another shift register unit according to an embodiment of the present application;

[0080] Figure 17 is a schematic diagram of a circuit structure of still another shift register unit according to an embodiment of the present application;

[0081] Figure 18 is a schematic diagram of a circuit structure of still another shift register unit according to an embodiment of the present application;

[0082] Figure 19 is a schematic diagram of a circuit structure of still another shift register unit according to an embodiment of the present application;

[0083] Figure 20 is a schematic diagram of a transistor structure of a shift register unit according to an embodiment of the present application;

[0084] Figure 21 is a schematic diagram of a transistor structure of a shift register unit according to an embodiment of the present application;

[0085] Figure 22 is a schematic diagram of a transistor structure of a shift register unit according to an embodiment of the present application;

[0086] Figure 23 is a schematic diagram of a module equivalent of a shift register unit according to an embodiment of the present application;

[0087] Figure 24 is a flowchart of a driving method of a shift register unit according to an embodiment of the present application;

[0088] Figure 25 is a timing diagram of a driving of a shift register unit according to an embodiment of the present application;

[0089] Figure 26 is a timing diagram of a driving simulation of a shift register unit according to an embodiment of the present application;

[0090] Figure 27 is a timing diagram of a driving of another shift register unit according to an embodiment of the present application;

[0091] Figure 28 is a timing diagram of a driving of yet another shift register unit according to an embodiment of the present application;

[0092] FIG. 29 is a driving timing diagram of another shift register unit according to an embodiment of the present application;

[0093] FIG. 30 is a driving timing diagram of another shift register unit according to an embodiment of the present application;

[0094] FIG. 31 is a structural diagram of a display driver according to an embodiment of the present application;

[0095] FIG. 32 is a structural diagram of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0096] For the purpose, technical solutions and advantages of the present application to be clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0097] It can be understood that the transistors used in all embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics, and the transistors used in the embodiments of the present application are mainly switching transistors according to their functions in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and drain can be interchangeable. In the embodiments of the present application, the source is referred to as the first pole and the drain is referred to as the second pole. According to the mode in the drawings, the middle end of the transistor is the control pole, which can also be referred to as the gate, the signal input end is the source, and the signal output end is the drain. In addition, the switching transistor used in the embodiments of the present application can include any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level, and the N-type switching transistor is turned on when the gate is at a high level and is turned off when the gate is at a low level. In addition, a plurality of signals in each embodiment of the present application correspond to a first potential and a second potential. The first potential and the second potential only represent two states of the potential of the signal, and do not represent that the first potential or the second potential has a specific value throughout the text.

[0098] The embodiments of the present application provide a shift register unit, which can not only better match the timing requirements of N-type transistors and / or P-type transistors in pixels, but also realize local reset, rich driving mode, good driving flexibility, and small working power consumption. As shown in FIG. 1, the shift register unit includes an input control circuit 01 and an output control circuit 02.

[0099] The input control circuit 01 is connected with a first clock end CKn, a second clock end CB, an input end IN_n and an input node Q_n respectively, and is configured to control the on-off of the input end IN_n and the input node Q_n in response to a first clock signal provided by the first clock end CKn and a second clock signal provided by the second clock end CB.

[0100] For example, the input control circuit 01 can control the input end IN_n to be connected to the input node Q_n when the first clock signal has the first potential and the second clock signal has the first potential, so that the input signal provided by the input end IN_n is output to the input node Q_n, and the potential of the input node Q_n is controlled to be the potential of the input signal; and the input control circuit 01 can control the input end IN_n to be disconnected from the input node Q_n when the first clock signal has the second potential or the second clock signal has the second potential.

[0101] It can be understood that "n" represents that the shift register unit is an nth shift register unit, and correspondingly, "n-1" represents a previous shift register unit connected in cascade with the shift register unit, and "n+1" represents a next shift register unit connected in cascade with the shift register unit, and n can be an integer greater than 1. Generally, a plurality of shift register units can be connected in one-to-one correspondence with a plurality of rows of pixels, and of course, are not limited to one-to-one correspondence. For example, each shift register unit can be connected with at least two rows of pixels.

[0102] Optionally, in the embodiment of the present application, the first potential can be a valid potential, and the second potential can be an invalid potential. For the P-type transistor in the pixel, the first potential can be a low potential (low, L) relative to the second potential. For the N-type transistor in the pixel, the first potential can be a high potential (high, H) relative to the second potential. It can be known accordingly that the signal output to the P-type transistor in reset means that the potential of the signal output to the P-type transistor is controlled to be the high potential H; and the signal output to the N-type transistor in reset means that the potential of the signal output to the N-type transistor is controlled to be the low potential L. In addition, the high potential can be represented by binary "1", and the low potential can be represented by binary "0".

[0103] With reference back to FIG. 1, the output control circuit 02 is connected with the input node Q_n, the enable end EN and the output end OUT_n respectively, and is configured to control the potential of the output end OUT_n based on the potential of the input node Q_n and the enable signal provided by the enable end EN, so as to output the gate driving signal to the data writing transistor in the pixel or output the reset signal to the reset transistor in the pixel through the output end OUT_n, so as to drive the pixel to emit light. That is, the shift register unit can output the display driving signal such as the gate driving signal or the reset control signal to the pixel.

[0104] For example, the output control circuit 02 can control the potential of the output terminal OUT_n to be low potential 0 when the potential of the input node Q_n is high potential 1 and / or the potential of the enable signal is high potential 1; and the output control circuit 02 can control the potential of the output terminal OUT_n to be high potential 1 when the potential of the input node Q_n is low potential 0 and the potential of the enable signal is low potential 0. Thus, the gate drive signal including high potential 1 and low potential 0 (i.e., including the first potential and the second potential) can be output through the output terminal OUT_n, and the pulse with the required timing can be output to the P-type transistor and / or the N-type transistor in the pixel, so as to meet the driving requirement of the PMOS switch type pixel, or meet the driving requirement of the NMOS switch type pixel, or meet the driving requirement of the CMOS switch type pixel.

[0105] In addition, the output reset and local brushing control can also be realized by flexibly setting the enable signal provided by the enable terminal EN. For example, in the normal output or high brushing area, the potential of the enable signal can be set to high potential 1, so that the output control circuit 02 normally works; and in the reset stage or low brushing area, the potential of the enable signal can be set to low potential 0, so that the output control circuit 02 controls the potential of the output signal to be invalid potential, and completes the reset. The low brushing area and the high brushing area refer to the display sub-area with relatively low refresh rate and the display sub-area with relatively high refresh rate. Generally, the display area can be divided into multiple display sub-areas, and different refresh rates are adopted for different display sub-areas.

[0106] For example, for the output terminal OUT_n connected to the N-type transistor in the pixel, the potential of the enable signal provided by the enable terminal EN can be set to high potential 1 (i.e., the enable signal is high) in the porch period (or when the display panel is powered on / powered off), so that the output control circuit 02 controls the potential of the output terminal OUT_n to be low potential 0, and realizes the reset of the display drive signal output to the N-type transistor. The P-type transistor is the same, and will not be described again.

[0107] It can be understood that the PMOS switch type pixel refers to the pixel in which the pixel circuit includes multiple P-type transistors; the NMOS switch type pixel refers to the pixel in which the pixel circuit includes multiple N-type transistors; and the CMOS switch type pixel refers to the pixel in which the pixel circuit includes at least one P-type transistor and at least one N-type transistor. MOS is the abbreviation of metal-oxide-semiconductor, i.e., the transistor in the pixel circuit can be a MOS transistor. In addition, the transistor can also be a thin film transistor (TFT). That is, the transistor in the pixel circuit can be a MOS TFT, the P-type transistor can be referred to as a PMOS TFT, and the N-type transistor can be referred to as an NMOS TFT. Of course, this is only illustrative.

[0108] Optionally, taking the CMOS switch type pixel as an example, FIG. 2 shows a circuit structure schematic diagram of a pixel provided in an embodiment of the present application. As shown in FIG. 2, the pixel can include a pixel circuit and a light emitting element L1. The pixel circuit can include 8 transistors T1 to T8 and 1 capacitor Cst, that is, a circuit of 8T1C structure. The light emitting element L1 can be an organic light-emitting diode (OLED). The connection mode of each part is referred to FIG. 2 and will not be described again. In addition, the signal end connected to the pixel includes a gate signal end Gate, reset signal ends Reset1, Reset2 and Reset3, a data signal end Vdata, reset power ends V1, V2 and V3, a light emitting control end EM, a pull-up power end EVDD and a pull-down power end ELVSS. Of course, in some other embodiments, the pixel circuit can also be of other structures, such as 8T2C structure. The light emitting element L1 can also be of other types. For example, a micro light-emitting diode (Micro-LED), also known as MLED. The present application does not limit this.

[0109] For the PMOS switch type pixel, the 8 transistors T1 to T8 can all be PMOS TFTs; for the NMOS switch type pixel, the 8 transistors T1 to T8 can all be NMOS TFTs; and for the CMOS switch type pixel, as shown in FIG. 2, T2, T3, T5 and T6 can be NMOS TFTs, and the other transistors except T2, T3, T5 and T6 can be PMOS TFTs. Correspondingly, taking the gate signal end Gate as an example, the gate signal end Gate connected to the transistor T2 is identified as Gate_N, and the gate signal end Gate connected to the transistor T1 is identified as Gate_P. “N” represents the relevant signal end connected to the NMOS TFT, and “P” represents the relevant signal end connected to the PMOS TFT. The identification of other signal ends can be the same.

[0110] For example, for the PMOS switch type pixel, since the transistors T1 and T2 receiving the gate drive signal are both PMOS TFTs, the same or similar P-type gate drive signal can be used to drive the transistors T1 and T2 to work. For the NMOS switch type pixel, since the transistors T1 and T2 receiving the gate drive signal are both NMOS TFTs, the same or similar N-type gate drive signal can be used to drive the transistors T1 and T2 to work. For the CMOS switch type pixel shown in FIG. 2, since the transistor T1 receiving the gate drive signal is a PMOS TFT and the transistor T2 is an NMOS TFT, the opposite P-type gate drive signal and N-type gate drive signal are needed to drive the transistors T1 and T2 to work, respectively. As described above, the P-type gate drive signal refers to the gate drive signal with the first potential being the low potential 0 and the second potential being the high potential 1, and the N-type control signal refers to the gate drive signal with the first potential being the high potential 1 and the second potential being the low potential 0.

[0111] Optionally, taking the pixel circuit shown in FIG. 2 as an example, FIG. 3 shows a driving timing diagram of the pixel circuit. As shown in FIG. 3, the driving timing can include stages t1 to t5 executed in sequence.

[0112] In stage t1, the potential of the light-emitting control signal provided by the light-emitting control end EM_P can be the high potential, and the potential of the light-emitting control signal provided by the light-emitting control end EM_N can be the low potential. Correspondingly, the transistors T4 and T5 can be both turned off. Further, the pull-up power supply end EVDD and the pull-down power supply end EVSS can be disconnected, so that the light-emitting of the light-emitting element L1 is turned off.

[0113] In stage t2, the potential of the gate drive signal provided by the gate signal end Gate_N is the high potential, and the potential of the reset signal provided by the reset signal end Reset1 is the high potential. Correspondingly, the transistors T2 and T3 can be both turned on. Further, the reset power supply end V2 can output the reset power supply signal to the nodes P3 and P1 in sequence through the turned-on transistors T3 and T2, so as to reset the nodes P1 and P3 to the potential V20 of the reset power supply signal provided by the reset power supply end V2, and the potential of the node P2 gradually becomes V20-Vth_Td, where Vth_Td refers to the threshold voltage of the transistor T8.

[0114] At stage t3, the potential of the reset signal provided by the reset signal terminal Reset1 becomes low, the potential of the gate drive signal provided by the gate signal terminal Gate_P is low, and the potential of the gate drive signal provided by the gate signal terminal Gate_N is high. Accordingly, the transistor T3 is turned off, and the transistors T1, T2 and T8 are turned on. Further, the data signal terminal Vdata transmits the data signal to the node P2 through the turned-on transistor T1, so as to charge the potential of the node P2 to the potential Vdata0 of the data signal, and charge the potentials of the node P3 and the node P1 to Vdata0+Vth_Td.

[0115] At stage t4, the potential of the gate drive signal provided by the gate signal terminal Gate_N becomes low, the potential of the reset signal provided by the reset signal terminal Reset2 (i.e., Reset_P) is low, and the potential of the reset signal provided by the reset signal terminal Reset3 (i.e., Reset_N) is high. Accordingly, the transistor T2 is turned off, and the transistors T6 and T7 are turned on. Further, the reset power terminal V3 outputs the reset power signal to the node P2 through the turned-on transistor T7, so as to reset the node P2 to the potential V30 of the reset power signal provided by the reset power terminal V3. If V30>Vdata0, the potential of the node P3 can become V30+Vth_Td, otherwise, the potential of the node P3 can remain Vdata0+Vth_Td. In addition, the reset power terminal V1 outputs the reset power signal to the node P4 (i.e., the anode of the OLED) through the turned-on transistor T6, so as to reset the node P4 to the potential of the reset power signal provided by the reset power terminal V1.

[0116] At stage t5, the potential of the reset signal provided by the reset signal terminal Reset2 (i.e., Reset_P) becomes high, the potential of the reset signal provided by the reset signal terminal Reset3 (i.e., Reset_N) becomes low, the potential of the light-emitting control signal provided by the light-emitting control terminal EM_P becomes low, and the potential of the light-emitting control signal provided by the light-emitting control terminal EM_N can become high. Accordingly, the transistors T6 and T7 are turned off, and the transistors T4, T5 and T8 are turned on. Further, a path is formed between the pull-up power terminal EVDD and the pull-down power terminal EVSS, so that the light-emitting element L1 can emit light. The light-emitting current Id positively correlated with the light-emitting brightness can be determined by the potential of the node P1 and the potential of the node P2. The potential of the node P1 is Vdata0+Vth_Td, and the potential of the node P2 is the potential EVDD0 of the pull-up power signal provided by the pull-up power terminal EVDD. Accordingly, based on the current calculation formula, Id=K(Vdata0-EVDD0) can be determined. 2K is determined by the intrinsic characteristics of the transistor T8, such as the width-length ratio W / L, the capacitance Cox, and the mobility μ. That is, the light-emitting current transmitted to the light-emitting element L1 by the pixel circuit can be independent of the threshold voltage Vth_Td of the driving transistor, and thus the drift of the threshold voltage Vth_Td of the transistor T8 will not affect the light-emitting brightness of the light-emitting element L1, and the light-emitting effect of the light-emitting element L1 can be ensured to be better.

[0117] It can be understood that, based on the above introduction of the driving principle, the transistors T1 and T2 can be referred to as data writing transistors, the transistors T3, T6, and T7 can be referred to as reset transistors, the transistors T4 and T5 can be referred to as light-emitting control transistors, and the transistor T8 can be referred to as a driving transistor.

[0118] Of course, in some other embodiments, as can be seen from the timing diagram of another pixel circuit shown in FIG. 4, the light-emitting control signal provided by the light-emitting control end EM_P becomes high potential, and the light-emitting control signal provided by the light-emitting control end EM_N becomes low potential in a time period, such as in stage t1, the action in stage t4 can be performed once more to increase the process of resetting the nodes P2 and P4 once. In this way, the purpose of quickly resetting the anode of the light-emitting element L1 can be achieved, and the contrast when the light-emitting element L1 emits light can be ensured to be better. At the same time, the refresh and strong bias process for the transistor T8 can be increased, and the display requirement of low frequency driving and low flicker can be more easily achieved. That is, the display effect of the display panel can be ensured to be better. Alternatively, the reset signal provided by the reset signal end Reset3 and the reset signal provided by the reset signal end Reset2 can also be the same.

[0119] In addition, in some other embodiments, as can be seen from the timing diagram of another pixel circuit shown in FIG. 5, compared with FIG. 3, the duration of stage t4 can be longer. That is, the duration of the low-potential reset signal provided by the reset signal end Reset_P and the high-potential reset signal provided by the reset signal end Reset_N can be longer, which is a kind of wide pulse signal. In this way, the transistors T6 and T7 can be turned on for a longer time, and thus the nodes P2 and P4 can be reliably reset, and the reset effect is better.

[0120] Optionally, the output terminal OUT_n of the shift register unit can be connected to a gate signal terminal (e.g., Gate_N or Gate_P shown in FIG. 2) of the pixel circuit, and used to provide a required gate driving signal to the gate signal terminal. For example, the P-type gate driving signal or the N-type gate driving signal shown in FIG. 3 can be provided to drive the transistors T1 and T2 in FIG. 2 to work reliably. Alternatively, the output terminal OUT_n of the shift register unit can be connected to a reset signal terminal (e.g., Reset_N and / or Reset_P shown in FIG. 2) of the pixel circuit, and used to provide a required reset signal to the reset signal terminal, such as the reset signal shown in any one of FIGS. 3 to 5. Of course, in some other embodiments, the output terminal OUT_n of the shift register unit can also be connected to other signal terminals (e.g., the light emitting control terminals EM_N and EM_P) of the pixel circuit, and used to provide signals to the other signal terminals.

[0121] With continued reference to FIG. 1, the switch control circuit 03 is connected between the enable terminal EN and the output control circuit 02, and also connected to the at least two first control terminals and the at least two second control terminals respectively, and used to control the connection between the enable terminal EN and the output control circuit 02 in response to the first control signals provided by each of the first control terminals and the second control signals provided by each of the second control terminals. That is, the output control circuit 02 is not directly connected to the enable terminal EN, but can be indirectly connected to the enable terminal EN through the switch control circuit 03.

[0122] For example, the switch control circuit 03 shown in FIG. 1 is connected to two first control terminals Con11 and Con12, and connected to two second control terminals Con21 and Con22. The switch control circuit 03 can control the enable terminal EN to be connected to the output control circuit 02 when the potentials of the first control signals provided by each of the first control terminals are all the first potential, and the potentials of the second control signals provided by each of the second control terminals are all the first potential, so that the enable signal provided by the enable terminal EN is transmitted to the output control circuit 02, which can also be considered as connecting the enable terminal EN to the output control circuit 02. In addition, the switch control circuit 03 can control the enable terminal EN to be disconnected from the output control circuit 02 when the potentials of the first control signals provided by each of the first control terminals are all the second potential, and / or the potentials of the second control signals provided by each of the second control terminals are all the second potential, which can also be considered as not connecting the enable terminal EN to the output control circuit 02.

[0123] As described above, based on the enable terminal EN being connected to the output control circuit 02, the output control circuit 02 can control the potential of the output terminal OUT_n based on the enable signal and the potential of the input node Q_n, so as to output the display driving signal to the pixel. In this way, the output of the shift register unit can be controlled by flexibly setting the control signal to connect or not to connect the enable terminal EN to the output control circuit 02, and the driving flexibility is good. Based on the partial shift register unit resetting the output signal, compared with all the shift register units resetting the output signal, the working power consumption of the shift register unit can be reduced.

[0124] As described above, the shift register unit provided by the embodiments of the present disclosure comprises an input control circuit, an output control circuit and a switch control circuit. The input control circuit can control the on-off of the input terminal and the input node under the control of the clock signals provided by the first clock terminal and the second clock terminal. The output control circuit can output the display driving signal to the pixel through the output terminal based on the potential of the input node and the enable signal provided by the enable terminal, so as to drive the pixel to emit light. The switch control circuit can control the on-off of the enable terminal and the output control circuit under the control of the control signals provided by the first control terminal and the second control terminal. In this way, the control signal can be flexibly set to select whether to connect or not to connect the enable terminal to the output control circuit. Based on the enable terminal being connected to the output control circuit, the output control circuit can control the potential of the output terminal, so as to output the required driving signal to the pixel to drive the pixel to emit light. Based on this, the enable signal and the clock signal can be flexibly set, so as to further make the shift register unit output the display driving signal matching the P-type transistor and / or the N-type transistor in the pixel to the output terminal. As can be seen, the driving mode of the shift register unit is rich, and the working power consumption is small.

[0125] Optionally, as described above, in the case that the shift register unit outputs the gate driving signal to the data writing transistor in the pixel through the output terminal OUT_n:

[0126] The output terminal OUT_n of the shift register unit can be used to connect with the N-type data writing transistor in the pixel, and used to output the gate driving signal to the N-type data writing transistor through the output terminal OUT_n. For example, as shown in FIG. 2, the output terminal OUT_n of the shift register unit can be connected with the gate signal terminal Gate_N of the N-type data writing transistor T2 in the pixel, and output the required N-type gate driving signal to the gate signal terminal Gate_N.

[0127] and / or,

[0128] The output end OUT_n of the shift register unit can be used to connect with the P-type data write transistor in the pixel, and is used to output the gate driving signal to the P-type data write transistor through the output end OUT_n. For example, in combination with FIG. 2, the output end OUT_n of the shift register unit can be connected with the gate signal end Gate_P of the P-type data write transistor T1 in the pixel, and outputs the required P-type gate driving signal to the gate signal end Gate_P.

[0129] Alternatively, as described above, in the case that the shift register unit outputs the reset signal to the reset transistor in the pixel through the output end OUT_n:

[0130] The output end OUT_n of the shift register unit is used to connect with the N-type reset transistor in the pixel, and is used to output the reset signal to the N-type reset transistor through the output end OUT_n. For example, in combination with FIG. 2, the output end OUT_n of the shift register unit can be connected with the reset signal end Reset3 of the N-type reset transistor T6 in the pixel, and outputs the required N-type reset signal to the reset signal end Reset3.

[0131] And / or,

[0132] The output end OUT_n of the shift register unit is used to connect with the P-type reset transistor in the pixel, and is used to output the reset signal to the P-type reset transistor through the output end OUT_n. For example, in combination with FIG. 2, the output end OUT_n of the shift register unit can be connected with the reset signal end Reset2 of the P-type reset transistor T7 in the pixel, and outputs the required P-type reset signal to the reset signal end Reset2.

[0133] Optionally, FIG. 6 shows a structural schematic diagram of another shift register unit provided by the embodiment of the present application. As shown in FIG. 6, the output control circuit 02 includes a first output control sub-circuit 021 and a second output control sub-circuit 022.

[0134] The first output control sub-circuit 021 can be connected with the input node Q_n and the first intermediate node Q1_n respectively, and is used to control the potential of the first intermediate node Q1_n based on the potential of the input node Q_n.

[0135] For example, the first output control sub-circuit 021 can output the potential of the input node Q_n to the first intermediate node Q1_n after inverting processing, that is, the potential of the first intermediate node Q1_n can be controlled to be opposite to the potential of the input node Q_n.

[0136] The second output control sub-circuit 022 can be connected with the first intermediate node Q1_n, the enable terminal EN and the output terminal OUT_n respectively, and can be configured to control the potential of the output terminal OUT_n based on the potential of the first intermediate node Q1_n and the enable signal.

[0137] For example, the second output control sub-circuit 022 can control the potential of the output terminal OUT_n to be low potential 0 when the potential of the first intermediate node Q1_n is high potential 1 and / or the potential of the enable signal is high potential 1; and the second output control sub-circuit 022 can control the potential of the output terminal OUT_n to be high potential 1 when the potential of the first intermediate node Q1_n is low potential 0 and the potential of the enable signal is low potential 0.

[0138] Optionally, based on FIG. 6, FIG. 7 shows another structure diagram of a shift register unit provided by an embodiment of the present application. As shown in FIG. 7, the second output control sub-circuit 022 can include a first output control unit 0221 and a second output control unit 0222.

[0139] The first output control unit 0221 can be connected with the first intermediate node Q1_n and the second intermediate node Q2_n respectively, and can be configured to control the potential of the second intermediate node Q2_n based on the potential of the first intermediate node Q1_n.

[0140] For example, the first output control unit 0221 can output the potential of the first intermediate node Q1_n after inversion processing to the second intermediate node Q2_n, that is, can control the potential of the second intermediate node Q2_n to be opposite to the potential of the first intermediate node Q1_n.

[0141] The second output control unit 0222 can be connected with the second intermediate node Q2_n, the enable terminal EN and the output terminal OUT_n respectively, and can be configured to control the potential of the output terminal OUT_n based on the potential of the second intermediate node Q2_n and the enable signal.

[0142] For example, the second output control unit 0222 can control the potential of the output terminal OUT_n to be low potential 0 when the potential of the second intermediate node Q2_n is high potential 1 and / or the potential of the enable signal is high potential 1; and the second output control unit 0222 can control the potential of the output terminal OUT_n to be high potential 1 when the potential of the second intermediate node Q2_n is low potential 0 and the potential of the enable signal is low potential 0.

[0143] Of course, in some other embodiments, the first output control unit 0221 can be connected with the enable terminal EN to control the potential of the second intermediate node Q2_n based on the enable signal and the potential of the first intermediate node Q1_n.

[0144] Optionally, based on FIG. 7, as an optional implementation manner, as shown in FIG. 8, the first output control unit 0221 in the second output control sub-circuit 022 can also be connected with the reset control terminal Trst, and can also be used to control the potential of the second intermediate node Q2_n based on the reset control signal provided by the reset control terminal Trst.

[0145] Optionally, based on FIG. 7, as another optional implementation manner, as shown in FIG. 9, the second output control unit 0222 in the second output control sub-circuit 022 can also be connected with the reset control terminal Trst, and can also be used to control the potential of the output terminal OUT_n based on the reset control signal provided by the reset control terminal Trst.

[0146] Optionally, based on FIG. 6, as still another optional implementation manner, as shown in FIG. 10, the first output control sub-circuit 021 can also be connected with the reset control terminal Trst, and can also be used to control the potential of the first intermediate node Q1_n based on the reset control signal provided by the reset control terminal Trst.

[0147] That is, in the embodiment of the present application, in the output control circuit 02, the first output control sub-circuit 021 or the second output control sub-circuit 022 can also be connected with the reset control terminal Trst, and can also control the potential of the output based on the reset signal provided by the reset control terminal Trst.

[0148] It can be understood that, in addition to the enable terminal EN, the reset control terminal Trst is also provided, and the potential of the output terminal OUT_n can be controlled to be the invalid potential by flexibly setting the reset signal provided by the reset control terminal Trst when the display panel is powered on or powered off or in the porch period, that is, the gate drive signal of the reset output is improved in reliability. In this way, the driving abnormality during the switching between the low brushing and the high brushing in the local refresh scene can also be avoided, and the driving power consumption of the shift register unit can be further reduced.

[0149] Optionally, as can be seen from FIGS. 7 to 10, the switch control circuit 03 can be connected with two first control terminals Con11 and Con12 and two second control terminals Con21 and Con22 respectively. The two first control terminals Con11 and Con12 correspond to the two second control terminals Con21 and Con22 one by one.

[0150] And, one-to-one corresponding first control end Con11 and one-to-one corresponding second control end Con21 can be connected with the second intermediate node Q2_n-1 and the first intermediate node Q1_n-1 of the previous stage shift register unit in the cascade shift register unit respectively, and one-to-one corresponding another first control end Con12 and one-to-one corresponding another second control end Con22 can be connected with the first intermediate node Q1_n and the second intermediate node Q2_n of the shift register unit respectively. Therefore, it can be known that the signals at the first intermediate node Q1_n and the second intermediate node Q2_n can be used as a stage transmission signal to drive the cascade shift register unit to work.

[0151] On this basis, it can be known that the stage-by-stage access to the enable end EN can be realized by the stage transmission signal control switch control circuit 03 of the adjacent two rows of shift register units, so that the shift register unit can reset only the GOA unit at the stage transmission start boundary line, and the GOA unit which has been started but not completed is not reset until the shift is completed. In this way, not only the driving requirement of consistent pulse width of pixel local brush output can be met, but also the working power consumption is saved compared with resetting all outputs. For example, for the switch control circuit 03, when the potential of the first intermediate node Q1_n-1 and the potential of the second intermediate node Q2_n-1 controlled by the previous stage shift register unit are both valid potentials, and the potential of the first intermediate node Q1_n and the potential of the second intermediate node Q2_n controlled by the current stage shift register unit are also valid potentials, the switch control circuit 03 controls the enable end EN to be conductive with the output control circuit 02, and the output control circuit 02 controls the potential of the output signal based on the enable signal provided by the enable end EN.

[0152] Optionally, it can also be seen from FIGS. 6 to 10 that the shift register unit disclosed in the embodiments of the present application can further include a latch circuit 04.

[0153] And, the latch circuit 04 can be connected with the third clock end CBn, the fourth clock end CK, the first intermediate node Q1_n and the input node Q_n respectively, and can be used to control the on-off of the first intermediate node Q1_n and the input node Q_n in response to the third clock signal provided by the third clock end CBn and the fourth clock signal provided by the fourth clock end CK, and output the potential of the first intermediate node Q1_n to the input node Q_n after the potential of the first intermediate node Q1_n is inverted.

[0154] In an example, the latch circuit 04 can control the first intermediate node Q1_n and the input node Q_n to be connected when the third clock signal has the first potential and the fourth clock signal has the first potential, and output the potential of the first intermediate node Q1_n to the input node Q_n after the potential of the first intermediate node Q1_n is inverted; and the latch circuit 04 can control the first intermediate node Q1_n and the input node Q_n to be disconnected when the third clock signal has the second potential or the fourth clock signal has the second potential. In this way, the potential of the input node Q_n can be the same as the potential of the first intermediate node Q1_n, so as to latch the potential of the input node Q_n, or the latch circuit 04 can also be called as being capable of storing the potential of the input node Q_n, so as to avoid the potential of the input node Q_n from being leaked.

[0155] Optionally, based on FIG. 10, FIG. 11 shows a structural schematic diagram of another shift register unit. As shown in FIG. 11, the first clock end CKn and the fourth clock end CK can be shared, and the second clock end CB and the third clock end CBn can be shared. For example, the first clock end CKn and the fourth clock end CK can both be the fourth clock end CK, and the second clock end CB and the third clock end CBn can both be the second clock end CB. That is, in an optional implementation manner, as shown in FIG. 11, two groups of clock ends (that is, two groups of clock signals) CK and CB can be used. Alternatively, in another optional implementation manner, as shown in FIG. 6 to FIG. 10, four groups of clock ends (that is, four groups of clock signals) CKn, CK, CBn and CB can be used.

[0156] Optionally, the period of the four groups of clock signals can be 2H, the clock signal provided by the clock end CK and the clock signal provided by the clock end CB can be different by 1H, the clock signal provided by the clock end CKn and the clock signal provided by the clock end CB can be inverse signals, and the clock signal provided by the clock end CBn and the clock signal provided by the clock end CK can be inverse signals. In addition, the pulse width of the low potential 0 of the clock signal provided by the clock end CK and the clock signal provided by the clock end CB is generally smaller than 0 to 2 microseconds (μs) or so, and can be selected according to the load resistance RC, so as to eliminate the influence of clock delay, avoid the input control circuit 01 and the latch circuit 04 from being simultaneously controlled to be connected and turned on, and cause the risk of competition between different circuits during state switching. Wherein, “H” can refer to a row period, and can be flexibly adjusted according to the number of cascaded groups of the shift register unit.

[0157] Optionally, it can also be seen from FIG. 6 to FIG. 11 that the shift register unit can further include a driving enhancement circuit 05.

[0158] And, the driving enhancement circuit 05 can be connected between the output control circuit 02 and the output terminal OUT_n, and can be used to output the potential of the output signal of the output control circuit 02 to the output terminal OUT_n after at least one time of inverting processing. In this way, the purpose of enhancing the driving capability of the shift register unit can be achieved.

[0159] Optionally, in some embodiments, as can be seen with reference to FIG. 11, the output terminal OUT_n can include a first output terminal OUTN_n and a second output terminal OUTP_n, and the potential of the first output terminal OUTN_n and the potential of the second output terminal OUTP_n can be opposite at the same time period.

[0160] For example, in combination with FIG. 2, the first output terminal OUTN_n and the second output terminal OUTP_n can be used to connect with the gate signal terminal Gate_N connected with the N-type transistor T2, and are used to provide the gate driving signal with opposite potential to the gate signal terminal Gate_N respectively. Of course, the gate driving signal with opposite potential is not provided to the N-type transistor T2 at the same time. Alternatively, in combination with FIG. 2, the first output terminal OUTN_n and the second output terminal OUTP_n can be used to connect with the reset signal terminal Reset3 connected with the N-type transistor T6 and the reset signal terminal Reset2 connected with the P-type transistor T7 respectively, and are used to provide the reset signal with opposite potential to the reset signal terminal Reset3 and the reset signal terminal Reset2 respectively.

[0161] On this basis, with continued reference to FIG. 11, the driving enhancement circuit 05 can include a first driving enhancement sub-circuit 051 and a second driving enhancement sub-circuit 052.

[0162] The first driving enhancement sub-circuit 051 can be connected between the output control circuit 02 and the first output terminal OUTN_n, and can be used to output the potential of the output signal of the output control circuit 02 to the first output terminal OUTN_n after even times of inverting processing. That is, the potential of the first output terminal OUTN_n is the same as the potential of the output signal of the output control circuit 02.

[0163] The second driving enhancement sub-circuit 052 can be connected between the output control circuit 02 and the second output terminal OUTP_n, and is used to output the potential of the output signal of the output control circuit 02 to the second output terminal OUTP_n after odd times of inverting processing. That is, the potential of the second output terminal OUTP_n is opposite to the potential of the output signal of the output control circuit 02.

[0164] Correspondingly, it can be understood that the output OUT_n shown in FIGS. 6-10 can be the first output OUTN_n or the second output OUTP_n. In other words, the driving enhancement circuit 05 shown in FIGS. 6-10 can be the first driving enhancement sub-circuit 051 or the second driving enhancement sub-circuit 052.

[0165] Optionally, based on the foregoing different embodiments, FIGS. 12-19 respectively show various circuit structure diagrams of the shift register unit. For the scenario of connecting the output OUT_n to the gate signal end Gate_N and providing the gate drive signal to the gate signal end Gate, the first output OUTN_n can also be identified as NN_n, the second output OUTP_n can also be identified as NP_n, the first intermediate node Q1_n can be identified as NNc_n, and the second intermediate node Q2_n can be identified as NPc_n. The first intermediate node Q1_n of the previous stage shift register unit can be identified as NNc_n-1, and the second intermediate node Q2_n of the previous stage shift register unit can be identified as NPc_n-1. In addition, the input end IN_n can be connected to the second intermediate node NPc_n-1 of the previous stage shift register unit in cascade, and of course the input end IN_1 of the first stage shift register unit needs to be connected to the start signal end STV to receive the start signal from the start signal end STV. Therefore, it can also be known that NPc_n and NNc_n can be referred to as stage transmission nodes for stage transmission signals.

[0166] Optionally, as can be seen with reference to FIGS. 12-19, the latch circuit 04 can include a first inverter INV1 and a first transmission gate Tg1 connected in series between the first intermediate node Q1_n and the input node Q_n, and the first transmission gate Tg1 can also be connected to the third clock end CBn and the fourth clock end CK, respectively. That is, the input end of the first inverter INV1 can be connected to the first intermediate node Q1_n, the output end of the first inverter INV1 can be connected to one end of the first transmission gate Tg1, and the other end of the first transmission gate Tg1 can be connected to the input node Q_n. It can be understood that the inverter can also be referred to as an inverter, and the transmission gate can also be referred to as a transmission switch.

[0167] Optionally, continuing to refer to FIGS. 12-19, it can be seen that the input control circuit 01 can include a second transmission gate Tg2, and the second transmission gate Tg2 can be connected between the input end IN_n and the input node Q_n, and can also be connected to the first clock end CKn and the second clock end CB, respectively.

[0168] In the circuit structure shown in FIGS. 12-16, the first clock terminal CKn and the fourth clock terminal CK are shared, both being the fourth clock terminal CK; the second clock terminal CB and the third clock terminal CBn are shared, both being the second clock terminal CB. In the structure shown in FIGS. 17-19, the first clock terminal CKn, the second clock terminal CB, the third clock terminal CBn and the fourth clock terminal CK are independent of each other.

[0169] Optionally, with reference to FIGS. 12-19, it can be seen that, in the first output control sub-circuit 021 and the second output control sub-circuit 022, the circuit connected to the enable terminal EN or the reset control terminal Trst can include a NOR gate or a NAND gate, and the circuit not connected to the enable terminal EN and not connected to the reset control terminal Trst includes a second inverter INV2.

[0170] Also, in the case where the first output control sub-circuit 021 is connected to the reset control terminal Trst and the second output control sub-circuit 022 is not connected to the reset control terminal Trst, with reference to FIG. 18, it can be seen that the first inverter INV1 included in the latch circuit 04 and the second inverter INV2 included in the second output control sub-circuit 022 can be shared. In this way, the structure can be simplified and the cost can be saved.

[0171] It can be understood that the logic operation principle of the NOR gate is that all 0s output 1 and all 1s output 0; that is, when the potentials of all the received signals are low potentials 0, the potential of the output signal can be controlled to be a high potential 1; otherwise, as long as the potential of a received signal is a high potential 1, the potential of the output signal is controlled to be a low potential 0. The logic operation principle of the NAND gate is that all 1s output 0 and all 0s output 1; that is, when the potentials of all the received signals are high potentials 1, the potential of the output signal can be controlled to be a low potential 0; otherwise, as long as the potential of a received signal is a low potential 0, the potential of the output signal is controlled to be a high potential 1. Different gate circuits correspond to different control modes, and the foregoing enumerated embodiments are all illustrated by taking the NOR gate as an example.

[0172] For example, referring to FIG. 12 and FIG. 13, it can be seen that the first output control sub-circuit 021 shown in FIG. 12 includes a second NOT gate INV2-1, the first output control unit 0221 in the second output control sub-circuit 022 includes another second NOT gate INV2-2, and the second output control unit 0222 includes a NOR gate. The difference is that the NOR gate in FIG. 12 is a two-input NOR gate, and the NOR gate in FIG. 13 is a three-input NOR gate. The input end of the second NOT gate INV2-1 is connected with the input node Q_n, and the output end of the second NOT gate INV2-1 is connected with the first intermediate node Q1_n. The input end of the second NOT gate INV2-2 is connected with the first intermediate node Q1_n, and the output end of the second NOT gate INV2-2 is connected with the second intermediate node Q2_n. The two input ends of the NOR gate in FIG. 12 are respectively connected with the second intermediate node Q2_n and the enable end EN. The three input ends of the NOR gate in FIG. 13 are respectively connected with the second intermediate node Q2_n, the enable end EN and the reset control end Trst. The NOR gate is indirectly connected with the enable end EN through the switch control circuit 03. In addition, the output end of the NOR gate in FIG. 12 and FIG. 13 is indirectly connected with the first output end OUTN_n through the first drive enhancement circuit 051, and is indirectly connected with the second output end OUTP_n through the second drive enhancement circuit 052.

[0173] For example, referring to FIG. 14, it can be seen that the first output control sub-circuit 021 shown in FIG. 14 includes a second NOT gate INV2-1, the first output control unit 0221 in the second output control sub-circuit 022 includes another second NOT gate INV2-2, and the second output control unit 0222 includes a NAND gate, which is a three-input NAND gate. The input end of the second NOT gate INV2-1 is connected with the input node Q_n, and the output end of the second NOT gate INV2-1 is connected with the first intermediate node Q1_n. The input end of the second NOT gate INV2-2 is connected with the first intermediate node Q1_n, and the output end of the second NOT gate INV2-2 is connected with the second intermediate node Q2_n. The three input ends of the NAND gate are respectively connected with the second intermediate node Q2_n, the enable end EN and the reset control end Trst, and the NAND gate is indirectly connected with the enable end EN through the switch control circuit 03. The output end of the NAND gate is indirectly connected with the first output end OUTN_n through the first drive enhancement circuit 051, and is indirectly connected with the second output end OUTP_n through the second drive enhancement circuit 052.

[0174] For example, referring to FIG. 15, it can be seen that the first output control sub-circuit 021 shown therein includes a second inverter INV2, the first output control unit 0221 in the second output control sub-circuit 022 includes a NAND gate, the second output control unit 0222 includes a NOR gate, and the NAND gate is a two-input NAND gate and the NOR gate is a two-input NOR gate. The input terminal of the second inverter INV2 is connected to the input node Q_n, and the output terminal of the second inverter INV2 is connected to the first intermediate node Q1_n. The two input terminals of the NAND gate are respectively connected to the first intermediate node Q1_n and the reset control terminal Trst, and the output terminal of the NAND gate is connected to the second intermediate node Q2_n. The two input terminals of the NOR gate are respectively connected to the second intermediate node Q2_n and the enable terminal EN, and the NOR gate is indirectly connected to the enable terminal EN through the switch control circuit 03. The output terminal of the NOR gate is indirectly connected to the first output terminal OUTN_n through the first drive enhancement circuit 051, and is indirectly connected to the second output terminal OUTP_n through the second drive enhancement circuit 052.

[0175] For example, referring to FIG. 16, it can be seen that the first output control sub-circuit 021 shown therein includes a second inverter INV2, the first output control unit 0221 in the second output control sub-circuit 022 includes a NOR gate, the second output control unit 0222 includes a NAND gate, and the NOR gate is a two-input NOR gate and the NAND gate is a two-input NAND gate. The input terminal of the second inverter INV2 is connected to the input node Q_n, and the output terminal of the second inverter INV2 is connected to the first intermediate node Q1_n. The two input terminals of the NOR gate are respectively connected to the first intermediate node Q1_n and the reset control terminal Trst, and the output terminal of the NOR gate is connected to the second intermediate node Q2_n. The two input terminals of the NAND gate are respectively connected to the second intermediate node Q2_n and the enable terminal EN, and the NAND gate is indirectly connected to the enable terminal EN through the switch control circuit 03. The output terminal of the NAND gate is indirectly connected to the first output terminal OUTN_n through the first drive enhancement circuit 051, and is indirectly connected to the second output terminal OUTP_n through the second drive enhancement circuit 052.

[0176] For example, referring to FIG. 17 and FIG. 18, the first output control sub-circuit 021 includes a NOR-1, the first output control unit 0221 in the second output control sub-circuit 022 includes a second inverter INV2, the second output control unit 0222 includes another NOR-2, the NOR-1 is a two-input NOR-1, and the NOR-2 is also a two-input NOR-2. The two inputs of the NOR-1 are connected to the input node Q_n and the reset control terminal Trst, respectively, and the output of the NOR-1 is connected to the first intermediate node Q1_n. The input of the second inverter INV2 is connected to the first intermediate node Q1_n, and the output of the second inverter INV2 is connected to the second intermediate node Q2_n. The two inputs of the NOR-2 are connected to the second intermediate node Q2_n and the enable terminal EN, respectively, and the NOR-2 is indirectly connected to the enable terminal EN through the switch control circuit 03. The difference is that, in FIG. 17, the output of the NOR-2 is connected to the first output terminal OUTN_n through the drive enhancement circuit 05. In FIG. 18, the output of the NOR-2 is connected to the second output terminal OUTP_n through the drive enhancement circuit 05. In addition, in FIG. 17, the second inverter INV2 is independent of the first inverter INV1. In FIG. 18, the second inverter INV2 shares the first inverter INV1.

[0177] For example, referring to FIG. 19, the first output control sub-circuit 021 includes a NOR, the second output control sub-circuit 022 includes a NAND, and the NOR is a two-input NOR, and the NAND is a two-input NAND. The two inputs of the NOR are connected to the input node Q_n and the reset control terminal Trst, respectively, and the output of the NOR is connected to the first intermediate node Q1_n. The two inputs of the NAND are connected to the first intermediate node Q1_n and the enable terminal EN, respectively, and the NAND is indirectly connected to the enable terminal EN through the switch control circuit 03. The output of the NAND is indirectly connected to the first output terminal OUTN_n through the drive enhancement circuit 05. It should be noted that, in this structure, the above-mentioned second intermediate node Q2_n (i.e., the node NPc_n) is a connection node between the first inverter INV1 and the first transmission gate Tg1.

[0178] Optionally, with continuous reference to FIGS. 12-19, it can be seen that the drive enhancement circuit 05 can include at least one third inverter INV3 connected in series between the output control circuit 02 and the output terminal OUT_n, and in the case where the drive enhancement circuit 05 includes multiple third inverters INV3, the multiple third inverters INV3 can be connected in series between the output control circuit 02 and the output terminal OUT_n in turn. That is, the input terminal of the first third inverter INV3 is connected with the output control circuit 02, the input terminal of the other third inverters INV3 is connected with the output terminal of the previous third inverter INV3 connected in series, and the output terminal of the last third inverter INV3 is connected with the output terminal OUT_n.

[0179] For example, with the structure shown in FIG. 11 as an example, with reference to FIGS. 12-16, it can be seen that the first drive enhancement sub-circuit 051 connected with the first output terminal OUTN_n can include an even number of third inverters INV3 connected in series in turn, for performing even times of inverting processing on the potential of the output signal of the output control circuit 02 and then outputting to the first output terminal OUTN_n. And the second drive enhancement sub-circuit 052 connected with the second output terminal OUTP_n can include an odd number of third inverters INV3 connected in series in turn, for performing odd times of inverting processing on the potential of the output signal of the output control circuit 02 and then outputting to the second output terminal OUTP_n.

[0180] Optionally, in some embodiments, the first drive enhancement sub-circuit 051 and the second drive enhancement sub-circuit 052 can share at least one third inverter INV3. In this way, the structure can be simplified and the cost can be saved.

[0181] For example, with reference to FIGS. 12-16, it can be seen that the first drive enhancement sub-circuit 051 shown therein each includes two third inverters INV3-1 and INV3-2, and the second drive enhancement sub-circuit 052 each includes three third inverters INV3-1, INV3-3 and INV3-4, that is, the first drive enhancement sub-circuit 051 and the second drive enhancement sub-circuit 052 share the third inverter INV3-1.

[0182] It can be understood that by providing that the drive enhancement circuit 05 includes multiple third inverters INV3 connected in series, the driving capability of the output signal output through the output terminal OUT_n can be amplified step by step, and the driving capability can be better enhanced.

[0183] Optionally, with continuous reference to FIGS. 12-19, it can be seen that the switch control circuit 03 can include at least two third transmission gates Tg3.

[0184] And, at least two third transmission gates Tg3 can be connected in series between the enable terminal EN and the output control circuit 02 in turn, and also connected with the at least two first control terminals Con11 and Con12 and the at least two second control terminals Con21 and Con22 respectively one by one, and each third transmission gate Tg3 can be connected with one first control terminal and one second control terminal respectively one by one.

[0185] For example, as shown in FIG. 12 and FIG. 19, the switch control circuit 03 shown in the figures each includes two third transmission gates Tg3-1 and Tg3-2. And, the third transmission gate Tg3-1 is connected with the first control terminal Con11 and the second control terminal Con21 respectively one by one, and the first control terminal Con11 is connected with the second intermediate node Q2_n-1 (i.e., NPc_n-1) of the previous stage shift register unit in the cascade, and the second control terminal Con21 is connected with the first intermediate node Q1_n-1 (i.e., NNc_n-1) of the previous stage shift register unit in the cascade. The third transmission gate Tg3-2 is connected with the first control terminal Con12 and the second control terminal Con22 respectively one by one, and the first control terminal Con12 is connected with the first intermediate node Q1_n (i.e., NNc_n) of the shift register unit, and the second control terminal Con22 is connected with the second intermediate node Q2_n (i.e., NPc_n) of the shift register unit. On this basis, it can be known that for the third transmission gates Tg3-1 and Tg3-2, when the potential of the stage transmission signal provided by NPc_n-1 is low, the potential of the stage transmission signal provided by NNc_n-1 is high, and the potential of the signal provided by NNc_n is low and the potential of the signal provided by NPc_n is high in the current stage shift register unit, the two third transmission gates Tg3-1 and Tg3-2 can be turned on at the same time, so that the enable terminal EN is connected to the output control circuit 02. For example, connected to the two-input NAND gate NAND shown in FIG. 19.

[0186] Optionally, based on the structure shown in FIG. 12 to FIG. 19, on the basis that the pulse width of the low potential 0 of the clock signal provided by the clock terminal CK and the clock signal provided by the clock terminal CB is smaller than 1H by about 0 to 2 μs, the first transmission gate Tg1 and the second transmission gate Tg2 can be prevented from being turned on at the same time, and the risk of competition between the gate circuit in the first output control sub-circuit 021 and the first inverter INV1 in the latch circuit 04 can be avoided.

[0187] That is, the embodiments of the present application can provide the following various embodiments of the shift register unit:

[0188] In the embodiment 1, referring to FIG. 12, the shift register unit can include four transmission gates (i.e., a first transmission gate Tg1, a second transmission gate Tg2, and two third transmission gates Tg3-1 and Tg3-2), one NOR gate, and seven inverters (i.e., a first inverter INV1, two second inverters INV2-1 and INV2-2, and four third inverters INV3-1, INV3-2, INV3-3, and INV3-4), totally 12 gate circuits. Among them, the third inverters INV3-1 and INV3-2 belong to the first driving enhancement sub-circuit 051 and are connected with the first output terminal OUTN_n; the third inverters INV3-1, INV3-3, and INV3-4 belong to the second driving enhancement sub-circuit 052 and are connected with the second output terminal OUTP_n. That is, the output terminal OUT_n can include the first output terminal OUTN_n and the second output terminal OUTP_n.

[0189] The pulse width of the output of the shift register unit is adjustable. In normal output or in the high brush area, the potential of the enable signal provided by the enable terminal EN can be set to low, that is, the potential of the control enable signal is set to low, to ensure normal output of the display driving signal. In reset (such as power-on of the display panel, power-off, or porch period) or in the low brush area, the potential of the enable signal provided by the enable terminal EN can be set to high, that is, the potential of the control enable signal is set to high, so that the potential of the first output terminal OUTN_n and the potential of the second output terminal OUTP_n controlled by the shift register unit are both invalid, to realize output reset without resetting the stage transfer signal.

[0190] It can be understood that the matching of the enable signal with the clock signals provided by the clock terminals CK and CB is taken as an example of 2H as a period. In some other embodiments, in other period scenarios, the enable signal can be matched with more clock signals provided by more clock terminals.

[0191] In the embodiment 2, referring to FIG. 13, the shift register unit can include four transmission gates (i.e., a first transmission gate Tg1, a second transmission gate Tg2, and two third transmission gates Tg3-1 and Tg3-2), one NOR gate, and seven inverters (i.e., a first inverter INV1, two second inverters INV2-1 and INV2-2, and four third inverters INV3-1, INV3-2, INV3-3, and INV3-4), totally 12 gate circuits. The difference from the embodiment 1 shown in FIG. 12 is that a reset control terminal Trst is added, and the two-input NOR gate is changed to a three-input NOR gate accordingly.

[0192] It can be understood that, in combination with the foregoing, on the basis of the structure, the potential of the reset control signal provided by the reset control end Trst can be set to a high potential during the power-on or power-off or porch period of the display panel, so that the potential of the first output end OUTN_n and the potential of the second output end OUTP_n are both invalid potentials, and output reset is realized. Here, all the shift register units can be globally reset to the output signals. In this way, the reliability of power-on and power-off can be improved.

[0193] In embodiment 3, referring to FIG. 14, the shift register unit can include four transmission gates (i.e., a first transmission gate Tg1, a second transmission gate Tg2, and two third transmission gates Tg3-1 and Tg3-2), a NAND gate, and seven NOT gates (i.e., a first NOT gate INV1, two second NOT gates INV2-1 and INV2-2, and four third NOT gates INV3-1, INV3-2, INV3-3, and INV3-4), a total of 12 gate circuits. The difference from embodiment 2 shown in FIG. 13 is that the three-input NOR gate is changed to a three-input NAND gate. On the basis of the structure, based on the logic operation mode, the difference from the driving mode of the structure shown in FIG. 13 is that the potential of the reset control signal provided by the reset control end Trst can be set to a low potential during the power-on or power-off or porch period of the display panel, so that the potential of the first output end OUTN_n and the potential of the second output end OUTP_n are both invalid potentials, and output reset is realized, thereby improving the reliability of power-on and power-off.

[0194] In embodiment 4, referring to FIG. 15, the shift register unit can include four transmission gates (i.e., a first transmission gate Tg1, a second transmission gate Tg2, and two third transmission gates Tg3-1 and Tg3-2), a NOR gate, a NAND gate, and six NOT gates (i.e., a first NOT gate INV1, a second NOT gate INV2, and four third NOT gates INV3-1, INV3-2, INV3-3, and INV3-4), a total of 12 gate circuits. The difference from embodiment 1 shown in FIG. 12 is that the second NOT gate INV2-2 is replaced by a two-input NAND gate, and the reset control end Trst is connected to the NAND gate.

[0195] It can be understood that, in combination with the foregoing, on the basis of the structure, the potential of the reset control signal provided by the reset control end Trst can be set to a low potential during the power-on or power-off or porch period of the display panel, so that the potential of the first output end OUTN_n and the potential of the second output end OUTP_n are both invalid potentials, and output reset is realized, thereby improving the reliability of power-on and power-off.

[0196] Embodiment 5, referring to FIG. 16, the shift register unit can include four transmission gates (i.e., a first transmission gate Tg1, a second transmission gate Tg2, and two third transmission gates Tg3-1 and Tg3-2), one NOR gate, one NAND gate, and six NOT gates (i.e., a first NOT gate INV1, a second NOT gate INV2, and four third NOT gates INV3-1, INV3-2, INV3-3, and INV3-4) for a total of 12 gate circuits. The difference from the embodiment 4 shown in FIG. 15 is that the NAND gate is exchanged with the NOR gate. Based on the logic operation mode, the difference from the driving mode of the structure shown in FIG. 15 is that, when the display panel is powered on or powered off or in the porch period, the potential of the reset control signal provided by the reset control end Trst is set to a high potential to control the potential of the first output end OUTN_n and the potential of the second output end OUTP_n to be invalid potentials, so as to realize output reset, thereby improving the reliability of power on and power off.

[0197] Embodiment 6, referring to FIG. 17, the shift register unit can include four transmission gates (i.e., a first transmission gate Tg1, a second transmission gate Tg2, and two third transmission gates Tg3-1 and Tg3-2), two NOR gates (i.e., NOR-1 and NOR-2), and four NOT gates (i.e., a first NOT gate INV1, a second NOT gate INV2, and two third NOT gates INV3-1 and INV3-2) for a total of 10 gate circuits. The difference from the embodiment 1 shown in FIG. 12 is that the second NOT gate INV2-1 is replaced by the NOR gate NOR-1, and the NOR gate NOR-1 is connected with the reset control end Trst, and only the driving enhancement circuit 05 is connected with the first output end OUTN_n, and four groups of clock signals are adopted.

[0198] Embodiment 7, referring to FIG. 18, the shift register unit can include four transmission gates (i.e., a first transmission gate Tg1, a second transmission gate Tg2, and two third transmission gates Tg3-1 and Tg3-2), two NOR gates (i.e., NOR-1 and NOR-2), and four NOT gates (i.e., a first NOT gate INV1, and three third NOT gates INV3-1, INV3-2, and INV3-3) for a total of 10 gate circuits. The difference from the embodiment 6 shown in FIG. 17 is that the first NOT gate INV1 and the second NOT gate INV2 are shared, and only the driving enhancement circuit 05 is connected with the second output end OUTP_n.

[0199] In the embodiment 8, as shown in FIG. 19, the shift register unit can include four transfer gates (i.e., a first transfer gate Tg1, a second transfer gate Tg2, and two third transfer gates Tg3-1 and Tg3-2), a NOR gate, a NAND gate, and four NOT gates (i.e., a first NOT gate INV1, and three third NOT gates INV3-1, INV3-2, and INV3-3), totally ten gate circuits. The difference from the embodiment 6 of FIG. 17 is that the second NOT gate INV2 is deleted, the NOR gate NOR-2 is replaced by the NAND gate NAND, and the driving enhancement circuit 05 is only connected to the second output terminal OUTP_n.

[0200] It can be understood that the above embodiments are only illustrative, and any gate circuit combination meeting the above control mode can be applied to the embodiments of the present application. For example, the input terminal IN_n can also be connected to the first intermediate node Q1_n-1 (i.e., NNc_n-1) of the previous stage shift register unit. For another example, in FIG. 12 and FIG. 13, the NOR gate can also be migrated to the second NOT gate INV2.

[0201] Alternatively, the shift register unit provided by the embodiments of the present application can have the structure shown in FIG. 19. That is, the input control circuit 01 can include the second transfer gate Tg2; the output control circuit 02 can include a first output control sub-circuit 021 and a second output control sub-circuit 022, and the first output control sub-circuit 021 can include a two-input NOR gate, and the second output control sub-circuit 022 can include a two-input NAND gate; the switch control circuit 03 can include two third transfer gates Tg3-1 and Tg3-2; the shift register unit can further include a latch circuit 04 and a driving enhancement circuit 05, and the latch circuit 04 can include a first NOT gate INV1 and a first transfer gate Tg1, and the driving enhancement circuit 05 can include three third NOT gates INV3-1, INV3-2, and INV3-3.

[0202] The second transfer gate Tg2 can be connected between the input terminal IN_n and the input node Q_n of the shift register unit, and can also be connected to the first clock terminal CKn and the second clock terminal CB, respectively.

[0203] The two input terminals of the two-input NOR gate can be connected to the input node Q_n and the reset control terminal Trst, respectively, and the output terminal of the two-input NOR gate can be connected to the first intermediate node Q1_n.

[0204] An input end of the two-input NAND gate can be connected with the first intermediate node Q1_n, another input end of the two-input NAND gate can be connected with the enable end EN through two third transmission gates Tg3-1 and Tg3-2, an output end of the two-input NAND gate can be connected with the output end OUT_n of the shift register unit through three third inverters INV3-1, INV3-2 and INV3-3, the two third transmission gates Tg3-1 and Tg3-2 are connected in series, the three third inverters INV3-1, INV3-2 and INV3-3 are connected in series, and one of the two third transmission gates Tg3-1 is further connected with the second intermediate node Q2_n-1 and the first intermediate node Q1_n-1 of the previous stage of the shift register unit, and the other of the two third transmission gates Tg3-2 is further connected with the first intermediate node Q1_n and the second intermediate node Q2_n of the shift register unit.

[0205] The input end of the first inverter INV1 can be connected with the first intermediate node Q1_n of the shift register unit, the output end of the first inverter INV1 can be connected with the input node Q_n through the first transmission gate Tg1, and the first transmission gate Tg1 is further connected with the third clock end CBn and the fourth clock end CK.

[0206] Furthermore, the output end OUT_n of the shift register unit can be used to be connected with the N-type transistor in the pixel. For example, in combination with FIG. 2, the gate signal end Gate_N connected with the N-type transistor T2.

[0207] Optionally, based on FIG. 15, FIG. 18 and FIG. 19, FIG. 20 to FIG. 22 also respectively show the TFT structure schematic diagram of the shift register unit. Taking the structure of FIG. 15 as an example, it can be seen from FIG. 20 that the circuit structure shown in FIG. 15 can include 14 PMOS TFTs and 14 NMOS TFTs, that is, a total of 28 TFTs, and the connection relationship is shown in FIG. 20, which will not be described in detail. The circuit structures of other shift register units can be evolved from this, and can be formed by combining and deleting basic modules, which will not be described one by one.

[0208] Optionally, it can also be seen from FIG. 20 to FIG. 22 that each of the plurality of third inverters INV3 can be respectively connected with the first power supply end VGH and the second power supply end VGL, and can be used to work based on the first power supply signal provided by the first power supply end VGH and the second power supply signal VGL provided by the second power supply end. The potential of the first power supply signal can be greater than the potential of the second power supply signal.

[0209] And, the potential of the first power signal provided by the first power terminal VGH connected to the last one of the third inverters INV3 can be greater than or equal to the potential of the first power signal provided by the first power terminal VGH connected to the other third inverters INV3.

[0210] The potential of the second power signal provided by the second power terminal VGL connected to the last one of the third inverters INV3 can be less than or equal to the potential of the second power signal provided by the second power terminal VGL connected to the other third inverters INV3.

[0211] The last one of the third inverters INV3 is the third inverter INV3 connected to the output terminal OUT among the plurality of third inverters INV3.

[0212] For distinction, the first power terminal VGH connected to the last one of the third inverters INV3 is denoted as VGH2, and the first power terminal VGH connected to the other third inverters INV3 is denoted as VGH1. Similarly, the second power terminal VGL connected to the last one of the third inverters INV3 is denoted as VGL2, and the second power terminal VGL connected to the other third inverters INV3 is denoted as VGL1. In addition, the first inverter INV1 and the second inverter INV2 can also be respectively connected to the first power terminal VGH1 and the second power terminal VGL1 to work based on the first power signal and the second power signal.

[0213] That is, in an embodiment, double VGH and double VGL power supply can be adopted. Alternatively, in another embodiment, single VGH and single VGL power supply can also be adopted, that is, any inverter in the shift register unit is connected to the same first power terminal VGH and second power terminal VGL.

[0214] For example, in the structure shown in FIG. 20, generally, the greater the channel width of the transistor, the closer the threshold voltage Vth of the transistor to 0. Thus, for the last one of the third inverters INV3 directly connected to the output terminal OUT, such as the third inverter INV3-4 connected to the second output terminal OUTP_n, for example, the second power terminal VGL:

[0215] If the potential of the second output terminal OUTP_n needs to be controlled to be high, the PMOS TFT in the third inverter INV3-4 needs to be controlled to be turned on, and the NMOS TFT needs to be controlled to be turned off, so that the first power supply terminal VGH2 connected to the third inverter INV3-4 is turned on with the second output terminal OUTP_n, and the first power supply signal with high potential is output to the second output terminal OUTP_n. If the PMOS TFT in the third inverter INV3-4 needs to be turned on, the previous third inverter INV3-3 connected to the third inverter INV3-4 needs to control the second power supply terminal VGL1 to be turned on with the third inverter INV3-4, so as to output the second power supply signal with low potential to the third inverter INV3-4. If the third inverter INV3-3 needs to control the second power supply terminal VGL1 to be turned on with the third inverter INV3-4, it can be known that the NMOS TFT in the third inverter INV3-3 needs to be controlled to be turned on, and the PMOS TFT in the third inverter INV3-3 needs to be controlled to be turned off. Therefore, for the NMOS TFT in the third inverter INV3-4, the gate-source voltage difference Vgs should be equal to the difference between the potential Vgl1 of the second power supply signal provided by the second power supply terminal VGL1 and the potential Vgl2 of the second power supply signal provided by the second power supply terminal VGL2. That is, Vgs = Vgl1-Vgl2. Moreover, if it is needed to ensure that the NMOS TFT in the third inverter INV3-4 can be reliably turned off, the gate-source voltage difference Vgs of the NMOS TFT needs to be controlled to be less than the threshold voltage Vth, that is, Vgs < Vth needs to be met. Since Vgs = Vgl1-Vgl2, it can be known that Vgl1-Vgl2 < Vth needs to be met. Based on this, when dual-VGL power supply is adopted, Vgl1-Vgl2 < Vth can be met by adjusting the potential Vgl2 of the second power supply signal provided by the second power supply terminal VGL2 to be lower, or adjusting the potential Vgl1 of the second power supply signal provided by the second power supply terminal VGL1 to be higher, so as to ensure that the NMOS TFT in the third inverter INV3-4 can be completely turned off, and the shift register unit can reliably control the potential of the second output terminal OUTP_n to be high. That is, the absolute value of the potential Vgl2 of the second power supply signal provided by the second power supply terminal VGL2 can be set to be smaller than the absolute value of the potential Vgl1 of the second power supply signal provided by the second power supply terminal VGL1. For example, the potential Vgl2 of the second power supply signal provided by the second power supply terminal VGL2 can be -5V, and the potential Vgl1 of the second power supply signal provided by the second power supply terminal VGL1 can be -7V.

[0216] The first power supply end VGH is the same. For example, still taking the third inverter INV3-4 connected to the second output end OUTP_n in FIG. 20 as an example, when double VGL power supply is adopted, the potential Vgh1 of the first power supply signal provided by the first power supply end VGH1 can be adjusted to be lower, or the potential Vgh2 of the first power supply signal provided by the first power supply end VGH2 can be adjusted to be higher, so that Vgh1-Vgh2Vth, and then the PMOS TFT in the third inverter INV3-4 can be completely turned off, only the NMOS TFT is turned on, so that the second power supply end VGL2 and the second output end OUTP_n are turned on, and the second output end OUTP_n outputs the second power supply signal with low potential. That is, the shift register unit can reliably control the potential of the second output end OUTP_n to be low.

[0217] In addition, by adopting double VGH and double VGL power supply, the charging and discharging speed of the third inverter INV3 directly connected to the output end OUT_n can be accelerated, thereby further improving the driving capability of the shift register unit, and the leakage current can be reduced and the power consumption can be saved.

[0218] Of course, in some other embodiments, it is not limited to double VGH and double VGL power supply. For example, referring to FIG. 20, the third inverter INV3-2 connected to the first input end OUTN_n can also be connected to the first power supply end VGH3 and the second power supply end VGL3 respectively, that is, triple VGH and triple VGL power supply can be adopted.

[0219] In addition, the potential of the first power supply signal provided by the first power supply end VGH3 can be the same as the potential of the first power supply signal provided by the first power supply end VGH2 or the first power supply end VGH1; or the potential of the first power supply signal provided by the first power supply end VGH3 can be different from the potential of the first power supply signal provided by the first power supply end VGH2 and the first power supply end VGH1, that is, the first power supply end VGH3, VGH2 and VGH1 can be independent of each other. The second power supply end VGL3 is the same, that is, the potential of the second power supply signal provided by the second power supply end VGL3 can be the same as the potential of the second power supply signal provided by the second power supply end VGL2 or the second power supply end VGL1; or the potential of the second power supply signal provided by the second power supply end VGL3 can be different from the potential of the second power supply signal provided by the second power supply end VGL2 and the second power supply end VGL1, that is, the second power supply end VGL3, VGL2 and VGL1 can be independent of each other.

[0220] It can be understood that, on the basis that the first power supply ends VGH3 and VGH2 are independent of each other, and the second power supply ends VGL3 and VGL2 are independent of each other, it can be considered that the third inverters INV3 connected to the first output end OUTN_n and the third inverters INV3 connected to the second output end OUTP_n are connected to different first power supply ends VGH and different second power supply ends VGL, respectively.

[0221] Optionally, on the basis of the foregoing, it can be known that, in some embodiments, as shown in FIG. 23, the shift register unit provided in the embodiments of the present application can actually be divided into three modules: an input shift module, a transmission and control module, and a driving enhancement module.

[0222] For example, taking the structure shown in FIG. 6 as an example, the input shift module can refer to a module composed of a circuit that controls the potential of the first intermediate node Q1_n based on the input signal provided by the input end IN_n; the transmission and control module can refer to a module composed of a circuit that controls the potential received by one end of the driving enhancement circuit 05 based on the potential of the first intermediate node Q1_n; and the driving enhancement module can refer to the driving enhancement circuit 05. Moreover, the shift register unit can be connected to at least the following signal ends: VGH, VGL, CK, CB, NPc_n-1, NNc_n-1, Trst, EN, NPc_n, NNc_n, OUTN_n, and OUTP_n. The connection mode is referred to FIG. 23, and will not be described here again.

[0223] In conclusion, the embodiments of the present disclosure provide a shift register unit. The shift register unit includes an input control circuit, an output control circuit, and a switch control circuit. The input control circuit can control the on-off of the input end and the input node under the control of the clock signals provided by the first clock end and the second clock end. The output control circuit can output a display driving signal to a pixel through the output end to drive the pixel to emit light based on the potential of the input node and the enable signal provided by the enable end. The switch control circuit can control the on-off of the enable end and the output control circuit under the control of the control signals provided by the first control end and the second control end. In this way, the enable end can be selected to be connected or not connected to the output control circuit by flexibly setting the control signals. On the basis that the enable end is connected to the output control circuit, the output control circuit can control the potential of the output end to output the required driving signal to the pixel to drive the pixel to emit light. On this basis, the shift register unit can further output a display driving signal matching the P-type transistor and / or the N-type transistor in the pixel to the output end by flexibly setting the enable signal and the clock signal. It can be known that the driving mode of the shift register unit is rich, and the working power consumption is small.

[0224] The embodiment of the present application further provides a driving method of the shift register unit, which can be used to drive the shift register unit as described above. As shown in FIG. 24, the method comprises the following steps:

[0225] In step 2401, in response to a first scan instruction, a first clock signal is provided to the first clock terminal, a second clock signal is provided to the second clock terminal, and an enable signal of a first potential is provided to the enable terminal.

[0226] In step 2402, in response to a second scan instruction, the first clock signal is provided to the first clock terminal, the second clock signal is provided to the second clock terminal, and an enable signal of a second potential is provided to the enable terminal.

[0227] The first clock signal and the second clock signal are used to drive the input control circuit to control the on-off of the input terminal and the input node. The enable signal is used to drive the output control circuit to control the potential of the output terminal based on the potential of the input node and the enable signal, so as to output the gate drive signal through the data writing transistor in the pixel or output the reset signal through the reset transistor in the pixel. In addition, the refresh frequency indicated by the first scan instruction is greater than the refresh frequency indicated by the second scan instruction. That is, the refresh area indicated by the first scan instruction can be a high refresh area, and the refresh area indicated by the second scan instruction can be a low refresh area.

[0228] Optionally, taking the structure shown in FIGS. 12-16 as an example, FIG. 25 shows a driving timing diagram of the shift register unit. Based on the structure shown in FIG. 20, FIG. 26 further shows a signal simulation schematic diagram. As shown in FIGS. 25 and 26, a set of inverted clock signals provided by the clock terminals CK and CB, and a set of display driving signals NP_n and NN_n outputted are shown. In addition, a set of stage transmission signals provided by the nodes NPc_n-1 and NNc_n-1 in the previous stage shift register unit, and a set of stage transmission signals NNp_n and NNc_n outputted are shown in FIG. 25. In addition, an opening signal provided by the opening signal terminal STV is shown in FIG. 26. The timing relationship is shown in the figures and will not be described herein. In addition, as can be seen from FIGS. 25 and 26, the pulse width of the low potential in the stage transmission signal provided by NPc_n-1 can be an integer multiple of the clock signal period provided by the clock terminal CK, so as to ensure complete output of the display driving signal. The non-integer multiple is generally reduced to an integer multiple of the pulse width.

[0229] In addition, the enable signal provided by the enable terminal EN and the reset control signal provided by the reset control terminal Trst are not shown in FIGS. 25 and 26. In combination with the structure shown in FIG. 20, a brief description is given as follows:

[0230] When the display panel is powered on or off or in the porch period, the potential of the reset control signal can be set low, so as to reset the output signal and the stage transfer signal, and improve the power-on and power-off reliability; in other periods, the potential of the reset control signal can be set high. In the normal output or in the high brush area, the potential of the enable signal can be set low to ensure the normal output of the shift register unit; in the reset or in the low brush area, the potential of the enable signal can be set high to reset the output signal without resetting the stage transfer signal. In addition, the enable signal can be transmitted to the shift register unit stage by stage. For example, when the previous stage of the cascaded shift register unit outputs the high potential stage transfer signal to the first intermediate node Q1_n-1 (i.e., NNc_n-1), and outputs the low potential stage transfer signal to the second intermediate node Q2_n-1 (i.e., NPc_n-1), and the current stage of the shift register unit outputs the low potential stage transfer signal to the first intermediate node Q1_n (i.e., NNc_n), and outputs the high potential stage transfer signal to the second intermediate node Q2_n (i.e., NPc_n), the enable signal is transmitted to the current stage of the shift register unit, so as to reset only the shift register unit at the stage transfer starting boundary, without resetting the shift register unit which has started but not completed the stage transfer. In this way, compared with resetting all outputs, the working power consumption can be reduced on the basis of meeting the local brush output requirement. It can be understood that the driving timing of other structures can be derived from the timing diagram of FIG. 25, which will not be described here.

[0231] Optionally, taking the circuit structure shown in FIGS. 12, 13 and 15, i.e., the NOR gate connected with the enable end EN, as an example, FIG. 27 shows a local brush driving timing diagram of a shift register unit. Taking the circuit structure shown in FIGS. 14 and 16, i.e., the NAND gate connected with the enable end EN, as an example, FIG. 28 shows another local brush driving timing diagram of a shift register unit.

[0232] As can be seen from FIGS. 27 and 28, on the basis of the NOR gate connected with the enable end EN, in any low brush area (two low brush areas and one high brush area are shown in the diagram), the enable signal provided by the enable end EN can be set high to reset the output. On the basis of the NAND gate connected with the enable end EN, in any low brush area, the enable signal provided by the enable end EN can be set low to reset the output. In addition, as can be seen from FIGS. 27 and 28, in the high brush area, the enable signal provided by the enable end EN can be set to the opposite potential of the low brush area to control the normal output of the shift register unit.

[0233] Optionally, taking the circuit structure shown in FIGS. 21 and 22 as an example, FIGS. 29 and 30 respectively show the driving timing diagram of another shift register unit, including the timing of A. high brush area and B. low brush area.

[0234] As shown in FIGS. 29 and 30, four groups of clock signals are provided, each of which can satisfy the above description and will not be repeated here. For the circuit structure shown in FIGS. 21 and 22, when the display panel is powered on or powered off, the reset control signal provided by the high reset control terminal Trst can be set to high, i.e., the potential of the reset control signal is high, so as to control the potential of the output terminal NP_n to be invalid (e.g., high), thereby resetting the output signal.

[0235] For the structure shown in FIG. 21, as shown in FIG. 29, in the high brush area, the enable signal provided by the enable terminal EN can be set to low, i.e., the potential of the enable signal is low, so that the potential of the output signal of the NOR-2 gate changes with the potential of NPc_n, i.e., the shift register unit normally outputs; in the low brush area, the enable signal provided by the enable terminal EN can be set to high, i.e., the potential of the enable signal is high, so that the potential of the output signal of the NOR-2 gate remains low and does not change with the potential of NPc_n. Further, the potential of the output terminal NP_n can be kept high, i.e., the potential of the display driving signal output to the pixel is invalid, and the corresponding switch in the pixel is not turned on. For the structure shown in FIG. 22, as shown in FIG. 30, in the high brush area, the enable signal provided by the enable terminal EN can be set to high, i.e., the potential of the enable signal is high, so that the potential of the output signal of the NAND gate changes with the potential of NNc_n, i.e., the shift register unit normally outputs; in the low brush area, the enable signal provided by the enable terminal EN can be set to low, i.e., the potential of the enable signal is low, so that the potential of the output signal of the NAND gate remains high and does not change with the potential of NNc_n. Further, the potential of the output terminal NN_n can be kept low, i.e., the potential of the display driving signal output to the pixel is invalid, and the corresponding switch in the pixel is not turned on.

[0236] Continuing to combine FIGS. 21 and 29, the driving principle of the shift register unit is described as follows:

[0237] Firstly, in the first stage t01 of the high brush area, a high potential first clock signal can be provided to the first clock end CKn, and a low potential second clock signal can be provided to the second clock end CB, so that the second transmission gate Tg2 is turned on. Further, the input end IN_n and the input node Q_n are turned on, and the input end IN_n (i.e., NPc_n-1) can output an input signal to the input node Q_n, and the potential of the output input signal can be high. In addition, a high potential reset control signal can be provided to the reset control end Trst, and then the potential of the node NNc_n can be controlled to be low through the NOR-1, and the potential of the node NPc_n can be controlled to be high through the second inverter INV2. Since the potential of the node NPc_n-1 is high, it can be known that the potential of the node NNc_n-1 is low, so that the transmission gate Tg3-1 is turned off, and the enable end EN is disconnected from the NOR-2. Since the potential of the node NPc_n is high, a low potential signal can be output through the NOR-2, and the low potential signal can make the potential of the output end NP_n high through the odd number of third inverters INV3. In addition, in the first stage t01, a low potential third clock signal can be provided to the third clock end CBn, and a high potential fourth clock signal can be provided to the fourth clock end CK, so that the first transmission gate Tg1 is turned off, and the node NNc_n is disconnected from the input node Q_n.

[0238] It can be understood that, as shown in FIG. 29, the pulse width of the low potential of the clock signal provided by the clock end CK and the clock signal provided by the clock end CB is less than the pulse width of the high potential, generally about 0 to 2 μs less than 1H, which can be flexibly selected according to the load RC. On the basis of the setting, the influence of clock delay can be eliminated, and the first transmission gate Tg1 and the second transmission gate Tg2 are avoided from being turned on at the same time, so as to cause the gate circuit (such as the NOR-1 shown in FIG. 21) in the first output control sub-circuit 021 and the first inverter INV1 in the latch circuit 04 to compete when the input state is switched, that is, when the potential of the input signal provided by the input end IN_n changes.

[0239] Secondly, in the second stage t02 of the high brush area, a low potential first clock signal can be provided to the first clock end CKn, and a high potential second clock signal can be provided to the second clock end CB, so that the second transmission gate Tg2 is turned off, and then the input end IN_n is disconnected from the input node Q_n. A high potential third clock signal can be provided to the third clock end CBn, and a low potential fourth clock signal can be provided to the fourth clock end CK, so that the first transmission gate Tg2 is turned on, and then the node NNc_n is connected to the input node Q_n, so that the potential of the input node Q_n is latched as the high potential of the node NPc_n. In addition, a low potential reset control signal can be provided to the reset control end Trst, so that the potential of the node NNc_n can be controlled as a low potential after the NOR-1, and the potential of the node NPc_n can be controlled as a high potential after the second inverter INV2. Since the potential of the node NPc_n-1 is a low potential, it can be known that the potential of the node NNc_n-1 is a high potential, so that the transmission gate Tg3-1 is turned on. Since the potential of the node NPc_n is a high potential, and the potential of the node NNc_n is a low potential, the transmission gate Tg3-2 is turned on. Then, the enable end EN and the NOR-2 are turned on, and the NOR-2 can control the potential of the output signal based on the enable signal provided by the enable end EN. At this time, as shown in FIG. 29, the potential of the enable signal is a low potential, and the potential of the node NPc_n is a high potential, so that the NOR-2 can output a low potential signal, and the low potential signal can make the potential of the output end NP_n a high potential after passing through an odd number of third inverters INV3.

[0240] In the third stage t03, the first clock signal with high potential can be provided to the first clock terminal CKn, and the second clock signal with low potential can be provided to the second clock terminal CB, so that the second transmission gate Tg2 is turned on, and then the input terminal IN_n is turned on with the input node Q_n, and the input terminal IN_n can output the input signal to the input node Q_n, and the potential (NPc_n-1) of the input signal can be low potential. In addition, the reset control signal with low potential can be provided to the reset control terminal Trst, and then the potential of the node NNc_n can be high potential after the NOR-1, and the potential of the node NPc_n can be low potential after the second inverter INV2. Since the potential of the node NPc_n-1 is low potential, it can be known that the potential of the node NNc_n-1 is high potential, and the transmission gate Tg3-1 is turned on. Since the potential of the node NPc_n is low potential, and the potential of the node NNc_n is high potential, the transmission gate Tg3-2 is turned off. Then, the enable terminal EN can be disconnected with the NOR-2. The potential of the enable signal can remain the low potential of the last stage, and since the potential of the node NPc_n is low potential, the high potential signal can be output from the NOR-2, and the potential of the output terminal NP_n can be low potential after the odd number of third inverters INV3. In addition, in the third stage t03, the third clock signal with low potential can be provided to the third clock terminal CBn, and the fourth clock signal with high potential can be provided to the fourth clock terminal CK, so that the first transmission gate Tg1 is turned off, and then the node NNc_n is disconnected with the input node Q_n.

[0241] The difference is that, in the low brush area, since the potential of the enable signal remains high potential, the potential of the output signal of the NOR-2 can remain low potential as described above, and then the low potential signal can make the potential of the output terminal NP_n remain high potential after the odd number of third inverters INV3 as shown in FIG. 29. The working principles of other stages are combined with the timing shown in FIG. 29, and will not be described one by one.

[0242] Optionally, the shift register unit can also be connected with a display driver IC (DIC), and be used to receive the signals provided by the DIC, such as the clock signal. That is, the DIC can provide the required signals to each signal terminal connected with the shift register unit, so that the shift register unit can output the required display driving signal to the pixel.

[0243] It can be understood that the driving mode of the shift register unit of other structures is the same, and will not be described one by one. In addition, since the driving method of the shift register unit can have basically the same technical effects as the shift register units described in the foregoing embodiments, for the purpose of brevity, the technical effects of the driving method of the shift register unit will not be described again here.

[0244] The embodiments of the present application also provide a display driver. As shown in FIG. 31, the display driver includes at least two cascade-connected shift register units GOA as described above.

[0245] For example, the shift register unit GOA shown in FIG. 31 is a shift register unit NGate GOA connected to the gate signal end Gate_N of the N-type transistor, that is, the output end OUT_n is connected to the gate signal end Gate_N of the pixel. Correspondingly, the display driver including the NGate GOA can also be referred to as a gate driving circuit. In addition, in the display driver shown in FIG. 31, four groups of clock signals (including four clock signal ends CK, CB, CKn and CBn) are used, and double VGH and double VGL (including first power supply ends VGH1 and VGH2, and second power supply ends VGL1 and VGL2) are used for power supply. In addition, the cascade connection mode is that the input end IN_1 of the first shift register unit NGate GOA is connected to the start signal end STV, and the input ends (such as IN_2, IN_n-1 and IN_n) of the other shift register units NGate GOA are connected to the second intermediate node Q2_n (that is, the node NPc_n) of the previous shift register unit NGate GOA. In addition, each shift register unit can also be connected to the node NNc_n-1 of the previous shift register unit to receive the stage transmission signal provided by the node NNc_n-1. Here, the third transmission gate Tg3-1 included in the shift register unit can be connected to the node NNc_n-1.

[0246] It can be understood that, since the potential of the node NNc_n and the potential of the node NPc_n are opposite potentials, for the first shift register unit, an inverter F1, also referred to as a NOT gate, can be added between the start signal end STV and the third transmission gate Tg3-1 to receive a signal with a potential opposite to that of the start signal. For other structures, reference can be made to the related description of the foregoing shift register unit, which will not be described one by one.

[0247] Optionally, in some embodiments, dummy shift register units, that is, dummy GOAs, can also be added in the first row or the last row to meet the required timing requirements or driving load.

[0248] It can be understood that the display driver has substantially the same technical effects as the shift register unit described in the foregoing embodiments, and thus the technical effects of the display driver are not repeated here for the sake of brevity.

[0249] The embodiments of the present application further provide a display device. As shown in FIG. 32, the display device includes the display panel 10 and the display driver 00 as shown in FIG. 31.

[0250] In combination with FIG. 2, the display panel 10 includes a plurality of pixels (not shown in FIG. 32), and the display driver 00 is connected with the plurality of pixels, such as the gate signal terminal Gate_N of the pixels, and is configured to transmit a gate driving signal or a reset signal to the plurality of pixels to drive the plurality of pixels to emit light.

[0251] It can be understood that the display device has substantially the same technical effects as the shift register unit described in the foregoing embodiments, and thus the technical effects of the display device are not repeated here for the sake of brevity.

[0252] Optionally, the display device can be an OLED display device, an active-matrix OLED (AMOLED) display device, or any product or component having a display function. The display device can also be any appropriate display device, including but not limited to a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and an e-book.

[0253] It can be understood that the terms used in the embodiments of the present application are only used to explain the embodiments, and are not intended to limit the present application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be understood as the common meanings understood by those skilled in the art.

[0254] For example, the use of words like "first," "second," "third," and similar terms does not indicate any order, quantity, or importance, but is merely used to distinguish different components. Similarly, words like "a" or "one" do not indicate a quantity limitation, but rather the presence of at least one. Words like "include" or "contain" mean that the element or object preceding "includes" covers the element or object listed after "includes" or "contains," and does not exclude other elements or objects. Words like "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up," "down," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly. "And / or" indicates that three relationships can exist; for example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following objects have an "or" relationship.

[0255] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A shift register unit, comprising: an input control circuit connected with a first clock terminal, a second clock terminal, an input terminal and an input node respectively, and configured to control the input terminal and the input node in response to a first clock signal provided by the first clock terminal and a second clock signal provided by the second clock terminal; an output control circuit connected with the input node, an enable terminal and an output terminal respectively, and configured to control the potential of the output terminal based on the potential of the input node and an enable signal provided by the enable terminal, so as to output a gate drive signal to a data write transistor in a pixel or a reset signal to a reset transistor in the pixel through the output terminal, so as to drive the pixel to emit light; a switch control circuit connected between the enable terminal and the output control circuit, and further connected with at least two first control terminals and at least two second control terminals respectively, and configured to control the enable terminal and the output control circuit in response to a first control signal provided by each of the first control terminals and a second control signal provided by each of the second control terminals.

2. The shift register cell of claim 1, wherein, The output control circuit comprises: a first output control sub-circuit connected with the input node and a first intermediate node respectively, and configured to control the potential of the first intermediate node based on the potential of the input node; a second output control sub-circuit connected with the first intermediate node, the enable terminal and the output terminal respectively, and configured to control the potential of the output terminal based on the potential of the first intermediate node and the enable signal.

3. The shift register cell of claim 2, wherein, The second output control sub-circuit comprises: a first output control unit connected with the first intermediate node and a second intermediate node respectively, and configured to control the potential of the second intermediate node based on the potential of the first intermediate node; a second output control unit connected with the second intermediate node, the enable terminal and the output terminal respectively, and configured to control the potential of the output terminal based on the potential of the second intermediate node and the enable signal.

4. The shift register cell of claim 3, wherein, The first output control unit in the second output control sub-circuit is further connected with a reset control terminal, and is further configured to control the potential of the second intermediate node based on a reset control signal provided by the reset control terminal.

5. The shift register cell of claim 3, wherein, The second output control unit in the second output control sub-circuit is further connected with a reset control terminal, and is further configured to control the potential of the output terminal based on a reset control signal provided by the reset control terminal.

6. The shift register cell of claim 2, wherein, The first output control sub-circuit is further connected with a reset control terminal, and is further configured to control the potential of the first intermediate node based on a reset control signal provided by the reset control terminal.

7. A shift register cell as claimed in any one of claims 3 to 6, wherein, The switch control circuit is connected with two first control terminals and two second control terminals respectively, and the two first control terminals and the two second control terminals correspond to each other one by one; and one first control terminal and one second control terminal corresponding to each other are connected with a second intermediate node and a first intermediate node of a previous shift register unit cascaded with the shift register unit respectively, and the other first control terminal and the other second control terminal corresponding to each other are connected with the first intermediate node and the second intermediate node of the shift register unit respectively.

8. The shift register cell of any one of claims 2 to 7, wherein, The shift register unit further comprises: The latch circuit is connected with the third clock end, the fourth clock end, the first intermediate node and the input node respectively, and is configured to control the on-off of the first intermediate node and the input node in response to a third clock signal provided by the third clock end and a fourth clock signal provided by the fourth clock end, and output the potential of the first intermediate node to the input node after being inverted.

9. The shift register cell of claim 8, wherein, The first clock end and the third clock end are shared, and the second clock end and the fourth clock end are shared.

10. The shift register cell of claim 8 or 9, wherein, The latch circuit comprises a first NAND gate and a first transmission gate connected in series between the first intermediate node and the input node, and the first transmission gate is further connected with the third clock end and the fourth clock end respectively.

11. The shift register cell of claim 10, wherein, The circuit connected with the enable end or the reset control end in the first output control sub-circuit and the second output control sub-circuit comprises a NOR gate or a NAND gate, and the circuit not connected with the enable end and the reset control end comprises a second NAND gate. In the case that the first output control sub-circuit is connected with the reset control end and the second output control sub-circuit is not connected with the reset control end, the first NAND gate included in the latch circuit is shared with the second NAND gate included in the second output control sub-circuit.

12. The shift register cell of any one of claims 1 to 11, wherein, The shift register unit further comprises: The driving enhancement circuit is connected between the output control circuit and the output end, and is configured to output the potential of the output signal of the output control circuit to the output end after at least one inversion.

13. The shift register cell of claim 12, wherein, The driving enhancement circuit comprises at least one third NAND gate connected in series between the output control circuit and the output end, and in the case that the driving enhancement circuit comprises a plurality of third NAND gates, the plurality of third NAND gates are connected in series between the output control circuit and the output end. Each of the plurality of third NAND gates is further connected with a first power supply end and a second power supply end respectively, and is configured to work based on a first power supply signal provided by the first power supply end and a second power supply signal provided by the second power supply end, wherein the potential of the first power supply signal is greater than the potential of the second power supply signal.

14. The shift register cell of claim 13, wherein, In the plurality of third NAND gates, the first power supply signal provided by the first power supply end connected to the last third NAND gate is greater than or equal to the first power supply signal provided by the first power supply end connected to other third NAND gates, and the last third NAND gate is the third NAND gate connected to the output end in the plurality of third NAND gates.

15. The shift register cell of claim 13 or 14, wherein, In the plurality of third NAND gates, the second power supply signal provided by the second power supply end connected to the last third NAND gate is less than or equal to the second power supply signal provided by the second power supply end connected to other third NAND gates, and the last third NAND gate is the third NAND gate connected to the output end in the plurality of third NAND gates.

16. The shift register cell of any one of claims 13 to 15, wherein, The output end comprises a first output end and a second output end, and in the same period, the potential of the first output end is opposite to the potential of the second output end; the driving enhancement circuit comprises: A first driving enhancer circuit is connected between the output control circuit and the first output terminal, and is configured to output the potential of the output signal of the output control circuit to the first output terminal after performing even times of inverting processing on the output signal of the output control circuit; A second driving enhancer circuit is connected between the output control circuit and the second output terminal, and is configured to output the potential of the output signal of the output control circuit to the second output terminal after performing odd times of inverting processing on the output signal of the output control circuit.

17. The shift register cell of claim 16, wherein, The first driving enhancer circuit comprises an even number of third NAND gates connected in series, and the second driving enhancer circuit comprises an odd number of third NAND gates connected in series, and the first driving enhancer circuit and the second driving enhancer circuit share at least one third NAND gate.

18. The shift register cell of any one of claims 1 to 17, wherein, The input control circuit comprises a second transmission gate; The second transmission gate is connected between the input terminal and the input node, and is further connected with the first clock terminal and the second clock terminal, respectively.

19. The shift register cell of any one of claims 1 to 18, wherein, The switch control circuit comprises at least two third transmission gates; The at least two third transmission gates are connected in series between the enable terminal and the output control circuit, and are further connected with the at least two first control terminals and the at least two second control terminals one by one in a one-to-one correspondence, respectively, and each third transmission gate is connected with one first control terminal and one second control terminal in a one-to-one correspondence, respectively. In a case where the shift register unit is configured to output a gate driving signal to a data writing transistor in a pixel through the output terminal:

20. The shift register cell of any one of claims 1 to 19, wherein, The output terminal of the shift register unit is configured to be connected with an N-type data writing transistor in the pixel, and is configured to output a gate driving signal to the N-type data writing transistor through the output terminal; and / or, The output terminal of the shift register unit is configured to be connected with a P-type data writing transistor in the pixel, and is configured to output a gate driving signal to the P-type data writing transistor through the output terminal. In a case where the shift register unit is configured to output a reset signal to a reset transistor in a pixel through the output terminal:

21. The shift register cell of any one of claims 1 to 19, wherein, The output terminal of the shift register unit is configured to be connected with an N-type reset transistor in the pixel, and is configured to output a reset signal to the N-type reset transistor through the output terminal; and / or, The output terminal of the shift register unit is configured to be connected with a P-type reset transistor in the pixel, and is configured to output a reset signal to the P-type reset transistor through the output terminal. The input control circuit comprises a second transmission gate; the output control circuit comprises a first output control sub-circuit and a second output control sub-circuit, and the first output control sub-circuit comprises a two-input NOR gate, and the second output control sub-circuit comprises a two-input NAND gate; the switch control circuit comprises two third transmission gates; the shift register unit further comprises a latch circuit and a driving enhancement circuit, and the latch circuit comprises a first NAND gate and a first transmission gate, and the driving enhancement circuit comprises three third NAND gates; 22. The shift register cell of any one of claims 1 to 21, wherein, The second transmission gate is connected between the input terminal of the shift register unit and the input node, and is further connected with the first clock terminal and the second clock terminal, respectively. ​ The two inputs of the two-input NOR gate are connected with the input node and the reset control terminal respectively, and the output of the two-input NOR gate is connected with the first intermediate node; One input of the two-input NOR gate is connected with the first intermediate node, and the other input of the two-input NOR gate is connected with the enable terminal through the two third transmission gates, the output of the two-input NOR gate is connected with the output of the shift register unit through the three third non-gates, the two third transmission gates are connected in series, the three third non-gates are connected in series, one of the two third transmission gates is further connected with the second intermediate node and the first intermediate node of the previous shift register unit in the cascade of the shift register unit respectively, and the other third transmission gate is further connected with the first intermediate node and the second intermediate node of the shift register unit respectively; The input of the first non-gate is connected with the first intermediate node of the shift register unit, the output of the first non-gate is connected with the input node through the first transmission gate, and the first transmission gate is further connected with the third clock terminal and the fourth clock terminal respectively; And the output of the shift register unit is used for being connected with the N-type transistor in the pixel. 23.A driving method of a shift register unit, used for driving the shift register unit according to any one of claims 1 to 22; the method comprising: in response to a first scan instruction, providing a first clock signal to the first clock terminal, providing a second clock signal to the second clock terminal, and providing an enable signal of a first potential to the enable terminal; in response to a second scan instruction, providing a first clock signal to the first clock terminal, providing a second clock signal to the second clock terminal, and providing an enable signal of a second potential to the enable terminal; wherein the first clock signal and the second clock signal are used for driving the input control circuit to control the on-off of the input terminal and the input node; the enable signal is used for driving the output control circuit to control the potential of the output terminal based on the potential of the input node and the enable signal, so as to output a gate driving signal to the data writing transistor in the pixel through the output terminal or output a reset signal to the reset transistor in the pixel, so as to drive the pixel to emit light; and the refresh frequency indicated by the first scan instruction is greater than the refresh frequency indicated by the second scan instruction.

24. A display driver, the display driver comprising: At least two shift register units according to any one of claims 1 to 22 are cascaded.

25. A display device comprising: a display panel, and the display driver according to claim 24; the display panel comprises a plurality of pixels, and the display driver is connected with the plurality of pixels and used for transmitting a gate driving signal or a reset signal to the plurality of pixels, so as to drive the plurality of pixels to emit light.

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