Automatically adaptive streaming access replacement method, cpu core, system on chip

Abstract

The embodiment of the present disclosure provides an automatically adaptive streaming access replacement method, a CPU core and a system-level chip. The method comprises the following steps: if the data prefetch unit monitors that the traversed data range reaches a first threshold according to the received training request of the first-level data cache, marking the backfill request from the second-level data cache to the first-level data cache, so that the backfilled data is marked as the data to be replaced preferentially; if the data prefetch unit monitors that the traversed data range reaches a second threshold, marking the backfill request from the third-level data cache to the second-level data cache, so that the backfilled data is marked as the data to be replaced preferentially, and the second threshold is greater than the first threshold. The embodiment of the present disclosure can keep part of the key data in the first-level data cache when the data is repeatedly accessed in a cycle, and keep part of the key data in the second-level data cache when the data is repeatedly accessed in a cycle, thereby improving the hit rate and reducing the cache miss of the data.

Description

Technical Field

[0001] This disclosure relates to the field of data caching technology, and in particular to an automatically adaptive streaming access replacement method, a CPU core, and a system-on-a-chip. Background Technology

[0002] In modern workloads during routine CPU operation, there are frequent operations involving the regular traversal of large datasets, often with a cyclical nature. However, when the range of data being traversed becomes too large, exceeding the capacity of the CPU's multi-level cache, the cache replacement strategy essentially fails. When the program enters the next loop and repeatedly accesses the data, significant data loss occurs. Furthermore, the large-scale data traversal also causes memory access latency. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide an automatically adaptive streaming access replacement method, a CPU core, and a system-on-a-chip to at least solve or alleviate the above-mentioned problems.

[0004] According to a first aspect of the present disclosure, an automatically adaptive streaming access replacement method is provided, applied to a CPU core. The CPU core includes a level 1 data cache, a level 2 data cache, and a data prefetch unit. The CPU core interacts with a level 3 data cache via an interconnect bus. The method includes: if the data prefetch unit detects that the range of traversed data reaches a first threshold based on a training request received from the level 1 data cache, then it marks a backfill request from the level 2 data cache to the level 1 data cache, and marks the backfilled data as data to be replaced preferentially; if the data prefetch unit detects that the range of traversed data reaches a second threshold, then it marks a backfill request from the level 3 data cache to the level 2 data cache, and marks the backfilled data as data to be replaced preferentially, wherein the second threshold is greater than the first threshold.

[0005] According to a second aspect of the present disclosure, an automatically adaptive streaming access replacement method is provided, applied to a system-on-a-chip (SoC). The SoC includes a CPU core and a three-level data cache. The CPU core includes a first-level data cache, a second-level data cache, and a data prefetching unit. The CPU core interacts with the third-level data cache via an interconnect bus. The method includes: if the data prefetching unit detects that the range of traversed data reaches a first threshold based on a received training request from the first-level data cache, it marks a backfill request from the second-level data cache to the first-level data cache, and marks the backfilled data as data to be replaced preferentially; if the data prefetching unit detects that the range of traversed data reaches a second threshold, it marks a backfill request from the third-level data cache to the second-level data cache, and marks the backfilled data as data to be replaced preferentially; if the data prefetching unit detects that the range of traversed data reaches a third threshold, it marks an eviction request from the second-level data cache to the third-level data cache, and the data evicted from the second-level data cache is no longer allocated to the third-level data cache, wherein the third threshold is greater than the second threshold, and the second threshold is greater than the first threshold.

[0006] According to a third aspect of the present disclosure, a CPU core is provided, the CPU core including a level 1 data cache, a level 2 data cache, and a data prefetch unit. The CPU core interacts with a level 3 data cache via an interconnect bus. The data prefetch unit, based on a received training request from the level 1 data cache, detects that the range of traversed data reaches a first threshold, and then marks a backfill request from the level 2 data cache to the level 1 data cache, making the backfilled data marked as data to be replaced preferentially. The data prefetch unit detects that the range of traversed data reaches a second threshold, and then marks a backfill request from the level 3 data cache to the level 2 data cache, making the backfilled data marked as data to be replaced preferentially, wherein the second threshold is greater than the first threshold.

[0007] According to a fourth aspect of the present disclosure, a system-on-a-chip (SoC) is provided, comprising a CPU core and a three-level data cache. The CPU core includes a first-level data cache, a second-level data cache, and a data prefetching unit. The CPU core interacts with the third-level data cache via an interconnect bus. The data prefetching unit, based on a received training request from the first-level data cache, detects that the range of traversed data reaches a first threshold, and then marks a backfill request from the second-level data cache to the first-level data cache, marking the backfilled data as data to be prioritized for replacement. If the data prefetching unit detects that the range of traversed data reaches a second threshold, it marks a backfill request from the third-level data cache to the second-level data cache, marking the backfilled data as data to be prioritized for replacement. If the data prefetching unit detects that the range of traversed data reaches a third threshold, it marks an eviction request from the second-level data cache to the third-level data cache, preventing the evicted data from the second-level data cache from being allocated to the third-level data cache. The third threshold is greater than the second threshold, and the second threshold is greater than the first threshold.

[0008] According to the automatically adaptive streaming access replacement scheme of this disclosure, the data prefetching unit, based on the received training requests from the first-level data cache, detects that the range of traversed data reaches a first threshold. If so, it marks a backfill request from the second-level data cache to the first-level data cache, making the backfilled data prioritized for replacement. This achieves the goal of retaining some critical data in the first-level data cache during repeated access, improving the hit rate and reducing cache misses. If the data prefetching unit detects that the range of traversed data reaches a second threshold, it marks a backfill request from the third-level data cache to the second-level data cache, making the backfilled data prioritized for replacement. The second threshold is greater than the first threshold. This achieves the goal of retaining some critical data in the second-level data cache during repeated access, improving the hit rate and reducing cache misses. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.

[0010] Figure 1 This is a hardware scenario diagram of an embodiment of the automatically adaptive streaming access replacement method of this disclosure.

[0011] Figure 2 This is a flowchart of an automatically adaptive streaming access replacement method according to another embodiment of this disclosure;

[0012] Figure 3 This is a flowchart of an automatically adaptive streaming access replacement method according to another embodiment of the present disclosure;

[0013] Figure 4 This is a flowchart of an automatically adaptive streaming access replacement method according to another embodiment of the present disclosure;

[0014] Figure 5 This is a flowchart of an automatically adaptive streaming access replacement method according to another embodiment of the present disclosure. Detailed Implementation

[0015] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0016] It should be noted that the headings of any section / subsection provided herein are not limiting. Various embodiments are described throughout this document, and embodiments of any type may be included under any section / subsection. Furthermore, embodiments described in any section / subsection may be combined in any way with any other embodiments described in the same section / subsection and / or different sections / subsections.

[0017] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may also be included below. The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0018] The embodiments of this disclosure may involve user data, data acquisition, and / or use. All of these aspects comply with applicable laws, regulations, and relevant provisions. In the embodiments of this disclosure, all data collection, acquisition, processing, manipulation, forwarding, and use are conducted with the user's knowledge and confirmation. Accordingly, in implementing the embodiments of this disclosure, the type, scope of use, and usage scenarios of any data or information that may be involved should be communicated to the user and their authorization obtained in accordance with relevant laws and regulations through appropriate means. The specific methods of notification and / or authorization may vary depending on the actual situation and application scenario, and the scope of this disclosure is not limited in this respect.

[0019] In this specification and the embodiments, any processing of personal information will be carried out only under the premise of legality (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be carried out within the scope stipulated or agreed upon. A user's refusal to process personal information beyond what is necessary for basic functions will not affect the user's use of basic functions.

[0020] The following describes in detail, with reference to the accompanying drawings, the automatically adaptable streaming access replacement scheme provided by the embodiments of this disclosure.

[0021] See Figure 1 This disclosure provides an automatically adaptive streaming access replacement method applied to CPU core 1. CPU core 1 includes a level 1 data cache 11, a level 2 data cache 12, and a data prefetch unit 13. CPU core 1 interacts with level 3 data cache 2 via an interconnect bus.

[0022] The CPU performs a regular traversal of a large range of data, i.e., iterates through a very large array or data structure. For example, a loop body needs to repeatedly access data blocks A[0] to A[N] (N is a natural number). A[0] to A[N] is a large range of data, meaning that N in the data block is very large, exceeding the capacity of the data cache in which it is located. Each loop starts from the starting point (such as A[0]) and gradually traverses backward.

[0023] Suppose that the first-level data cache 11 stores data blocks A[0] to A[M], where M is a natural number less than N. The first-level data cache 11 is constantly filled with new prefetched data, causing old data (including data blocks A[0] to A[M]) to be evicted. When data blocks A[0] to A[N] are accessed again, and the loop restarts from A[0], data blocks A[0] to A[M] are missing and need to be reloaded from the second-level data cache 12 or memory, resulting in a total miss and high latency.

[0024] This embodiment of the present disclosure intervenes in the replacement process of backfill data in the first-level data cache 11 by monitoring and marking the data prefetching unit 13, and preferentially retains data blocks A[0] to A[M] that may be accessed repeatedly between cycles, thereby avoiding the re-fetching of data blocks A[0] to A[M] from the second-level data cache 12 and reducing the latency of memory access.

[0025] See Figure 2 The automatically adaptive streaming access replacement method of this disclosure includes:

[0026] Step S1: If the data prefetching unit detects that the range of data traversed has reached the first threshold based on the training request received from the first-level data cache, then it marks the backfill request from the second-level data cache to the first-level data cache, and marks the backfilled data as the data to be replaced first.

[0027] Specifically, see Figure 1 The data prefetching unit 13 monitors the range of data to be traversed based on the training requests received from the first-level data cache 11. If the monitored range of data to be traversed reaches a first threshold, a backfill request from the second-level data cache 12 to the first-level data cache 11 is marked. The first threshold is set based on the learning of the regularity of memory access requests and the monitoring of traversal characteristics, and the first threshold is related to the capacity of the first-level data cache or the typical loop body size.

[0028] Specifically, the system monitors the number of consecutive addresses in the Level 1 data cache 11. For example, with a cache capacity of 64KB and 4-way set-associative, a first threshold of 48KB is set; or with a cache capacity of 64KB and 8-way set-associative, a first threshold of 56KB is set. This controls the size of the cache occupied by data at consecutive addresses. That is, if the cache capacity is 64KB, 4-way set-associative, and a first threshold of 48KB is set, then when the traversed data range reaches 48KB, a backfill request from Level 2 data cache 12 to Level 1 data cache 11 is marked, and the backfilled data is marked as priority replacement data. Thus, 48KB of consecutive address data is retained in Level 1 data cache 11.

[0029] For example, the first threshold size can also be calculated directly as cachesize × (way-1) / way, where cachesize is the cache capacity and way is the number of way groups.

[0030] Data prefetching unit 13 detects that the range of data being traversed has reached a first threshold, triggering an additional marking of the backfill request from the second-level data cache 12 to the first-level data cache 11. This marking guides the replacement algorithm of the first-level data cache 11, prioritizing the replacement of backfill data (i.e., data prefetched from the second-level data cache to the first-level data cache). In other words, backfill data is marked as easily replaceable (e.g., adjusted to low priority), thereby protecting old data already existing in the traversal operation of the first-level data cache 11 from being easily evicted. This ensures that during repeated accesses, some critical data is retained in the first-level data cache 11, improving the hit rate and reducing cache misses.

[0031] Taking the traversal of data blocks A[0] to A[N] as an example, the data prefetching unit 13 detects that the traversed data range has reached the first threshold, triggering additional marking of the replacement data for the backfill request from the second-level data cache 12 to the first-level data cache 11. Additional marking of the replacement data for the backfill request causes the first-level data cache 11 to retain the old data blocks A[0] to A[M], while marking the new backfill data prefetched from the second-level data cache 12 as the data to be replaced first. Thus, the first-level data cache 11 retains the old data blocks A[0] to A[M], and when new backfill data is prefetched from the second-level data cache 12 again, the data marked as the data to be replaced first in the first-level data cache 11 is replaced first. Since the first-level data cache 11 retains the old data blocks A[0] to A[M], when traversing data blocks A[0] to A[N] in a loop, some data (data blocks A[0] to A[M]) can be hit.

[0032] Step S2: If the data prefetching unit detects that the range of traversed data has reached the second threshold, then the backfill request from the third-level data cache to the second-level data cache is marked, and the backfilled data is marked as the data to be replaced first, and the first threshold is less than the second threshold.

[0033] When the data range traversed by data prefetching unit 13 increases further, exceeding the first threshold and reaching the second threshold. The second threshold is for larger-scale traversal operations, and its setting is based on the same criteria as the first threshold, but the second threshold is greater than the first threshold. The second threshold is set based on the learning of memory access request patterns and the monitoring of traversal characteristics, and the second threshold is related to the capacity of the second-level data cache or the typical loop body size.

[0034] Specifically, the number of consecutive addresses in the Level 2 data cache 12 is monitored. For example, with a cache capacity of 512 KB and 4-way set-associative, a second threshold of 384 KB is set; or with a cache capacity of 512 KB and 8-way set-associative, a second threshold of 448 KB is set. This controls the size of the cache occupied by data at consecutive addresses. That is, if the cache capacity is 64 KB, 4-way set-associative, and a second threshold of 384 KB is set, then when the traversed data range reaches 384 KB, a backfill request from Level 3 data cache 2 to Level 2 data cache 12 is marked, and the backfilled data is marked as priority replacement data. In this way, 48 KB of consecutive address data is retained in Level 2 data cache 12.

[0035] For example, the second threshold size can also be calculated directly as cachesize × (way-1) / way, where cachesize is the cache capacity and way is the number of road groups.

[0036] Data prefetching unit 13 detects that the range of traversed data has reached a second threshold, triggering additional marking of the replacement data in the backfill requests from level 3 data cache 2 to level 2 data cache 12. This additional marking of the replacement data in the backfill requests guides the replacement algorithm of level 2 data cache 12, prioritizing the replacement of backfill data (i.e., data prefetched from level 3 data cache to level 2 data cache). In other words, backfill data is marked as easily replaceable (e.g., adjusted to low priority), thereby protecting old data already existing in the traversal operation of level 2 data cache 12 from being easily evicted. This ensures that during repeated accesses, some critical data is retained in level 2 data cache 12, improving the hit rate and reducing cache misses.

[0037] The embodiments disclosed herein help to protect older data in the secondary data cache from being replaced during a wider traversal, thereby providing more stable backup support for the prefetching of the primary data cache.

[0038] In some specific implementations of the embodiments of this disclosure, the data in the first-level data cache 11 is stored in the second-level data cache 12. The embodiments of this disclosure extend the protection mechanism of the first threshold to the second-level cache, ensuring that under the inclusion relationship of multi-level caches (the data in the first-level data cache must be in the second-level data cache), the data stored in the second-level data cache 12 can also be partially traversed and hit during cyclic access.

[0039] In some specific implementations of the embodiments disclosed herein, see [link to relevant documentation]. Figure 3 Step S1, preceding which also includes:

[0040] Step S0: Trigger the data prefetching unit to simultaneously initiate prefetch requests to both the first-level data cache and the second-level data cache.

[0041] See Figure 1 Since the data in the first-level data cache 11 is stored in the second-level data cache 12, the data prefetching unit 13 of this embodiment can simultaneously initiate prefetching requests to the first-level data cache and the second-level data cache. That is, the first-level data cache and the second-level data cache accept memory access requests within the kernel. By learning the memory access patterns, the prefetching of the first-level data cache and the second-level data cache is triggered.

[0042] In some specific implementations of this disclosure, the prefetch distance of the secondary data cache is longer than that of the primary data cache. The secondary data cache in this disclosure is used to cover situations requiring greater access latency.

[0043] In some specific implementations of the embodiments disclosed herein, see [link to relevant documentation]. Figure 4 The method in this disclosure embodiment further includes:

[0044] Step S3: If the data prefetching unit detects that the range of data to be traversed has reached the third threshold, then it marks the eviction request from the second-level data cache to the third-level data cache, so that the data evicted from the second-level data cache will no longer be allocated to the third-level data cache.

[0045] When the range of traversed data reaches the third threshold (i.e., the maximum threshold), a flag is triggered to indicate an eviction request from Level 2 data cache 12 to Level 3 data cache 2, and the evicted data is additionally marked. The third threshold is set based on a comparison between the traversed range and the capacity of Level 3 data cache 2, involving the system-on-a-chip (SOC level), and is used to avoid unnecessary pollution of the third data cache 14.

[0046] Specifically, the system monitors the number of consecutive addresses in Level 3 data cache 2. For example, with a cache capacity of 2 MBytes and 4-way set-associative, a third threshold of 1.5 MBytes is set; or with a cache capacity of 2 MBytes and 8-way set-associative, a third threshold of 1.75 MBytes is set. This controls the amount of data occupying consecutive addresses in the cache. That is, if the cache capacity is 2 MBytes, 4-way set-associative, and a third threshold of 1.5 MBytes is set, then when the traversed data range reaches 1.5 MBytes, an eviction request from Level 2 data cache 12 to Level 3 data cache 2 is marked. This prevents data evicted from Level 2 data cache 12 from being allocated to Level 3 data cache, thus retaining 48K consecutive addresses of data in Level 3 data cache 2.

[0047] For example, the third threshold size can also be calculated directly as cachesize × (way-1) / way, where cachesize is the cache capacity and way is the number of way groups.

[0048] The marking of eviction requests for Level 2 data cache 12 will additionally mark the evicted data from Level 2 data cache 12. Data prefetch unit 13 controls the interconnect bus to no longer allocate evicted data from Level 2 data cache 12 to Level 3 data cache 2, thereby preventing old data in Level 3 data cache 2 from being replaced by evicted data from Level 2 data cache 12 (i.e., preventing new data from polluting the Level 3 data cache). This embodiment of the disclosure retains old data in Level 3 data cache 2, ensuring that the retained old data is hit in Level 3 data cache 2 during the next cycle access, improving the data hit rate and covering memory access latency.

[0049] The thresholds in this embodiment are progressively increased (first threshold < second threshold < third threshold), forming an automatically adaptive hierarchical strategy. This embodiment starts with a small-scale traversal and gradually activates higher-level protection mechanisms to ensure optimized data cache hit rates under workloads of varying sizes.

[0050] In some specific implementations of the embodiments disclosed herein, the Level 3 data cache 2 and the CPU core 1 are mutually exclusive. The system-on-a-chip includes a Level 3 data cache 2, which is mutually exclusive with the CPU core 1, and data evicted from the Level 2 data cache 12 is allocated to the Level 3 data cache 2.

[0051] The mutual exclusion relationship between the Level 3 data cache 2 and the CPU core 1 in this embodiment avoids redundant data storage in multi-level caches, thereby allowing the Level 3 data cache 2 to store more data blocks and improving the overall system cache utilization. This is especially suitable for SOC (System-on-a-Chip) environments where the large-capacity Level 3 data cache 2 serves as a shared cache. In traversal operations with a large data range, this can accommodate more repeatedly accessed data, reducing memory access frequency.

[0052] In some specific implementations of the embodiments of this disclosure, the data evicted from the secondary data cache 12 determines whether to allocate the data evicted from the secondary data cache 12 to the tertiary data cache 2 by initiating different types of requests to the interconnect bus.

[0053] Specifically, see Figure 1 If the evicted data corresponding to the eviction request of Level 2 data cache 12 has an additional tag, the interconnect bus initiates a replacement request without allocating a cache request, and the evicted data from Level 2 data cache 12 is not allocated to Level 3 data cache 2. The evicted data from Level 2 data cache 12 is discarded by the memory controller or stored in other memory. If the evicted data corresponding to the eviction request of Level 2 data cache 12 does not have an additional tag, the interconnect bus initiates a replacement request to allocate a cache request, allocating it to Level 3 data cache 2.

[0054] This disclosure utilizes bus request types as control signals to provide a flexible, non-intrusive cache management mechanism that avoids the complexity of hardware modifications.

[0055] See Figure 1 The present disclosure also provides an automatically adaptive streaming access replacement method, applied to a system-on-a-chip (SoC). The SoC includes a CPU core 1 and a level 3 data cache 2. The CPU core 1 includes a level 1 data cache 11, a level 2 data cache 12, and a data prefetch unit 13. The CPU core 1 interacts with the level 3 data cache 2 via an interconnect bus.

[0056] See Figure 5 The method includes:

[0057] Step S1: If the data prefetching unit detects that the range of data traversed has reached the first threshold based on the training request received from the first-level data cache, then it marks the backfill request from the second-level data cache to the first-level data cache, and marks the backfilled data as the data to be replaced first.

[0058] Step S2: If the data prefetching unit detects that the range of data being traversed has reached the second threshold, then the backfill request from the third-level data cache to the second-level data cache is marked, and the backfilled data is marked as the data to be replaced first.

[0059] Step S3: If the data prefetching unit detects that the range of data to be traversed has reached the third threshold, then mark the eviction request from the second-level data cache to the third-level data cache, so that the data evicted from the second-level data cache will no longer be allocated to the third-level data cache. The third threshold is greater than the second threshold, and the second threshold is greater than the first threshold.

[0060] See Figure 1 This disclosure also provides a CPU core 1, which includes a level 1 data cache 11, a level 2 data cache 12 and a data prefetch unit 13. The CPU core 1 interacts with the level 3 data cache 2 through an interconnect bus.

[0061] Based on the training request received from the first-level data cache 11, the data prefetching unit 13 detects that the range of traversed data has reached the first threshold, and then marks the backfill request from the second-level data cache 12 to the first-level data cache 11, so that the backfilled data is marked as the data to be replaced first.

[0062] If the data prefetching unit 13 detects that the range of data to be traversed has reached the second threshold, it marks the backfill requests from the third-level data cache 2 to the second-level data cache 12, and marks the backfill data as the data to be replaced first. The second threshold is greater than the first threshold.

[0063] See Figure 1 This disclosure also provides a system-on-a-chip, which includes a CPU core 1 and a level 3 data cache 2. The CPU core 1 includes a level 1 data cache 11, a level 2 data cache 12 and a data prefetch unit 13. The CPU core 1 interacts with the level 3 data cache 2 through an interconnect bus.

[0064] Based on the training request received from the first-level data cache 11, the data prefetching unit 13 detects that the range of traversed data has reached the first threshold, and then marks the backfill request from the second-level data cache 12 to the first-level data cache 11, so that the backfilled data is marked as the data to be replaced first.

[0065] If the data prefetching unit 13 detects that the range of data to be traversed has reached the second threshold, it marks the backfill requests from the third-level data cache 2 to the second-level data cache 12, and marks the backfill data as the data to be replaced first.

[0066] If the data prefetching unit 13 detects that the range of data to be traversed has reached the third threshold, it marks the eviction request from the second-level data cache 12 to the third-level data cache 2, so that the data evicted from the second-level data cache 12 will no longer be allocated to the third-level data cache 2. The third threshold is greater than the second threshold, and the second threshold is greater than the first threshold.

[0067] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions of other embodiments.

[0068] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0069] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.

[0070] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. An automatically adaptive streaming access replacement method, applied to a CPU core, characterized in that, The CPU core includes a level 1 data cache, a level 2 data cache, and a data prefetch unit. The CPU core interacts with the level 3 data cache via an interconnect bus. The method includes: If the data prefetching unit detects that the range of traversed data has reached a first threshold based on the training request received from the first-level data cache, it marks the backfill request from the second-level data cache to the first-level data cache, and marks the backfilled data as the data to be replaced first. If the data prefetching unit detects that the range of data to be traversed reaches the second threshold, it marks the backfill request from the third-level data cache to the second-level data cache, and marks the backfilled data as the data to be replaced first. The second threshold is greater than the first threshold. The range of data to be traversed is the amount of data to be traversed.

2. The method according to claim 1, characterized in that, The data in the first-level data cache is stored in the second-level data cache.

3. The method according to claim 2, characterized in that, If the data prefetching unit detects that the range of traversed data has reached a first threshold based on the received training request from the first-level data cache, it marks the backfill request from the second-level data cache to the first-level data cache, and marks the backfilled data as data to be replaced first. This is further supported by the following steps: The data prefetching unit is triggered to simultaneously initiate prefetch requests to the first-level data cache and the second-level data cache.

4. The method according to claim 3, characterized in that, The prefetch distance of the secondary data cache is longer than that of the primary data cache.

5. The method according to claim 4, characterized in that, The method further includes: If the data prefetching unit detects that the range of data being traversed reaches the third threshold, it marks the eviction request from the second-level data cache to the third-level data cache, so that the data evicted from the second-level data cache will no longer be allocated to the third-level data cache, and the third threshold is greater than the second threshold.

6. The method according to claim 5, characterized in that, The three-level data cache and the CPU core are mutually exclusive.

7. The method according to claim 6, characterized in that, The data evicted from the secondary data cache determines whether to allocate the evicted data to the tertiary data cache by initiating different types of requests to the interconnect bus.

8. An automatically adaptive streaming access replacement method, applied to a system-on-a-chip, characterized in that, The system-on-a-chip includes a CPU core and a three-level data cache. The CPU core includes a level 1 data cache, a level 2 data cache, and a data prefetch unit. The CPU core interacts with the level 3 data cache via an interconnect bus. The method includes: If the data prefetching unit detects that the range of traversed data has reached a first threshold based on the training request received from the first-level data cache, it marks the backfill request from the second-level data cache to the first-level data cache, and marks the backfilled data as the data to be replaced first. If the data prefetching unit detects that the range of traversed data reaches the second threshold, it marks the backfill request from the third-level data cache to the second-level data cache, and marks the backfilled data as the data to be replaced first. If the data prefetching unit detects that the range of data to be traversed reaches the third threshold, it marks the eviction request from the second-level data cache to the third-level data cache, so that the data evicted from the second-level data cache will no longer be allocated to the third-level data cache. The third threshold is greater than the second threshold, and the second threshold is greater than the first threshold. The range of data to be traversed is the amount of data to be traversed.

9. A CPU core, characterized in that, The CPU core includes a level 1 data cache, a level 2 data cache, and a data prefetch unit. The CPU core interacts with the level 3 data cache via an interconnect bus. The data prefetching unit detects that the range of traversed data has reached a first threshold based on the training request received from the first-level data cache. Then, it marks the backfill request from the second-level data cache to the first-level data cache and marks the backfilled data as the data to be replaced first. If the data prefetching unit detects that the range of traversed data has reached the second threshold, it marks the backfill request from the third-level data cache to the second-level data cache, and marks the backfilled data as the data to be replaced first. The second threshold is greater than the first threshold. The range of data to be traversed is the amount of data to be traversed.

10. A system-on-a-chip, characterized in that, The system-on-a-chip includes a CPU core and a three-level data cache. The CPU core includes a level 1 data cache, a level 2 data cache, and a data prefetch unit. The CPU core interacts with the level 3 data cache via an interconnect bus. The data prefetching unit detects that the range of traversed data has reached a first threshold based on the training request received from the first-level data cache. Then, it marks the backfill request from the second-level data cache to the first-level data cache and marks the backfilled data as the data to be replaced first. If the data prefetching unit detects that the range of traversed data has reached the second threshold, it will mark the backfill request from the third-level data cache to the second-level data cache, and mark the backfilled data as the data to be replaced first. If the data prefetching unit detects that the range of data to be traversed has reached the third threshold, it marks the eviction request from the second-level data cache to the third-level data cache, so that the data evicted from the second-level data cache will no longer be allocated to the third-level data cache. The third threshold is greater than the second threshold, and the second threshold is greater than the first threshold. The range of data to be traversed is the amount of data to be traversed.

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