Test card and host

Abstract

The application discloses a test card and a host computer, and relates to the technical field of testing.The technical scheme of the application is characterized in that: firstly, after a plurality of different test interfaces are arranged on the test card, the different test interfaces of the test card can be used to test the plurality of different slots of the host computer, so that the problem that some slots cannot be tested can be avoided, and the test coverage can be improved; secondly, the test interface comprises an identification pin, and a controller can determine a target test interface connected to the host computer based on the voltage of the identification pin of each test interface, so that the different test interfaces can be connected to the host computer in turn during the test process, and the test flexibility is improved; and finally, the test card supports loopback test and card function test, and a configuration end of an information loading circuit can be used to select a test mode, so that each slot of the host computer can be tested according to a plurality of different test modes, and the test coverage is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of testing, in particular to a test card and a host. BACKGROUND

[0002] The host refers to any computer device capable of running programs or providing services, including but not limited to servers, tablets, laptops, etc. In order to ensure the stability and reliability of each PCIe (Peripheral Component Interconnect Express) slot on the host, the PCIe slot of the host is usually tested for functions, performance, etc. before the host is shipped.

[0003] At present, in some technologies, when testing the PCIe slot, a single interface form of PCIe standard card is usually used for testing. The test coverage of this test method is not high. SUMMARY

[0004] The present application provides a test card and a host to at least solve the problem of low test coverage in the related art.

[0005] The present application provides a test card, which comprises:

[0006] A plurality of different test interfaces, the test interface comprising a communication pin and an identification pin, the voltage of the identification pin of the test interface being a first voltage when the test interface is connected to the host, and the voltage of the identification pin of the test interface being a second voltage when the test interface is disconnected from the host;

[0007] An information loading circuit comprising a configuration end and a detection end, the detection end being connected to the identification pin, and the configuration end being configured to receive a configuration signal representing a test mode;

[0008] A controller connected to the detection end, the configuration end and the communication pin of each test interface, configured to detect the voltage of the identification pin of each test interface through the detection end, and based on the detected voltage of the identification pin, determine a target test interface connected to the host, and when the configuration signal received by the configuration end represents a first test mode, perform loopback test with the host through the communication pin of the target test interface, and when the configuration signal received by the configuration end represents a second test mode, perform card function test with the host through the communication pin of the target test interface.

[0009] The present application also provides a host, wherein the test card as described above is used to test the host.

[0010] In some embodiments of this application, firstly, after the test card is equipped with multiple different test interfaces, when the host includes multiple different slots, each slot can be tested separately through the different test interfaces of the test card. This avoids the problem of some slots being untestable, thereby improving test coverage. Secondly, the test interface includes an identification pin. When the test interface is connected to the host, the voltage of the identification pin is a first voltage, and when the test interface is disconnected from the host, the voltage of the identification pin is a second voltage. The controller can determine the target test interface connected to the host based on the voltage of the identification pin of each test interface. Thus, during the testing process, different test interfaces can be connected to the host sequentially according to actual needs, improving testing flexibility. Finally, the test card supports loopback testing and card function testing, and the test mode can be selected through the configuration terminal of the information loading circuit. This allows for testing of each slot of the host according to multiple different test modes, further improving test coverage. Attached Figure Description

[0011] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A top view of a test card provided for some embodiments of this application;

[0013] Figure 2 A schematic diagram of the dimensions of the test card provided for some embodiments of this application;

[0014] Figure 3 A schematic diagram illustrating the docking relationship between the second test interface and the host slot corresponding to the first test interface, provided in some embodiments of this application;

[0015] Figure 4 Dimensional schematic diagrams of test cards provided for other embodiments of this application;

[0016] Figure 5 A schematic diagram of a test card provided for some embodiments of this application;

[0017] Figure 6 A schematic diagram illustrating the first positional relationship between the first fixing component and the baffle provided for some embodiments of this application;

[0018] Figure 7 A schematic diagram illustrating the second positional relationship between the first fixing component and the baffle provided for some embodiments of this application;

[0019] Figure 8 A third position relationship schematic diagram between the first fixed assembly and the baffle provided for some embodiments of the present application;

[0020] Figure 9 A fourth position relationship schematic diagram between the first fixed assembly and the baffle provided for some embodiments of the present application;

[0021] Figure 10 A top view size of the first baffle corresponding to the first test interface provided for some embodiments of the present application;

[0022] Figure 11 A side view size of the first baffle corresponding to the first test interface provided for some embodiments of the present application;

[0023] Figure 12 A top view size of the second baffle corresponding to the first test interface provided for some embodiments of the present application;

[0024] Figure 13 A side view size of the second baffle corresponding to the first test interface provided for some embodiments of the present application;

[0025] Figure 14 A top view size of the first baffle corresponding to the second test interface provided for some embodiments of the present application;

[0026] Figure 15 A side view size of the first baffle corresponding to the second test interface provided for some embodiments of the present application;

[0027] Figure 16 A top view size of the second baffle corresponding to the second test interface provided for some embodiments of the present application;

[0028] Figure 17 A side view size of the second baffle corresponding to the second test interface provided for some embodiments of the present application;

[0029] Figure 18 An assembly schematic diagram of the test card connected with the host provided for the first embodiment of the present application;

[0030] Figure 19 An assembly schematic diagram of the test card connected with the host provided for the second embodiment of the present application;

[0031] Figure 20 An assembly schematic diagram of the test card connected with the host provided for the third embodiment of the present application;

[0032] Figure 21 An assembly schematic diagram of the test card connected with the host provided for the fourth embodiment of the present application;

[0033] Figure 22 The test card provided for the fifth embodiment of the present application is connected to the host computer, and an assembly diagram is shown in the figure.

[0034] Figure 23 The test card provided for some embodiments of the present application is connected to the host computer, and an assembly diagram is shown in the figure.

[0035] Figure 24 The test card provided for some embodiments of the present application is connected to the host computer, and an assembly diagram is shown in the figure.

[0036] Figure 25 The test card provided for some embodiments of the present application is connected to the host computer, and an assembly diagram is shown in the figure.

[0037] Figure 26 The test card provided for some embodiments of the present application is connected to the host computer, and an assembly diagram is shown in the figure.

[0038] Figure 27 The test card provided for some embodiments of the present application is connected to the host computer, and an assembly diagram is shown in the figure.

[0039] Figure 28 The test card provided for some embodiments of the present application is connected to the host computer, and an assembly diagram is shown in the figure. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, any other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0041] It should be noted that, in the description of the present application, the terms “include”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0042] In order for those skilled in the art to better understand the technical solutions of the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0043] PCIe standard card refers to a PCIe device used to implement a single function, such as a standalone network card, a GPU (Graphics Processing Unit), a PCIe solid state disk, and the like. When some technologies use PCIe standard cards to test PCIe slots of a host, the following problems exist:

[0044] 1) Each PCIe standard card only supports a single PCIe version or a specified number of channels, and when a host includes multiple generations of PCIe slots, there is a problem of low test coverage. For example, when a host includes PCIe X8 and PCIe X16 slots, if a standard card supporting PCIe X8 is used for testing, the PCIe X16 slot cannot be covered. If a standard card supporting PCIe X16 is used for testing, the PCIe X18 slot cannot be covered. If a standard card supporting PCIe X8 and a standard card supporting PCIe X16 are used for testing, respectively, multiple standard cards are needed, and the test cost is high.

[0045] 2) In order to reduce the test cost, a standard card supporting a low rate is used to test a PCIe slot supporting a high rate. For example, a PCIe 5.0 version standard card supports a high rate, and a PCIe 3.0 version standard card only supports a low rate, but since the cost of the PCIe 5.0 version standard card is relatively high, the PCIe 3.0 version standard card is used to test the PCIe 5.0 version PCIe slot. This test method cannot comprehensively test the PCIe 5.0 version PCIe slot, and thus there is a problem of low test coverage.

[0046] 3) During the test process, the PCIe standard card needs to be frequently plugged in and out between different PCIe slots, resulting in a high loss rate of the PCIe standard card, and the PCIe standard card needs to be frequently replaced, increasing the test cost.

[0047] 4) not applicable to loopback test. The so-called loopback test refers to that the PCIe standard card needs to directly return the original data signal issued by the host, so as to verify the communication signal quality and protocol compliance of the PCIe slot and PCIe link. For example, in the loopback test, after the host issues the original data signal A to the PCIe standard card, the PCIe standard card needs to return the original data signal A to the host, and the host compares the data signal issued and the data signal returned by the PCIe standard card. If the signals are small, it proves that the communication signal quality of the PCIe slot and PCIe link is good, and if the signals are large, it proves that the communication signal quality of the PCIe slot and PCIe link is poor. At present, the firmware and circuit design of the PCIe standard card are mainly used for actual business, and there is no firmware and circuit design related to loopback test. Therefore, when the PCIe standard card is used to test the PCIe slot, loopback test cannot be performed, thereby causing the problem of low test coverage.

[0048] In view of this, the application provides a test card which can solve the above problems. In combination with Figure 1 The top view of the test card 100 provided by some embodiments of the application is shown in the figure. Figure 1 In this embodiment, the test card 100 includes a plurality of different test interfaces 11, an information loading circuit 12 and a controller 13. The test interface 11 includes a communication pin 111 and an identification pin 112. In the case where the test interface 11 is connected to the host, the voltage of the identification pin of the test interface 11 is a first voltage, and in the case where the test interface 11 is disconnected from the host, the voltage of the identification pin of the test interface 11 is a second voltage. The information loading circuit 12 includes a configuration end 122 and a detection end 121. The detection end 121 is connected to the identification pin 112, and the configuration end 122 is used to receive a configuration signal representing a test mode. The controller 13 is connected to the detection end 121, the configuration end 122 and the communication pin 111 of each test interface 11, and is used to detect the voltage of the identification pin of each test interface 11 through the detection end 121, and based on the detected voltage of the identification pin, determine the target test interface 11 connected to the host, and when the configuration signal received by the configuration end 122 represents a first test mode, perform loopback test with the host through the communication pin 111 of the target test interface 11, and when the configuration signal received by the configuration end 122 represents a second test mode, perform card function test with the host through the communication pin 111 of the target test interface 11.

[0049] Specifically, in this embodiment, the plurality of test interfaces 11 include PCIe X4 interface, PCIe X8 interface and PCIe X16 interface. For example, Figure 1In the embodiment, the test interface 11 marked as A can be a PCIe X8 interface, the test interface 11 marked as B can be a PCIe X4 interface, and the test interface 11 marked as C can be a PCIe X16 interface. Different test interfaces 11 can support different protocols, or multiple test interfaces 11 can all support the same protocol but different test interfaces 11 support different protocol versions.

[0050] In the embodiment, the information loading circuit 12 can include a power supply end. Each test interface 11 can be connected to the power supply end of the information loading circuit 12. A pull-up resistor is arranged between the power supply end and the test interface 11. In the case where the test interface 11 is connected to the host, the identification pin 112 of the test interface 11 can be connected to the ground end of the host, so that the voltage of the identification pin 112 is a first voltage, i.e., the ground voltage. In the case where the test interface 11 is disconnected from the host, due to the presence of the pull-up resistor, the voltage of the identification pin 112 can be a second voltage, i.e., the power supply voltage. The controller 13 can detect the voltage of the identification pin of each test interface 11 through the detection end 121. For any test interface 11, if the voltage of the identification pin of the test interface 11 is the ground voltage, it indicates that the test interface 11 is connected to the host, and if the voltage of the identification pin of the test interface 11 is the power supply voltage, it indicates that the test interface 11 is disconnected from the host.

[0051] In other embodiments, the information loading circuit 12 can also include a ground end. Each test interface 11 can be connected to the ground end of the information loading circuit 12. In the case where the test interface 11 is connected to the host, the identification pin 112 of the test interface 11 can be connected to the power supply end of the host, so that the voltage of the identification pin 112 is a first voltage, i.e., the power supply voltage. In the case where the test interface 11 is disconnected from the host, the identification pin 112 is grounded, and the voltage of the identification pin 112 can be a second voltage, i.e., the ground voltage. The controller 13 can detect the voltage of the identification pin of each test interface 11 through the detection end 121. For any test interface 11, if the voltage of the identification pin of the test interface 11 is the power supply voltage, it indicates that the test interface 11 is connected to the host, and if the voltage of the identification pin of the test interface 11 is the ground voltage, it indicates that the test interface 11 is disconnected from the host.

[0052] After determining the target test interface 11 connected to the host, the controller 13 can determine the test mode based on the configuration signal received by the configuration end 122, and communicate with the host through the communication pin 111 of the target test interface 11.

[0053] Specifically, in the firmware and circuit design of the test card 100, the following two aspects of firmware and circuit design can be included: 1) firmware and circuit design related to loopback testing; and 2) firmware and circuit design related to the service function of the test card 100.

[0054] The configuration end 122 of the information loading circuit 12 can be connected to a host computer or the like, and a test personnel can select a test mode based on the host computer or the like. For example, if the test personnel needs to perform loopback testing, the test personnel can issue a first configuration signal (for example, a high level) to the configuration end 122 through the host computer or the like. When the configuration signal received by the configuration end 122 is the first configuration signal, the controller 13 can communicate with the host through firmware and circuit design related to loopback testing to complete the loopback testing. Conversely, if the test personnel needs to complete related testing of the PCIe slot of the host through functional testing of the test card 100, the test personnel can issue a second configuration signal (for example, a low level) to the configuration end 122 through the host computer or the like. When the configuration signal received by the configuration end 122 is the second configuration signal, the controller 13 can communicate with the host through firmware and circuit design related to the business function of the test card 100 to complete the functional testing of the test card 100.

[0055] In summary, in the technical solutions of some embodiments of the present application, first, after the test card 100 is provided with a plurality of different test interfaces 11, when the host includes a plurality of different slots, the different test interfaces 11 of the test card 100 can be used to test the slots respectively. In this way, the problem that some slots cannot be tested can be avoided, and the test coverage can be improved. Second, the test interface 11 includes an identification pin 112, and when the test interface 11 is connected to the host, the voltage of the identification pin of the test interface 11 is a first voltage, and when the test interface 11 is disconnected from the host, the voltage of the identification pin of the test interface 11 is a second voltage. The controller 13 can determine the target test interface 11 connected to the host based on the voltage of the identification pin of each test interface 11. In this way, during the testing process, different test interfaces 11 can be connected to the host in sequence according to actual needs, improving the test flexibility. Finally, the test card 100 supports loopback testing and card function testing, and the configuration end 122 of the information loading circuit 12 can be used to select a test mode. In this way, each slot of the host can be tested in a plurality of different test modes, further improving the test coverage.

[0056] In addition, the identification pin 112 is arranged at each test interface 11, which can be understood as an improved scheme suitable for multiple different test interfaces 11, because in some technologies, each standard card only includes one test interface, and the controller does not need to determine the target test interface connected with the host in multiple test interfaces. Therefore, the standard card in some technologies does not have the problem of determining the target test interface. However, the test card 100 of the present application includes multiple different test interfaces 11, and the controller 13 necessarily needs to determine the target test interface 11 connected with the host in multiple test interfaces 11, and communicates with the host through the communication pin 111 of the target test interface 11. Therefore, the test card 100 of the present application has the problem of needing to determine the target test interface, and the arrangement of the identification pin 112 at each test interface 11 is used to solve this problem.

[0057] Further, taking the PCIe protocol as an example. In the host designed based on the PCIe protocol, PCIe X4, PCIe X8 and PCIe X16 slots can have various corresponding widths, for example, the width of the PCIe X16 slot is greater than the width of the PCIe X8, so that the PCIe X16 slot can support more channel numbers. At the same time, the external space size of the PCIe X16 slot and the PCIe X8 slot is the same, and the external space size of the PCIe X4 slot is different from the external space size of the PCIe X8 and PCIe X16 slots. Among them, the external space size refers to the space area reserved outside the PCIe slot for accommodating the PCIe standard card and the test card.

[0058] When the test card 100 simultaneously includes three types of test interfaces 11 of PCIe X4, PCIe X8 and PCIe X16, the size of the test card 100 can be reasonably designed to ensure that these test interfaces 11 can be docked with the corresponding PCIe slots. For ease of understanding, refer to Figure 2 The size of the test card 100 provided by some embodiments of the present application is shown in the schematic diagram. Figure 2 In the test card 100, the first end EF and the second end GH are arranged opposite to each other, and the third end FH and the fourth end EG are arranged opposite to each other. The multiple different test interfaces 11 include a first test interface and a second test interface, and the first test interface and the second test interface are used to connect the host slot. The first test interface is arranged at the first end EF, the second test interface is arranged at the second end GH, the distance between the first test interface and the third end FH is a first distance, the distance between the second test interface and the fourth end EG is a second distance, and the first distance is equal to the second distance.

[0059] Specifically, the first test interface can be a PCIe X16 interface, and the second test interface can be a PCIe X8 interface. The first distance and the second distance are 56.2 millimeters specified by the PCIe protocol.

[0060] Since the PCIe X16 slot corresponding to the first test interface and the PCIe X8 slot corresponding to the second test interface have the same external space size in the PCIe protocol, the first test interface and the second test interface are arranged at opposite ends of the test card 100, and the first distance between the first test interface and the third end FH is equal to the second distance between the second test interface and the fourth end EG, so that the first test interface can adapt to the external space size of the PCIe X16 slot, and the second test interface can adapt to the external space size of the PCIe X8 slot. In short, after the PCIe X16 interface is connected with the PCIe X16 slot of the host, the test card 100 is counterclockwise rotated, and the PCIe X8 interface can also be connected with the PCIe X8 slot of the host, or after the PCIe X8 interface is connected with the PCIe X8 slot of the host, the test card 100 is clockwise rotated, and the PCIe X16 interface can also be connected with the PCIe X16 slot of the host. That is, with the counterclockwise or clockwise rotation of the test card 100, the PCIe X16 interface and the PCIe X8 interface can adapt to the same external space size.

[0061] Further, continuing to refer to Figure 2 In some embodiments, the second test interface (i.e., the PCIe X8 interface) can be connected with the host slot corresponding to the first test interface (i.e., the PCIe X16 interface), but since the width of the first test interface is greater than the width of the second test interface, if the second test interface is flush with the third end FH, the second test interface cannot be inserted into the host slot corresponding to the first test interface. In view of this, the second test interface and the third end include a recessed area DH, the recessed area DH takes the end of the second test interface closest to the third end FH as a starting point and extends to the third end FH, the extension length L of the recessed area DH is greater than or equal to the difference between the width of the first test interface and the width of the second test interface, and the height h1 of the recessed area DH is greater than or equal to the height h2 of the first test interface. In this way, after the test card 100 in Figure 2 is rotated in the counterclockwise direction, the recessed area DH can be used to accommodate part of the host slot corresponding to the first test interface (i.e., the PCIe X16 interface). For ease of understanding, refer to Figure 3 The second test interface provided by some embodiments of the present application and the connection relationship between the host slot corresponding to the first test interface are shown in the schematic diagram. Figure 3In some embodiments, the thick rectangular region can be regarded as a host slot corresponding to the first test interface. The second test interface can be connected to the shadow region of the host slot, while the non-shadow region of the host slot is located in the recessed region of the test card 100. In this way, the second test interface (i.e., the PCIe X8 interface) can be inserted into the host slot corresponding to the first test interface (i.e., the PCIe X16 interface).

[0062] Referring back to Figure 2 In some embodiments, the plurality of different test interfaces 11 further includes a third test interface configured to connect to a hard disk backplane of the host, and the third test interface is disposed at the third end FH or the fourth end EG. Specifically, the third test interface can be a PCIe X4 interface. When the test card 100 is connected to the host through the third test interface, the test card 100 can serve as a hard disk device of the host and communicate with the host. Since the external space size of the PCIe X4 slot is different from that of the PCIe X8 and X16 slots in the PCIe protocol, the third test interface can be disposed at the third end FH or the fourth end EG. In this way, the width of the third end FH or the fourth end EG can be set according to the external space requirement of the PCIe X4 slot. Specifically, based on the PCIe protocol, the width of the third end FH or the fourth end EG can be 68.9 mm.

[0063] Referring back to Figure 4 A size diagram of the test card 100 is provided for some embodiments of the present application. Figure 4 In some embodiments, the card thickness of the test card 100 is equal to a second thickness, and the second thickness refers to the card thickness specified by the communication protocol between the test interface 11 and the host. Specifically, when the communication protocol between the test interface 11 and the host is the PCIe protocol, the second thickness is 1.57 mm. In this way, the design of the test card 100 complies with the specification of the communication protocol, so that the test card 100 can be applicable to the host slot test designed according to the communication protocol.

[0064] The above Figure 2 And Figure 4 In the embodiments shown in the above, by reasonably designing the size of the test card 100, each test interface 11 of the test card 100 can adapt to the slot size requirement and the external space size requirement specified by the communication protocol, thereby improving the applicability of the test card 100.

[0065] In some embodiments, at least part of the test interfaces 11 include a gold finger configured to contact the host to connect the test interface 11 to the host. For example, referring back to Figure 5 A diagram of the test card 100 is provided for some embodiments of the present application. Figure 5In some embodiments, the areas marked as a and b can be the gold finger setting areas. In the communication protocol, the gold plating thickness of the gold finger can be specified. For example, in the PCIe protocol, the gold plating thickness of the gold finger can be specified as 0.8 microns.

[0066] In some embodiments of the present application, considering that the test card 100 needs to be frequently plugged in and out between various hosts, the wear of the test interface 11 is large, therefore, the gold plating thickness of the gold finger can be greater than or equal to the first thickness, wherein the first thickness refers to the gold plating thickness specified in the communication protocol between the test interface 11 and the host. For example, in the PCIe protocol, the gold plating thickness of the gold finger is specified as 0.8 microns, and in the test card 100 of the present application, the gold plating thickness of the gold finger can be 1.25 microns. In this way, the durability of the test card 100 is increased, and the service life of the test card 100 is improved.

[0067] Further, in combination with reference to Figures 6 to 9 In some embodiments, the third end FH of the test card 100 is provided with a first fixing assembly 141, and the fourth end GE is provided with a second fixing assembly 143, at least one of the first fixing assembly 141 and the second fixing assembly 143 is used to fix the first end of the baffle 142, and the second end of the baffle 142 is fixed to the host when the first test interface or the second test interface is connected to the host slot, and the baffle 142 is used to keep the first test interface or the second test interface in contact with the host slot.

[0068] Specifically, when the second test interface (i.e., the PCIe X8 interface) is connected to the host, the first fixing assembly 141 can be used to fix the baffle 142. When the first test interface (i.e., the PCIe X16 interface) is connected to the host, the second fixing assembly 143 can be used to fix the baffle 142. Of course, it can be understood that in actual application, the fixing assembly used can also be dynamically adjusted, for example, when the first test interface (i.e., the PCIe X16 interface) is connected to the host, the first fixing assembly 141 can be used to fix the baffle 142. When the second test interface (i.e., the PCIe X8 interface) is connected to the host, the second fixing assembly 143 can be used to fix the baffle 142. For another example, when the first test interface (i.e., the PCIe X16 interface) and the second test interface (i.e., the PCIe X8 interface) are connected to the host, the first fixing assembly 141 or the second fixing assembly 143 is used to fix the baffle 142. The present application does not limit this.

[0069] By providing the first fixing assembly 141 and the second fixing assembly 143 for fixing the baffle on the test card 100, the test interface 11 and the host slot can be kept in good contact when the test interface 11 is connected to the host slot, thereby improving the communication reliability and avoiding communication interruption and other problems caused by poor contact between the test interface 11 and the host slot.

[0070] In some embodiments, the baffle includes a first baffle and a second baffle. The first baffle is used to adapt to a host of a first height, and the second baffle is used to adapt to a host of a second height. The first height host refers to a half-height host, and the second height host refers to a full-height host. Simply put, when testing the host slot of a half-height host using the test card 100, if the host is half-height, the first baffle is fixed using either the first fixing component 141 or the second fixing component 143; if the host is full-height, the second baffle is fixed using either the first fixing component 141 or the second fixing component 143. That is, depending on the height of the host under test, the first fixing component 141 can be used to fix either the first baffle or the second baffle. Similarly, the second fixing component 143 can also be used to fix either the first baffle or the second baffle.

[0071] In some embodiments, according to the PCIe protocol, the first bezels corresponding to the first test interface (i.e., PCIe X16 interface) and the second test interface (i.e. PCIe X8 interface) have different sizes, and the second bezels corresponding to the first test interface (i.e., PCIe X16 interface) and the second test interface (i.e. PCIe X8 interface) also have different sizes.

[0072] For ease of understanding, please refer to the following: Figures 10 to 17 . Figure 10 Top view dimensions of the first baffle corresponding to the first test interface provided in some embodiments of this application. Figure 11 The side view dimensions of the first baffle corresponding to the first test interface provided in some embodiments of this application. Figure 12 Top view dimensions of the second baffle corresponding to the first test interface provided in some embodiments of this application. Figure 13 The side view dimensions of the second baffle corresponding to the first test interface provided in some embodiments of this application. Figure 14 The top view dimensions of the first baffle corresponding to the second test interface provided in some embodiments of this application. Figure 15 The side view dimensions of the first baffle corresponding to the second test interface provided in some embodiments of this application. Figure 16 The top view dimensions of the second baffle corresponding to the second test interface provided in some embodiments of this application. Figure 17 The side view dimensions of the second baffle corresponding to the second test interface provided in some embodiments of this application. Because... Figures 10 to 17 The baffle size conforms to the PCIe protocol, therefore it can be used for testing any PCIe-based host slot, making it more versatile.

[0073] In the above embodiments, the first baffle and the second baffle of different sizes are designed according to the height of the host and the type of the test interface, so that the test card 100 can be applied to hosts of different heights, and the applicability is better.

[0074] The following gives a partial assembly diagram of the test card 100 after being connected with the host, so as to be understood.

[0075] For reference Figure 18 The assembly diagram of the test card 100 provided by the first embodiment of the application after being connected with the host is shown. Figure 18 In the embodiment, a plurality of test cards 100 are connected with the host board slot (i.e., the host slot on the host board) of the half-height host. The height of the host board slot is half the height of the standard PCIe slot, so as to adapt to the half-height host. Specifically, the test card 100 is connected with the host slot through one of the first test interface (i.e., the PCIe X16 interface) and the second test interface (i.e., the PCIe X8 interface), and the baffle of the test card 100 is the first baffle.

[0076] For reference Figure 19 The assembly diagram of the test card 100 provided by the second embodiment of the application after being connected with the host is shown. Figure 19 In the embodiment, a plurality of test cards 100 are connected with the host slot of the Riser card. The host is a half-height host, and the height of the host slot is half the height of the standard PCIe slot, so as to adapt to the half-height host. Specifically, the test card 100 is connected with the host slot through one of the first test interface (i.e., the PCIe X16 interface) and the second test interface (i.e., the PCIe X8 interface), and the baffle of the test card 100 is the first baffle.

[0077] For reference Figure 20 The assembly diagram of the test card 100 provided by the third embodiment of the application after being connected with the host is shown. Figure 20 In the embodiment, a plurality of test cards 100 are connected with the host slot of the full-height host. The height of the host slot is the same as the height of the standard PCIe slot, so as to adapt to the full-height host. Specifically, the test card 100 is connected with the host slot through one of the first test interface (i.e., the PCIe X16 interface) and the second test interface (i.e., the PCIe X8 interface), and the baffle of the test card 100 is the second baffle.

[0078] For reference Figure 21 The assembly diagram of the test card 100 provided by the fourth embodiment of the application after being connected with the host is shown. Figure 21 In the embodiment, a plurality of test cards 100 are connected with the hard disk backboard of the host vertically through the third test interface (i.e., the PCIe X4 interface). According to the height of the host, the baffle of the test card 100 can be the first baffle or the second baffle.

[0079] Referring to Figure 22 The assembly diagram of the test card 100 connected with the host computer is provided for the fifth embodiment of the present application. Figure 22 In the embodiment, a plurality of test cards 100 are connected with the hard disk backboard of the host computer through the third test interface (i.e., the PCIe X4 interface) in the transverse direction. According to the height of the host computer, the backboard of the test card 100 can be the first backboard or the second backboard.

[0080] The hardware design of the test card 100 is described below.

[0081] Referring to Figure 23 The partial module diagram of the test card 100 is provided for some embodiments of the present application. Figure 23 In the embodiment, the test card 100 includes a test interface 11, a controller 13, a clock source 191, a power supply 193, a storage medium 18, a sensor 192, an indicator light 194, and an auxiliary component 17. The test interface 11 includes a first test interface, a second test interface, and a third test interface. The auxiliary component 17 includes, but is not limited to, a UART (Universal Asynchronous Receiver / Transmitter), a TAP_SEL (Test Access Port Selector), a reset button, an I2C (Inter-Integrated Circuit), and the like. The clock source 191 is used to generate a clock signal. The controller 13 works according to the clock signal generated by the clock source 191. The power supply 193 is used to output voltages such as 12V and 5V to supply power to the components (such as the controller 13) on the test card 100. The indicator light 194 is used to show the working state of the test card 100, which can include, but is not limited to, working, standby, and working abnormally. The sensor 192 is used to collect data of the test card 100, such as the temperature of the test card 100. The sensor 192 is connected with the controller 13. The controller 13 can receive the data collected by the sensor 192.

[0082] The storage medium 18 is used to store test parameters. The controller 13 communicates with the host computer based on the test parameters. Specifically, the test parameters refer to the communication parameters in the communication process between the controller 13 and the host computer, including, but not limited to, the clock frequency and the communication rate. When the controller 13 detects that one of the test interfaces is connected with the host computer, the controller 13 reads the test parameters from the storage medium 18 and communicates with the host computer based on the test parameters.

[0083] In some embodiments, different test modes correspond to different test parameters. The controller 13 reads the configuration parameters corresponding to the target test mode from the storage medium 18 based on the target test mode corresponding to the configuration signal, and communicates with the host based on the read configuration parameters. For example, the storage medium 18 can store a first set of test parameters corresponding to the first test mode and a second set of test parameters corresponding to the second test mode. The first set of test parameters and the second set of test parameters can be the same or different. Figure 1 When the configuration signal received by the configuration terminal indicates the first test mode, the controller 13 reads the first set of test parameters from the storage medium 18 and communicates with the host according to the first set of test parameters. Figure 1 When the configuration signal received by the configuration terminal represents the second test mode, the controller 13 reads the second set of test parameters from the storage medium 18 and communicates with the host according to the second set of test parameters.

[0084] Test parameters are divided according to test modes, and the test parameters corresponding to different test modes are stored in the storage medium 18 of the test card 100. In this way, different test parameters can be set for different test modes, improving test flexibility.

[0085] Similarly, in some embodiments, different test interfaces 11 correspond to different test parameters. The controller 13 reads the configuration parameters corresponding to the target test interface 11 from the storage medium 18 and communicates with the host based on the read configuration parameters. For example, the storage medium 18 can store a third set of test parameters corresponding to the first test interface, a fourth set of test parameters corresponding to the second test interface, and a fifth set of test parameters corresponding to the third test interface. The third, fourth, and fifth sets of test parameters can be the same or different. When the controller 13 detects that the first test interface is connected to the host, it can read the third set of test parameters corresponding to the first test interface from the storage medium 18 and communicate with the host based on the third set of test parameters. When the controller 13 detects that the second test interface is connected to the host, it can read the fourth set of test parameters corresponding to the second test interface from the storage medium 18 and communicate with the host based on the fourth set of test parameters. And so on.

[0086] Test parameters are divided according to test interfaces, and the test parameters corresponding to different test interfaces are stored in the storage medium of test card 100. In this way, different test parameters can be set for different test interfaces, improving testing flexibility.

[0087] Continue reading Figure 23In some embodiments, the controller 13 includes a plurality of physical lanes, which are divided into at least two logical ports based on the number of test interfaces of the test card 100 and the number of communication pins of each test interface 11, and each logical port corresponds to a test interface, and the physical lanes of each logical port are used to connect the corresponding test interface 11. For example, when the first test interface is a PCIe X16 interface, the second test interface is a PCIe X8 interface, and the third test interface is a PCIe X4 interface, the controller 13 can include 28 physical lanes, the first to sixteenth physical lanes are divided into the logical port P1, the seventeenth to twenty-fourth physical lanes are divided into the logical port P2, and the twenty-fifth to twenty-eighth physical lanes are divided into the logical port P3. The physical lanes of the logical port P1 are connected to the communication pins 111 of the first test interface, the physical lanes of the logical port P2 are connected to the communication pins 111 of the second test interface, and the physical lanes of the logical port P3 are connected to the communication pins 111 of the third test interface. In addition, in the PCIe protocol, since each physical lane includes two signal lines, the number of communication pins of each test interface 11 is equal to four times the number of physical lanes supported by the corresponding test interface 11. For example, the PCIe X16 interface has 62 communication pins.

[0088] In this way, the physical lanes between the test interfaces 11 can be independent of each other, improving the test flexibility.

[0089] In some embodiments, the physical lane division logic can be pre-burned in the storage medium 18. The controller 13 divides the physical lanes into a plurality of logical ports based on the physical lane division logic in the storage medium 18. The physical lane division logic includes, but is not limited to, the binding relationship between the physical lanes and the logical ports, the correspondence between the logical ports and the physical lanes, etc. By pre-burning the physical lane division logic in the storage medium 18, the physical lanes can be divided as needed, thereby improving the flexibility of lane division.

[0090] For reference Figure 24 The module schematic diagram of the controller 13 provided for some embodiments of the present application is shown. Figure 24In some embodiments, the clock source 191 can also be referred to as a local clock source. The controller 13 further comprises a local clock pin 133. The local clock pin 133 is connected to the local clock source 191. The controller 13 performs data processing operations other than data uploading according to the clock signal generated by the local clock source 191. For example, the controller 13 performs data packet routing, register configuration, cache management, and other operations according to the clock signal generated by the local clock pin 133. The local clock source 191 and the host clock source can be independent of each other. In the case of host failure, the controller 13 can perform operations according to the clock signal generated by the local clock source 191, thereby improving the anti-failure capability.

[0091] With reference to Figure 23 In some embodiments, the clock source 191 located on the test card 100 can also be referred to as a local clock source. The controller 13 further comprises a local clock pin 133. The local clock pin 133 is connected to the local clock source 191. The controller 13 performs data processing operations other than data uploading according to the clock signal generated by the local clock source 191. For example, the controller 13 performs data packet routing, register configuration, cache management, and other operations according to the clock signal generated by the local clock pin 133. The local clock source 191 and the host clock source can be independent of each other. In the case of host failure, the controller 13 can perform operations according to the clock signal generated by the local clock source 191, thereby improving the anti-failure capability.

[0092] With reference to Figure 25 A module diagram of the test interface 11 is provided for some embodiments of the present application. Figure 24 In some embodiments, the test interface 11 comprises an I2C pin in addition to the communication pin 111 and the identification pin 112. The sensor 192 can be connected to the I2C pin of the test interface 11 through the controller 13. The BMC (Baseboard Management Controller) in the host can obtain the data collected by the sensor 192 (such as the temperature of the test card 100) through the I2C pin of the test interface 11, and manage the test card 100 based on the data collected by the sensor 192. For example, when the temperature of the test card 100 is too high, the test card 100 is controlled to stop working. At the same time, the host can also burn data (such as channel division logic) into the storage medium 18 of the test card 100 through the I2C pin of the test interface 11, thereby achieving management of the test card 100.

[0093] Further, Figure 24In some embodiments, the I2C pin of the test interface 11 can be connected to the sensor 192 and the storage medium 18 through the voltage conversion module 195. In this way, voltage matching between the test interface 11 and the sensor 192 and the storage medium 18 is achieved.

[0094] Further, Figure 24 In some embodiments, a switch 196 can be further included between the voltage conversion module 195 and the storage medium 18. The switch 196 is used to control the on-off between the voltage conversion module 195 and the storage medium 18, so as to avoid misoperation on the storage medium 18.

[0095] With reference to Figure 26 The schematic diagram of the interaction between the controller 13 and other components of the test card 100 is provided for some embodiments of the present application. Figure 26 In some embodiments, the auxiliary port can include, but is not limited to, a GPIO port, an I2C port, and an SPI (Serial Peripheral Interface). The working principle of the controller 13 can be referred to the above description, which is not repeated here.

[0096] Based on the above description, with reference to Figure 27 The schematic diagram of the test card 100 is provided for some embodiments of the present application. Figure 27 In some embodiments, the components marked as 16 are other chip components of the test card 100 except the controller 13. The other components can be referred to the above description, which is not repeated here.

[0097] With reference to Figure 28 The module schematic diagram of the host 200 is provided for some embodiments of the present application. The test card 100 described above is used to test the host 200.

[0098] Specifically, the host 200 includes a hard disk backboard. In the case that a plurality of test cards 100 are connected to the hard disk backboard, the plurality of test cards 100 are arranged in the same accommodating container, which is used to keep the hard disk backboard and the plurality of test cards 100 in contact. In this way, the communication reliability between the test card 100 and the host 200 is ensured.

[0099] The test card and the host provided by the present application are described in detail above. The principles and implementation manners of the present application are described by applying specific examples in this paper. The above description of the embodiments is only used to help understand the method of the present application and its core idea. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, some improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A test card, characterized by The test card comprises: a plurality of different test interfaces, the test interfaces comprising a communication pin and an identification pin, the identification pin of the test interface being at a first voltage when the test interface is connected to the host, and the identification pin of the test interface being at a second voltage when the test interface is disconnected from the host; an information loading circuit comprising a configuration end and a detection end, the detection end being connected to the identification pin, and the configuration end being configured to receive a configuration signal representing a test mode; a controller connected to the detection end, the configuration end, and the communication pin of each test interface, configured to detect the voltage of the identification pin of each test interface through the detection end, and determine a target test interface connected to the host based on the detected voltage of the identification pin, and when the configuration signal received by the configuration end represents a first test mode, perform loopback test with the host through the communication pin of the target test interface, and when the configuration signal received by the configuration end represents a second test mode, perform card function test with the host through the communication pin of the target test interface.

2. The test card of claim 1, wherein, The test card comprises a first end, a second end, a third end, and a fourth end, the first end and the second end being oppositely arranged, and the third end and the fourth end being oppositely arranged; the plurality of different test interfaces comprises a first test interface and a second test interface, the first test interface and the second test interface being configured to connect to a host slot, the first test interface being arranged at the first end, and the second test interface being arranged at the second end, the distance between the first test interface and the third end being a first distance, and the distance between the second test interface and the fourth end being a second distance, the first distance being equal to the second distance.

3. The test card of claim 2, wherein, The plurality of different test interfaces further comprises a third test interface, the third test interface being configured to connect to a hard disk backplane of the host, and the third test interface being arranged at the third end or the fourth end.

4. The test card of claim 2, wherein, The width of the first test interface is greater than the width of the second test interface, the second test interface and the third end comprise a recessed area, the recessed area having a starting point at the end of the second test interface closest to the third end, and extending towards the third end, the extension length of the recessed area being greater than or equal to the difference between the width of the first test interface and the width of the second test interface, and the height of the recessed area being greater than or equal to the height of the first test interface.

5. The test card of claim 2, wherein, The third end of the test card is provided with a first fixing assembly, and the fourth end is provided with a second fixing assembly, at least one of the first fixing assembly and the second fixing assembly being configured to fix a first end of a baffle, the second end of the baffle being fixed to the host when the first test interface or the second test interface is connected to the host slot, and the baffle being configured to keep the first test interface or the second test interface in contact with the host slot; and the baffle comprises a first baffle and a second baffle, the first baffle being configured to adapt to a host of a first height, and the second baffle being configured to adapt to a host of a second height.

6. The test card of any one of claims 1 to 5, wherein, At least part of the test interface includes a gold finger, the gold finger is used to contact the host to connect the test interface with the host, the gold thickness of the gold finger is greater than or equal to a first thickness, the first thickness refers to the gold thickness specified by the communication protocol between the test interface and the host.

7. The test card of any one of claims 1 to 5, wherein, The card thickness of the test card is equal to a second thickness, the second thickness refers to the card thickness specified by the communication protocol between the test interface and the host.

8. The test card of claim 1, wherein, The controller includes a plurality of physical channels, based on the number of test interfaces of the test card and the number of communication pins of each test interface, the plurality of physical channels are divided into at least two logical ports, the logical ports correspond to the test interfaces one by one, and the physical channels of each logical port are used to connect the corresponding test interface.

9. The test card of claim 8, wherein, The controller further includes an uplink clock pin, the uplink clock pin is used to connect a host clock source, in the case that the logical port of the controller includes an uplink port, the physical layer of the uplink port generates a clock signal according to the host clock source, and performs timing matching with the host.

10. The test card of claim 9, wherein, The controller further includes a local clock pin, the test card further includes a local clock source, the local clock pin is connected with the local clock source, and the controller performs data processing operations other than data uploading according to the clock signal generated by the local clock source.

11. The test card of claim 1, wherein, The test card further includes a storage medium, the storage medium is used to store test parameters, and the controller communicates with the host based on the test parameters.

12. The test card of claim 11, wherein, Different test modes correspond to different test parameters, the controller reads the configuration parameters corresponding to the target test mode according to the target test mode corresponding to the configuration signal from the storage medium, and communicates with the host according to the read configuration parameters.

13. The test card of claim 11, wherein, Different test interfaces correspond to different test parameters, the controller reads the configuration parameters corresponding to the target test interface from the storage medium, and communicates with the host according to the read configuration parameters.

14. A host, characterized by The test card of any one of claims 1 to 13 is used to test the host.

15. The host of claim 14, wherein, The host includes a hard disk backboard, in the case that a plurality of test cards are connected with the hard disk backboard, the plurality of test cards are arranged in the same accommodation container, and the accommodation container is used to keep the hard disk backboard and the plurality of test cards in contact.

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