An ECO timing optimization method and device based on logic re-routing

Abstract

The application discloses an ECO timing optimization method and device based on logical rewiring, and belongs to the technical field of ECO. The method comprises the following steps: receiving a design netlist and a functional patch netlist; performing logical-level rewiring optimization on the functional patch netlist before introducing physical layout information; integrating the optimized patch netlist with the overall design netlist and introducing the physical layout information; identifying a timing critical path containing a patch module; performing physical-aware rewiring optimization under the premise of considering physical layout constraints; and verifying whether the optimization scheme meets timing requirements. The application significantly improves the ECO timing optimization capability, reduces area and power consumption overhead, improves the timing convergence success rate, and ensures that the optimization scheme is physically realizable through a two-stage rewiring optimization strategy.

Description

Technical Field

[0001] This invention relates to the field of ECO technology, and in particular to an ECO timing optimization method and apparatus based on logic rerouting. Background Technology

[0002] In the integrated circuit design flow, especially in the later stages of design, Engineering Change Orders (ECOs) are a key technology for handling logic function changes, fixing timing violations, and addressing power consumption issues. When modifying RTL code after the layout has been generated, without dedicated ECO tools, the entire process must be re-executed from scratch. Using an ECO tool, however, is equivalent to applying patches directly to the existing layout, eliminating the need for a complete rework and significantly saving time and resources.

[0003] Existing ECO timing optimization methods mainly rely on techniques such as buffer insertion, gate sizing, and cell replacement. Buffer insertion enhances drive capability by adding buffers on the critical path, but increases area and power consumption; gate sizing optimizes timing by adjusting the drive strength of standard cells, but the optimization space is very limited in the later stages when the drive strength and load capacitance are fixed; cell replacement replaces cells with cells that have the same logic function but different timing characteristics, but the choices are limited.

[0004] Existing technologies have the following drawbacks: limited optimization capabilities; after placement and routing, physical resources are scarce, and the above methods often cannot effectively solve serious timing violations, especially in congested areas; they introduce new negative effects, such as inserting buffers, which increases area and dynamic power consumption, may exacerbate routing congestion, and may even lead to new timing problems; and they are difficult to converge, for high-frequency designs or critical paths with extremely tight timing budgets, traditional methods often fail to achieve timing closure, resulting in extended design cycles.

[0005] Logic rewiring is a technique that optimizes circuit structure by changing the connection relationships of wires in a circuit. It can reduce the number of logic levels or the load on the critical path by changing the connection structure without changing the logic function of the circuit, thereby optimizing timing.

[0006] However, this technology is currently mainly used in the logic synthesis stage, and there is no innovative solution to apply it to the ECO process in the physical design backend to solve the problem of ECO timing convergence. Summary of the Invention

[0007] This invention overcomes the shortcomings of existing ECO timing optimization techniques by intelligently applying rewiring technology in two key stages of the ECO process, significantly improving timing optimization performance, achieving rapid timing convergence, and avoiding the area and power consumption overhead of traditional methods, thereby improving ECO timing optimization capabilities and success rate.

[0008] To achieve the above objectives, in a first aspect, the present invention provides an ECO timing optimization method based on logic rerouting, the method comprising the following steps:

[0009] Step S1: Receive the design netlist input by the user and the function patch netlist generated by the ECO tool.

[0010] Step S2: Before introducing physical layout information, perform logical-level rerouting optimization on the functional patch netlist to generate an optimized patch netlist.

[0011] Step S3: Integrate the optimized patch netlist with the overall design netlist and introduce physical layout information.

[0012] Step S4: Perform static timing analysis on the integrated design to identify the timing critical paths containing the patch modules.

[0013] Step S5: For the time-critical path, physical-aware rewiring optimization is performed while taking into account physical layout constraints.

[0014] Step S6: Verify whether the optimization scheme meets the timing requirements. If it does, output the final version of the netlist. If it does not, return to step S5 for adjustment.

[0015] Furthermore, the logical-level rerouting optimization of the aforementioned functional patch netlist includes:

[0016] Step S2.1: Extract the functional patch netlist and convert it into a directed acyclic graph data structure.

[0017] Step S2.2: Analyze the internal logical structure of the patch netlist and identify candidate nodes and nets that can be rewired.

[0018] Step S2.3: Apply the rerouting algorithm to minimize the logical depth of the critical path without changing the logical function.

[0019] Step S2.4: Generate the optimized new patch netlist.

[0020] Furthermore, the rerouting algorithm optimizes the logic depth by bypassing multiple logic gates through rerouting; the bypassing of multiple logic gates through rerouting is based on optional line addition and removal rules or error cancellation rules, and performs pure logic structure optimization under the condition of not being constrained by physical layout.

[0021] Furthermore, the timing path containing the patch module refers to the timing path that at least partially passes through the functional patch module, identified through static timing analysis in the integrated design netlist.

[0022] Static timing analysis is performed on the timing path containing the patch module to obtain the timing critical path containing the patch module. This specifically includes the following steps:

[0023] Step S4.1: Perform a global static timing analysis on the integrated design and calculate the delay of all paths.

[0024] Step S4.2: Identify all timing paths that pass through the functional patch modules and establish a set of patch-related paths.

[0025] Step S4.3: In the set of patch-related paths, select paths with timing margins less than a preset threshold as timing critical paths.

[0026] Step S4.4: Sort the time-critical paths in ascending order of time-remaining margin, and prioritize optimizing the path with the smallest time-remaining margin.

[0027] Furthermore, the timing margin is defined as the timing constraint requirement value of the path minus the actual delay value. When the timing margin is negative, it indicates that there is a timing violation in the path.

[0028] Furthermore, the physical awareness rewiring optimization specifically includes the following steps:

[0029] Step S5.1: For the time-critical path, extract its local netlist, which includes the cells on the critical path and their fan-in and fan-out cells;

[0030] Step S5.2: Apply the rerouting algorithm while considering physical layout constraints, including cell location, net load and capacitance, and wiring congestion.

[0031] Step S5.3: The optimization objective is to minimize the actual delay of the path. The impact of changes in network load after rerouting on the delay is evaluated, and the rerouting scheme that can reduce the total delay of the critical path and is physically feasible is selected first.

[0032] Furthermore, the physical layout constraints in step S5.2 also include design rule check constraints to ensure that no new design rule checks are introduced to prevent violations.

[0033] Furthermore, the physical layout information introduced in step S3 includes DEF files and LEF files; the DEF file is used to define the physical layout of the design, and the LEF file is used to define the physical characteristics of the standard cells.

[0034] Furthermore, verifying whether the optimization scheme meets the timing requirements includes: using formal verification tools to ensure that the logical functions before and after rerouting are equivalent, and checking whether the timing constraints are met, including establishing timing constraints and maintaining timing constraints.

[0035] In a second aspect, the present invention discloses an ECO timing optimization apparatus based on logic rerouting, the apparatus comprising an ECO timing optimization system, the ECO timing optimization system being used to execute the method of the first aspect.

[0036] Furthermore, the ECO timing optimization system includes: a netlist receiving module, a logic-level optimization module, a netlist integration module, a static timing analysis module, a physical sensing optimization module, and a verification module.

[0037] The netlist receiving module receives the design netlist and the functional patch netlist generated by the ECO tool; the logic-level optimization module performs rerouting optimization on the functional patch netlist before introducing physical layout information; the netlist integration module integrates the optimized patch netlist with the overall design netlist and introduces physical layout information; the static timing analysis module identifies timing critical paths; the physical awareness optimization module performs rerouting optimization on critical paths while considering physical layout constraints; and the verification module verifies the logical equivalence, timing constraints, and design rule constraints of the optimization scheme.

[0038] Furthermore, the logic-level optimization module includes: a data structure conversion unit, a candidate identification unit, and a rerouting engine; the data structure conversion unit is used to convert the functional patch netlist into a directed acyclic graph data structure; the candidate identification unit is used to identify candidate nodes and nets that can be rerouted; and the rerouting engine is used to apply rerouting algorithms to optimize the logic depth.

[0039] Furthermore, the physical perception optimization module includes: a local netlist extraction unit, a physical constraint analysis unit, and a delay optimization unit; the local netlist extraction unit is used to extract the local netlist of the critical path; the physical constraint analysis unit is used to analyze the unit location, net load, capacitance, and cabling congestion; the delay optimization unit is used to evaluate the impact of rerouting schemes on delay and select the optimal scheme.

[0040] Compared with the prior art, the beneficial effects of the present invention are:

[0041] The logic rerouting method of this invention can fundamentally change the circuit structure, reduce the number of logic levels and net load, and more effectively solve severe timing violations compared to simply adjusting cell size or inserting buffers. Through a two-stage optimization strategy, the logic depth of the critical path can be optimized in the logic-level optimization stage, and the actual delay can be precisely optimized in the physical-aware optimization stage, significantly improving timing convergence capability. The method of this invention is applicable to integrated circuit designs of different scales and process nodes, and can be effectively applied to both small-to-medium scale designs and large-scale complex chips, exhibiting good versatility and scalability. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the composition of the ECO timing optimization system of the present invention. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention are described clearly and completely below. Obviously, the described embodiments are only a part of the embodiments of this invention, not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0044] It should be noted that the terms and their English equivalents involved in this invention include: ECO (Engineering Change Order); Rewiring; DEF (Design Exchange Format) file; LEF (Library Exchange Format) file; ATPG (Automatic Test Pattern Generation); DAG (Directed Acyclic Graph); STA (Static Timing Analysis); Timing Violation; Timing Closure; Setup Time; Hold Time; DRC (Design Rule Check); Formal Verification; RTL (Register Transfer Level); Buffer Insertion; Gate Sizing; Cell Replacement; Congested Area; Logic Level; Fanin; Fanout; Slack.

[0045] Rerouting is usually optimized by changing the connection relationship. It often does not require adding extra buffers or larger drive units, and may even remove redundant logic, thus avoiding the area and power consumption penalties of traditional methods.

[0046] Example 1

[0047] This embodiment discloses an ECO timing optimization method based on logic rerouting, which includes the following steps:

[0048] Step S1: Receive the design netlist input by the user and the function patch netlist generated by the ECO tool.

[0049] Step S2: Before introducing physical layout information, perform logical-level rerouting optimization on the functional patch netlist to generate an optimized patch netlist.

[0050] Logical-level rerouting optimization of the aforementioned functional patch netlist includes:

[0051] Step S2.1: Extract the functional patch netlist and convert it into a directed acyclic graph data structure.

[0052] Step S2.2: Analyze the internal logical structure of the patch netlist and identify candidate nodes and nets that can be rewired.

[0053] Step S2.3: Apply the rerouting algorithm to minimize the logical depth of the critical path without changing the logical function.

[0054] Step S2.4: Generate the optimized new patch netlist.

[0055] The rewiring algorithm employs either an algorithm based on Automatic Test Generation (ATPG) or a graph theory-based algorithm. By rewiring, it bypasses multiple logic gates, optimizing the logic depth to 30%-70% of the original depth.

[0056] The method of bypassing multiple logic gates by rewiring is based on optional line addition and removal rules or error cancellation rules, and performs pure logic structure optimization under the condition of not being constrained by physical layout.

[0057] Step S3: Integrate the optimized patch netlist with the overall design netlist and introduce physical layout information.

[0058] The introduced physical layout information includes DEF files and LEF files; the DEF files are used to define the physical layout of the design, and the LEF files are used to define the physical characteristics of the standard cells.

[0059] Step S4: Perform static timing analysis on the integrated design to identify the timing critical paths containing the patch modules.

[0060] Timing paths that include patch modules refer to timing paths that, through static timing analysis, at least partially pass through functional patch modules in the integrated design netlist.

[0061] Static timing analysis is performed on the timing path containing the patch module to obtain the timing critical path containing the patch module. This specifically includes the following steps:

[0062] Step S4.1: Perform a global static timing analysis on the integrated design and calculate the delay of all paths;

[0063] Step S4.2: Identify all timing paths that pass through the functional patch modules and establish a set of patch-related paths;

[0064] Step S4.3: In the set of patch-related paths, select paths with a timing margin less than a preset threshold as timing critical paths, where the preset threshold is no more than 200 picoseconds.

[0065] Step S4.4: Sort the time-critical paths in ascending order of time-remaining margin, and prioritize optimizing the path with the smallest time-remaining margin.

[0066] The timing margin is defined as the timing constraint requirement value of the path minus the actual delay value. When the timing margin is negative, it indicates that there is a timing violation in the path.

[0067] Step S5: For the time-critical path, physical-aware rewiring optimization is performed while taking into account physical layout constraints.

[0068] The physical sensing rewiring optimization specifically includes the following steps:

[0069] Step S5.1: For the time-critical path, extract its local netlist, which includes the cells on the critical path and their fan-in and fan-out cells.

[0070] Step S5.2: Apply the rerouting algorithm while considering physical layout constraints, which include cell location, net load and capacitance, and wiring congestion. The physical layout constraints also include design rule check constraints to ensure that no new design rules are introduced to check for violations.

[0071] Step S5.3: The optimization objective is to minimize the actual delay of the path. The impact of changes in network load after rerouting on the delay is evaluated, and the rerouting scheme that can reduce the total delay of the critical path and is physically feasible is selected first.

[0072] Step S6: Verify whether the optimization scheme meets the timing requirements. If it does, output the final version of the netlist. If it does not, return to step S5 for adjustment.

[0073] Verifying whether the optimization scheme meets timing requirements includes: using formal verification tools to ensure that the logical functions before and after rerouting are equivalent, and checking whether timing constraints are met, including establishing timing constraints and maintaining timing constraints.

[0074] By employing a two-stage optimization strategy, preprocessing is first performed at the logic layer when the cost of errors is low, and then stubborn violations are precisely targeted at the physical layer, which greatly improves the success rate of ECO timing convergence. Compared with the traditional ECO method, this invention can increase the timing convergence success rate from 60%-70% to 85%-95% and shorten the design cycle by 20%-30%.

[0075] The second phase of optimization fully considers layout information, including unit location, network load, capacitance, and wiring congestion, to ensure that the proposed rewiring scheme is physically feasible. This avoids the problem of idealized optimization schemes being unable to be wired, and improves the practicality and effectiveness of the scheme.

[0076] To better illustrate the practical application effect of the method of the present invention, the following detailed explanation is provided through a specific case of ECO timing optimization of a digital signal processor (DSP) chip.

[0077] A company's DSP chip required a functional upgrade. A serious timing violation was detected in the functional patch netlist generated after RTL code modification. The DSP chip's basic parameters are as follows: it uses a 28nm process, operates at 1.2GHz, has approximately 1.8 million logic gates, and includes 52 main output ports. After the RTL code modification, a logic equivalence checker detected functional differences in 28 output ports, requiring correction using an ECO tool to generate functional patches.

[0078] The initial functional patch netlist generated by the ECO tool consisted of 15,234 logic gates and 42 critical paths. Of these, 18 paths contained timing violations, with the most severe violation reaching -185 picoseconds (negative values ​​indicate violations of timing requirements). After processing using traditional ECO timing optimization methods (buffer insertion and gate size adjustment), while some timing violations were corrected, six critical paths still failed to converge, with timing margins of -45ps, -38ps, -52ps, -61ps, -48ps, and -55ps, respectively. Furthermore, 1,247 new buffers were added, increasing area overhead by 8.3% and dynamic power consumption by 6.7%.

[0079] The ECO timing optimization method based on logic rerouting of this invention is used for processing, and the specific process is as follows:

[0080] In the logic-level rerouting optimization stage (Pre-DEF stage) of step S2, the functional patch netlist is converted into a directed acyclic graph data structure containing 15,234 nodes and 23,567 edges. Analysis revealed a large amount of logical redundancy and optimizable connections within the patch netlist. An ATPG-based rerouting algorithm was used to identify 347 candidate rerouting nodes. Alternative wire and error cancellation rules were applied to optimize the critical path without altering the logical functionality.

[0081] Specifically, for a critical path with an original logic depth of 15 levels (passing through 15 logic gates), after rerouting optimization, the path is optimized to pass through only 6 logic gates by utilizing shared logic in the patch netlist, reducing the logic depth by 60%. After logic-level optimization, the entire patch netlist contains 14,856 logic gates, a reduction of 378 logic gates compared to the initial patch.

[0082] In step S3, the optimized patch netlist is integrated with the overall design netlist. During the integration process, the 23 input ports of the patch are connected to the internal signal nodes of the original netlist, and the 28 output ports replace the corresponding error output ports. DEF and LEF files are imported. The DEF file defines the physical layout of the chip, including the precise location coordinates of each standard cell; the LEF file defines the physical characteristics of the standard cell library used, including the area, pin positions, delay model, and other information for each cell.

[0083] In step S4, a global static timing analysis was performed on the integrated design. It was found that after logic-level optimization, 12 of the original 18 timing violation paths had achieved timing convergence, with timing margins ranging from 15ps to 78ps. The remaining 6 paths, while showing improved timing, still contained violations, with timing margins of -12ps, -8ps, -15ps, -18ps, -9ps, and -13ps, respectively. These 6 paths all at least partially passed through the functional patch module, conforming to the definition of a timing critical path containing a patch module. Specifically, 4 paths started at registers in the original design netlist, passed through the functional patch module, and ended at registers in the original design netlist; 2 paths were entirely located within the functional patch module.

[0084] In the physical awareness rerouting optimization stage (Post-DEF stage) of step S5, local netlists are extracted for these 6 timing-critical paths. Taking the path with the worst timing margin (-18ps) as an example, this path passes through 3 logic gates of the patch module, with 5 fan-in units and 2 fan-out units, and the local netlist contains a total of 18 units. Considering physical layout constraints, analysis reveals that the output of an AND gate on this path drives a large net load (total capacitance of 0.35pF), and the two input signals of this AND gate are physically close (only 12 micrometers apart).

[0085] The physical sensing rerouting algorithm utilizes an idle OR gate (8 micrometers away) near the AND gate. By rerouting, the signal path that originally needed to pass through the AND gate is changed to use the OR gate and the surrounding inverters to achieve the same logic function. This rerouting scheme reduces the net load on the path from 0.35pF to 0.18pF without increasing the number of logic stages.

[0086] After delay calculation, the total latency of the path was reduced by 23ps, and the timing margin was improved from -18ps to +5ps, successfully achieving timing convergence.

[0087] A similar physical-aware rerouting optimization strategy was adopted for the remaining 5 timing-critical paths. After the first round of optimization, 4 paths were successfully repaired, and the remaining path (timing margin -15ps) required a second round of optimization. In the second round of optimization, a more complex rerouting was performed on this path, involving adjustments to the connection relationships of 3 logic gates, which ultimately improved the timing margin to +8ps.

[0088] In step S6, the optimized scheme is fully verified. Formal verification tools are used to verify the logical functional equivalence before and after rerouting. The verification results show that the logical functions of all 28 output ports are completely consistent with the target netlist. A global static timing analysis is performed to confirm that all timing paths meet timing requirements, with a minimum setup time margin of +5ps and a minimum hold time margin of +12ps. A design rule check is performed to confirm that there are no violations.

[0089] The final optimization results are as follows: Compared to the initial ECO patch, the final patch netlist generated by the method of this invention contains 14,523 logic gates, a reduction of 4.7%; compared to the traditional ECO method (which requires the insertion of 1,247 buffers), the method of this invention only inserts 83 buffers, a reduction of 93.3% in the number of buffers; the area overhead increases by only 0.8% (compared to 8.3% in the traditional method), saving 90.4% of the area overhead; the dynamic power consumption increases by 1.2% (compared to 6.7% in the traditional method), saving 82.1% of the power consumption overhead; all timing violations are corrected, and the timing convergence success rate is 100% (compared to 66.7% in the traditional method); the total optimization time is 2.3 hours, of which logic-level optimization takes 35 minutes, physical sensing optimization takes 1 hour and 25 minutes, and verification takes 30 minutes.

[0090] This application case fully demonstrates the advantages of the method of the present invention: through a two-stage rewiring optimization strategy, the logic depth of the critical path is significantly reduced in the logic-level optimization stage, laying a good foundation for subsequent optimization; in the physical awareness optimization stage, physical layout information is fully considered to accurately optimize stubborn timing violations and achieve 100% timing convergence; compared with traditional methods, it significantly reduces area and power consumption overhead and improves the quality and efficiency of ECO optimization.

[0091] Example 2

[0092] This embodiment discloses an ECO timing optimization device based on logic rerouting. The device includes an ECO timing optimization system, such as... Figure 1 The diagram shown is a schematic representation of the composition of the ECO timing optimization system of the present invention.

[0093] The ECO timing optimization system includes: a netlist receiving module, a logic-level optimization module, a netlist integration module, a static timing analysis module, a physical sensing optimization module, and a verification module.

[0094] The netlist receiving module receives the design netlist and the functional patch netlist generated by the ECO tool; the logic-level optimization module performs rerouting optimization on the functional patch netlist before introducing physical layout information; the netlist integration module integrates the optimized patch netlist with the overall design netlist and introduces physical layout information; the static timing analysis module identifies timing critical paths; the physical awareness optimization module performs rerouting optimization on critical paths while considering physical layout constraints; and the verification module verifies the logical equivalence, timing constraints, and design rule constraints of the optimization scheme.

[0095] The logic-level optimization module includes: a data structure conversion unit, a candidate identification unit, and a rerouting engine; the data structure conversion unit is used to convert the functional patch netlist into a directed acyclic graph data structure; the candidate identification unit is used to identify candidate nodes and nets that can be rerouted; and the rerouting engine is used to apply rerouting algorithms to optimize the logic depth.

[0096] The physical sensing optimization module includes a local netlist extraction unit, a physical constraint analysis unit, and a delay optimization unit. The local netlist extraction unit is used to extract the local netlist of the critical path. The physical constraint analysis unit is used to analyze the unit location, net load, capacitance, and cabling congestion. The delay optimization unit is used to evaluate the impact of rerouting schemes on delay and select the optimal scheme.

[0097] To further illustrate the practical application of the device of the present invention, a detailed description of a complete system workflow is provided below.

[0098] An integrated circuit design company used the ECO timing optimization device of this invention to perform ECO optimization on an image processing chip. The chip uses a 16nm FinFET process, has a design scale of 2.2 million logic gates, and operates at a frequency of 1.5GHz. In the later stages of the design process, it was necessary to upgrade the image enhancement algorithm module, involving modifications to the RTL code and the generation of ECO patches.

[0099] The netlist receiving module receives the user-input design netlist and the function patch netlist generated by the ECO tool. The original design netlist is in Verilog format, containing 2,203,542 logic gate instances, using 7nm process cells from a standard cell library. The function patch netlist generated by the ECO tool (Easylogic ECO) based on modified RTL code contains 18,956 logic gates, involving functional modifications to 35 output ports. The netlist receiving module performs syntax checks and integrity verification on the input netlist, confirming that the netlist format is correct and that the referenced standard cell library is consistent.

[0100] The logic-level optimization module performs Pre-DEF rerouting optimization on the functional patch netlist. The data structure conversion unit converts the Verilog format patch netlist into a directed acyclic graph (DAG) data structure, which contains 18,956 nodes (corresponding to logic gates) and 29,473 directed edges (corresponding to signal connections). The candidate identification unit performs topology analysis on the DAG to identify critical paths and optimizable connections.

[0101] Candidate identification unit analysis revealed 412 candidate rerouting nodes on these critical paths. These nodes met the following conditions: their logical functions could be implemented by reconnecting other surrounding logic gates; rerouting could reduce the number of logic levels or fan-out load on the path; and rerouting would not affect the overall logical function of the patch. The rerouting engine employed a graph theory-based rerouting algorithm, combined with Alternative Wire-based Add-Remove (AWAR) rules, to evaluate the feasibility and optimization effect of rerouting for each of these 412 candidate nodes.

[0102] The rewiring engine's workflow is as follows:

[0103] For each candidate node, alternative logic gates for rerouting are searched within its surrounding logic cone. The impact of each rerouting scheme on logic depth and fan-out load is then evaluated. The rerouting scheme with the best optimization effect is selected. The rerouting transformation is applied to update the DAG data structure. The logical functional equivalence after rerouting is verified. After rerouting optimization, the average logic depth of the 23 critical paths decreased from level 15.1 to level 8.4, an optimization of 44.4%. The optimized patch netlist contains 18,234 logic gates, a reduction of 722 logic gates (3.8%) compared to the initial patch.

[0104] The netlist integration module integrates the optimized patch netlist with the overall design netlist. The integration process includes: converting the patch netlist back to Verilog format; locating the 35 error output ports that need correction in the original design netlist; connecting the patch's input ports to the corresponding signal nodes in the original netlist, with connection points determined by signal name matching; replacing the error output ports in the original netlist with the patch's output ports; and updating the netlist hierarchy, integrating the patch module as a sub-module into the top-level design.

[0105] After netlist integration, the module imports physical layout information. The DEF file (Design Exchange Format) contains complete chip layout information, including chip size (3.2mm × 3.5mm), the position of standard cell rows, the precise coordinates of all standard cell instances (represented in database units DBU, 1 DBU = 0.001 micrometers), power grid layout, and routing paths for special nets. The LEF file (Library Exchange Format) defines the physical characteristics of the standard cell library, including the physical dimensions of each cell, pin locations, metal layer information, delay models, etc. The module parses these files to build a complete physical design database.

[0106] The Static Timing Analysis (STA) module performs global STA analysis on the integrated design. This module uses industry-standard timing analysis tools (such as PrimeTime) to perform accurate delay calculations based on the physical design database. Analysis parameters are set as follows: operating frequency 1.5GHz (clock cycle 666.67ps); operating voltage 0.8V; operating temperature 125℃ (worst case corner); on-chip variation is considered; net delay is based on RC extraction results after actual routing.

[0107] Timing analysis revealed a total of 1,247,892 timing paths in the design, of which 2,358 were related to functional patch modules. Among these patch-related paths, 47 were critical paths with timing margins less than a preset threshold (set to 100ps). These paths were marked as timing critical paths requiring further optimization. The module sorted these 47 paths by timing margin from smallest to largest, with the top 10 paths having timing margins of -23ps, -18ps, -15ps, -12ps, -9ps, -6ps, -4ps, +8ps, +12ps, and +15ps. The first 7 paths exhibited timing violations (negative margins) and required focused optimization.

[0108] The physical sensing optimization module performs Post-DEF rerouting optimization on the identified timing-critical paths. The local netlist extraction unit extracts a local netlist for each critical path, containing all elements of that path, along with their Level 2 fan-in and Level 1 fan-out elements. Taking the path with the worst timing margin (-23ps) as an example, this path starts at the Q terminal of a register, passes through four logic gates (two AND gates, one OR gate, and one XOR gate) within the patching module, and reaches the D terminal of another register. The extracted local netlist contains the four logic gates on this path, along with their 12 fan-in elements and 3 fan-out elements, totaling 19 elements.

[0109] The physical constraint analysis unit performs detailed physical analysis on the local netlist. This unit extracts the precise location coordinates of each unit from the physical design database, calculates the Manhattan distance between units, analyzes the fan-out quantity, bus length, and total capacitance of each net, assesses the degree of cabling congestion in each area, avoids adding new connections in already congested areas, and checks design rule constraints to ensure that the rewiring scheme meets the rule requirements such as minimum spacing and maximum fan-out.

[0110] The delay optimization unit performed a precise delay assessment on the rerouting scheme: the output delay of U_AND_123 decreased from 78ps to 32ps, an improvement of 46ps; the output delay of U_AND_456 increased from 15ps to 38ps, an increase of 23ps; however, since U_AND_456 is not on the critical path, its delay increase does not affect the overall timing; the total delay of the critical path was reduced by 46ps, and the timing margin improved from -23ps to +23ps, successfully achieving timing convergence.

[0111] The physical sensing optimization module adopted a similar optimization strategy for the remaining 46 timing critical paths. After two rounds of iterative optimization, it successfully repaired all 7 timing violation paths, and the timing margin of the remaining 40 paths was further improved, with the average timing margin increasing from +28ps to +67ps.

[0112] The verification module comprehensively verifies the optimized solution. Logical equivalence verification uses a formal verification tool (Formality) to compare the rerouted netlist with the target netlist, verifying that the logical functions of all 35 corrected output ports are completely consistent, with a 100% pass rate. Timing verification involves rerunning static timing analysis to confirm that all timing paths meet the requirements: minimum setup time margin is +23ps, minimum hold time margin is +18ps, and there are no timing violations. Design rule checks verify that the rerouted netlist meets all physical design rules, including maximum fan-out limit (≤16), maximum transition time limit (≤150ps), and maximum capacitance limit (≤0.5pF), with no DRC violations.

[0113] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An ECO timing optimization method based on logic rerouting, characterized in that, The method includes the following steps: Step S1: Receive the design netlist input by the user and the function patch netlist generated by the ECO tool; Step S2: Before introducing physical layout information, perform logical-level rerouting optimization on the functional patch netlist to generate an optimized patch netlist. Step S3: Integrate the optimized patch netlist with the overall design netlist and introduce physical layout information; Step S4: Perform static timing analysis on the integrated design to identify the timing critical path containing the patch module; Step S5: For the time-critical path, perform physical-aware rewiring optimization while considering physical layout constraints. Step S6: Verify whether the optimization scheme meets the timing requirements. If it does, output the final version of the netlist. If it does not, return to step S5 for adjustment.

2. The ECO timing optimization method based on logic rerouting according to claim 1, characterized in that, Logical-level rerouting optimization of the aforementioned functional patch netlist includes: Step S2.1: Extract the functional patch netlist and convert it into a directed acyclic graph data structure; Step S2.2: Analyze the internal logical structure of the patch netlist and identify candidate nodes and nets that can be rewired. Step S2.3: Apply the rerouting algorithm to minimize the logic depth of the timing critical path without changing the logic function. Step S2.4: Generate the optimized new patch netlist.

3. The ECO timing optimization method based on logic rerouting according to claim 2, characterized in that, The rerouting algorithm optimizes the logic depth by bypassing multiple logic gates through rerouting. The method of bypassing multiple logic gates by rewiring is based on optional line addition and removal rules or error cancellation rules, and performs pure logic structure optimization under the condition of not being constrained by physical layout.

4. The ECO timing optimization method based on logic rerouting according to claim 3, characterized in that, Timing paths containing patch modules refer to timing paths that, in the integrated design netlist, at least partially pass through functional patch modules, identified through static timing analysis. Static timing analysis is then performed on these timing paths to obtain the critical timing paths containing the patch modules, specifically including the following steps: Step S4.1: Perform a global static timing analysis on the integrated design and calculate the delay of all paths; Step S4.2: Identify all timing paths that pass through the functional patch modules and establish a set of patch-related paths; Step S4.3: In the set of patch-related paths, select paths with timing margins less than a preset threshold as timing critical paths; Step S4.4: Sort the time-critical paths in ascending order of time-remaining margin, and prioritize optimizing the path with the smallest time-remaining margin. The timing margin is defined as the timing constraint requirement value of the path minus the actual delay value. When the timing margin is negative, it indicates that there is a timing violation in the path.

5. The ECO timing optimization method based on logic rerouting according to claim 4, characterized in that, The physical sensing rewiring optimization specifically includes the following steps: Step S5.1: For the time-critical path, extract its local netlist, which includes the units on the time-critical path and their fan-in and fan-out units; Step S5.2: Apply the rerouting algorithm while considering physical layout constraints, including cell location, net load and capacitance, and wiring congestion. Step S5.3: The optimization objective is to minimize the actual delay of the path. The impact of changes in network load after rerouting on the delay is evaluated, and the rerouting scheme that can reduce the total delay of the time-critical path and is physically feasible is selected first.

6. The ECO timing optimization method based on logic rerouting according to claim 5, characterized in that, The physical layout constraints in step S5.2 also include design rule check constraints to ensure that no new design rule checks are introduced to prevent violations.

7. The ECO timing optimization method based on logic rerouting according to claim 6, characterized in that, The physical layout information introduced in step S3 includes DEF files and LEF files; the DEF file is used to define the physical layout of the design, and the LEF file is used to define the physical characteristics of the standard cells.

8. An ECO timing optimization device based on logic rerouting, characterized in that, The apparatus includes an ECO timing optimization system, which is used to perform the method according to any one of claims 1-7; The ECO timing optimization system includes: a netlist receiving module, a logic-level optimization module, a netlist integration module, a static timing analysis module, a physical sensing optimization module, and a verification module; The netlist receiving module is used to receive the design netlist and the function patch netlist generated by the ECO tool; The logic-level optimization module is used to perform rerouting optimization on the functional patch netlist before introducing physical layout information; The netlist integration module is used to integrate the optimized patch netlist with the overall design netlist and to introduce physical layout information; The static timing analysis module is used to identify timing critical paths; The physical perception optimization module is used to optimize rewiring of time-critical paths while taking into account physical layout constraints. The verification module is used to verify the logical equivalence, timing constraints, and design rule constraints of the optimization scheme.

9. The ECO timing optimization device based on logic rerouting according to claim 8, characterized in that, The logic-level optimization module includes: a data structure transformation unit, a candidate identification unit, and a rewiring engine; The data structure conversion unit is used to convert the functional patch netlist into a directed acyclic graph data structure. The candidate identification unit is used to identify candidate nodes and nets that can undergo rewiring transformation; The rerouting engine is used to apply rerouting algorithms to optimize logic depth.

10. The ECO timing optimization device based on logic rerouting according to claim 9, characterized in that, The physical perception optimization module includes: a local netlist extraction unit, a physical constraint analysis unit, and a delay optimization unit; The local netlist extraction unit is used to extract the local netlist of the time-critical path; The physical constraint analysis unit is used to analyze unit location, network load, capacitance, and wiring congestion. The delay optimization unit is used to evaluate the impact of rewiring schemes on delay and select the optimal scheme.

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