Content addressable memory matching line structure and high-reliability search scheme thereof

Abstract

The invention provides a content addressable memory matching line structure and a high-reliability search scheme thereof, and relates to the field of integrated circuit design. The matching line structure comprises n-bit CAM circuit units, matching lines, sampling transistors, phase inverters and discharging transistors, wherein the n-bit CAM circuit units are completely identical, and the phase inverters and the discharging transistors are used for connecting the CAM circuit units and the matching lines. The interiors of the n-bit CAM circuit units are respectively composed of a magnetic tunnel junction / CMOS hybrid logic network and a reading circuit, the output of the first-bit CAM circuit unit is connected with a matching line through a sampling transistor, and the matching line is charged when a search result is matching, so that the matching line is kept at a high level; the outputs of the rest n-1 CAM circuit units are connected with the input ends of n-1 phase inverters, and the outputs of the phase inverters control the grid electrodes of the corresponding discharge transistors so as to control whether the matching lines discharge or not. The latch structure of the reading circuit is effectively utilized, charges are supplemented for ML when the ML has an electric leakage trend, the ML is stably kept at a high level, and a correct result is output.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design, and in particular to a content addressable memory match line structure and a high-reliability search scheme thereof. BACKGROUND

[0002] With the rapid development of integrated circuit technology, complementary metal-oxide-semiconductor (CMOS) devices are continuously evolving towards miniaturization and high performance. In this process, the problem of leakage current is increasingly prominent, becoming a key bottleneck restricting the further improvement of CMOS technology. In CMOS devices, when the transistor gate voltage is lower than the threshold voltage, there will still be a small current flowing through, which is due to the reduction of the potential barrier between the source and drain of the transistor in the sub-threshold region, and the enhancement of the carrier tunneling effect, which is closely related to the physical structure of the device, material properties, etc., and is affected by environmental factors such as temperature. For example, in the sub-threshold region of the transistor, the increase in temperature reduces the energy barrier between the source and channel of the transistor, resulting in a significant increase in sub-threshold leakage current. At the same time, the increase in temperature will exacerbate the process of heat generation and recombination of carriers, causing the reverse leakage current of the source-drain junction to increase. The aggravation of the leakage current problem not only increases the static power consumption of the CMOS circuit, reduces the power efficiency, but also may affect the logic function stability, signal transmission accuracy and overall reliability of the circuit. Especially in the application scenarios of low-power and high-performance integrated circuits, this problem is increasingly prominent and needs to be further studied and effectively solved.

[0003] Content addressable memory (CAM) has been widely used in various applications such as network routers, lookup tables and virus checkers due to its high speed and fully parallel data search characteristics. In traditional memory structures, data reading and writing operations often rely on fixed address mapping rules, making it difficult to flexibly cope with the increase in data volume and the diversification of data access patterns, to some extent, limiting the overall performance improvement of the system. Especially in key areas such as large-scale data processing, real-time control and multi-task parallel processing, traditional memories gradually expose deficiencies in address allocation efficiency, data access speed and storage resource dynamic management, etc. CAM aims to break through these limitations, providing more efficient, flexible and reliable storage solutions for electronic devices and information systems through innovative addressing mechanisms and storage architecture design. Due to the unique high-parallel characteristics of CAM, the small sub-threshold current of the discharge transistor in each bit circuit is combined into a larger leakage current, causing the match line to fail to maintain at a high level. Especially under high temperature conditions, the fast leakage speed of the match line causes its logic value to flip, resulting in incorrect search results.

[0004] Existing technologies primarily employ NAND or NOR type CAM matching line structures. While the NAND type structure offers advantages such as low power consumption and high temperature resistance, its low reliability and high latency fail to meet the demands of high-speed query applications. Therefore, the NOR type structure is more commonly used in existing CAM applications, but it still suffers from extremely low reliability under high-temperature environments. Summary of the Invention

[0005] Purpose of the invention: To address the shortcomings of the prior art, this invention proposes a matching line structure for content addressable memory. In high-temperature environments, the matching line is charged by utilizing the interlocking structure in the precharge read amplifier circuit (PCSA), which suppresses the matching line leakage problem caused by subthreshold current and improves the search reliability of the circuit.

[0006] To achieve the above technical objectives, the present invention proposes a content addressable memory match line structure comprising an identical n-bit CAM circuit unit, a match line, a sampling transistor, and an inverter and a discharge transistor for connecting the CAM circuit unit and the match line.

[0007] Each n-bit CAM circuit unit consists of a magnetic tunnel junction / CMOS hybrid logic network and a read circuit. The output of the first CAM circuit unit is connected to the matching line via a sampling transistor. When a match is found, the matching line is charged, keeping it at a high level. The outputs of the remaining n-1 CAM circuit units are connected to the inputs of n-1 inverters. The outputs of the inverters control the gates of the corresponding discharge transistors, thereby controlling whether the matching line is discharged.

[0008] When the search result is a match, the C1 circuit unit outputs a high level to charge the matching line, C2-C n The high-level output causes the discharge transistor N7-N to discharge. n+5 When switched off, the matching line remains high because there is no discharge path. However, due to transistor N7-N... n+5 If the transistor cannot be in the ideal cutoff region, a small leakage current will flow, causing slow leakage in the matching line. This is especially true under high-temperature conditions, where the temperature rise causes the N7-N transistor to leak. n+5 Increased leakage current causes the matching line to leak to a low level more quickly, resulting in incorrect output. In the high-temperature resistant CAM matching line structure proposed in this invention, when the matching line tends to discharge incorrectly, the latching structure in circuit unit C1 replenishes the charge of the matching line, forcibly maintaining the voltage of the matching line at a high level, ensuring that the circuit is not affected by high-temperature conditions and operates normally.

[0009] As a preferred embodiment, the aforementioned high-temperature resistant and highly reliable CAM matching line structure includes: the output of the C1 circuit unit is connected to the drain of the sampling transistor N6, the source of N6 is connected to the matching line ML, and its gate is controlled by the sampling signal SAM; C2-C n Given n-1 identical circuit units, their outputs are respectively connected to inverters I1-I n-1 Connect the input terminals of the inverter I1-I to the inverter. n-1 The output terminals are respectively connected to discharge transistors N7-N n+5 Gate of the discharge transistor N7-N n+5 The source is grounded, and the drain is connected to the matching line ML.

[0010] As a preferred embodiment, the aforementioned magnetic tunnel junction / CMOS hybrid logic network includes: an NMOS transistor N2, whose drain is connected to the source of N0, whose source is connected to the upper end of the magnetic tunnel junction M1, and whose gate is connected to the input search signal SL; an NMOS transistor N3, whose drain is connected to the source of N0, whose source is connected to the upper end of the magnetic tunnel junction M0, and whose gate is connected to the input search signal SLB; an NMOS transistor N4, whose drain is connected to the source of N1, whose source is connected to the upper end of the magnetic tunnel junction M1, and whose gate is connected to the input search signal SLB; an NMOS transistor N5, whose drain is connected to the source of N1, whose source is connected to the upper end of the magnetic tunnel junction M0, and whose gate is connected to the input search signal SL; a magnetic tunnel junction M0, whose upper end is connected to the sources of N3 and N5, and whose lower end is grounded; and a magnetic tunnel junction M1, whose upper end is connected to the sources of N2 and N4, and whose lower end is grounded.

[0011] As a preferred embodiment, the above-mentioned read circuit includes: a PMOS transistor P0, whose source is connected to VDD, and whose drain is connected to the drain of N0, the drain of P1, and the gates of N1 and P2, forming a node QB, and whose gate is connected to the precharge input signal PRE; a PMOS transistor P1, whose source is connected to VDD, and whose drain is connected to the drain of N0, the drain of P0, and the gates of N1 and P2, and whose gate is connected to node Q; and a PMOS transistor P2, whose source is connected to VDD, and whose drain is connected to the drain of N1 and the drain of P3. The PMOS transistor P3 has its source connected to VDD, its drain connected to the drains of N1 and P2, and the gates of N0 and P1, and its gate connected to the precharge input signal PRE; the NMOS transistor N0 has its drain connected to node QB, its source connected to the drains of N2 and N3, and its gate connected to node Q; the NMOS transistor N1 has its drain connected to node Q, its source connected to the drains of N4 and N5, and its gate connected to node QB.

[0012] Furthermore, this invention also discloses a highly reliable search scheme for the above-mentioned addressable memory matching line structure, which enables the above-mentioned CAM matching line structure to have high reliability and stability when the search results are both matched and unmatched, as detailed below: When all search results for the n-bit CAM unit circuit are matches: In C1-C n In the circuit unit, the discharge speed of the left discharge branch is greater than that of the right discharge branch. The logic value of node QB is '0', and the logic value of node Q is '1'. Node Q in circuit unit C1 charges the matching line to a high level. Circuit unit C2-C n Node Q in the circuit outputs a logic value of '0' after passing through inverter I1-In-1, causing discharge transistors N7-N to discharge. n+5 In the off state, the matching line ML remains at a high level because there is no discharge path; under high temperature conditions, the discharge transistor N7-N n+5 The leakage current is relatively large, and the leakage speed of the matching line ML is relatively fast. When the matching line ML starts to show leakage tendency, the node Q voltage decreases, P2 in the read circuit latch structure is in the conducting state, and VDD continuously charges the node Q, so that the matching line ML is kept at a high level and the correct result is output.

[0013] When the search result for C1 is a non-match, C2-C n When all search results are matches: In circuit unit C1, the discharge rate of the left discharge branch is less than that of the right discharge branch, the logic value of node QB is '1', and the logic value of node Q is '0'; node Q in circuit unit C1 cannot provide charge to the matching line ML, and the voltage of ML will remain at a low level; in circuit unit C2-C n In the circuit, the discharge speed of the left discharge branch is greater than that of the right discharge branch. The logic value of node QB is '0', and the logic value of node Q is '1'. Node Q passes through inverter I1-I n-1 The output logic value is '0', causing the discharge transistors N7-N to discharge. n+5 When in the cutoff state, the matching line ML remains at a low level; therefore, high temperature conditions have no significant effect on the voltage state of the matching line.

[0014] When the search result for C1 is a match, C2-C n When the search results show one or more mismatches: In circuit unit C1, the discharge rate of the left discharge branch is greater than that of the right discharge branch. The logic value of node QB is '0', and the logic value of node Q is '1'. Node Q in circuit unit C1 charges the matching line to a high level. In circuit units C2-C... nIn the matching bits, the discharge speed of the left discharge branch is greater than that of the right discharge branch. The logic value of node QB is '0', and the logic value of node Q is '1'. After passing through the corresponding inverter, node Q outputs a logic value of '0', causing the corresponding discharge transistor to be in the off state. In circuit unit C2-C n In the mismatched bits, the discharge speed of the left discharge branch is less than that of the right discharge branch. The logic value of node QB is '1', and the logic value of node Q is '0'. After passing through the corresponding inverter, node Q outputs a logic value of '1', which makes the corresponding discharge transistor in the conducting state. The matching line ML will discharge quickly to a low level through the corresponding discharge path. Therefore, high temperature conditions have no significant effect on the voltage state of the matching line.

[0015] Beneficial Effects: This invention proposes a high-temperature resistant, high-reliability CAM matching line structure. In an n-bit parallel CAM circuit, when the search result is a mismatch, high temperature conditions have no significant impact on the voltage state of the matching line ML. However, when the search result is a full match, high temperature conditions increase the leakage current of the discharge transistor, causing ML to fail to maintain a high level and thus outputting an incorrect matching result. This invention uses the C1 circuit unit as the voltage source for the matching line, effectively utilizing the latching structure of the read circuit in the C1 unit to replenish charge to ML when it shows a leakage tendency, thus stabilizing it at a high level and outputting the correct result. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a high-reliability CAM matching line structure that is resistant to high temperatures.

[0017] Figure 2 This is a schematic diagram of the internal circuit structure of the CAM unit.

[0018] Figure 3 This is a functional diagram of a high-reliability CAM matching line that is resistant to high temperatures. Detailed Implementation

[0019] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0020] See Figure 1This invention proposes a high-reliability CAM matching line structure resistant to high temperatures, comprising n identical CAM circuit units, a matching line, a sampling transistor, and inverters and discharge transistors for connecting the CAM circuit units to the matching line. The output of the first CAM circuit unit is connected to the matching line via the sampling transistor, serving as a voltage source to supply voltage to the matching line when a match is found. The outputs of the remaining n-1 CAM circuit units are connected to the inputs of n-1 inverters. The outputs of the inverters control the gates of the corresponding discharge transistors, thereby controlling whether the matching line discharges.

[0021] See Figure 2 Each n-bit CAM circuit unit consists of two parts: a magnetic tunnel junction / CMOS hybrid logic network and a read circuit. The magnetic tunnel junction / CMOS hybrid logic network includes NMOS transistors N2-N5 and magnetic tunnel junctions M0 and M1; the read circuit includes PMOS transistors P0-P3 and NMOS transistors N0 and N1.

[0022] The connection relationships of each component are as follows: The source of P0 is connected to VDD, and the drain of P0 is connected to the drain of N0, the drain of P1, the gate of N1, and the gate of P2. The gate of P1 is connected to the precharge signal PRE. The source of P1 is connected to VDD. The drain of P1 is connected to the drain of N0, the drain of P0, the gate of N1, and the gate of P2. The gate of P1 is connected to the gate of N0, the drain of P2, the drain of N1, and the drain of P3. The source of P2 is connected to VDD. The drain of P2 is connected to the drain of N1, the drain of P3, the gate of N0, and the gate of P1. The gate of P2 is connected to the gate of N1, the drain of P1, the drain of N0, and the drain of P0. The source of P3 is connected to VDD, and the drain of P3 is connected to the drain of N0, the drain of P1, the gate of P4, the gate of N1, and the gate of P2. The gate of P3 is connected to the precharge signal PRE. The source of N0 is connected to the drain of N2 and the drain of N3. The drain of N0 is connected to the drain of P0, the drain of P1, the gate of N1, and the gate of P2. The gate of N0 is connected to the gate of P1, the drain of P2, the drain of N1, and the drain of P3. The source of N1 is connected to the drain of N4 and the drain of N5. The drain of N1 is connected to the drain of P2, the drain of P3, the gate of N0, and the gate of P1. The gate of N1 is connected to the gate of P2, the drain of P1, the drain of N0, and the drain of P0. The source of N2 is connected to the upper end of the magnetic tunnel junction M1 and the source of N4. The drain of N2 is connected to the source of N0 and the drain of N3. The gate search signal of N2 is SL. The source of N3 is connected to the upper end of the magnetic tunnel junction M0 and the source of N5. The drain of N3 is connected to the source of N0 and the drain of N2. The gate search signal of N3 is SLB. The source of N4 is connected to the upper end of the magnetic tunnel junction M1 and the source of N2. The drain of N4 is connected to the source of N1 and the drain of N5. The gate search signal of N4 is SLB. The source of N5 is connected to the upper end of the magnetic tunnel junction M0 and the source of N3. The drain of N5 is connected to the source of N1 and the drain of N3. The gate search signal of N5 is SL. The upper end of the magnetic tunnel junction M0 is connected to the source of N3 and the source of N5, and the lower end of the magnetic tunnel junction M0 is grounded. The upper end of the magnetic tunnel junction M1 is connected to the source of N2 and the source of N4, and the lower end of the magnetic tunnel junction M1 is grounded. It should be noted that there is some repetition in the above connections, but this has been retained for ease of understanding.

[0023] See Figure 3 The aforementioned CAM matching line structure exhibits high reliability and stability in both matched and unmatched search results. Under high-temperature conditions, the matching line ML can still suppress the impact of leakage current on the matching results and maintain a high level for an extended period. The specific search process is as follows: (1) When all search results for the n-bit CAM unit circuit are matches: In C1-C n In the circuit unit, the discharge speed of the left discharge branch is greater than that of the right discharge branch. The logic value of node QB is '0', and the logic value of node Q is '1'. Node Q in circuit unit C1 charges the matching line to a high level. Circuit unit C2-C n Node Q in the circuit passes through inverter I1-I n-1 The output logic value is '0', causing the discharge transistors N7-N to discharge. n+5 In the off state, the matching line ML remains at a high level because there is no discharge path; under high temperature conditions, the discharge transistor N7-N n+5 The leakage current is relatively large, and the leakage speed of the matching line ML is relatively fast. When the matching line ML starts to show leakage tendency, the node Q voltage decreases, P2 in the read circuit latch structure is in the conducting state, and VDD continuously charges the node Q, so that the matching line ML is kept at a high level and the correct result is output.

[0024] (2) When the search result for C1 is a mismatch, C2-C n When all search results are matches: In circuit unit C1, the discharge rate of the left discharge branch is less than that of the right discharge branch, the logic value of node QB is '1', and the logic value of node Q is '0'; node Q in circuit unit C1 cannot provide charge to the matching line ML, and the voltage of ML will remain at a low level; in circuit unit C2-C n In the circuit, the discharge speed of the left discharge branch is greater than that of the right discharge branch. The logic value of node QB is '0', and the logic value of node Q is '1'. Node Q passes through inverter I1-I n-1 The output logic value is '0', causing the discharge transistors N7-N to discharge. n+5 When in the cutoff state, the matching line ML remains at a low level; therefore, high temperature conditions have no significant effect on the voltage state of the matching line.

[0025] (3) When the search result for C1 is a match, C2-C n When the search results show one or more mismatches: In circuit unit C1, the discharge rate of the left discharge branch is greater than that of the right discharge branch. The logic value of node QB is '0', and the logic value of node Q is '1'. Node Q in circuit unit C1 charges the matching line to a high level. In circuit units C2-C... n In the matching bits, the discharge speed of the left discharge branch is greater than that of the right discharge branch. The logic value of node QB is '0', and the logic value of node Q is '1'. After passing through the corresponding inverter, node Q outputs a logic value of '0', causing the corresponding discharge transistor to be in the off state. In circuit unit C2-C n In the mismatched bits, the discharge speed of the left discharge branch is less than that of the right discharge branch. The logic value of node QB is '1', and the logic value of node Q is '0'. After passing through the corresponding inverter, node Q outputs a logic value of '1', which makes the corresponding discharge transistor in the conducting state. The matching line ML will discharge quickly to a low level through the corresponding discharge path. Therefore, high temperature conditions have no significant effect on the voltage state of the matching line.

[0026] It is worth noting that the mismatches described in (2) and (3) above are in Figure Three The same waveform and search result are observed in both cases. The high-temperature resistant and highly reliable CAM matching line structure proposed in this invention, in an n-bit parallel CAM circuit, when the search result is mismatched, the high temperature condition has no significant impact on the voltage state of the matching line ML. When the search result is a full match, the high temperature condition increases the leakage current of the discharge transistor, causing ML to fail to maintain a high level normally, thus outputting an incorrect matching result. This invention uses the C1 circuit unit as the voltage source of the matching line, effectively utilizing the latching structure of the read circuit in the C1 unit to replenish charge to ML when it has a leakage tendency, so that it can be stably maintained at a high level and output the correct result.

[0027] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A content-addressable memory matching line structure, characterized in that, include: Identical n-bit CAM circuit units, matching lines, sampling transistors, and inverters and discharge transistors for connecting the CAM circuit units to the matching lines; Each of the n-bit CAM circuit units consists of two parts: a magnetic tunnel junction / CMOS hybrid logic network and a read circuit. The output of the first CAM circuit unit is connected to the matching line through a sampling transistor. When the search result is a match, the matching line is charged to keep it at a high level. The outputs of the remaining n-1 CAM circuit units are connected to the inputs of n-1 inverters. The outputs of the inverters control the gates of the corresponding discharge transistors, thereby controlling whether the matching line is discharged.

2. The content-addressable memory matching line structure according to claim 1, characterized in that, The output of CAM circuit unit C1 is connected to the drain of sampling transistor N6, the source of N6 is connected to the matching line ML, and its gate is controlled by the sampling signal SAM. CAM circuit unit C2-C n The outputs are respectively connected to inverters I1-I n-1 The input terminals are connected to the inverter I1-I. n-1 The output terminals are respectively connected to discharge transistors N7-N n+5 Gate of the discharge transistor N7-N n+5 The source is grounded, and the drain is connected to the matching line ML.

3. The content-addressable memory matching line structure according to claim 1, characterized in that, The magnetic tunnel junction / CMOS hybrid logic network includes: NMOS transistor N2 has its drain connected to the source of N0, its source connected to the upper end of magnetic tunnel junction M1, and its gate connected to the input search signal SL. NMOS transistor N3 has its drain connected to the source of N0, its source connected to the upper end of magnetic tunnel junction M0, and its gate connected to the input search signal SLB. The drain of N4 is connected to the source of N1, the source is connected to the upper end of the magnetic tunnel junction M1, and the gate is connected to the input search signal SLB. NMOS transistor N5 has its drain connected to the source of N1, its source connected to the upper end of magnetic tunnel junction M0, and its gate connected to the input search signal SL. The magnetic tunnel junction M0 has its upper end connected to the sources of N3 and N5, and its lower end grounded. The magnetic tunnel junction M1 is connected to the sources of N2 and N4 at its upper end and grounded at its lower end.

4. The content-addressable memory matching line structure according to claim 1, characterized in that, The read circuit includes: PMOS transistor P0 has its source connected to VDD, its drain connected to the drain of N0, the drain of P1, and the gates of N1 and P2, and a node QB is set. Its gate is connected to the precharge input signal PRE. PMOS transistor P1 has its source connected to VDD, its drain connected to the drain of N0, the drain of P0, and the gates of N1 and P2, and its gate connected to node Q. PMOS transistor P2 has its source connected to VDD, its drain connected to the drain of N1, the drain of P3, and the gates of N0 and P1, and is configured with node Q, with its gate connected to node QB. PMOS transistor P3 has its source connected to VDD, its drain connected to the drain of N1, the drain of P2, and the gates of N0 and P1, and its gate connected to the precharge input signal PRE. NMOS transistor N0 has its drain connected to node QB, its source connected to the drains of N2 and N3, and its gate connected to node Q. NMOS transistor N1 has its drain connected to node Q, its source connected to the drains of N4 and N5, and its gate connected to node QB.

5. A highly reliable search scheme based on the content-addressable memory matching line structure according to any one of claims 1 to 4, characterized in that, When all search results for the n-bit CAM unit circuit are matches: In CAM circuit unit C1-C n In the circuit, the discharge speed of the left discharge branch is greater than that of the right discharge branch. The logic value of node QB is '0', and the logic value of node Q is '1'. Node Q in CAM circuit unit C1 charges the matching line to a high level. CAM circuit unit C2-C n Node Q in the circuit outputs a logic value of '0' after passing through inverter I1-In-1, causing discharge transistors N7-N to discharge. n+5 When in the cutoff state, the matching line ML remains at a high level because there is no discharge path; Under high temperature conditions, discharge transistor N7-N n+5 When the leakage current exceeds the predetermined value, the leakage speed of the matching line ML reaches the preset condition. When the matching line ML starts to show leakage tendency, the voltage of node Q decreases, P2 in the read circuit latch structure is in the on state, and VDD continuously charges node Q, so that the matching line ML is kept at a high level and the correct result is output.

6. A highly reliable search scheme based on the content-addressable memory matching line structure according to any one of claims 1 to 4, characterized in that, When the search result for CAM circuit unit C1 is a mismatch, CAM circuit unit C2-C n When all search results are matches: In CAM circuit unit C1, the discharge rate of the left discharge branch is less than that of the right discharge branch. The logic value of node QB is '1' and the logic value of node Q is '0'. Node Q in CAM circuit unit C1 cannot provide charge to the matching line ML, and the voltage of ML will remain at a low level. In CAM circuit unit C2-C n In the circuit, the discharge speed of the left discharge branch is greater than that of the right discharge branch. The logic value of node QB is '0', and the logic value of node Q is '1'. Node Q passes through inverter I1-I n-1 The output logic value is '0', causing the discharge transistors N7-N to discharge. n+5 When in the off state, the matching line ML remains at a low level.

7. A highly reliable search scheme based on the content-addressable memory matching line structure according to any one of claims 1 to 4, characterized in that, When the search result for CAM circuit unit C1 is a match, CAM circuit unit C2-C n When the search results show one or more mismatches: In CAM circuit unit C1, the discharge speed of the left discharge branch is greater than that of the right discharge branch. The logic value of node QB is '0', and the logic value of node Q is '1'. Node Q in CAM circuit unit C1 charges the matching line to a high level. In CAM circuit unit C2-C n In the matching bit, the discharge speed of the left discharge branch is greater than that of the right discharge branch. The logic value of node QB is '0', the logic value of node Q is '1', and the output logic value of node Q is '0' after passing through the corresponding inverter, so that the corresponding discharge transistor is in the off state. In CAM circuit unit C2-C n In the mismatch bit, the discharge speed of the left discharge branch is less than that of the right discharge branch. The logic value of node QB is '1', and the logic value of node Q is '0'. After passing through the corresponding inverter, node Q outputs a logic value of '1', which makes the corresponding discharge transistor in the on state. The matching line ML will discharge to the low level quickly through the corresponding discharge path.

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