An ultrathin planar back contact cell, a preparation method thereof and a battery assembly

Abstract

The present application belongs to the technical field of back contact cells, and particularly relates to an ultrathin planar back contact cell, a preparation method thereof and a battery assembly, which comprises a crystalline silicon substrate and an amorphous silicon layer arranged in sequence, wherein the side surface of the amorphous silicon layer away from the crystalline silicon substrate has alternately formed N-type doped regions and P-type doped regions, and an isolation region arranged between the N-type doped regions and the P-type doped regions; wherein the ratio of the highest H doped concentration to the highest P doped concentration in the N-type doped region is 0.2-10, the ratio of the highest H doped concentration to the highest B doped concentration in the P-type doped region is not less than 1.2, and the thickness of the N-type doped region and the P-type doped region is independently not more than 10 nm. The present application can improve the carrier transport performance and reduce the carrier recombination rate under the condition of adopting a flat back contact cell structure, thereby improving the cell conversion efficiency; meanwhile, the stress concentration and edge recombination are reduced, and the risk of film explosion and electric leakage is reduced.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of back contact cells, and particularly relates to an ultrathin planar back contact cell and a preparation method and a cell assembly thereof. BACKGROUND

[0002] At present, the back contact cell generally adopts a structure in which the thickness of the P-type region is higher than that of the N-type region. This structure meets the process requirements to some extent, but has many deficiencies. For example, due to the thickness difference between the P-type region and the N-type region, stress is concentrated at the junction of the N / P regions of the cell, and the edge recombination problem is aggravated.

[0003] In addition, the thickness difference also causes the back surface reflection layer to be uneven in appearance, reduces the back reflectivity, and affects the cell conversion efficiency of the cell. At the same time, stress mismatch also causes the film to be prone to burst in subsequent processes, increasing the production cost and risk. Therefore, it is of important practical significance and application value to develop a new type of ultrathin planar back contact cell to solve the defects in the prior art.

[0004] It should be noted that this part of the present application only provides background technology related to the present application, and does not necessarily constitute prior art or public knowledge. SUMMARY

[0005] The purpose of the present application is to overcome the defects of the conventional back contact cell structure in the prior art, such as edge recombination, reduced back reflectivity, low cell conversion efficiency, and increased risk of film burst, and to provide an ultrathin planar back contact cell and a preparation method and a cell assembly thereof. The cell assembly can improve the carrier transport performance and reduce the carrier recombination rate while adopting a flat back contact cell structure, thereby improving the cell conversion efficiency; at the same time, it can reduce stress concentration and edge recombination, and reduce the risk of film burst and electrical leakage.

[0006] To achieve the above-mentioned purpose, in a first aspect, the present application provides an ultrathin planar back contact cell, comprising a crystalline silicon substrate and an amorphous silicon layer arranged in sequence, wherein the side surface of the amorphous silicon layer away from the crystalline silicon substrate has alternately formed N-type doped regions and P-type doped regions, and an isolation region arranged between the N-type doped regions and the P-type doped regions; wherein the ratio of the highest H concentration to the highest P doping concentration in the N-type doped region is 0.2-10, the ratio of the highest H concentration to the highest B doping concentration in the P-type doped region is not less than 1.2, and the thickness of the amorphous silicon layer is 7-60 nm, and the thickness of each of the N-type doped region and the P-type doped region is not greater than 10 nm.

[0007] In some preferred embodiments of the present application, the ratio of the highest H concentration to the highest P doping concentration in the N-type doped region is 0.3-6, and / or the ratio of the highest H concentration to the highest B doping concentration in the P-type doped region is 1.2-15.

[0008] Preferably, the ratio of the thickness of the N-type doped region and the P-type doped region to the thickness of the amorphous silicon layer is (0.01-1):1.

[0009] In some preferred embodiments of the present invention, the isolation region is an amorphous silicon isolation region.

[0010] In some preferred embodiments of the present invention, the H concentration in the N-type doped region is 1e20cm⁻¹. -3 up to 5e22cm -3 P doping concentration is 1e20cm -3 up to 5e22cm -3 ; and / or, the H concentration in the P-type doped region is 1e20cm⁻¹ -3 up to 5e22cm -3 The boron doping concentration is 1e20cm. -3 up to 5e22cm -3 .

[0011] In some preferred embodiments of the present invention, the width ratio of the P-type doped region, the N-type doped region, and the isolation region is (3-20):(2-15):1, and / or the width of the isolation region is 30-200µm.

[0012] In some preferred embodiments of the present invention, the width of the P-type doped region is 300-1500µm, the width of the N-type doped region is 200-1000µm; and / or, the amorphous silicon layer is intrinsic amorphous silicon.

[0013] In some preferred embodiments of the present invention, the ultrathin planar back contact battery also has at least one of the following structures:

[0014] Structure 1: The ultra-thin planar back contact battery also includes: a transparent conductive film layer disposed on the outer surface of the amorphous silicon layer, and metal electrodes disposed on the outer surface of the transparent conductive film layers in the corresponding regions of the N-type doped region and the P-type doped region, respectively; and an isolation groove is formed on the transparent conductive film layer corresponding to the isolation region.

[0015] Structure 2: The surface of the amorphous silicon layer is planar;

[0016] Structure 3, the ultra-thin planar back contact battery also includes: depositing a passivation layer and an anti-reflection layer on the front side of a crystalline silicon substrate.

[0017] Secondly, the present invention provides a method for preparing an ultrathin planar back contact battery, comprising the following steps:

[0018] S1. Provide a crystalline silicon substrate;

[0019] S2. An intrinsic amorphous silicon layer is deposited on the back side of a crystalline silicon substrate. The thickness of the intrinsic amorphous silicon layer is 7-60 nm.

[0020] S3, performing first ion doping on a preset P-type doped region on the outer surface of the intrinsic amorphous silicon layer to form a P-type doped region;

[0021] S4, performing second ion doping on a preset N-type doped region on the outer surface of the intrinsic amorphous silicon layer to form an N-type doped region, and leaving an amorphous silicon isolation region between the preset P-type doped region and the preset N-type doped region, thereby forming an amorphous silicon layer, and the thickness of the amorphous silicon layer is 7-60 nm;

[0022] In the N-type doped region, the ratio of the highest concentration of H to the highest doping concentration of P is 0.2-10, and in the P-type doped region, the ratio of the highest concentration of H to the highest doping concentration of B is not less than 1.2, and the thickness of the N-type doped region and the P-type doped region is independently not more than 10 nm.

[0023] In some preferred embodiments of the present application, the preparation method further comprises at least one of the following processes:

[0024] Process one, in S2, the deposition of the intrinsic amorphous silicon layer is performed by a PECVD method;

[0025] Process two, in S3, the first ion doping and in S4, the second ion doping are each independently performed by forming a corresponding plasma by using a radio frequency power source, and a low frequency power source or a direct current power source;

[0026] Process three, in S3, the first ion doping is performed under the following conditions: a mixed gas containing diborane or trimethylboron and hydrogen is introduced, and at least one inert gas is introduced;

[0027] Process four, in S4, the second ion doping is performed under the following conditions: a mixed gas containing phosphine and hydrogen is introduced, and at least one inert gas is introduced.

[0028] In some preferred embodiments of the present application, the preparation method further comprises:

[0029] S5, depositing a transparent conductive film layer on the outer surface of the amorphous silicon layer, and opening an isolation groove on the transparent conductive film layer corresponding to the isolation region; and S6, respectively arranging a metal electrode on the transparent conductive film layer in the corresponding region of the N-type doped region and the P-type doped region.

[0030] And / or, depositing a passivation layer and an anti-reflection layer on the front surface of the crystalline silicon substrate.

[0031] In a third aspect, the present application provides an ultra-thin planar back contact cell prepared by the preparation method of the ultra-thin planar back contact cell according to the second aspect.

[0032] In a fourth aspect, the present application provides a battery assembly comprising the ultra-thin planar back contact cell according to the first aspect, or the ultra-thin planar back contact cell according to the third aspect.

[0033] Advantages:

[0034] The present application, by the above technical scheme, especially setting the flat amorphous silicon layer surface with N-type doped region, isolation region and P-type doped region at least partially in thickness, the isolation region is arranged between the N-type doped region and the P-type doped region, for effectively isolating the N-type doped region and the P-type doped region, preventing the generation of leakage, and the ratio of the highest concentration of H in the N-type doped region to the highest doping concentration of P, and the ratio of the highest concentration of H in the P-type doped region to the highest doping concentration of B are respectively in the appropriate range, and the thickness of the N-type doped region and the P-type doped region is respectively not more than 10 nm, it is found that the problem of different hole and electron transmission speeds of the N-type doped region and the P-type doped region can be overcome, and lower series resistance can still be obtained under the condition that the thickness of the two is the same, and low carrier recombination can be realized under a relatively thin thickness, which reconstructs the carrier transmission path, improves the effective hole mobility, and improves the ionization rate, bridges the carrier transmission speed difference between the N-type doped region and the P-type doped region, and obtains excellent transmission performance and low carrier recombination rate. At the same time, the conversion efficiency with commercial value can be obtained under the overall thickness of the battery. A possible speculation is that the ratio of the highest concentration of H in the N-type doped region to the highest doping concentration of P, and the ratio of the highest concentration of H in the P-type doped region to the highest doping concentration of B are controlled in a certain range, which reconstructs the carrier transmission path, and in the P region, the H-B complex may improve the effective hole mobility, and the doping of H weakens the B-Si bond and improves the ionization rate; the above-mentioned doping concentration ratio of H and P and the doping concentration ratio of H and B bridge the carrier transmission speed difference between the N-type doped region and the P-type doped region, and excellent transmission performance and low carrier recombination rate are obtained.

[0035] Furthermore, the flat amorphous silicon layer of the present application forms an ultra-thin planar back contact structure, effectively reduces the stress concentration at the junction of the N / P region, reduces the edge recombination, improves the battery conversion efficiency of the battery; at the same time, the morphology of the back reflector is flat, the back reflectivity is improved, and the battery conversion efficiency is further improved, and the risk of membrane rupture and leakage is reduced; at the same time, the ultra-thin planar back contact structure is adopted, the stress mismatch is reduced, the risk of membrane rupture is reduced, and the production cost and risk are reduced. The present application realizes the conversion efficiency with commercial value by comprehensively controlling the ratio of the highest concentration of H in the N-type doped region to the highest doping concentration of P, and the ratio of the highest concentration of H in the P-type doped region to the highest doping concentration of B under the overall thickness of the battery. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0037] Figure 1 Structure schematic diagram of a specific embodiment of the ultra-thin planar back contact cell of the present application.

[0038] Legend of reference signs

[0039] 1, crystalline silicon substrate; 2, intrinsic amorphous silicon layer; 3, P-type doped region; 4, N-type doped region; 5, transparent conductive film layer; 6, metal electrode. DETAILED DESCRIPTION

[0040] In the present application, the terms "first", "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0041] In the present application, unless otherwise explicitly specified and limited, the "on" or "under" of the first feature to the second feature can be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the "over", "above" and "on" of the first feature to the second feature can be that the first feature is directly above or obliquely above the second feature, or only means that the horizontal height of the first feature is higher than that of the second feature. The "under", "below" and "under" of the first feature to the second feature can be that the first feature is directly below or obliquely below the second feature, or only means that the horizontal height of the first feature is less than that of the second feature.

[0042] In this disclosure, the endpoints of the ranges and any values are not limited to the precise values stated. The ranges and values should be construed as including values that are approximately the same as the stated values. For numerical ranges, the end points of the ranges are included in the ranges, the end points of the ranges and the individual point values are combinable with each other to form one or more new numerical ranges, which should be considered as specifically disclosed herein. Among them, the terms "optional", "optional" mean that it can be included, or it can not be included (or it can be, or it can not be).

[0043] In the present application, the near crystalline silicon substrate is inside, and the far from the crystalline silicon substrate is outside.

[0044] In a first aspect, the present application provides an ultra-thin planar back contact cell, comprising a crystalline silicon substrate and an amorphous silicon layer arranged in sequence, wherein a side surface of the amorphous silicon layer away from the crystalline silicon substrate has N-type doped regions and P-type doped regions alternately formed, and an isolation region arranged between the N-type doped regions and the P-type doped regions; wherein a ratio of a highest H concentration in the N-type doped regions to a highest P doping concentration is 0.2-10, and a ratio of a highest H concentration in the P-type doped regions to a highest B doping concentration is not less than 1.2.

[0045] In the present application, the surface of the amorphous silicon layer is planar. The present application uses a planar amorphous silicon layer to form an ultra-thin planar back contact cell, so that a lower series resistance can be obtained under the condition that the thicknesses of the N / P regions of different polarities are the same, and low carrier recombination can be achieved at a relatively thin thickness, which reconstructs the carrier transport path, improves the effective hole mobility, and improves the ionization rate, thereby narrowing the difference in carrier transport speed between the N-type doped regions and the P-type doped regions, obtaining excellent transport performance and low carrier recombination rate, and reducing the risk of film explosion and leakage. At the same time, a conversion efficiency with commercial value can be obtained at a relatively thin thickness of the entire cell.

[0046] In the present application, the highest H concentration in the N-type doped regions and the highest P doping concentration refer to the highest concentration of any element contained in the N-type doped regions. Similarly, the highest H concentration in the P-type doped regions and the highest B doping concentration refer to the highest concentration of any element contained in the P-type doped regions. It can be understood that the N-type doped regions and the P-type doped regions can be uniformly doped or non-uniformly doped independently, and the non-uniform doping can be gradient doping, for example, gradient doping in the thickness direction. When the doping is uniform, the highest concentration is the uniform doping concentration.

[0047] In the present application, the ratio of the highest H concentration in the N-type doped regions to the highest P doping concentration is 0.2-10, for example, specifically 0.3, 0.5, 1, 1.5, 1.8, 2, 2.3, 2.5, 2.6, 2.7, 3, 3.3, 3.5, 3.7, 4, 4.2, 4.5, 4.7, 5, 6, 7, 8, 9 or 10, and any range between different point values. In some preferred embodiments of the present application, the ratio of the highest H concentration in the N-type doped regions to the highest P doping concentration is 0.3-6, more preferably 1-6.

[0048] Preferably, the ratio of the highest concentration of H to the highest concentration of B in the P-type doped region is 1.2-15, for example specifically 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2, 2.2, 2.5, 2.8, 3, 3.3, 3.5, 3.7, 4, 4.2, 4.5, 4.8, 5, 5.5, 6, 6.5, 7, 7.5, 8, 8.8, 9, 9.5, 10, 10.5, 11, 11.5, 12, 12.5, 13, 13.5, 14, 14.5, or 15, and ranges between any two different point values.

[0049] The present application employs N-type doped regions and / or P-type doped regions with suitable range of doping ratio, which is more conducive to improve the carrier lifetime and maintain good contact characteristics, and further reduce the risk of film explosion and leakage.

[0050] Preferably, the thickness of the amorphous silicon layer is 7-60nm, for example specifically 7nm, 7.5nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm, 20nm, 21nm, 22nm, 23nm, 24nm, 25nm, 26nm, 27nm, 28nm, 29nm, 30nm, 31nm, 32nm, 33nm, 34nm, 35nm, 36nm, 37nm, 38nm, 39nm, 40nm, 41nm, 42nm, 43nm, 44nm, 45nm, 46nm, 47nm, 48nm, 49nm, 50nm, 51nm, 52nm, 53nm, 54nm, 55nm, 56nm, 57nm, 58nm, 59 or 60nm, and ranges between any two different point values. The present application can form a back contact cell with an ultra-thin planar structure, while obtaining good cell conversion efficiency.

[0051] In the present application, the thickness of the N-type doped region and the P-type doped region is independently not more than 10nm, for example specifically 0.1nm, 0.3nm, 0.5nm, 0.8nm, 0.9nm, 1nm, 1.5nm, 2nm, 2.5nm, 3nm, 3.5nm, 4nm, 4.5nm, 5.5nm, 6nm, 6.5nm, 7nm, 7.5nm, 8nm, 8.5nm, 9nm, 9.5nm or 10nm, and ranges between any two different point values. The present application employs N-type doped regions and P-type doped regions with suitable thinness, which is more conducive to reduce carrier recombination loss, and further reduce the risk of film explosion and leakage.

[0052] Preferably, the ratio of the thickness of the N-type doped region and the P-type doped region to the thickness of the amorphous silicon layer is (0.01-1):1, for example, specifically, it can be 0.01:1, 0.05:1, 0.1:1, 0.2:1, 0.3:1, 0.32:1, 0.35:1, 0.38:1, 0.4:1, 0.42:1, 0.45:1, 0.48:1, 0.5:1, 0.6:1, 0.7:1, 0.8:1, 0.9:1 or 1:1, etc., and the range between any different point values, for example, it can be preferably (0.167-1):1, further preferably (0.167-0.9):1.

[0053] In the present application, the isolation region is an amorphous silicon isolation region. The amorphous silicon isolation region can be doped or undoped amorphous silicon.

[0054] In some preferred embodiments of the present application, the H concentration in the N-type doped region is 1e20 cm-3 to 5e22 cm-3. -3 to 5e22 cm-3. -3 , the P doping concentration is 1e20 cm-3 to 5e22 cm-3. -3 to 5e22 cm-3. -3 .

[0055] Preferably, the H concentration in the P-type doped region is 1e20 cm-3 to 5e22 cm-3. -3 to 5e22 cm-3. -3 , the B doping concentration is 1e20 cm-3 to 5e22 cm-3. -3 to 5e22 cm-3. -3 .

[0056] In some preferred embodiments of the present application, the width ratio of the P-type doped region, the N-type doped region and the isolation region is (3-20):(2-15):1, for example, it can be (3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 or 20):(2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 or 15):1, for example, specifically, it can be 3:2:1, 3:10:1, 5:2:1, 5:3:1, 5:4:1, 5:5:1, 5:15:1, 6:2:1, 6:3:1, 6:4:1, 6:5:1, 6:15:1, 7:2:1, 7:3:1, 7:4:1, 7:5:1, 20:2:1 or 2:15:1, etc., and the range between any different point values. The present application adopts the P-type doped region, the N-type doped region and the isolation region with a suitable range of width ratio, which is more conducive to increasing the effective collection area of carriers, reducing the series resistance and the recombination loss, and further reducing the risk of film explosion and leakage.

[0057] In some preferred embodiments of the present invention, the width of the isolation region is 30-200µm. An isolation region of suitable width is more conducive to effectively isolating N-type doped regions and P-type doped regions, further preventing the risk of leakage.

[0058] In some preferred embodiments of the present invention, the width of the P-type doped region is 300-1500µm.

[0059] Preferably, the width of the N-type doped region in this invention is 200-1000µm.

[0060] In some preferred embodiments of the present invention, the amorphous silicon layer is intrinsic amorphous silicon, which is more conducive to improving the surface passivation effect. It is understood that the undoped amorphous region is intrinsic amorphous silicon.

[0061] In some preferred embodiments of the present invention, the ultrathin planar back contact battery further includes: a transparent conductive film layer disposed on the outer surface of an amorphous silicon layer, and metal electrodes disposed on the outer surfaces of the transparent conductive film layers in the corresponding regions of the N-type doped region and the P-type doped region, respectively. The deposition method, thickness, and type of the transparent conductive film layer can refer to existing techniques, such as physical vapor deposition (PVD) or activated plasma deposition (RPD). For example, the thickness of the transparent conductive film layer is 40-100 nm, and the material of the transparent conductive film layer can be an indium oxide-based thin film doped with at least one of tin, tungsten, titanium, zinc, and gallium, or a zinc oxide-based thin film doped with at least one of aluminum, gallium, and boron; both can be used in the present invention. It is understood that the metal electrodes include a first metal electrode and a second metal electrode. The first metal electrode is disposed on the outer surface of the corresponding region of the N-type doped region, and a second metal electrode with a different polarity than the first metal electrode is also disposed on the outer surface of the corresponding region of the P-type doped region. The metal electrodes are existing technology and will not be described in detail here.

[0062] Preferably, in this invention, an isolation trench is formed on the transparent conductive film layer corresponding to the isolation region to isolate the N-type doped region and the P-type doped region.

[0063] In some preferred embodiments of the present invention, the ultrathin planar back contact battery further includes: depositing a passivation layer and an antireflection layer on the front side of a crystalline silicon substrate.

[0064] Secondly, the present invention provides a method for preparing an ultrathin planar back contact battery, comprising the following steps:

[0065] S1. Provide a crystalline silicon substrate;

[0066] S2. An intrinsic amorphous silicon layer is deposited on the back side of a crystalline silicon substrate. The thickness of the intrinsic amorphous silicon layer is 7-60 nm.

[0067] S3. Perform first ion doping on the preset P-type doped region on the outer surface of the intrinsic amorphous silicon layer to form a P-type doped region;

[0068] S4. A second ion doping is performed on the preset N-type doped region on the outer surface of the intrinsic amorphous silicon layer to form an N-type doped region, and an amorphous silicon isolation region is left between the preset P-type doped region and the preset N-type doped region, thereby forming an amorphous silicon layer with a thickness of 7-60nm.

[0069] Preferably, the ratio of the highest H concentration to the highest P doping concentration in the N-type doped region is controlled to be 0.2-10, the ratio of the highest H concentration to the highest B doping concentration in the P-type doped region is not less than 1.2, and the thickness of the N-type doped region and the P-type doped region are each independently not greater than 10 nm.

[0070] In some preferred embodiments of the present invention, in S2, the deposition of the intrinsic amorphous silicon layer is carried out using the PECVD method, which is more conducive to passivating the silicon wafer surface and subsequent fabrication of doped layers.

[0071] In some preferred embodiments of the present invention, the first ion doping in S3 and the second ion doping in S4 are each independently generated into corresponding plasmas using a radio frequency power supply and a low-frequency power supply or a DC power supply. More preferably, using a radio frequency power supply and a low-frequency power supply is more conducive to increasing the effective doping concentration.

[0072] In some preferred embodiments of the present invention, in step S3, the conditions for the first ion doping include: introducing a gas mixture containing diborane or trimethylborane and hydrogen, and introducing at least one inert gas. The flow rate of the mixed gas can be, for example, 10,000-100,000 sccm, and the flow rate ratio of diborane or trimethylborane to hydrogen can be, for example, (0.003-0.4):1, as long as a target film layer with the target doping concentration and thickness can be obtained.

[0073] In some preferred embodiments of the present invention, in step S4, the conditions for the second ion doping include: introducing a mixed gas containing phosphine and hydrogen, and introducing at least one inert gas. The flow rate of the mixed gas can be, for example, 10,000-100,000 sccm, and the flow rate ratio of phosphine to hydrogen can be, for example, (0.003-0.5):1, as long as the target doping concentration and thickness of the target film layer can be obtained.

[0074] In this invention, the inert gas can be, for example, argon and / or helium.

[0075] In some preferred embodiments of the present invention, the preparation method further includes: S5, depositing a transparent conductive film layer on the outer surface of the amorphous silicon layer, and forming an isolation trench on the transparent conductive film layer corresponding to the isolation region; S6, respectively setting metal electrodes on the outside of the transparent conductive film layer in the corresponding regions of the N-type doped region and the P-type doped region.

[0076] In some preferred embodiments of the present invention, a passivation layer and an antireflection layer are deposited on the front side of a crystalline silicon substrate. The crystalline silicon substrate is made of materials such as monocrystalline silicon. The steps of depositing the passivation layer and the antireflection layer can be performed in S1, or after the corresponding doped region is formed in S4 and before the transparent conductive film layer is formed in S5.

[0077] Thirdly, the present invention provides an ultrathin planar back contact battery, which is prepared by the method for preparing an ultrathin planar back contact battery described in the second aspect. The structure and performance of the ultrathin planar back contact battery of the third aspect are the same as those of the ultrathin planar back contact battery of the first aspect, and will not be described again here.

[0078] Fourthly, the present invention provides a battery assembly comprising the ultrathin planar back contact battery described in the first aspect, or comprising the ultrathin planar back contact battery described in the third aspect.

[0079] The embodiments of the present invention described below are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0080] Example 1

[0081] An ultra-thin planar back contact battery, such as Figure 1 As shown, it is prepared by the following method:

[0082] S1. Select a single-crystal silicon substrate with an area of ​​156mm×156mm as the crystal silicon substrate 1;

[0083] S2. An intrinsic amorphous silicon layer 2 is deposited on the back side of the crystalline silicon substrate 1 using the PECVD method. The thickness of the intrinsic amorphous silicon layer 2 is 13 nm.

[0084] S3. In a predetermined P-type doped region on the outer surface of the intrinsic amorphous silicon layer 2, a mixture of diborane and hydrogen gas is introduced at a flow rate of 23000 sccm, with a diborane to hydrogen flow ratio of 0.02:1. Argon gas is also introduced as an inert gas. Plasma is generated using a radio frequency power supply and a low frequency power supply, allowing boron ions to enter the intrinsic amorphous silicon layer 2 for the first ion doping, forming a P-type doped region 3. The highest H doping concentration in the P-type doped region 3 is 4e21cm³. -3 The highest doping concentration of boron is 3e21cm. -3 The thickness of P-type doped region 3 is 5 nm; the calculated ratio of the highest H doping concentration to the highest B doping concentration in P-type doped region 3 is 1.33.

[0085] S4. In a predetermined N-type doped region on the outer surface of the intrinsic amorphous silicon layer 2, a mixture of phosphine and hydrogen gas is introduced at a flow rate of 27000 sccm, with a phosphine to hydrogen flow rate ratio of 0.1:1. Helium is introduced as an inert gas. A plasma is generated using a radio frequency power supply and a low-frequency power supply, allowing phosphorus ions to enter the intrinsic amorphous silicon layer 2 for second ion doping, forming an N-type doped region 4. An isolation region (i.e., intrinsic amorphous silicon) is left between the predetermined P-type doped region 3 and the predetermined N-type doped region 4. Thus, the doped film layer 2 forms an amorphous silicon layer (with the same thickness as the intrinsic amorphous silicon layer 2). The highest H doping concentration in the N-type doped region 4 is 4e21cm³. -3 The highest phosphorus doping concentration is 1.5e21cm. -3 The thickness is 5 nm. At this point, the calculated ratio of the highest H doping concentration to the highest P doping concentration in N-type doped region 4 is 2.67. The thicknesses of both N-type doped region 4 and P-type doped region 3 are 38% of the amorphous silicon layer thickness. P-type doped region 3 and N-type doped region 4 are separated by an isolation region. The width ratio of P-type doped region 3, N-type doped region 4, and the isolation region is 5:3:1. The width of the isolation region is 100 µm.

[0086] Then, a passivation layer (not shown in the figure) and an antireflection layer (not shown in the figure) are deposited on the front side of the crystalline silicon substrate 1.

[0087] S5. A transparent conductive film layer 5, i.e., an ITO layer, is deposited on the back side using the PVD method to cover the entire back side. An isolation trench is formed on the transparent conductive film layer 5 outside the isolation region between the P-type doped region 3 and the N-type doped region 4. The thickness of the ITO layer is 80 nm.

[0088] S6. Metal electrodes 6 are respectively set on the outer surfaces of the P-type doped region 3 and the N-type doped region 4, and the metal electrodes 6 are formed by screen printing using silver paste.

[0089] Example 2

[0090] The procedure was carried out in accordance with Example 1, except that the highest P doping concentration in the N-type doped region was adjusted to 1e21cm. -3 This results in a ratio of 4 between the highest H doping concentration and the highest P doping concentration in the N-type doped region.

[0091] Example 3

[0092] The procedure was carried out in accordance with Example 1, except that the highest boron doping concentration in the p-type doped region was adjusted to 2e21cm. -3 This results in a ratio of 2 between the highest H doping concentration and the highest B doping concentration in the P-type doped region.

[0093] Example 4

[0094] The same procedure was followed as in Example 1, except that the width of the N-type doped region was adjusted to 400µm, so that the width ratio of the N-type doped region to the isolation region was 4:1.

[0095] Example 5

[0096] The same procedure was followed as in Example 1, except that the width of the P-type doped region was adjusted to 600µm, so that the width ratio of the P-type doped region to the isolation region was 6:1.

[0097] Example 6

[0098] The same procedure was performed as in Example 1, except that the thickness of the N-type doped region was adjusted to 6 nm, so that the thickness of the N-type doped region was 46% of the thickness of the amorphous silicon layer.

[0099] Comparative Example 1

[0100] A conventional back-contact battery is prepared by the following method:

[0101] S101, Provides a crystalline silicon substrate;

[0102] S102. A first semiconductor layer and a mask layer are sequentially formed on the back side of a crystalline silicon substrate. The first semiconductor layer is an intrinsic amorphous silicon layer (thickness of 5 nm) and an N-type doped amorphous silicon layer (thickness and doping concentration are the same as the N-type doped region in Example 1).

[0103] S103. The back side obtained in S102 is etched with a first opening to form a second semiconductor opening region;

[0104] S104. Texturing and cleaning: Remove the mask layer and the first semiconductor layer remaining in the second semiconductor opening area, and form a textured surface on the front side of the crystalline silicon substrate and the second semiconductor opening area. Then, completely remove the mask layer or retain part of the mask layer.

[0105] S105. A passivation layer and an anti-reflection layer are formed on the front side of the crystalline silicon substrate after texturing and cleaning in S104. Then, the wrapping plating on the back side of the crystalline silicon substrate is removed by cleaning.

[0106] S106. Deposit a second semiconductor layer on the back side obtained in S105; the second semiconductor layer is an intrinsic amorphous silicon layer (thickness of 5nm) and a P-type doped amorphous silicon layer (thickness and doping concentration are the same as the P-type doped region in Example 1).

[0107] S107. A second etching opening is made on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region.

[0108] S108. Deposit a transparent conductive film layer on the back side obtained in S107;

[0109] S109. A third etching opening is made on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench.

[0110] S110, metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

[0111] Comparative Example 2

[0112] The same procedure was followed as in Example 1, except that the highest P doping concentration in the N-type doped region was adjusted so that the ratio of the highest H doping concentration to the highest P doping concentration in the N-type doped region was 20.

[0113] Comparative Example 3

[0114] The same procedure was followed as in Example 1, except that the highest B doping concentration in the P-type doped region was adjusted so that the ratio of the highest H doping concentration to the highest B doping concentration in the P-type doped region was 1.0.

[0115] Test case

[0116] The back contact batteries obtained in the above embodiments and comparative examples were subjected to performance tests, and the results are shown in Table 1. The method for testing the risk of film bursting is as follows: After scratching the surface of the test sample with a blade, special adhesive tape was applied and quickly peeled off. The morphology of the cut line edge was observed under an optical microscope. The appearance of serrated cracks or slight curling or peeling of the cut line indicates poor surface adhesion and a high risk of film bursting. The appearance of neat cut line edges without curling or peeling indicates high surface adhesion and a low risk of film bursting.

[0117] Table 1

[0118]

[0119] The results above show that, compared with the comparative example, the embodiment of the present invention, which adopts a flat back contact battery structure, can still have a lower series resistance and lower carrier recombination at the same thickness in the N / P region, thus achieving good battery conversion efficiency. At the same time, it reduces stress concentration and edge recombination, thereby reducing the risk of film bursting and leakage.

[0120] Furthermore, as can be seen from Examples 1 and 2-6, the preferred scheme of the present invention is more conducive to obtaining higher battery conversion efficiency.

[0121] The preferred embodiments of the present invention have been described in detail above; however, the present invention is not limited thereto. Within the scope of the inventive concept, various simple modifications can be made to the technical solutions of the present invention, including combinations of various technical features in any other suitable manner. These simple modifications and combinations should also be considered as the content disclosed in the present invention and are all within the protection scope of the present invention.

Claims

1. An ultra-thin planar back contact battery, characterized in that, The amorphous silicon layer comprises a crystalline silicon substrate and an amorphous silicon layer arranged sequentially. The surface of the amorphous silicon layer away from the crystalline silicon substrate has alternately formed N-type doped regions and P-type doped regions, as well as an isolation region disposed between the N-type doped regions and the P-type doped regions. The ratio of the highest H concentration to the highest P doping concentration in the N-type doped region is 0.2-10, the ratio of the highest H concentration to the highest B doping concentration in the P-type doped region is not less than 1.2, and the thickness of the amorphous silicon layer is 7-60 nm. The thickness of the N-type doped region and the P-type doped region are each independently not greater than 10 nm.

2. The ultra-thin planar back contact battery according to claim 1, characterized in that, The ratio of the highest H concentration to the highest P doping concentration in the N-type doped region is 0.3-6, and / or the ratio of the highest H concentration to the highest B doping concentration in the P-type doped region is 1.2-15.

3. The ultra-thin planar back contact battery according to claim 1, characterized in that, The isolation region is an amorphous silicon isolation region, and / or the amorphous silicon layer is intrinsic amorphous silicon.

4. The ultra-thin planar back contact battery according to claim 1, characterized in that, The H concentration in the N-type doped region is 1e20cm⁻¹. -3 up to 5e22cm -3 P doping concentration is 1e20cm -3 up to 5e22cm -3 ; and / or, the H concentration in the P-type doped region is 1e20cm⁻¹ -3 up to 5e22cm -3 The boron doping concentration is 1e20cm. -3 up to 5e22cm -3 .

5. The ultrathin planar back contact battery according to any one of claims 1-4, characterized in that, The width ratio of the P-type doped region, the N-type doped region, and the isolation region is (3-20):(2-15):1, and / or the width of the isolation region is 30-200µm.

6. The ultra-thin planar back contact battery according to claim 1, characterized in that, The width of the P-type doped region is 300-1500 µm, and the width of the N-type doped region is 200-1000 µm; and / or, The ratio of the thickness of the N-type doped region and the P-type doped region to the thickness of the amorphous silicon layer is (0.01-1):

1.

7. The ultra-thin planar back contact battery according to claim 1, characterized in that, The ultra-thin planar back contact battery also has at least one of the following structures: Structure 1: The ultra-thin planar back contact battery also includes: a transparent conductive film layer disposed on the outer surface of the amorphous silicon layer, and metal electrodes disposed on the outer surface of the transparent conductive film layers in the corresponding regions of the N-type doped region and the P-type doped region, respectively; and an isolation groove is formed on the transparent conductive film layer corresponding to the isolation region. Structure 2: The surface of the amorphous silicon layer is planar; Structure 3, the ultra-thin planar back contact battery also includes: depositing a passivation layer and an anti-reflection layer on the front side of a crystalline silicon substrate.

8. A method for preparing an ultrathin planar back contact battery, characterized in that, Includes the following steps: S1. Provide a crystalline silicon substrate; S2. An intrinsic amorphous silicon layer is deposited on the back side of a crystalline silicon substrate. The thickness of the intrinsic amorphous silicon layer is 7-60 nm. S3. Perform first ion doping on the preset P-type doped region on the outer surface of the intrinsic amorphous silicon layer to form a P-type doped region; S4. A second ion doping is performed on the preset N-type doped region on the outer surface of the intrinsic amorphous silicon layer to form an N-type doped region, and an amorphous silicon isolation region is left between the preset P-type doped region and the preset N-type doped region, thereby forming an amorphous silicon layer with a thickness of 7-60nm. Specifically, the ratio of the highest H concentration to the highest P concentration in the N-type doped region is controlled to be 0.2-10, the ratio of the highest H concentration to the highest B concentration in the P-type doped region is not less than 1.2, and the thickness of the N-type doped region and the P-type doped region are each independently not greater than 10 nm.

9. The method for preparing an ultrathin planar back contact battery according to claim 8, characterized in that, The preparation method also includes at least one of the following processes: In process 1, S2, the intrinsic amorphous silicon layer is deposited using the PECVD method; In process 2, the first ion doping in S3 and the second ion doping in S4 each independently form corresponding plasmas using radio frequency power supply, low frequency power supply or DC power supply. In process three, S3, the conditions for first ion doping include: introducing a gas containing diborane or trimethylborane, and a mixture thereof with hydrogen, and introducing at least one inert gas. In process four, S4, the conditions for second ion doping include: introducing a mixed gas containing phosphine and hydrogen, and introducing at least one inert gas.

10. The method for preparing an ultrathin planar back contact battery according to claim 8, characterized in that, The preparation method also includes: S5. Deposit a transparent conductive film on the outer surface of the amorphous silicon layer, and open an isolation trench on the transparent conductive film corresponding to the isolation region; S6. Set metal electrodes on the outside of the transparent conductive film in the corresponding regions of the N-type doped region and the P-type doped region, respectively; And / or, deposit a passivation layer and an antireflection layer on the front side of a crystalline silicon substrate.

11. An ultra-thin planar back contact battery, characterized in that, It is prepared by the method of any one of claims 8-10 for the preparation of an ultrathin planar back contact battery.

12. A battery assembly, characterized in that, It includes the ultrathin planar back contact battery as described in any one of claims 1-7, or the ultrathin planar back contact battery as described in claim 11.

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