Image forming apparatus

Abstract

The present technology relates to an imaging device capable of performing adjustments to prevent a phenomenon (such as trailing) that causes degradation of image quality. The imaging device includes a comparator circuit including: a first transistor to which a pixel signal output from a pixel is input; a second transistor to which the reference signal is input; a third transistor connected to a common terminal of the first transistor and the second transistor; and a capacitor disposed on a conductive line connecting a gate terminal of the third transistor and one end of the first transistor. This technique can be applied, for example, to an imaging device.

Description

TECHNICAL FIELD

[0001] The present technology relates to an imaging device, and particularly to an imaging device capable of suppressing image quality degradation. BACKGROUND

[0002] There has been a complementary metal-oxide semiconductor (CMOS) image sensor that performs analog-digital (AD) conversion of a pixel signal by comparing the pixel signal with a reference signal having a ramp waveform with a linear decrease by a comparator, and counting a time until the reference signal falls below the pixel signal (for example, refer to Patent Literature 1).

[0003] LIST OF CITATIONS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: JP 2009-171397 A SUMMARY

[0006] PROBLEMS

[0007] For example, in a case where a scene in which a partial strong light exists in a dark place is imaged, an image in which a bright or dark level band appears in a dark portion around an area where light hits can be imaged. This phenomenon is called smearing, and causes image quality degradation. Desirably, adjustment can be made so that the phenomenon called smearing does not occur.

[0008] The present technology is made in view of such a situation, and aims to make it possible to adjust sensitivity with respect to a phenomenon that causes image quality degradation.

[0009] SOLUTION TO PROBLEM

[0010] A first imaging device according to one aspect of the present technology includes a comparator circuit including: a first transistor to which a pixel signal output from a pixel is input; a second transistor to which a reference signal is input; a third transistor connected to a common terminal of the first transistor and the second transistor; and a capacitor provided on a wiring connecting a gate terminal of the third transistor and one end of the first transistor.

[0011] A second imaging device according to one aspect of the present technology includes a comparator circuit including: a differential pair to which a pixel signal output from a pixel and a reference signal are input; an amplifier circuit connected to an output terminal of the differential pair and including one end connected to a first high power supply voltage and the other end connected to a first low power supply voltage; an inverter circuit connected to an output terminal of the amplifier circuit and including one end connected to a second high power supply voltage and the other end connected to a second low power supply voltage; and a capacitor provided on a wiring connecting the output terminal of the amplifier circuit and the second low power supply voltage or on a wiring connecting the output terminal of the amplifier circuit and the first high power supply voltage.

[0012] A third imaging device according to one aspect of the present technology includes a comparator circuit including: a differential pair to which a pixel signal output from a pixel and a reference signal are input; and an amplifier circuit connected to an output terminal of the differential pair and including one end connected to a high power supply voltage and the other end connected to a low power supply voltage. The amplifier circuit includes a first transistor including a gate terminal connected to the output terminal of the differential pair and a second transistor including a gate terminal connected to one end of a capacitor. The other end of the capacitor is connected to the high power supply voltage or the low power supply voltage.

[0013] A fourth imaging device according to one aspect of the present technology includes a comparator circuit including: a differential pair to which a pixel signal output from a pixel and a reference signal are input; an amplifier circuit connected to an output terminal of the differential pair and including one end connected to a first high power supply voltage and the other end connected to a first low power supply voltage; an inverter circuit connected to an output terminal of the amplifier circuit and including one end connected to a second high power supply voltage and the other end connected to a second low power supply voltage; and a transistor provided on a wiring connecting the output terminal of the inverter circuit and the second high power supply voltage or on a wiring connecting the output terminal of the inverter circuit and the second low power supply voltage.

[0014] In a first imaging device according to one aspect of the present technology, a comparator circuit is provided, the comparator circuit including: a first transistor to which a pixel signal output from a pixel is input; a second transistor to which a reference signal is input; a third transistor connected to a common terminal of the first transistor and the second transistor; and a capacitor provided on a wiring connecting a gate terminal of the third transistor and one end of the first transistor.

[0015] In a second imaging device according to an aspect of the present technology, a comparator circuit is provided, the comparator circuit including: a differential pair to which a pixel signal output from a pixel and a reference signal are input; an amplifier circuit connected to an output terminal of the differential pair and including one end connected to a first high power supply voltage and the other end connected to a first low power supply voltage; an inverter circuit connected to an output terminal of the amplifier circuit and including one end connected to a second high power supply voltage and the other end connected to a second low power supply voltage; and a capacitor provided on a wiring connecting the output terminal of the amplifier circuit and the second low power supply voltage, or on a wiring connecting the output terminal of the amplifier circuit and the first high power supply voltage.

[0016] In a third imaging device according to an aspect of the present technology, a comparator circuit is provided, the comparator circuit including: a differential pair and an amplifier circuit to which a pixel signal output from a pixel and a reference signal are input; the amplifier circuit connected to an output terminal of the differential pair and including one end connected to a high power supply voltage and the other end connected to a low power supply voltage. The amplifier circuit includes a first transistor including a gate terminal connected to the output terminal of the differential pair and a second transistor including a gate terminal connected to one end of a capacitor. The other end of the capacitor is connected to the high power supply voltage or the low power supply voltage.

[0017] In a fourth imaging device according to an aspect of the present technology, a comparator circuit is provided, the comparator circuit including: a differential pair to which a pixel signal output from a pixel and a reference signal are input; an amplifier circuit connected to an output terminal of the differential pair and including one end connected to a first high power supply voltage and the other end connected to a first low power supply voltage; an inverter circuit connected to an output terminal of the amplifier circuit and including one end connected to a second high power supply voltage and the other end connected to a second low power supply voltage; and a transistor provided on a wiring connecting the output terminal of the inverter circuit and the second high power supply voltage, or on a wiring connecting the output terminal of the inverter circuit and the second low power supply voltage.

[0018] Note that the imaging device can be a stand-alone device or can be an internal block constituting one device. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a diagram describing a configuration of an embodiment of an imaging device to which the present technology is applied.

[0020] Figure 2 is a circuit diagram describing a configuration example of a pixel.

[0021] Figure 3 is a diagram for describing smearing.

[0022] Figure 4is a diagram describing an example of a circuit configuration of a comparator.

[0023] Figure 5 is a diagram describing an example of a circuit configuration of a comparator.

[0024] Figure 6 is a diagram describing a configuration of an amplifier circuit according to a first embodiment.

[0025] Figure 7 is a diagram describing another configuration of an amplifier circuit according to the first embodiment.

[0026] Figure 8 is a diagram for describing that smearing can be adjusted.

[0027] Figure 9 is a diagram describing a configuration of an amplifier circuit according to a second embodiment.

[0028] Figure 10 is a diagram describing a configuration of an amplifier circuit according to a third embodiment.

[0029] Figure 11 is a diagram describing a configuration of an amplifier circuit according to a fourth embodiment.

[0030] Figure 12 is a diagram describing a configuration of an amplifier circuit according to a fifth embodiment.

[0031] Figure 13 is a diagram describing another configuration of an amplifier circuit according to the fifth embodiment.

[0032] Figure 14 is a diagram describing a configuration of an amplifier circuit according to a sixth embodiment.

[0033] Figure 15 is a diagram describing a configuration of an amplifier circuit according to a seventh embodiment.

[0034] Figure 16 is a diagram depicting a configuration of an amplifier circuit according to an eighth embodiment.

[0035] Figure 17 is a diagram describing a configuration of an amplifier circuit according to a ninth embodiment.

[0036] Figure 18 is a diagram describing a configuration of an amplifier circuit according to a tenth embodiment.

[0037] Figure 19 is a block diagram describing an example of a schematic configuration of a vehicle control system.

[0038] Figure 20is an explanatory diagram that describes an example of a mounting position of an outside-vehicle information detecting section and an imaging section. DETAILED DESCRIPTION

[0039] Hereinafter, a mode for implementing the present technology (hereinafter, referred to as an embodiment) will be described.

[0040] Configuration example of imaging device

[0041] Figure 1 is a diagram that describes a configuration of an embodiment of the imaging device 100 to which the present technology is applied.

[0042] The imaging device 100 (also referred to as an imaging element or an image sensor) includes a pixel section 101, a timing control circuit 102, a vertical scanning circuit 103, a digital-analog conversion device (DAC) 104, an analog-digital conversion device (ADC) group 105, a horizontal transfer scanning circuit 106, an amplifier circuit 107, and a signal processing circuit 108.

[0043] In the pixel section 101, unit pixels (hereinafter, also simply referred to as pixels) are arranged in a matrix, and each unit pixel includes a photoelectric conversion element that photoelectrically converts incident light into an amount of electric charge corresponding to a light quantity thereof. Hereinafter, a specific circuit configuration of the unit pixel will be described with reference to Figure 2 A specific circuit configuration of the unit pixel will be described. Further, in the pixel section 101, a pixel drive line 109 is provided in a left-right direction (pixel array direction of a pixel row; horizontal direction) for each row of a pixel array having a matrix shape, and a vertical signal line 110 is provided in an up-down direction (pixel array direction of a pixel column; vertical direction). One end of each pixel drive line 109 is connected to an output terminal corresponding to each row of the vertical scanning circuit 103. Note that, although one pixel drive line 109 is shown for each pixel row in Figure 1 two or more pixel drive lines 109 can be provided for each pixel row.

[0044] The timing control circuit 102 includes a timing generator (not shown) that generates various timing signals. The timing control circuit 102 controls driving of the vertical scanning circuit 103, the DAC 104, the ADC group 105, the horizontal transfer scanning circuit 106, and the like, on the basis of various timing signals generated by the timing generator on the basis of a control signal or the like supplied from the outside.

[0045] The vertical scanning circuit 103 is constituted by a shift register, an address decoder, and the like. Although a specific configuration is omitted in the drawing, the vertical scanning circuit 103 includes a readout scanning system and a sweep scanning system.

[0046] The readout scanning system sequentially performs selective scanning on the unit pixels of the readout signal in units of rows. On the other hand, before the readout scanning by the readout scanning system is performed for a period of time corresponding to a shutter speed, the sweep scanning system performs sweep scanning (resetting) of unnecessary charges of the photoelectric conversion elements of the unit pixels from the readout row on the readout row to be read out by the readout scanning system. By the sweep scanning system sweeping (resetting) the unnecessary charges, a so-called electronic shutter operation is performed. Here, the electronic shutter operation refers to an operation of discarding photocharges of the photoelectric conversion elements and newly starting exposure (starting accumulation of photocharges). The signal read out by the readout operation of the readout scanning system corresponds to the amount of light incident since the immediately preceding readout operation or the start of the electronic shutter operation. Then, the period of time from the readout timing of the immediately preceding readout operation or the sweep timing of the electronic shutter operation to the readout timing of the current readout operation is the accumulation period (exposure period) of photocharges of the unit pixel.

[0047] The pixel signal VSL output from each unit pixel of the pixel row selectively scanned by the vertical scanning circuit 103 is supplied to the ADC group 105 via the vertical signal line 110 of each column.

[0048] The DAC 104 generates a reference signal VIN_REF which is a signal having a ramp waveform that linearly increases, and supplies the reference signal VIN_REF to the ADC group 105.

[0049] The ADC group 105 includes comparators (comparator circuits) 121-1 to 121-n, counters 122-1 to 122-n, and latches 123-1 to 123-n. Note that hereinafter, the comparators 121-1 to 121-n, the counters 122-1 to 122-n, and the latches 123-1 to 123-n are simply referred to as comparators 121, counters 122, and latches 123, respectively, in cases where individual distinction is not needed.

[0050] The comparators 121, the counters 122, and the latches 123 are provided one for each column of the pixel section 101, and constitute an ADC. That is, in the ADC group 105, an ADC is provided for each column of the pixel section 101.

[0051] The comparator 121 compares the voltage of a signal obtained by adding the pixel signal VSL output from each pixel to the reference signal VIN_REF through a capacitor with a predetermined reference voltage, and supplies an output signal indicating the comparison result to the counter 122.

[0052] The counter 122 counts based on the output signal of the comparator 121 until the time when the signal obtained by adding the pixel signal VSL to the reference signal VIN_REF by the capacitor exceeds a predetermined reference voltage, thereby converting the analog pixel signal into a digital pixel signal represented by a count value. The counter 122 supplies the count value to the latch 123.

[0053] The latch 123 holds the count value supplied from the counter 122. Further, the latch 123 performs correlated double sampling (CDS) by calculating the difference between the count value of the D phase corresponding to the pixel signal having the signal level and the count value of the P phase corresponding to the pixel signal having the reset level.

[0054] The horizontal transfer scanning circuit 106 is constituted by a shift register, an address decoder, and the like, and sequentially and selectively scans the circuit portion corresponding to the pixel column of the ADC group 105. Through the selective scanning by the horizontal transfer scanning circuit 106, the digital pixel signal held in the latch 123 is sequentially transferred to the amplifier circuit 107 via the horizontal transfer line 111.

[0055] The amplifier circuit 107 amplifies the digital pixel signal supplied from the latch 123, and supplies the amplified digital pixel signal to the signal processing circuit 108.

[0056] The signal processing circuit 108 performs predetermined signal processing on the digital pixel signal supplied from the amplifier circuit 107 to generate two-dimensional image data. For example, the signal processing circuit 108 corrects vertical line defects and point defects, or clamps the signal, or performs digital signal processing such as parallel-to-serial conversion, compression, encoding, addition, averaging, and intermittent operation. The signal processing circuit 108 outputs the generated image data to a device in a subsequent stage.

[0057] Configuration example of pixel

[0058] Figure 2 is a circuit diagram describing a configuration example of the pixel 150 provided in the pixel portion 101.

[0059] The pixel 150 includes, for example, a photodiode 151 as a photoelectric conversion element, and includes four transistors as active elements, that is, a transfer transistor 152 for the photodiode 151, an amplification transistor 154, a selection transistor 155, and a reset transistor 156.

[0060] The photodiode 151 photoelectrically converts incident light into an amount of charge (here, an electron) corresponding to the light quantity thereof.

[0061] The transfer transistor 152 is connected between the photodiode 151 and a floating diffusion (FD) 153. When turned on by a drive signal TX supplied from the vertical scanning circuit 103, the transfer transistor 152 transfers the electric charge accumulated in the photodiode 151 to the FD 153.

[0062] The gate of the amplification transistor 154 is connected to the FD 153. The amplification transistor 154 is connected to the vertical signal line 110 with a selection transistor 155 interposed therebetween, and constitutes a source follower with a constant current source 157 outside the pixel section 101. When the selection transistor 155 is turned on by a drive signal SEL supplied from the vertical scanning circuit 103, the amplification transistor 154 amplifies the potential of the FD 153, and outputs a pixel signal indicating the voltage corresponding to the potential to the vertical signal line 110. Then, the pixel signal output from each pixel 150 is supplied to each comparator 121 of the ADC group 105 via the vertical signal line 110.

[0063] The reset transistor 156 is connected between the power supply VDD and the FD 153. When the reset transistor 156 is turned on by a drive signal RST supplied from the vertical scanning circuit 103, the potential of the FD 153 is reset to the potential of the power supply VDD.

[0064] Smear

[0065] In a case where an elongated light source is imaged in a darkroom by the above-described imaging device 100, for example, an image such as that shown in Figure 3 A1 can be imaged. In the image A1 shown in Figure 3 In the image A1 shown in

[0066] The darkened region A3 is a region having the same color as the region other than the light input region A2 in the image A1, but appears darker, forming a region that appears sunken and blackened. This phenomenon is called smear. In the embodiment described below, the sensitivity to such smear can be adjusted.

[0067] Configuration of comparator

[0068] Figure 4 is a diagram that describes an example of the configuration of the comparator (comparator circuit) 121. The comparator 121 is constituted by a first amplifier circuit 201, a second amplifier circuit 202, and a third amplifier circuit 203. The first amplifier circuit 201 and the second amplifier circuit 202 are each connected to a high power supply voltage VDDA and a low power supply voltage VSSA. The voltage VDD of the high power supply voltage VDDA is higher than the voltage VSS of the low power supply voltage VSSA. The "A" in the high power supply voltage VDDA and the low power supply voltage VSSA indicates that the power supply voltage is for an analog circuit.

[0069] The third amplifier circuit 203 is connected to a high power supply voltage VDDD and a low power supply voltage VSSD. The "D" in the high power supply voltage VDDD and the low power supply voltage VSSD indicates that the power supply voltages are used for digital circuits.

[0070] The voltage values of the high power supply voltage VDDA and the high power supply voltage VDDD can be different or can be the same voltage value. For example, the voltage value of the high power supply voltage VDDA is higher than the voltage value of the high power supply voltage VDDD. The low power supply voltage VSSA and the low power supply voltage VSSD can be different in voltage value or can be the same voltage value. As an example, the low power supply voltage VSSA and the low power supply voltage VSSD are both at a ground potential (0 V).

[0071] The reference signal VIN_REF from the DAC 104 ( Figure 1 ) and the pixel signal VIN_PIX from the pixel 150 in the pixel section 101 are input to the first amplifier circuit 201. As described below, the first amplifier circuit 201 can be configured as a differential amplifier circuit. In the first amplifier circuit 201, the bias current VGCM is also supplied to the transistor 315 in the transistor 315 serving as a constant current source. Figure 5

[0072] The signal VOUT1 from the first amplifier circuit 201 is supplied to the second amplifier circuit 202. The second amplifier circuit 202 converts the input signal VOUT1 into a signal VOUT2 that rises as the input signal VOUT1 falls, and supplies the signal VOUT2 to the third amplifier circuit 203.

[0073] The third amplifier circuit 203 is a circuit that performs an inverting operation and outputs a signal VOUT3 that falls in the case where the input signal VOUT2 rises.

[0074] Figure 5 is a diagram that describes an example of a circuit configuration of the comparator 121.

[0075] The first amplifier circuit 201 is a differential amplifier circuit, and includes the transistors 313 and 314 forming a differential pair, the transistors 311 and 312 constituting a current mirror, and the transistor 315 serving as a constant current source that supplies a current corresponding to the input bias current VGCM.

[0076] The transistors 313, 314, and 315 are constituted by negative channel metal oxide semiconductor (NMOS) transistors, and the transistors 311 and 312 are constituted by positive channel MOS (PMOS) transistors.

[0077] The reference signal VIN_REF from the DAC 104 ( Figure 1 ​) The output reference signal VIN_REF is input to the gate of the transistor 313 of the transistors 313 and 314 forming a differential pair, and the pixel signal VIN_PIX output from the pixel 150 in the pixel section 101 is input to the gate of the transistor 314. Figure 1 and Figure 2 ) The pixel signal VIN_PIX output is input to the gate of the transistor 314. The sources of the transistors 313 and 314 are connected to the drain of the transistor 315, and the source of the transistor 315 is connected to the low power supply voltage VSSA (may be ground). A bias current VGCM is supplied to the gate of the transistor 315.

[0078] The drain of the transistor 313 is connected to the gates of the transistors 311 and 312 and the drain of the transistor 311 constituting a current mirror circuit. The drain of the transistor 314 is connected to the drain of the transistor 312. The sources of the transistors 311 and 312 are connected to the high power supply voltage VDDA.

[0079] The connection point of the drain of the transistor 312 and the drain of the transistor 314 is the output terminal of the first amplifier circuit 201, and a signal VOUT1 is output to the second amplifier circuit 202.

[0080] The second amplifier circuit 202 also functions as a buffer for buffering the output signal VOUT1 from the first amplifier circuit 201, so that the output signal VOUT1 is output at an appropriate level to the third amplifier circuit 203. That is, the second amplifier circuit 202 amplifies the output signal VOUT1 of the first amplifier circuit 201 with a predetermined gain, and outputs the output signal VOUT2 obtained as a result from the output terminal.

[0081] The second amplifier circuit 202 includes a transistor 411 and a transistor 412. The transistor 411 can be constituted by an NMOS transistor, and the transistor 412 can be constituted by a PMOS transistor.

[0082] The source of the transistor 412 is connected to the high power supply voltage VDDA, the gate of the transistor 412 is connected to the output terminal of the first amplifier circuit 201, and the drain of the transistor 412 is connected to the drain of the transistor 411 and the output terminal (third amplifier circuit 203). The source of the transistor 411 is connected to the low power supply voltage VSSA (may be ground GND), and the gate of the transistor 411 is connected to a bias generation circuit (not shown) and is supplied with a bias voltage VBN.

[0083] In the example described in Figure 5 , a configuration is described in which the voltage VBN from the bias generation circuit is supplied to the second amplifier circuit 202. Although Figure 5The configuration in which the bias voltage is supplied from the outside is described, but in the case where the second amplifier circuit 202 is of a self-bias type as described below, a configuration in which the supply of the bias voltage VBN from the bias generation circuit is omitted can also be adopted.

[0084] In the case where the bias voltage is supplied from the outside to the second amplifier circuit 202, a bias generation circuit is provided in the imaging device 100. The bias generation circuit is configured to be connected to Figure 1 each of the comparators 121-1 to 121-n in the imaging device 100 illustrated, and collectively supplies the bias voltage to each of the comparators 121-1 to 121-n.

[0085] The third amplifier circuit 203 includes a transistor 511 and a transistor 512. The transistor 511 can be constituted by an NMOS transistor, and the transistor 512 can be constituted by a PMOS transistor. The third amplifier circuit 203 functions as an inverter. Here, a case in which the third amplifier circuit 203 is constituted by the transistor 511 and the transistor 512 is described as an example; however, another configuration using a NAND circuit, an OR circuit, or the like can also be appropriately adopted.

[0086] The source of the transistor 512 is connected to the power supply VDDD, and the drain of the transistor 512 is connected to the drain of the transistor 511 and the output terminal VOUT3. The source of the transistor 511 is connected to a low power supply voltage VSSD (which can be a ground GND). The gate of the transistor 512 and the gate of the transistor 511 are connected to the output terminal VOUT2 of the second amplifier circuit 202, and the signal VOUT2 from the second amplifier circuit 202 is input to the gates.

[0087] Note that the configuration of the comparator 121 described here is an example, and can be appropriately changed according to another configuration such as a configuration in which the PMOS transistor described above is replaced with an NMOS transistor, and the present technology can be applied to the configuration after the change.

[0088] Hereinafter, each of the first amplifier circuit 201, the second amplifier circuit 202, and the third amplifier circuit 203 having a configuration for adjusting the sensitivity of the smearing will be further described.

[0089] Note that the adjustment of the sensitivity of the smearing refers to, for example, guiding a region in which darkening occurs in a whitening direction, or guiding a region in which whitening occurs in a blackening direction. By performing such adjustment, even if smearing occurs, an image in which the effect of the smearing is reduced is acquired.

[0090] First Embodiment

[0091] Figure 6is a diagram describing a configuration example of the first amplifier circuit 201a according to the first embodiment having a configuration for adjusting sensitivity of smearing. In the following description, components common to the configurations of the first amplifier circuit 201, the second amplifier circuit 202, and the third amplifier circuit 203 described in Figure 5

[0092] According to the first embodiment described in Figure 6 , the first amplifier circuit 201a has a configuration obtained by adding a capacitor 321 to the first amplifier circuit 201 described in Figure 5

[0093] One end of the capacitor 321 is connected to a common terminal (a portion indicated by TAIL in the figure; hereinafter referred to as the common terminal TAIL), and the source of the transistor 313 and the source of the transistor 314 are connected to the common terminal TAIL. The other end of the capacitor 321 is connected to the gate terminal of the transistor 315.

[0094] The capacitor 321 is provided on a wiring connecting the transistor 315 serving as a constant current source and the transistor 314 to which the pixel signal VIN_PIX is input. The capacitor 321 is provided on a wiring connecting the transistor 315 serving as a constant current source and the transistor 313 to which the reference signal VIN_REF is input. The capacitor 321 can be, for example, a capacitor including a high dielectric having a relative dielectric constant greater than a predetermined value (for example, 100).

[0095] A configuration in which a switch 322 is provided in the first amplifier circuit 201a' as shown in Figure 7 Figure 7 In the first amplifier circuit 201a' described in

[0096] In the example described in Figure 7 , the switch 322 is composed of an NMOS transistor, and the drain of the switch 322 is connected to the common terminal TAIL and the source of the switch 322 is connected to the capacitor 321. The switch 322 is configured so that a signal CVGCMEN is supplied to the gate of the switch 322 for on and off control.

[0097] The applicant of the present application confirmed by simulation that, in the first amplifier circuit 201a' described in Figure 7 , how much the appearance of dimming (appearance of smearing) changes between the case where the switch 322 is on and the case where the switch 322 is off.​​​Figure 8 The graphs showing the amount of tailing when switch 322 is on and when switch 322 is off are shown. The horizontal axis represents VSL[V], and the vertical axis represents the LSB value of the tailing.

[0098] exist Figure 8 In the graph shown, the curve represented by the dashed line represents the measurement when switch 322 is open (in other words, when capacitor 321 is open and a first amplifier circuit in the prior art that does not include capacitor 321 is used). Figure 8 The graph shown, represented by the solid line, indicates the state when switch 322 is on (in other words, when capacitor 321 is connected and used in…). Figure 6 The measurement quantity described herein (in the case of the first amplifier circuit 201a).

[0099] exist Figure 8 As can be seen, compared to the pattern when switch 322 is off, the pattern when switch 322 is on is closer to a position where the trailing amount is close to 0. This confirms that when switch 322 is on, i.e., by setting capacitor 321, the trailing amount is reduced and the area where the trailing occurs is guided in the whitening direction, thereby suppressing the trailing effect.

[0100] Therefore, according to this technology, the sensitivity of the trailing effect can be adjusted, the occurrence of trailing can be suppressed, and even when such trailing occurs, the effect of trailing can be reduced in image imaging.

[0101] Switch 322 can be configured to control its on or off state based on the characteristics of the image to be imaged. For example, a configuration may be adopted in which switch 322 is turned on when an image with a large difference between bright and dark areas (specifically, an image where dark areas occupy most of the image and may have a trailing effect) is being imaged.

[0102] The amount of trailing appears according to the pixel unit 101 ( Figure 1 In different cases, modules that tend to produce more trailing can be combined with switch 322 set to the ON state during manufacturing.

[0103] As a specific example, when a module combined with an imaging device is used as a sample product for imaging testing while the switch 322 is in the off state, if a trailing effect occurs in the darkening direction, the amount of trailing can be reduced by turning the imaging device combined with the module into the on state by turning the switch 322 on.

[0104] Similarly, in the case where trailing occurs in the whitening direction when the module combined with the imaging device is imaged as a sample product in a state where the switch 322 is in the on state, the amount of trailing can be reduced by combining the imaging device with the module by changing the switch 322 to the off state. Therefore, even in the case where trailing occurs during the imaging test, a module in which the amount of trailing is reduced without increasing the developing period can be developed and manufactured.

[0105] The capacitance of the capacitor 321 can be set according to the amount of trailing that can occur in the combined module (pixel portion 101), and the comparator 121 including the first amplifier circuit 201a including the capacitor 321 with a suitable capacitance can be combined with the module at the time of manufacture.

[0106] In the second embodiment and subsequent embodiments described below, in the case where the configuration of the switch is set, it is controlled according to the characteristics of the image to be taken whether the switch is on or off, or the on or off state is set according to the module to be combined as described above.

[0107] Second Embodiment

[0108] Figure 9 is a view showing a configuration example of the first amplifier circuit 201b according to the second embodiment. The first amplifier circuit 201b according to the second embodiment is different from the first amplifier circuit 201a' according to the first embodiment described in Figure 7 the first amplifier circuit 201a' according to the first embodiment described in

[0109] In the first amplifier circuit 201b shown in Figure 9 In the first amplifier circuit 201b shown in Figure 9 In the example described in

[0110] The drain of the transistor constituting the switch 331 is connected to the common terminal TAIL, and the source of the transistor is connected to the switch 322 and the switch 332. A configuration in which a signal SW1 is supplied to the gate of the switch 331 is employed. The drain of the transistor constituting the switch 332 is connected to the switch 331, and the source of the transistor is connected to the transistor 315. A configuration in which a signal SW2 is supplied to the gate of the switch 332 is employed.

[0111] In this way, a configuration in which the switch 331 and the switch 332 are inserted between the common terminal TAIL and the transistor 315 can also be employed. In the first amplifier circuit 201b also having this configuration, the sensitivity of the trailing can be adjusted.

[0112] Note that a configuration in which the switch 322 is removed in the first amplifier circuit 201b according to the second embodiment shown in FIG. 12 can also be employed. Figure 9

[0113] Third Embodiment

[0114] Figure 10 is a diagram that shows a configuration example of the first amplifier circuit 201c according to the third embodiment. Figure 10 The first amplifier circuit 201c according to the third embodiment depicted in FIG. 13 has a configuration obtained by adding a switch 341 and a capacitor 342 to the first amplifier circuit 201 depicted in FIG. 12. Figure 5

[0115] In the first amplifier circuit 201c according to the third embodiment, the switch 341 is connected between the transistor 314 and the transistor 315. Figure 10 In the first amplifier circuit 201c according to the third embodiment, the switch 341 is connected between the transistor 314 and the transistor 315.

[0116] Thus, a structure in which the switch 341 and the capacitor 342 are inserted between the transistor 314 that inputs a signal from the pixel 150 and the transistor 315 that is a constant current source can also be employed. In the first amplifier circuit 201c that also has this configuration, the sensitivity of the tail can be adjusted.

[0117] Note that a configuration in which the switch 341 is removed in the first amplifier circuit 201c according to the third embodiment shown in FIG. 13 can also be employed. Figure 10

[0118] Fourth Embodiment

[0119] Figure 11 is a diagram that depicts a configuration example of the first amplifier circuit 201d according to the fourth embodiment. The first amplifier circuit 201d according to the fourth embodiment is different from the first amplifier circuit 201c according to the third embodiment shown in FIG. 13 in that a switch 351 and a switch 352 are added, and other points remain the same. Figure 10

[0120] In the first amplifier circuit 201d shown in FIG. 15, the switch 351 and the switch 352 composed of transistors are connected between the common terminal TAIL and the transistor 315. In the example described in FIG. 15, an example in which the switch 351 and the switch 352 are composed of NMOS transistors is described. Figure 11 In the first amplifier circuit 201d shown in FIG. 15, the switch 351 and the switch 352 composed of transistors are connected between the common terminal TAIL and the transistor 315. In the example described in FIG. 15, an example in which the switch 351 and the switch 352 are composed of NMOS transistors is described. Figure 11 In the first amplifier circuit 201d shown in FIG. 15, the switch 351 and the switch 352 composed of transistors are connected between the common terminal TAIL and the transistor 315. In the example described in FIG. 15, an example in which the switch 351 and the switch 352 are composed of NMOS transistors is described.​​​​

[0121] The drain of the transistor constituting switch 351 is connected to the common terminal TAIL, and the source of the transistor is connected to switch 352. Signal SW1 is provided to the gate of switch 351. The drain of the transistor constituting switch 352 is connected to switch 351, and the source of the transistor is connected to transistor 315. Signal SW2 is provided to the gate of switch 352.

[0122] Alternatively, a configuration can be adopted in which switches 351 and 352 are inserted between the common terminal TAIL and transistor 315. In the first amplifier circuit 201d, which also has this configuration, the sensitivity of the trailing effect can be adjusted.

[0123] Note that it can also be used in Figure 11 The configuration of switch 341 is removed in the first amplifier circuit 201d of the fourth embodiment shown.

[0124] Fifth Implementation Method

[0125] Figure 12 This is a diagram illustrating an example configuration of a second amplifier circuit 202a according to a fifth embodiment, having a configuration for adjusting the sensitivity of the trailing effect. (Compared to...) Figure 5 The same components of the second amplifier circuit 202 described herein are indicated by the same reference numerals, and their descriptions are omitted as appropriate.

[0126] Figure 12 The second amplifier circuit 202a according to the fifth embodiment shown has the capability of adding capacitor 421. Figure 5 The configuration obtained by the second amplifier circuit 202 shown. One end of capacitor 421 is connected to the output terminal (referred to as output terminal VOUT2) of the second amplifier circuit 202a, and the other end is connected to the low supply voltage VSSD of the third amplifier circuit 203.

[0127] With Figure 13 The second amplifier circuit 202a' described herein can be configured with setting switch 422, similar to the one in the previous description. Figure 13 In the second amplifier circuit 202a' shown, switch 422 is connected between the output terminal VOUT2 and capacitor 421. In other embodiments, switch 422 may be constructed from a transistor. Furthermore, in another embodiment, such as... Figure 13 The switch 422 described herein may also be configured such that the switch described herein as a transistor is composed of switches other than transistors.

[0128] Figure 12 and Figure 13The second amplifier circuits 202a and 202a' described in the above-mentioned second embodiment describe a configuration of a case where a bias voltage VBN is supplied from the outside to the transistor 411. In a case where a configuration in which the bias voltage VBN is supplied from the outside as in the second amplifier circuits 202a and 202a', a bias generation circuit is provided in the imaging device 100 (1000) Figure 1 ) described in the above-mentioned first embodiment. The bias generation circuit is, for example, configured to be connected to each of the comparators 121-1 to 121-n in the imaging device 100 (1000) described in the above-mentioned first embodiment, and to commonly supply a bias voltage to each of the comparators 121-1 to 121-n. Figure 1

[0129] In the second amplifier circuits 202a and 202a' also having such a configuration, the sensitivity of the tailing can be adjusted.

[0130] Sixth Embodiment

[0131] Figure 14 is a view showing a configuration example of the second amplifier circuit 202b according to the sixth embodiment. The same components as the configuration of the second amplifier circuit 202 described in the above-mentioned first embodiment are denoted by the same reference numerals, and the description thereof is appropriately omitted. Figure 5

[0132] The second amplifier circuit 202b according to the sixth embodiment described in the above-mentioned first embodiment has a configuration obtained by adding a capacitor 431 and a switch 432 to the second amplifier circuit 202 described in the above-mentioned first embodiment. Figure 14 Figure 5 One end of the capacitor 431 is connected to the high power supply voltage VDDA, and the other end is connected to the switch 432. One end of the switch 432 is connected to the capacitor 431, and the other end is connected to the output terminal VOUT2.

[0133] The second amplifier circuit 202b depicted in the above-mentioned first embodiment has a configuration in which the capacitor 431 is provided on the high power supply voltage VDDA side, and the second amplifier circuit 202a' depicted in the above-mentioned first embodiment has a configuration in which the capacitor 421 is provided on the low power supply voltage VSSD side. The capacitors 421 and 431 for boosting the output signal VOUT2 can be provided on the low power supply voltage VSSD side or the high power supply voltage VDDA side. In the second amplifier circuit 202b also having such a configuration, the sensitivity of the tailing can be adjusted. Figure 14 Figure 13 Note that a configuration in which the switch 432 is removed in the second amplifier circuit 202b according to the sixth embodiment described in the above-mentioned first embodiment can also be employed.

[0134] Figure 14

[0135] Seventh Embodiment

[0136] ​​​​​​Figure 15 is a view that describes a configuration example of the second amplifier circuit 202c according to the seventh embodiment. The seventh embodiment and the eighth embodiment described below have a configuration in which the second amplifier circuit 202 is designed as a self-bias type.

[0137] Figure 15 The second amplifier circuit 202c described in FIG. 44 has a configuration obtained by adding a capacitor 441 and a switch 442 to the second amplifier circuit 202 described in FIG. 42. Figure 5 One end of the capacitor 441 is connected to the low power supply voltage VSSA, and the other end is connected to the switch 442 and the gate of the transistor 412.

[0138] The gate of the transistor 412 is connected to the low power supply voltage VSSA via the capacitor 441.

[0139] One end of the switch 442 is connected to the capacitor 441, and the other end is connected to the output terminal VOUT2. The drain of the transistor 412 is also connected to the output terminal VOUT2. The switch 442 is connected between the drain and the gate of the transistor 412.

[0140] The present technology can also be applied to the second amplifier circuit 202c of the self-bias type having such a configuration. In the second amplifier circuit 202c also having such a configuration, the sensitivity of the tail can be adjusted.

[0141] Note that a configuration in which the switch 442 is removed in the second amplifier circuit 202c according to the seventh embodiment described in FIG. 44 can also be adopted. Figure 15 Eighth Embodiment

[0142]

[0143] Figure 16 is a view that shows a configuration example of the second amplifier circuit 202d according to the eighth embodiment. Figure 16 The second amplifier circuit 202d shown in FIG. 45 is obtained by reversing the polarities of the transistors of the second amplifier circuit 202c shown in FIG. 44. Figure 15

[0144] Figure 16 The second amplifier circuit 202c depicted in FIG. 44 is configured by adding a capacitor 451 and a switch 452 to the second amplifier circuit 202 depicted in FIG. 42, and is different in that the transistor to which the output signal VOUT1 input from the first amplifier circuit 201 is connected is connected to the low power supply voltage VSSA side. Figure 5

[0145] ​​​The source of the transistor 462 is connected to the low power supply voltage VSSA. A configuration in which the gate of the transistor 462 is connected to the output terminal VOUT1 of the first amplifier circuit 201, and the output signal VOUT1 is supplied to the gate of the transistor 462 is adopted. The drain of the transistor 462 is connected to the drain of the transistor 461, the output terminal VOUT2, and one end of the switch 452.

[0146] The source of the transistor 461 is connected to the high power supply voltage VDDA, and the gate of the transistor 461 is connected to the high power supply voltage VDDA via the capacitor 451.

[0147] One end of the switch 452 is connected to the gate of the transistor 461, and is connected to the high power supply voltage VDDA via the capacitor 451, and the other end is connected to the drain of the transistor 461 and the output terminal VOUT2. The switch 452 is connected between the drain and the gate of the transistor 461.

[0148] The present technology is also applicable to the second amplifier circuit 202d of the self-bias type having such a configuration. In the second amplifier circuit 202d having such a configuration, the sensitivity of the tail can be adjusted.

[0149] Note that, in the second amplifier circuit 202d according to the eighth embodiment shown in Figure 16 , a configuration in which the switch 432 is removed can also be adopted.

[0150] Ninth Embodiment

[0151] Figure 17 is a view showing a configuration example of the third amplifier circuit 203a having a configuration for adjusting the sensitivity of the tail according to the ninth embodiment. The same components as the configuration of the third amplifier circuit 203 described in Figure 5 are denoted using the same reference numerals, and the description thereof is omitted as appropriate.

[0152] The third amplifier circuit 203a according to the ninth embodiment shown in Figure 17 has a configuration obtained by adding a switch 521 and a transistor 522 to the third amplifier circuit 203 shown in Figure 5 . An example in which the transistor 522 is constituted by an NMOS transistor is described. The transistor 522 is provided on a wiring connecting the low power supply voltage VSSD and an inverter circuit constituted by the transistor 511 and the transistor 512.

[0153] The drain of the transistor 522 is connected to the output terminal VOUT3 of the third amplifier circuit 203, and the source of the transistor 522 is connected to one end of the switch 521.

[0154] The gate of the transistor 522 is supplied with the output signal VOUT2 from the second amplifier circuit 202. A configuration in which the output signal VOUT2 from the second amplifier circuit 202 is supplied to the gate of the transistor 511, the gate of the transistor 512, and the gate of the transistor 522 is employed.

[0155] One end of the switch 521 is connected to the transistor 522, and the other end is connected to the low power supply voltage VSSD. A configuration in which the switch 521 is removed can also be employed as the third amplifier circuit 203a.

[0156] Figure 17 The third amplifier circuit 203a shown in FIG. 6 has a configuration obtained by increasing the number of NMOS transistors for driving the output signal VOUT3 from the third amplifier circuit 203a, and a configuration obtained by adding the gate capacitance thereof to the output signal VOUT2 from the second amplifier circuit 202.

[0157] Also in the third amplifier circuit 203a having such a configuration, the sensitivity of the tail can be adjusted.

[0158] Tenth Embodiment

[0159] Figure 18 is a diagram depicting a configuration example of the third amplifier circuit 203b according to the tenth embodiment.

[0160] Figure 18 The third amplifier circuit 203b according to the tenth embodiment shown in FIG. 7 has a configuration obtained by adding a switch 531 and a transistor 532 to the third amplifier circuit 203. Figure 5 The configuration shown in FIG. 7 is obtained by adding a switch 531 and a transistor 532 to the third amplifier circuit 203. An example in which the transistor 532 is constituted by a PMOS transistor is depicted. The transistor 532 is provided on a wiring connecting the high power supply voltage VDDD and the inverter circuit constituted by the transistor 511 and the transistor 512.

[0161] The source of the transistor 532 is connected to the high power supply voltage VDDD via the switch 531, and the drain of the transistor 532 is connected to the output terminal VOUT3 of the third amplifier circuit 203.

[0162] The gate of the transistor 532 is supplied with the output signal VOUT2 from the second amplifier circuit 202. A configuration in which the output signal VOUT2 from the second amplifier circuit 202 is supplied to the gate of the transistor 511, the gate of the transistor 512, and the gate of the transistor 532 is employed.

[0163] One end of the switch 531 is connected to the transistor 532, and the other end is connected to the high power supply voltage VDDD. A configuration in which the switch 531 is removed can also be employed in the third amplifier circuit 203b.

[0164] Figure 18 The third amplifier circuit 203b shown in FIG. 12 has a configuration obtained by increasing the number of PMOS transistors for driving the output signal VOUT3 from the third amplifier circuit 203b, and a configuration obtained by adding the gate capacitance thereof to the output signal VOUT2 from the second amplifier circuit 202.

[0165] In the third amplifier circuit 203b also having such a configuration, the sensitivity of the tailing can be adjusted.

[0166] The first to fourth embodiments related to the first amplifier circuit 201, the fifth to eighth embodiments related to the second amplifier circuit 202, and the ninth and tenth embodiments related to the third amplifier circuit 203 can be implemented independently or can be implemented in combination.

[0167] For example, the comparator 121 can be the comparator 121 to which any one of the first to tenth embodiments is applied.

[0168] For example, the comparator 121 can be the comparator 121 including the first amplifier circuit 201 to which any one of the first to fourth embodiments is applied and the second amplifier circuit 202 to which any one of the fifth to eighth embodiments is applied.

[0169] For example, the comparator 121 can be the comparator 121 including the first amplifier circuit 201 to which any one of the first to fourth embodiments is applied and the third amplifier circuit 203 to which any one of the ninth and tenth embodiments is applied.

[0170] For example, the comparator 121 can be the comparator 121 including the second amplifier circuit 202 to which any one of the fifth to eighth embodiments is applied and the third amplifier circuit 203 to which any one of the ninth and tenth embodiments is applied.

[0171] For example, the comparator 121 can be the comparator 121 including the first amplifier circuit 201 to which any one of the first to fourth embodiments is applied, the second amplifier circuit 202 to which any one of the fifth to eighth embodiments is applied, and the third amplifier circuit 203 to which any one of the ninth and tenth embodiments is applied.

[0172] By applying the present technology, the sensitivity of the tailing can be adjusted. In a case where the sensitivity of the tailing can be adjusted, the sensitivity can be adjusted with respect to a phenomenon that causes image quality degradation and the image quality degradation can be suppressed.

[0173] Application example of mobile body

[0174] The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein can be implemented as a device installed on any type of mobile body, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, aircraft, drones, ships, and robots.

[0175] Figure 19 This is a block diagram illustrating an example of a schematic configuration of a vehicle control system, which is an example of a mobile body control system to which the technology according to embodiments of this disclosure can be applied.

[0176] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 19 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, as examples of the functional structure of the integrated control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0177] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 is used as a control device for drive force generating devices (such as internal combustion engines, drive motors, etc.) that generate drive force for the vehicle, drive force transmission mechanisms that transmit drive force to the wheels, steering mechanisms that adjust the vehicle's steering angle, and braking devices that generate braking force for the vehicle.

[0178] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 serves as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, taillights, brake lights, turn signals, fog lights, etc. In this case, radio waves or signals from various switches, which are alternatives to buttons, can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locks, power windows, lights, etc.

[0179] The vehicle exterior information detection unit 12030 detects information outside the vehicle including the vehicle control system 12000. For example, an imaging section 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging section 12031 to take an image of the outside of the vehicle, and receives the taken image. In addition, the vehicle exterior information detection unit 12030 can also perform processing of detecting a person, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto, based on the received image.

[0180] The imaging section 12031 is an optical sensor that receives light and outputs an electric signal corresponding to the amount of light of the received light. The imaging section 12031 can output the electric signal as an image, or can output the electric signal as information on a measured distance. Furthermore, the light received by the imaging section 12031 can be visible light, or can be invisible light such as infrared rays.

[0181] The vehicle interior information detection unit 12040 detects information on the inside of the vehicle. The vehicle interior information detection unit 12040 is connected to, for example, a driver state detection section 12041 that detects the state of the driver. The driver state detection section 12041 includes, for example, a camera that takes an image of the driver. Based on detection information input from the driver state detection section 12041, the vehicle interior information detection unit 12040 can calculate the degree of fatigue of the driver or the degree of concentration of the driver, or can determine whether or not the driver is dozing off.

[0182] The microcomputer 12051 can calculate a control target value of a driving force generation device, a steering mechanism, or a brake device based on information on the inside or outside of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing functions of an advanced driver assistance system (ADAS) including collision avoidance or shock absorption for the vehicle, follow-up driving based on a follow-up distance, maintenance of the vehicle speed of the vehicle during driving, warning of a vehicle collision, warning of deviation of the vehicle from a lane, and the like.

[0183] In addition, the microcomputer 12051 can perform cooperative control for automatic driving by controlling the driving force generation device, the steering mechanism, the brake device, and the like based on information on the outside or inside of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, which makes the vehicle automatically travel without depending on the operation of the driver or the like.

[0184] In addition, the microcomputer 12051 can output a control command to the body system control unit 12030 on the basis of information about the outside of the vehicle obtained by the outside information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control intended to prevent glare by controlling the headlamp to change from high beam to low beam in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030.

[0185] The sound / image output section 12052 transmits an output signal of at least one of sound and image to an output device that can visually or aurally notify information to an occupant of the vehicle or outside of the vehicle. In Figure 19 Examples of the output device include an audio speaker 12061, a display section 12062, and an instrument panel 12063. The display section 12062 can include at least one of an on-board display and a head-up display.

[0186] Figure 20 is a schematic view that describes an example of a mounting position of the imaging section 12031.

[0187] In Figure 20 , the imaging section 12031 includes imaging sections 12101, 12102, 12103, 12104, and 12105.

[0188] The imaging sections 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions on the front nose, side mirrors, rear bumper, and rear door of the vehicle 12100 and at a position on the upper portion of the interior windshield. The imaging section 12101 provided to the front nose portion inside the vehicle interior and the imaging section 12105 provided to the upper portion of the windshield mainly obtain images of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the side mirrors mainly obtain images of the side of the vehicle 12100. The imaging section 12104 provided to the rear bumper or the rear door mainly obtains images of the rear of the vehicle 12100. The imaging section 12105 provided to the upper portion of the windshield inside the vehicle interior is mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, and the like.

[0189] Incidentally, Figure 20Examples of the imaging ranges of the imaging sections 12101 to 12104 are described. The imaging range 12111 indicates the imaging range of the imaging section 12101 provided to the front nose. The imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging sections 12102 and 12103 provided to the side mirrors. The imaging range 12114 indicates the imaging range of the imaging section 12104 provided to the rear bumper or the rear door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing image data imaged by the imaging sections 12101 to 12104.

[0190] At least one of the imaging sections 12101 to 12104 can have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 can be a stereo camera constituted by a plurality of imaging elements, or can be an imaging element having pixels for phase difference detection.

[0191] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the time change of the distance (relative speed with respect to the vehicle 12100) on the basis of the distance information obtained from the imaging sections 12101 to 12104, whereby it extracts a three-dimensional object present on the travel path of the vehicle 12100, moving in substantially the same direction as the vehicle 12100 at a prescribed speed (for example, equal to or greater than 0 km / hour). In addition, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), and the like. Thus, it is possible to perform cooperative control for automatic driving of the vehicle, which is independent of the operation of the driver or the like.

[0192] For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects on the basis of the distance information obtained from the imaging sections 12101 to 12104 into three-dimensional object data of two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. In the case where the collision risk is equal to or higher than a set value and thus there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062, and performs forced deceleration or avoidance steering via the drive system control unit 12010. The microcomputer 12051 can thereby assist the driver to avoid collision.

[0193] At least one of the imaging sections 12101 to 12104 can be an infrared camera that detects infrared rays. The microcomputer 12051 can recognize a pedestrian, for example, by determining whether a pedestrian is present in a captured image of the imaging sections 12101 to 12104. This recognition of a pedestrian is performed, for example, by a process of extracting feature points in an imaged image of the imaging sections 12101 to 12104 as an infrared camera and a process of performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the imaged image of the imaging sections 12101 to 12104 and thus recognizes a pedestrian, the sound / image output section 12052 controls the display section 12062 so that a square outline for emphasis is displayed superimposed on the recognized pedestrian. The sound / image output section 12052 can also control the display section 12062 so that an icon or the like representing a pedestrian is displayed at a desired position.

[0194] In this specification, a system refers to an entirety of devices constituted by a plurality of devices.

[0195] Note that the effects described in this specification are merely examples and are not limiting, and other effects can be provided.

[0196] Note that embodiments of the present technology are not limited to the above-described embodiments, and various changes can be made without departing from the gist of the present technology.

[0197] Note that the present technology can also adopt a configuration such as the following. (1)

[0199] An imaging device includes: a comparator circuit including a first transistor to which a pixel signal output from a pixel is input, a second transistor to which a reference signal is input, a third transistor connected to a common terminal of the first transistor and the second transistor, and a capacitor provided on a wiring connecting a gate terminal of the third transistor and one end of the first transistor. (2)

[0201] The imaging device according to (1), wherein the comparator circuit further includes a switch connected in series with the capacitor on the wiring. (3)

[0203] The imaging device according to (1) or (2), wherein the wiring connects the gate terminal of the third transistor and the common terminal. (4)

[0205] The imaging device according to (1) or (2), wherein the wiring connects a gate terminal of the third transistor and a gate terminal of the first transistor. (5)

[0207] An imaging device comprising: a comparator circuit including a differential pair to which a pixel signal output from a pixel and a reference signal are input, an amplifier circuit connected to an output terminal of the differential pair and including one end connected to a first high power supply voltage and the other end connected to a first low power supply voltage, an inverter circuit connected to an output terminal of the amplifier circuit and including one end connected to a second high power supply voltage and the other end connected to a second low power supply voltage, and a capacitor provided on a wiring connecting the output terminal of the amplifier circuit and the second low power supply voltage or on a wiring connecting the output terminal of the amplifier circuit and the first high power supply voltage. (6)

[0209] The imaging device according to (5), wherein the comparator circuit further includes a switch connected in series with the capacitor on the wiring. (7)

[0211] An imaging device comprising: a comparator circuit including a differential pair to which a pixel signal output from a pixel and a reference signal are input, and an amplifier circuit connected to an output terminal of the differential pair and including one end connected to a high power supply voltage and the other end connected to a low power supply voltage, wherein the amplifier circuit includes a first transistor including a gate terminal connected to the output terminal of the differential pair and a second transistor including a gate terminal connected to one end of a capacitor, and the other end of the capacitor is connected to the high power supply voltage or the low power supply voltage. (8)

[0213] The imaging device according to (7), wherein one end of the capacitor is connected to an output terminal of the amplifier circuit via a switch. (9)

[0215] An imaging device comprising: A comparator circuit includes: a differential pair to which a pixel signal output from a pixel and a reference signal are input; an amplifier circuit connected to an output terminal of the differential pair and including one end connected to a first high power supply voltage and the other end connected to a first low power supply voltage; an inverter circuit connected to an output terminal of the amplifier circuit and including one end connected to a second high power supply voltage and the other end connected to a second low power supply voltage; and a transistor provided on a wiring connecting the output terminal of the inverter circuit and the second high power supply voltage or on a wiring connecting the output terminal of the inverter circuit and the second low power supply voltage. (10)

[0217] The imaging device according to (9), wherein the comparator circuit further includes a switch connected in series with the transistor on the wiring.

[0218] Reference List

[0219] 100 imaging device, 101 pixel section, 102 timing control circuit, 103 vertical scanning circuit, 105 ADC group, 106 horizontal transfer scanning circuit, 107 amplifier circuit, 108 signal processing circuit, 109 pixel drive line, 110 vertical signal line, 111 horizontal transfer line, 121 comparator, 122 counter, 123 latch, 150 pixel, 151 photodiode, 152 transfer transistor, 154 amplification transistor, 155 selection transistor, 156 reset transistor, 157 constant current source, 201 first amplifier circuit, 202 second amplifier circuit, 203 third amplifier circuit, 311 transistor, 312 transistor, 313 transistor, 314 transistor, 315 transistor, 321 capacitor, 322 switch, 331, 332 switch, 341 switch, 342 capacitor, 351, 352 switch, 411, 412 transistor, 421 capacitor, 422 switch, 431 capacitor, 432 switch, 441 capacitor, 442 switch, 451 capacitor, 452 switch, 461, 462 transistor, 511, 512 transistor, 521 switch, 522 transistor, 531 switch, 532 transistor.

Claims

1. An imaging device, comprising: The comparator circuit includes: a first transistor to which a pixel signal output from a pixel is input; a second transistor to which a reference signal is input; a third transistor connected to a common terminal of the first transistor and the second transistor; and a capacitor disposed on a wiring connecting the gate terminal of the third transistor and one end of the first transistor.

2. The imaging device according to claim 1, in, The comparator circuit further includes a switch connected in series with the capacitor on the wiring.

3. The imaging device according to claim 1, in, The wiring connects the gate terminal of the third transistor and the common terminal.

4. The imaging device according to claim 1, in, The wiring connects the gate terminal of the third transistor and the gate terminal of the first transistor.

5. An imaging device, comprising: A comparator circuit includes: a differential pair, to which a pixel signal output from a pixel and a reference signal are input; an amplifier circuit connected to the output terminal of the differential pair and including one end connected to a first high power supply voltage and the other end connected to a first low power supply voltage; an inverter circuit connected to the output terminal of the amplifier circuit and including one end connected to a second high power supply voltage and the other end connected to a second low power supply voltage; and a capacitor disposed on a wiring connecting the output terminal of the amplifier circuit and the second low power supply voltage, or disposed on a wiring connecting the output terminal of the amplifier circuit and the first high power supply voltage.

6. The imaging apparatus according to claim 5, in, The comparator circuit further includes a switch connected in series with the capacitor on the wiring.

7. An imaging device, comprising: The comparator circuit includes a differential pair and an amplifier circuit. A pixel signal and a reference signal from the pixel output are input to the differential pair. The amplifier circuit is connected to the output terminal of the differential pair and includes a terminal connected to a high power supply voltage and a terminal connected to a low power supply voltage. The amplifier circuit includes a first transistor and a second transistor. The first transistor includes a gate terminal connected to the output terminal of the differential pair, and the second transistor includes a gate terminal connected to one end of a capacitor. The other end of the capacitor is connected to either the high power supply voltage or the low power supply voltage.

8. The imaging apparatus according to claim 7, in, One end of the capacitor is connected to the output terminal of the amplifier circuit via a switch.

9. An imaging device, comprising: A comparator circuit includes: a differential pair, to which a pixel signal output from a pixel and a reference signal are input; an amplifier circuit connected to the output terminal of the differential pair and including a terminal connected to a first high power supply voltage and a terminal connected to a first low power supply voltage; an inverter circuit connected to the output terminal of the amplifier circuit and including a terminal connected to a second high power supply voltage and a terminal connected to a second low power supply voltage; and a transistor disposed on a wiring connecting the output terminal of the inverter circuit to the second high power supply voltage, or disposed on a wiring connecting the output terminal of the inverter circuit to the second low power supply voltage.

10. The imaging apparatus according to claim 9, in, The comparator circuit further includes a switch connected in series with the transistor on the wiring.

Images